Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.40 97.15 90.83 97.67 83.58 94.42 98.45 91.68


Total test records in report: 1476
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1309 /workspace/coverage/default/27.i2c_host_may_nack.2474129810 May 12 12:47:37 PM PDT 24 May 12 12:47:45 PM PDT 24 759809646 ps
T1310 /workspace/coverage/default/26.i2c_target_stress_rd.3212737842 May 12 12:47:34 PM PDT 24 May 12 12:48:01 PM PDT 24 1422163229 ps
T1311 /workspace/coverage/default/12.i2c_host_override.3242805317 May 12 12:47:02 PM PDT 24 May 12 12:47:03 PM PDT 24 29363317 ps
T1312 /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1958450234 May 12 12:48:37 PM PDT 24 May 12 12:48:40 PM PDT 24 721855001 ps
T1313 /workspace/coverage/default/37.i2c_target_intr_stress_wr.2350128113 May 12 12:48:24 PM PDT 24 May 12 12:52:43 PM PDT 24 14152540089 ps
T1314 /workspace/coverage/default/24.i2c_target_stress_rd.3115129714 May 12 12:47:32 PM PDT 24 May 12 12:47:40 PM PDT 24 1356008483 ps
T1315 /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3649887559 May 12 12:47:16 PM PDT 24 May 12 12:48:34 PM PDT 24 10056551370 ps
T1316 /workspace/coverage/default/43.i2c_target_smoke.2906767216 May 12 12:48:49 PM PDT 24 May 12 12:49:07 PM PDT 24 1112516068 ps
T1317 /workspace/coverage/default/23.i2c_host_override.2063242872 May 12 12:47:28 PM PDT 24 May 12 12:47:30 PM PDT 24 32254513 ps
T1318 /workspace/coverage/default/31.i2c_target_bad_addr.286021207 May 12 12:47:57 PM PDT 24 May 12 12:48:08 PM PDT 24 890768268 ps
T1319 /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4151781281 May 12 12:49:26 PM PDT 24 May 12 12:49:32 PM PDT 24 200396312 ps
T1320 /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2215796913 May 12 12:46:26 PM PDT 24 May 12 12:46:35 PM PDT 24 182704515 ps
T1321 /workspace/coverage/default/38.i2c_host_error_intr.3147444941 May 12 12:48:29 PM PDT 24 May 12 12:48:32 PM PDT 24 262263041 ps
T1322 /workspace/coverage/default/46.i2c_host_smoke.1572580550 May 12 12:49:05 PM PDT 24 May 12 12:49:51 PM PDT 24 1892180533 ps
T1323 /workspace/coverage/default/19.i2c_target_smoke.3539006911 May 12 12:47:23 PM PDT 24 May 12 12:47:38 PM PDT 24 3853491647 ps
T1324 /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1541262089 May 12 12:47:26 PM PDT 24 May 12 12:47:28 PM PDT 24 156794959 ps
T1325 /workspace/coverage/default/8.i2c_target_stretch.2724145948 May 12 12:46:32 PM PDT 24 May 12 01:29:03 PM PDT 24 14703017694 ps
T1326 /workspace/coverage/default/48.i2c_host_smoke.2284478439 May 12 12:49:09 PM PDT 24 May 12 12:49:43 PM PDT 24 6666575537 ps
T1327 /workspace/coverage/default/36.i2c_host_stress_all.1361114972 May 12 12:48:25 PM PDT 24 May 12 01:02:01 PM PDT 24 27597917540 ps
T1328 /workspace/coverage/default/36.i2c_target_hrst.313881950 May 12 12:48:23 PM PDT 24 May 12 12:48:28 PM PDT 24 2105388814 ps
T1329 /workspace/coverage/default/30.i2c_target_hrst.3407011979 May 12 12:47:49 PM PDT 24 May 12 12:47:53 PM PDT 24 510222047 ps
T1330 /workspace/coverage/default/46.i2c_target_bad_addr.1104220693 May 12 12:48:59 PM PDT 24 May 12 12:49:03 PM PDT 24 2385785671 ps
T1331 /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1691373056 May 12 12:48:34 PM PDT 24 May 12 12:48:42 PM PDT 24 667900954 ps
T1332 /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1293071490 May 12 12:46:50 PM PDT 24 May 12 12:46:52 PM PDT 24 236545425 ps
T1333 /workspace/coverage/default/4.i2c_target_hrst.1405383168 May 12 12:46:21 PM PDT 24 May 12 12:46:24 PM PDT 24 2008517025 ps
T1334 /workspace/coverage/default/38.i2c_host_may_nack.3156228637 May 12 12:48:36 PM PDT 24 May 12 12:48:49 PM PDT 24 5269551763 ps
T1335 /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1258015871 May 12 12:46:59 PM PDT 24 May 12 12:47:00 PM PDT 24 327384367 ps
T1336 /workspace/coverage/default/32.i2c_target_stress_rd.804111702 May 12 12:48:03 PM PDT 24 May 12 12:48:49 PM PDT 24 5589350695 ps
T1337 /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1013385019 May 12 12:47:40 PM PDT 24 May 12 12:48:50 PM PDT 24 10072703053 ps
T1338 /workspace/coverage/default/22.i2c_host_override.4113622309 May 12 12:47:27 PM PDT 24 May 12 12:47:28 PM PDT 24 19542772 ps
T1339 /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3976748895 May 12 12:49:15 PM PDT 24 May 12 12:49:17 PM PDT 24 174577582 ps
T1340 /workspace/coverage/default/27.i2c_target_hrst.4027229211 May 12 12:47:32 PM PDT 24 May 12 12:47:37 PM PDT 24 509012745 ps
T1341 /workspace/coverage/default/5.i2c_host_error_intr.3963608122 May 12 12:46:16 PM PDT 24 May 12 12:46:18 PM PDT 24 619680131 ps
T1342 /workspace/coverage/default/31.i2c_host_error_intr.2782634358 May 12 12:48:06 PM PDT 24 May 12 12:48:08 PM PDT 24 383480878 ps
T1343 /workspace/coverage/default/8.i2c_target_intr_smoke.2936070064 May 12 12:46:32 PM PDT 24 May 12 12:46:40 PM PDT 24 1344129938 ps
T1344 /workspace/coverage/default/4.i2c_host_mode_toggle.683881833 May 12 12:46:22 PM PDT 24 May 12 12:47:06 PM PDT 24 4456559058 ps
T37 /workspace/coverage/default/36.i2c_host_mode_toggle.490077957 May 12 12:48:36 PM PDT 24 May 12 12:49:59 PM PDT 24 6908523297 ps
T78 /workspace/coverage/default/39.i2c_host_perf.4178106441 May 12 12:48:24 PM PDT 24 May 12 12:48:56 PM PDT 24 19952456156 ps
T1345 /workspace/coverage/default/21.i2c_target_bad_addr.828028886 May 12 12:47:21 PM PDT 24 May 12 12:47:26 PM PDT 24 3522420782 ps
T1346 /workspace/coverage/default/19.i2c_host_override.2559361003 May 12 12:47:12 PM PDT 24 May 12 12:47:13 PM PDT 24 102391941 ps
T1347 /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1200942936 May 12 12:46:45 PM PDT 24 May 12 12:46:47 PM PDT 24 546946899 ps
T1348 /workspace/coverage/default/31.i2c_target_intr_smoke.3951876149 May 12 12:48:02 PM PDT 24 May 12 12:48:08 PM PDT 24 5070961659 ps
T1349 /workspace/coverage/default/39.i2c_target_stress_wr.2360623767 May 12 12:48:35 PM PDT 24 May 12 12:59:23 PM PDT 24 44518639744 ps
T1350 /workspace/coverage/default/48.i2c_host_fifo_watermark.441028004 May 12 12:49:04 PM PDT 24 May 12 12:54:42 PM PDT 24 4298034930 ps
T1351 /workspace/coverage/default/47.i2c_target_bad_addr.2444938733 May 12 12:49:23 PM PDT 24 May 12 12:49:29 PM PDT 24 5613842771 ps
T1352 /workspace/coverage/default/34.i2c_host_fifo_full.2539077983 May 12 12:48:09 PM PDT 24 May 12 12:49:38 PM PDT 24 10002860433 ps
T1353 /workspace/coverage/default/28.i2c_target_smoke.1280300205 May 12 12:47:46 PM PDT 24 May 12 12:48:10 PM PDT 24 4695703926 ps
T1354 /workspace/coverage/default/23.i2c_host_may_nack.3142223923 May 12 12:47:28 PM PDT 24 May 12 12:47:53 PM PDT 24 715241682 ps
T1355 /workspace/coverage/default/34.i2c_target_hrst.2688597815 May 12 12:48:21 PM PDT 24 May 12 12:48:26 PM PDT 24 549094024 ps
T1356 /workspace/coverage/default/48.i2c_target_stress_rd.760490098 May 12 12:49:11 PM PDT 24 May 12 12:49:42 PM PDT 24 2657585652 ps
T1357 /workspace/coverage/default/29.i2c_target_intr_stress_wr.4108709168 May 12 12:47:43 PM PDT 24 May 12 12:49:28 PM PDT 24 16015232140 ps
T1358 /workspace/coverage/default/37.i2c_target_smoke.1506658595 May 12 12:48:19 PM PDT 24 May 12 12:48:29 PM PDT 24 1439496644 ps
T1359 /workspace/coverage/default/26.i2c_target_timeout.4242610444 May 12 12:47:31 PM PDT 24 May 12 12:47:40 PM PDT 24 5937368058 ps
T1360 /workspace/coverage/default/16.i2c_target_stress_wr.3004303060 May 12 12:47:05 PM PDT 24 May 12 12:47:15 PM PDT 24 7691961240 ps
T1361 /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1706641621 May 12 12:49:10 PM PDT 24 May 12 12:49:14 PM PDT 24 121089486 ps
T1362 /workspace/coverage/default/16.i2c_host_mode_toggle.3412943920 May 12 12:46:49 PM PDT 24 May 12 12:47:22 PM PDT 24 10791559397 ps
T1363 /workspace/coverage/default/17.i2c_host_fifo_watermark.2838295953 May 12 12:46:47 PM PDT 24 May 12 12:47:49 PM PDT 24 7066801270 ps
T1364 /workspace/coverage/default/45.i2c_target_timeout.635096682 May 12 12:49:07 PM PDT 24 May 12 12:49:15 PM PDT 24 1391222647 ps
T1365 /workspace/coverage/default/25.i2c_host_stress_all.2218695886 May 12 12:47:42 PM PDT 24 May 12 01:01:54 PM PDT 24 9994327477 ps
T1366 /workspace/coverage/default/44.i2c_target_bad_addr.3876697774 May 12 12:48:50 PM PDT 24 May 12 12:48:55 PM PDT 24 2504534329 ps
T1367 /workspace/coverage/default/29.i2c_target_intr_smoke.1884838232 May 12 12:47:59 PM PDT 24 May 12 12:48:04 PM PDT 24 2342242039 ps
T1368 /workspace/coverage/default/24.i2c_target_smoke.3377984721 May 12 12:47:28 PM PDT 24 May 12 12:47:43 PM PDT 24 8108548248 ps
T1369 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2952202311 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 16375779 ps
T1370 /workspace/coverage/cover_reg_top/39.i2c_intr_test.68285253 May 12 12:45:02 PM PDT 24 May 12 12:45:04 PM PDT 24 44496600 ps
T1371 /workspace/coverage/cover_reg_top/15.i2c_intr_test.850581624 May 12 12:44:54 PM PDT 24 May 12 12:44:55 PM PDT 24 50683986 ps
T145 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1723051419 May 12 12:45:06 PM PDT 24 May 12 12:45:08 PM PDT 24 164148453 ps
T88 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2938163961 May 12 12:45:04 PM PDT 24 May 12 12:45:06 PM PDT 24 21903297 ps
T146 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1482285077 May 12 12:45:12 PM PDT 24 May 12 12:45:14 PM PDT 24 659608056 ps
T171 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4080104795 May 12 12:45:01 PM PDT 24 May 12 12:45:03 PM PDT 24 25148333 ps
T222 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3180244610 May 12 12:44:49 PM PDT 24 May 12 12:44:51 PM PDT 24 23270838 ps
T223 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.845707095 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 364059972 ps
T1372 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3738099005 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 18820822 ps
T89 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1255201182 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 31407953 ps
T224 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2601726814 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 53373555 ps
T208 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1695887525 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 72085213 ps
T209 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.251725061 May 12 12:44:49 PM PDT 24 May 12 12:44:51 PM PDT 24 40074815 ps
T1373 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3148154657 May 12 12:44:40 PM PDT 24 May 12 12:44:48 PM PDT 24 146934369 ps
T1374 /workspace/coverage/cover_reg_top/5.i2c_intr_test.962461689 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 33682234 ps
T1375 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.804241971 May 12 12:44:51 PM PDT 24 May 12 12:44:53 PM PDT 24 33174938 ps
T1376 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2917632399 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 90377911 ps
T1377 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2866404706 May 12 12:44:50 PM PDT 24 May 12 12:44:52 PM PDT 24 18096574 ps
T172 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1298352941 May 12 12:44:41 PM PDT 24 May 12 12:44:44 PM PDT 24 897308339 ps
T188 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1688525641 May 12 12:44:52 PM PDT 24 May 12 12:44:55 PM PDT 24 136633512 ps
T225 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1196222120 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 34024034 ps
T210 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.155439966 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 73163233 ps
T187 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3989551075 May 12 12:44:58 PM PDT 24 May 12 12:45:01 PM PDT 24 442075634 ps
T205 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4056314537 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 89194600 ps
T1378 /workspace/coverage/cover_reg_top/32.i2c_intr_test.4265604280 May 12 12:45:17 PM PDT 24 May 12 12:45:19 PM PDT 24 42907701 ps
T1379 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2761176785 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 20132498 ps
T90 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1140684239 May 12 12:44:45 PM PDT 24 May 12 12:44:47 PM PDT 24 357872404 ps
T226 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1900916492 May 12 12:44:46 PM PDT 24 May 12 12:44:48 PM PDT 24 60051663 ps
T1380 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3555182160 May 12 12:44:59 PM PDT 24 May 12 12:45:00 PM PDT 24 83251039 ps
T1381 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2835446506 May 12 12:45:25 PM PDT 24 May 12 12:45:27 PM PDT 24 48347927 ps
T211 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.515584637 May 12 12:44:50 PM PDT 24 May 12 12:44:52 PM PDT 24 62169947 ps
T1382 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.18569502 May 12 12:45:05 PM PDT 24 May 12 12:45:07 PM PDT 24 100672830 ps
T1383 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2638250251 May 12 12:44:49 PM PDT 24 May 12 12:44:51 PM PDT 24 206493853 ps
T1384 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2561659134 May 12 12:45:20 PM PDT 24 May 12 12:45:21 PM PDT 24 25042860 ps
T91 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3641295310 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 32137160 ps
T212 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2440145625 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 16707980 ps
T1385 /workspace/coverage/cover_reg_top/26.i2c_intr_test.4144063466 May 12 12:44:50 PM PDT 24 May 12 12:44:52 PM PDT 24 20845629 ps
T92 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1162336552 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 232022583 ps
T189 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3256259564 May 12 12:45:01 PM PDT 24 May 12 12:45:05 PM PDT 24 527454500 ps
T1386 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1889926754 May 12 12:44:57 PM PDT 24 May 12 12:44:59 PM PDT 24 25401228 ps
T190 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2525134805 May 12 12:44:52 PM PDT 24 May 12 12:44:55 PM PDT 24 140053174 ps
T93 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3835818831 May 12 12:44:55 PM PDT 24 May 12 12:45:03 PM PDT 24 151345203 ps
T94 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3277581289 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 62056705 ps
T206 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.894152674 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 61327430 ps
T95 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3748273040 May 12 12:44:46 PM PDT 24 May 12 12:44:47 PM PDT 24 256889151 ps
T1387 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2806938624 May 12 12:45:07 PM PDT 24 May 12 12:45:08 PM PDT 24 33352667 ps
T207 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.462260468 May 12 12:44:55 PM PDT 24 May 12 12:44:58 PM PDT 24 32807182 ps
T213 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2012287195 May 12 12:44:49 PM PDT 24 May 12 12:44:53 PM PDT 24 115564490 ps
T1388 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3148450751 May 12 12:45:02 PM PDT 24 May 12 12:45:04 PM PDT 24 18636246 ps
T1389 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.931775539 May 12 12:45:03 PM PDT 24 May 12 12:45:05 PM PDT 24 271285074 ps
T1390 /workspace/coverage/cover_reg_top/3.i2c_intr_test.351277595 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 39259445 ps
T1391 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2957154681 May 12 12:45:11 PM PDT 24 May 12 12:45:18 PM PDT 24 68982250 ps
T1392 /workspace/coverage/cover_reg_top/4.i2c_intr_test.2880935311 May 12 12:44:55 PM PDT 24 May 12 12:44:56 PM PDT 24 18858922 ps
T194 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3677654641 May 12 12:44:50 PM PDT 24 May 12 12:44:53 PM PDT 24 41951654 ps
T96 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3191957370 May 12 12:45:11 PM PDT 24 May 12 12:45:12 PM PDT 24 25791983 ps
T1393 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2484476059 May 12 12:45:00 PM PDT 24 May 12 12:45:01 PM PDT 24 16172505 ps
T214 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3695970541 May 12 12:44:40 PM PDT 24 May 12 12:44:46 PM PDT 24 86056677 ps
T1394 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1157734269 May 12 12:44:50 PM PDT 24 May 12 12:44:53 PM PDT 24 36821622 ps
T195 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3520037314 May 12 12:44:48 PM PDT 24 May 12 12:44:52 PM PDT 24 124488627 ps
T191 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.366935763 May 12 12:45:00 PM PDT 24 May 12 12:45:03 PM PDT 24 974640666 ps
T1395 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3553027294 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 32969816 ps
T1396 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1237637474 May 12 12:44:45 PM PDT 24 May 12 12:44:47 PM PDT 24 202943494 ps
T1397 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3821690300 May 12 12:44:52 PM PDT 24 May 12 12:44:55 PM PDT 24 28140189 ps
T97 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1736529442 May 12 12:44:56 PM PDT 24 May 12 12:45:03 PM PDT 24 141830651 ps
T117 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3282043318 May 12 12:44:42 PM PDT 24 May 12 12:44:43 PM PDT 24 95811486 ps
T1398 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1668034991 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 36898036 ps
T1399 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2041890235 May 12 12:44:50 PM PDT 24 May 12 12:44:51 PM PDT 24 15952111 ps
T1400 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1849281602 May 12 12:44:46 PM PDT 24 May 12 12:44:48 PM PDT 24 61444883 ps
T1401 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2183609371 May 12 12:45:02 PM PDT 24 May 12 12:45:03 PM PDT 24 16968945 ps
T1402 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2352539372 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 43798875 ps
T215 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1451071200 May 12 12:44:50 PM PDT 24 May 12 12:44:51 PM PDT 24 17292235 ps
T1403 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2345039508 May 12 12:45:02 PM PDT 24 May 12 12:45:04 PM PDT 24 39646296 ps
T196 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3511855035 May 12 12:44:48 PM PDT 24 May 12 12:44:51 PM PDT 24 50933273 ps
T197 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.905650386 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 242558650 ps
T1404 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2539910838 May 12 12:44:53 PM PDT 24 May 12 12:44:59 PM PDT 24 179216017 ps
T1405 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2425242154 May 12 12:44:53 PM PDT 24 May 12 12:44:55 PM PDT 24 68467729 ps
T1406 /workspace/coverage/cover_reg_top/33.i2c_intr_test.971680139 May 12 12:45:09 PM PDT 24 May 12 12:45:10 PM PDT 24 46507474 ps
T1407 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.142005850 May 12 12:44:58 PM PDT 24 May 12 12:45:01 PM PDT 24 105588922 ps
T1408 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3668891848 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 22116385 ps
T1409 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1030247921 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 29534032 ps
T1410 /workspace/coverage/cover_reg_top/22.i2c_intr_test.855038898 May 12 12:44:50 PM PDT 24 May 12 12:44:52 PM PDT 24 16361070 ps
T1411 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1085262108 May 12 12:44:57 PM PDT 24 May 12 12:45:00 PM PDT 24 22111898 ps
T202 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2070909136 May 12 12:45:03 PM PDT 24 May 12 12:45:06 PM PDT 24 304494503 ps
T216 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3892603246 May 12 12:44:47 PM PDT 24 May 12 12:44:50 PM PDT 24 25774011 ps
T1412 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1944305297 May 12 12:44:56 PM PDT 24 May 12 12:44:57 PM PDT 24 108871721 ps
T1413 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2797333125 May 12 12:44:57 PM PDT 24 May 12 12:44:59 PM PDT 24 33455898 ps
T1414 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2993507058 May 12 12:44:57 PM PDT 24 May 12 12:45:00 PM PDT 24 224160754 ps
T1415 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2893817277 May 12 12:45:03 PM PDT 24 May 12 12:45:06 PM PDT 24 501511926 ps
T198 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.34893955 May 12 12:44:46 PM PDT 24 May 12 12:44:49 PM PDT 24 97745316 ps
T1416 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1622242940 May 12 12:44:42 PM PDT 24 May 12 12:44:51 PM PDT 24 122490939 ps
T1417 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2453000458 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 144618046 ps
T1418 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2032562895 May 12 12:45:04 PM PDT 24 May 12 12:45:06 PM PDT 24 89324134 ps
T1419 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2938266751 May 12 12:45:19 PM PDT 24 May 12 12:45:22 PM PDT 24 504405209 ps
T1420 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3604583391 May 12 12:44:54 PM PDT 24 May 12 12:44:56 PM PDT 24 29571955 ps
T1421 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1412909003 May 12 12:44:50 PM PDT 24 May 12 12:44:52 PM PDT 24 40786364 ps
T1422 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1235532965 May 12 12:45:01 PM PDT 24 May 12 12:45:03 PM PDT 24 63387805 ps
T1423 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3528680375 May 12 12:44:48 PM PDT 24 May 12 12:44:51 PM PDT 24 138323976 ps
T1424 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4075301572 May 12 12:45:11 PM PDT 24 May 12 12:45:13 PM PDT 24 58264370 ps
T275 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1567220595 May 12 12:44:39 PM PDT 24 May 12 12:44:40 PM PDT 24 28038112 ps
T1425 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2363025384 May 12 12:44:51 PM PDT 24 May 12 12:44:53 PM PDT 24 70594397 ps
T1426 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3063196537 May 12 12:44:54 PM PDT 24 May 12 12:44:55 PM PDT 24 23506687 ps
T1427 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2734180091 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 23537393 ps
T192 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.913181809 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 413099365 ps
T1428 /workspace/coverage/cover_reg_top/8.i2c_intr_test.617203437 May 12 12:44:59 PM PDT 24 May 12 12:45:05 PM PDT 24 34690778 ps
T1429 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2808890581 May 12 12:44:31 PM PDT 24 May 12 12:44:33 PM PDT 24 52882650 ps
T1430 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.668360120 May 12 12:45:21 PM PDT 24 May 12 12:45:23 PM PDT 24 213048419 ps
T1431 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2258793107 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 44821742 ps
T1432 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1520908483 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 72931228 ps
T193 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3844799410 May 12 12:44:46 PM PDT 24 May 12 12:44:49 PM PDT 24 768212607 ps
T1433 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.807782860 May 12 12:44:45 PM PDT 24 May 12 12:44:48 PM PDT 24 400545507 ps
T1434 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1887617796 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 208351440 ps
T1435 /workspace/coverage/cover_reg_top/35.i2c_intr_test.936767399 May 12 12:44:58 PM PDT 24 May 12 12:45:00 PM PDT 24 22286933 ps
T217 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3561267820 May 12 12:44:57 PM PDT 24 May 12 12:45:04 PM PDT 24 1243104604 ps
T1436 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3236448442 May 12 12:44:44 PM PDT 24 May 12 12:44:45 PM PDT 24 28128181 ps
T1437 /workspace/coverage/cover_reg_top/45.i2c_intr_test.3999260660 May 12 12:45:14 PM PDT 24 May 12 12:45:16 PM PDT 24 20645948 ps
T1438 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.655453584 May 12 12:45:00 PM PDT 24 May 12 12:45:04 PM PDT 24 107895987 ps
T1439 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.799538986 May 12 12:45:11 PM PDT 24 May 12 12:45:13 PM PDT 24 123786376 ps
T218 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1708463342 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 26430130 ps
T243 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.738625831 May 12 12:45:01 PM PDT 24 May 12 12:45:04 PM PDT 24 287510743 ps
T1440 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1218087956 May 12 12:44:53 PM PDT 24 May 12 12:44:55 PM PDT 24 59302256 ps
T219 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.193434172 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 20189207 ps
T1441 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1248615918 May 12 12:45:09 PM PDT 24 May 12 12:45:10 PM PDT 24 16964796 ps
T1442 /workspace/coverage/cover_reg_top/0.i2c_intr_test.2043457209 May 12 12:44:39 PM PDT 24 May 12 12:44:40 PM PDT 24 83664355 ps
T1443 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1769514671 May 12 12:44:56 PM PDT 24 May 12 12:44:58 PM PDT 24 17764449 ps
T1444 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.875273384 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 29082601 ps
T1445 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2739742815 May 12 12:44:48 PM PDT 24 May 12 12:44:51 PM PDT 24 74020082 ps
T1446 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2702116689 May 12 12:45:07 PM PDT 24 May 12 12:45:15 PM PDT 24 50177896 ps
T200 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.335073110 May 12 12:45:01 PM PDT 24 May 12 12:45:03 PM PDT 24 141425291 ps
T199 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2016055670 May 12 12:44:53 PM PDT 24 May 12 12:45:05 PM PDT 24 619405579 ps
T1447 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1460614989 May 12 12:45:03 PM PDT 24 May 12 12:45:05 PM PDT 24 39910986 ps
T1448 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2765675757 May 12 12:44:50 PM PDT 24 May 12 12:44:53 PM PDT 24 25555895 ps
T1449 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2649266567 May 12 12:44:59 PM PDT 24 May 12 12:45:00 PM PDT 24 16809403 ps
T1450 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4196463851 May 12 12:44:53 PM PDT 24 May 12 12:44:57 PM PDT 24 264816872 ps
T1451 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3100251127 May 12 12:45:27 PM PDT 24 May 12 12:45:29 PM PDT 24 20049553 ps
T1452 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1383557494 May 12 12:45:01 PM PDT 24 May 12 12:45:02 PM PDT 24 22846169 ps
T1453 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1492551954 May 12 12:44:46 PM PDT 24 May 12 12:44:48 PM PDT 24 129863022 ps
T1454 /workspace/coverage/cover_reg_top/13.i2c_intr_test.4059151902 May 12 12:44:53 PM PDT 24 May 12 12:44:54 PM PDT 24 19025743 ps
T220 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2980617849 May 12 12:45:01 PM PDT 24 May 12 12:45:03 PM PDT 24 54764376 ps
T1455 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.513793988 May 12 12:44:48 PM PDT 24 May 12 12:44:50 PM PDT 24 197094072 ps
T1456 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2572933460 May 12 12:44:46 PM PDT 24 May 12 12:44:48 PM PDT 24 15463110 ps
T1457 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2665734719 May 12 12:45:11 PM PDT 24 May 12 12:45:12 PM PDT 24 30868630 ps
T1458 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3855446575 May 12 12:44:48 PM PDT 24 May 12 12:44:54 PM PDT 24 265993612 ps
T1459 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3609398434 May 12 12:44:50 PM PDT 24 May 12 12:44:51 PM PDT 24 47352194 ps
T1460 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1610701755 May 12 12:45:13 PM PDT 24 May 12 12:45:14 PM PDT 24 30812286 ps
T1461 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4124033972 May 12 12:44:54 PM PDT 24 May 12 12:44:56 PM PDT 24 48032279 ps
T1462 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2662371297 May 12 12:44:47 PM PDT 24 May 12 12:44:49 PM PDT 24 270160663 ps
T1463 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1012817155 May 12 12:45:00 PM PDT 24 May 12 12:45:02 PM PDT 24 31977954 ps
T1464 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4062075679 May 12 12:44:52 PM PDT 24 May 12 12:44:55 PM PDT 24 242620167 ps
T1465 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1564682683 May 12 12:44:53 PM PDT 24 May 12 12:44:55 PM PDT 24 15366837 ps
T1466 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3146794646 May 12 12:44:48 PM PDT 24 May 12 12:44:52 PM PDT 24 351743641 ps
T1467 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2688784843 May 12 12:44:50 PM PDT 24 May 12 12:44:53 PM PDT 24 233895651 ps
T1468 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3747920483 May 12 12:45:00 PM PDT 24 May 12 12:45:04 PM PDT 24 280558098 ps
T1469 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3022914686 May 12 12:44:52 PM PDT 24 May 12 12:44:54 PM PDT 24 59983570 ps
T1470 /workspace/coverage/cover_reg_top/43.i2c_intr_test.175132567 May 12 12:45:00 PM PDT 24 May 12 12:45:01 PM PDT 24 53479217 ps
T1471 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.990482762 May 12 12:44:50 PM PDT 24 May 12 12:44:55 PM PDT 24 326899125 ps
T201 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2728026122 May 12 12:44:47 PM PDT 24 May 12 12:44:51 PM PDT 24 516835208 ps
T1472 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2441541474 May 12 12:45:14 PM PDT 24 May 12 12:45:18 PM PDT 24 2397758321 ps
T203 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3314187964 May 12 12:44:45 PM PDT 24 May 12 12:44:47 PM PDT 24 287989011 ps
T1473 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3675525138 May 12 12:44:46 PM PDT 24 May 12 12:44:48 PM PDT 24 437359761 ps
T1474 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3062114054 May 12 12:44:50 PM PDT 24 May 12 12:44:54 PM PDT 24 1636649482 ps
T221 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2071951471 May 12 12:44:55 PM PDT 24 May 12 12:44:57 PM PDT 24 21232543 ps
T1475 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4168888596 May 12 12:44:53 PM PDT 24 May 12 12:44:57 PM PDT 24 151888720 ps
T1476 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.423637097 May 12 12:44:52 PM PDT 24 May 12 12:44:56 PM PDT 24 446454316 ps

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3714595174
Short name T3
Test name
Test status
Simulation time 19107904398 ps
CPU time 152.1 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 1322208 kb
Host smart-b4e1f30f-5ee2-423f-a2ec-1d148d0929a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714595174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3714595174
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3161347840
Short name T7
Test name
Test status
Simulation time 3285923119 ps
CPU time 4.99 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:47:18 PM PDT 24
Peak memory 212416 kb
Host smart-e873dddd-3f2f-4b5e-8e59-28a9ee8e1291
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161347840 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3161347840
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3020123622
Short name T22
Test name
Test status
Simulation time 7896152535 ps
CPU time 9.24 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 213012 kb
Host smart-ccf1f90d-e7e6-43bf-addb-f847aa531e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020123622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3020123622
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.2215605414
Short name T38
Test name
Test status
Simulation time 103333413668 ps
CPU time 1026.91 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 01:05:40 PM PDT 24
Peak memory 798124 kb
Host smart-3845d6a4-442b-4fbb-8612-525242610baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215605414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2215605414
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1140684239
Short name T90
Test name
Test status
Simulation time 357872404 ps
CPU time 0.94 seconds
Started May 12 12:44:45 PM PDT 24
Finished May 12 12:44:47 PM PDT 24
Peak memory 203664 kb
Host smart-3fc8cfd3-0d9f-4792-954f-426e17c25696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140684239 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1140684239
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1489257449
Short name T106
Test name
Test status
Simulation time 8298151093 ps
CPU time 314.91 seconds
Started May 12 12:49:22 PM PDT 24
Finished May 12 12:54:38 PM PDT 24
Peak memory 1274116 kb
Host smart-56301ed6-466e-4b76-a160-08ac012e8d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489257449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1489257449
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.4200472158
Short name T76
Test name
Test status
Simulation time 1011872684 ps
CPU time 11.29 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:54 PM PDT 24
Peak memory 204280 kb
Host smart-3d2a70e8-1a2f-4243-9e49-7de5a78be8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200472158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.4200472158
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.915453579
Short name T49
Test name
Test status
Simulation time 45557492 ps
CPU time 0.63 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 203992 kb
Host smart-fb4165e7-03fa-4d18-a0ad-5a30ea10fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915453579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.915453579
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1482285077
Short name T146
Test name
Test status
Simulation time 659608056 ps
CPU time 1.5 seconds
Started May 12 12:45:12 PM PDT 24
Finished May 12 12:45:14 PM PDT 24
Peak memory 203796 kb
Host smart-db236159-6a24-491f-90bf-a8332e39b577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482285077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1482285077
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.903971810
Short name T19
Test name
Test status
Simulation time 17941730737 ps
CPU time 107.33 seconds
Started May 12 12:49:29 PM PDT 24
Finished May 12 12:51:18 PM PDT 24
Peak memory 1485692 kb
Host smart-7bbc662f-a767-424f-a649-a8dd507f8410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903971810 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.903971810
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2287053335
Short name T68
Test name
Test status
Simulation time 10528518495 ps
CPU time 13.11 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 284768 kb
Host smart-084053bf-e2a5-4024-949b-1ca992f1dec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287053335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2287053335
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3001232080
Short name T86
Test name
Test status
Simulation time 87569468370 ps
CPU time 2351.72 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 01:26:22 PM PDT 24
Peak memory 1815480 kb
Host smart-93bfcd9d-b3b8-4d0d-b403-9d50bc2d9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001232080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3001232080
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2351915875
Short name T143
Test name
Test status
Simulation time 130964559 ps
CPU time 0.59 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 204160 kb
Host smart-5eefed13-693e-48f1-83af-014fa3e07172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351915875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2351915875
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.251725061
Short name T209
Test name
Test status
Simulation time 40074815 ps
CPU time 0.71 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203528 kb
Host smart-c08f60f9-eb41-4065-9b58-9b6e0484c1c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251725061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.251725061
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.901612451
Short name T45
Test name
Test status
Simulation time 162448692 ps
CPU time 1.06 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 204272 kb
Host smart-d9082012-21ca-4dee-8824-f307f81a302b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901612451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.901612451
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1376367943
Short name T178
Test name
Test status
Simulation time 146939106 ps
CPU time 0.85 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 221304 kb
Host smart-03ce94c3-126b-4a27-88a3-33280f2d3baf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376367943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1376367943
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.693347440
Short name T334
Test name
Test status
Simulation time 9570200338 ps
CPU time 29.32 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 239196 kb
Host smart-08dcafb2-2687-4d4a-a0eb-55ad74295466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693347440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.693347440
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3351670804
Short name T12
Test name
Test status
Simulation time 971125647 ps
CPU time 2.84 seconds
Started May 12 12:46:51 PM PDT 24
Finished May 12 12:46:54 PM PDT 24
Peak memory 204272 kb
Host smart-37862480-fd4d-4812-a403-b0c9ba9abae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351670804 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3351670804
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2083920046
Short name T35
Test name
Test status
Simulation time 1313636198 ps
CPU time 25.32 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 318004 kb
Host smart-e38785ca-b337-487c-8821-d834be28d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083920046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2083920046
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2525134805
Short name T190
Test name
Test status
Simulation time 140053174 ps
CPU time 2.36 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203800 kb
Host smart-91d8bd94-2f2d-42c8-ba10-fe07ea1d5271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525134805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2525134805
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1967691893
Short name T28
Test name
Test status
Simulation time 1731469809 ps
CPU time 2.57 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 204216 kb
Host smart-476512e7-96af-4896-940b-7777bf3274de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967691893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1967691893
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2435314885
Short name T264
Test name
Test status
Simulation time 7099057934 ps
CPU time 523.96 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 1179220 kb
Host smart-f0f7b31e-2887-47a6-9d50-0d419a15789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435314885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2435314885
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3877650614
Short name T39
Test name
Test status
Simulation time 27155425605 ps
CPU time 483.55 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:55:33 PM PDT 24
Peak memory 904844 kb
Host smart-92e56524-1e40-4001-92ec-b6dc089e9e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877650614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3877650614
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3475604063
Short name T61
Test name
Test status
Simulation time 38815008302 ps
CPU time 1169.06 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 01:05:33 PM PDT 24
Peak memory 2977504 kb
Host smart-f83a3d66-47f3-4ef1-b451-a591bd05dd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475604063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3475604063
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.342683528
Short name T82
Test name
Test status
Simulation time 12266796003 ps
CPU time 870.39 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 01:02:03 PM PDT 24
Peak memory 1130368 kb
Host smart-988ad4ef-0636-4304-979e-0cc678b1c667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342683528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.342683528
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3256259564
Short name T189
Test name
Test status
Simulation time 527454500 ps
CPU time 2.32 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203648 kb
Host smart-a1f0f8ec-8e75-4726-9ef7-d68113d69c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256259564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3256259564
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2820785939
Short name T144
Test name
Test status
Simulation time 527947341 ps
CPU time 3.12 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:38 PM PDT 24
Peak memory 223616 kb
Host smart-4464d8eb-d937-4d70-8ab2-afe65cf9e3a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820785939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2820785939
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.1563932913
Short name T16
Test name
Test status
Simulation time 2971832716 ps
CPU time 4.47 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 205344 kb
Host smart-4a6befd1-0bef-4a0b-b61e-ea690c747971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563932913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.1563932913
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.931717777
Short name T241
Test name
Test status
Simulation time 2570164186 ps
CPU time 6.94 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 204352 kb
Host smart-8ab5fb51-5131-487c-85f2-d14c51afc831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931717777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.931717777
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.927348646
Short name T119
Test name
Test status
Simulation time 58882762954 ps
CPU time 770.41 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:59:14 PM PDT 24
Peak memory 1302072 kb
Host smart-033c4973-31fa-450f-bed1-a93558fc0184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927348646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.927348646
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2071951471
Short name T221
Test name
Test status
Simulation time 21232543 ps
CPU time 0.78 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203484 kb
Host smart-dbdf5835-8dbc-46e5-8c8a-b2f2247216d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071951471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2071951471
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/default/1.i2c_host_override.2579481796
Short name T44
Test name
Test status
Simulation time 31951142 ps
CPU time 0.65 seconds
Started May 12 12:46:02 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 204028 kb
Host smart-0c96194f-794b-4bc2-9856-e0efb7b04741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579481796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2579481796
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.347784697
Short name T790
Test name
Test status
Simulation time 368578175 ps
CPU time 2.35 seconds
Started May 12 12:47:19 PM PDT 24
Finished May 12 12:47:22 PM PDT 24
Peak memory 204184 kb
Host smart-79b2956e-cde5-416d-8f26-dc9bf79972d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347784697 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.347784697
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2483950748
Short name T231
Test name
Test status
Simulation time 10266564081 ps
CPU time 15.48 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 263468 kb
Host smart-16f55462-f246-4e21-94d6-144c3d98f811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483950748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2483950748
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1547484646
Short name T41
Test name
Test status
Simulation time 2471589297 ps
CPU time 25.85 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 337244 kb
Host smart-51dbd2f6-7f3f-4906-bc27-b5eb2bc2c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547484646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1547484646
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1436497354
Short name T235
Test name
Test status
Simulation time 245043572 ps
CPU time 1.03 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 204396 kb
Host smart-b348506a-abce-4759-a098-0c4e85d37df9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436497354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1436497354
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_override.204359605
Short name T248
Test name
Test status
Simulation time 26673745 ps
CPU time 0.66 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:10 PM PDT 24
Peak memory 204084 kb
Host smart-4f3a0364-c77f-4926-92d2-1df05c3f7078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204359605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.204359605
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3835818831
Short name T93
Test name
Test status
Simulation time 151345203 ps
CPU time 2.33 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203764 kb
Host smart-b9dd3e38-a5d5-4da1-ac5c-fc23549a64b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835818831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3835818831
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/39.i2c_host_perf.4178106441
Short name T78
Test name
Test status
Simulation time 19952456156 ps
CPU time 30.32 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:56 PM PDT 24
Peak memory 411676 kb
Host smart-65e5cfc8-c5e3-4ee5-b4e3-b59fff5d2e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178106441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4178106441
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2289943928
Short name T66
Test name
Test status
Simulation time 10143336020 ps
CPU time 69.59 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 507496 kb
Host smart-368fb370-7983-40f6-9eca-0c048b319f9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289943928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2289943928
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1567220595
Short name T275
Test name
Test status
Simulation time 28038112 ps
CPU time 0.73 seconds
Started May 12 12:44:39 PM PDT 24
Finished May 12 12:44:40 PM PDT 24
Peak memory 203540 kb
Host smart-9c52c51f-55c8-4d6f-871f-958c96a3097c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567220595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1567220595
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2525154191
Short name T55
Test name
Test status
Simulation time 11335238401 ps
CPU time 160.3 seconds
Started May 12 12:47:03 PM PDT 24
Finished May 12 12:49:44 PM PDT 24
Peak memory 684468 kb
Host smart-92b879b5-f16a-4a50-a9ea-796021c068c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525154191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2525154191
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.720420333
Short name T266
Test name
Test status
Simulation time 4785367044 ps
CPU time 128.05 seconds
Started May 12 12:46:50 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 1214416 kb
Host smart-c4dd60a1-acfa-494e-b917-ce4c68e3a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720420333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.720420333
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.538229276
Short name T1152
Test name
Test status
Simulation time 353426491 ps
CPU time 2.58 seconds
Started May 12 12:47:20 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 204268 kb
Host smart-fe6b0e13-be8a-4120-9db4-69bc6f2519e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538229276 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.538229276
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.164842375
Short name T258
Test name
Test status
Simulation time 1621725760 ps
CPU time 30.3 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:48:02 PM PDT 24
Peak memory 212436 kb
Host smart-4db19646-8600-4d89-930c-276afd435e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164842375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.164842375
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3747758251
Short name T250
Test name
Test status
Simulation time 1685612275 ps
CPU time 29.99 seconds
Started May 12 12:48:25 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 228188 kb
Host smart-1d6bc667-3a1a-4f9e-a678-e28346b77a00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747758251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3747758251
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3844799410
Short name T193
Test name
Test status
Simulation time 768212607 ps
CPU time 2.09 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203764 kb
Host smart-f00ac759-1445-4ee9-a2ef-d045bdaecaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844799410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3844799410
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3511855035
Short name T196
Test name
Test status
Simulation time 50933273 ps
CPU time 1.33 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203808 kb
Host smart-3c71a5be-8bb5-4b7d-bd03-afa653f1ee2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511855035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3511855035
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.335073110
Short name T200
Test name
Test status
Simulation time 141425291 ps
CPU time 1.38 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203804 kb
Host smart-2c6fd10a-1aa4-436d-ae45-c96770678c42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335073110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.335073110
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2106047983
Short name T1101
Test name
Test status
Simulation time 10119304547 ps
CPU time 13 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:47:02 PM PDT 24
Peak memory 285096 kb
Host smart-bb79e721-e215-4365-a7df-02e1ceaedaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106047983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2106047983
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.423637097
Short name T1476
Test name
Test status
Simulation time 446454316 ps
CPU time 2.11 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203808 kb
Host smart-74161d29-a0c8-4826-b274-5d9cd88cf5b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423637097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.423637097
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3855446575
Short name T1458
Test name
Test status
Simulation time 265993612 ps
CPU time 5.3 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203752 kb
Host smart-ac2be283-e308-48f7-be2d-f4515e964d04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855446575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3855446575
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.155439966
Short name T210
Test name
Test status
Simulation time 73163233 ps
CPU time 0.77 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203476 kb
Host smart-98a2045f-7d2d-483b-a241-f103b34087df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155439966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.155439966
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3282043318
Short name T117
Test name
Test status
Simulation time 95811486 ps
CPU time 0.82 seconds
Started May 12 12:44:42 PM PDT 24
Finished May 12 12:44:43 PM PDT 24
Peak memory 203876 kb
Host smart-67782dec-9418-4b19-a8fd-c97516052dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282043318 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3282043318
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1255201182
Short name T89
Test name
Test status
Simulation time 31407953 ps
CPU time 0.8 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203888 kb
Host smart-f0316ac4-652f-4cd2-afae-a6857d5f17b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255201182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1255201182
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.2043457209
Short name T1442
Test name
Test status
Simulation time 83664355 ps
CPU time 0.64 seconds
Started May 12 12:44:39 PM PDT 24
Finished May 12 12:44:40 PM PDT 24
Peak memory 203404 kb
Host smart-d1468696-d537-4855-a4fc-187f99489740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043457209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2043457209
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1162336552
Short name T92
Test name
Test status
Simulation time 232022583 ps
CPU time 0.86 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203524 kb
Host smart-42769ce3-78d8-45e9-b425-8fe9b1d2559f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162336552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1162336552
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1012817155
Short name T1463
Test name
Test status
Simulation time 31977954 ps
CPU time 1.24 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:02 PM PDT 24
Peak memory 203776 kb
Host smart-42360e1d-568f-4dd5-b1f4-fe207b8cbd8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012817155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1012817155
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.990482762
Short name T1471
Test name
Test status
Simulation time 326899125 ps
CPU time 3.42 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203780 kb
Host smart-12adc376-86ca-4b54-a1d4-163c26e679a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990482762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.990482762
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3528680375
Short name T1423
Test name
Test status
Simulation time 138323976 ps
CPU time 0.93 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203596 kb
Host smart-3e2dc80f-2709-4ffd-b95c-fea7c3420f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528680375 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3528680375
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1668034991
Short name T1398
Test name
Test status
Simulation time 36898036 ps
CPU time 0.65 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203784 kb
Host smart-e87d8a8b-7fa8-4367-9da3-400cf86d3707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668034991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1668034991
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2808890581
Short name T1429
Test name
Test status
Simulation time 52882650 ps
CPU time 1.2 seconds
Started May 12 12:44:31 PM PDT 24
Finished May 12 12:44:33 PM PDT 24
Peak memory 203736 kb
Host smart-6715bbb3-ecf8-44d5-bf8d-3652d984fa3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808890581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2808890581
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3146794646
Short name T1466
Test name
Test status
Simulation time 351743641 ps
CPU time 2.31 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203816 kb
Host smart-523d9fc8-a102-46ae-8591-1f099243bd55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146794646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3146794646
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2688784843
Short name T1467
Test name
Test status
Simulation time 233895651 ps
CPU time 1.48 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203852 kb
Host smart-7c56b712-e322-4f42-ae48-0f7e1aaec07a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688784843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2688784843
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4056314537
Short name T205
Test name
Test status
Simulation time 89194600 ps
CPU time 0.92 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203648 kb
Host smart-78939ba6-1097-41d7-a605-b495d62105f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056314537 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4056314537
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1157734269
Short name T1394
Test name
Test status
Simulation time 36821622 ps
CPU time 0.69 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203476 kb
Host smart-c5636194-f8e2-473b-ae04-63e4c6e4a645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157734269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1157734269
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2797333125
Short name T1413
Test name
Test status
Simulation time 33455898 ps
CPU time 0.67 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:44:59 PM PDT 24
Peak memory 203412 kb
Host smart-eb635aa4-276a-4416-a82a-87f7da6a27f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797333125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2797333125
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2601726814
Short name T224
Test name
Test status
Simulation time 53373555 ps
CPU time 1.18 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203632 kb
Host smart-36b4e4d9-5142-48dd-91a7-96f30accb0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601726814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2601726814
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2893817277
Short name T1415
Test name
Test status
Simulation time 501511926 ps
CPU time 2.32 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203776 kb
Host smart-3b8ef51a-4165-40c1-a143-266402bc297a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893817277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2893817277
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3277581289
Short name T94
Test name
Test status
Simulation time 62056705 ps
CPU time 0.79 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203932 kb
Host smart-18eb1c63-6e2f-4026-913e-403a61c1f622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277581289 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3277581289
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2952202311
Short name T1369
Test name
Test status
Simulation time 16375779 ps
CPU time 0.65 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203436 kb
Host smart-8802bd61-69e8-4a46-b10e-00eddaae664e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952202311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2952202311
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.845707095
Short name T223
Test name
Test status
Simulation time 364059972 ps
CPU time 0.9 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203484 kb
Host smart-23538d5e-fb64-46e3-8218-86d49bf084f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845707095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.845707095
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3989551075
Short name T187
Test name
Test status
Simulation time 442075634 ps
CPU time 2.53 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203700 kb
Host smart-54621b43-246b-4040-b907-b25e856f9aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989551075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3989551075
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2016055670
Short name T199
Test name
Test status
Simulation time 619405579 ps
CPU time 1.59 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203804 kb
Host smart-10a4cb90-0930-4748-a730-1de15b24fd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016055670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2016055670
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4075301572
Short name T1424
Test name
Test status
Simulation time 58264370 ps
CPU time 1.41 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:13 PM PDT 24
Peak memory 203872 kb
Host smart-46851717-396b-4d13-ab38-3c065ad52371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075301572 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.4075301572
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2938163961
Short name T88
Test name
Test status
Simulation time 21903297 ps
CPU time 0.7 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203460 kb
Host smart-aa0281f3-0568-4095-8934-7a8cb2bebb44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938163961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2938163961
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3148450751
Short name T1388
Test name
Test status
Simulation time 18636246 ps
CPU time 0.7 seconds
Started May 12 12:45:02 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203404 kb
Host smart-ae6ba180-cc88-4550-b324-7777fdb81acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148450751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3148450751
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3553027294
Short name T1395
Test name
Test status
Simulation time 32969816 ps
CPU time 0.88 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203564 kb
Host smart-7ec28b82-2c21-4834-bcb2-7cdbd43c9089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553027294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3553027294
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.142005850
Short name T1407
Test name
Test status
Simulation time 105588922 ps
CPU time 2.1 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 204184 kb
Host smart-8ba11d58-ee9d-4e20-8981-efa8648ac852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142005850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.142005850
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.931775539
Short name T1389
Test name
Test status
Simulation time 271285074 ps
CPU time 1.6 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 204228 kb
Host smart-f2b75a06-547e-47cd-be44-17e416cd1e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931775539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.931775539
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2363025384
Short name T1425
Test name
Test status
Simulation time 70594397 ps
CPU time 0.77 seconds
Started May 12 12:44:51 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203640 kb
Host smart-e18e56b2-5e07-4771-aec0-c1047b571996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363025384 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2363025384
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.513793988
Short name T1455
Test name
Test status
Simulation time 197094072 ps
CPU time 0.72 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203516 kb
Host smart-effce2d7-4842-48c8-b0d8-9527c1a25a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513793988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.513793988
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.4059151902
Short name T1454
Test name
Test status
Simulation time 19025743 ps
CPU time 0.64 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203004 kb
Host smart-09130aef-907a-4672-bcf1-f5865f75c822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059151902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.4059151902
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3604583391
Short name T1420
Test name
Test status
Simulation time 29571955 ps
CPU time 1.13 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203856 kb
Host smart-cd9cb7a1-c259-4f5a-ac30-b4c1f8d76aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604583391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3604583391
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.799538986
Short name T1439
Test name
Test status
Simulation time 123786376 ps
CPU time 1.52 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:13 PM PDT 24
Peak memory 203800 kb
Host smart-d892a21a-7087-4d5a-b344-7a520404a19d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799538986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.799538986
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4168888596
Short name T1475
Test name
Test status
Simulation time 151888720 ps
CPU time 2.42 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 204148 kb
Host smart-73746cee-1c98-424b-892f-24493b460947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168888596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4168888596
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.462260468
Short name T207
Test name
Test status
Simulation time 32807182 ps
CPU time 1.07 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203636 kb
Host smart-121881c4-34fe-40eb-bd4a-8b7cffd0f9ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462260468 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.462260468
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3191957370
Short name T96
Test name
Test status
Simulation time 25791983 ps
CPU time 0.75 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203428 kb
Host smart-41e54c43-c351-40bc-8ff3-93860bc15f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191957370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3191957370
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1520908483
Short name T1432
Test name
Test status
Simulation time 72931228 ps
CPU time 0.66 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203376 kb
Host smart-aeff3e49-7a95-478d-985a-c5581eca8543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520908483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1520908483
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2425242154
Short name T1405
Test name
Test status
Simulation time 68467729 ps
CPU time 0.85 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203608 kb
Host smart-bebba792-28bb-4ac5-8a91-c3d72e1bbb9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425242154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2425242154
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3520037314
Short name T195
Test name
Test status
Simulation time 124488627 ps
CPU time 2.48 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203784 kb
Host smart-434d334d-91b8-4082-80ad-b704bdc79d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520037314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3520037314
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2739742815
Short name T1445
Test name
Test status
Simulation time 74020082 ps
CPU time 1.45 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203832 kb
Host smart-b526a27b-bff7-428a-a184-bd0e9dff05b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739742815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2739742815
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2765675757
Short name T1448
Test name
Test status
Simulation time 25555895 ps
CPU time 1.07 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203652 kb
Host smart-c2b80532-8393-48b5-8f92-3b7e99c8905b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765675757 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2765675757
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3063196537
Short name T1426
Test name
Test status
Simulation time 23506687 ps
CPU time 0.71 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203560 kb
Host smart-e3e96167-68f3-45d6-981d-1dc8f07d8f0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063196537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3063196537
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.850581624
Short name T1371
Test name
Test status
Simulation time 50683986 ps
CPU time 0.66 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203436 kb
Host smart-82889fe5-49d9-4f50-9282-cd73f411af76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850581624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.850581624
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3180244610
Short name T222
Test name
Test status
Simulation time 23270838 ps
CPU time 0.86 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203492 kb
Host smart-b1ad2849-ebea-411d-a93a-32eec55470ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180244610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3180244610
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3675525138
Short name T1473
Test name
Test status
Simulation time 437359761 ps
CPU time 1.37 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203888 kb
Host smart-9036c4e9-06f4-43c2-828b-5701863cf4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675525138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3675525138
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3668891848
Short name T1408
Test name
Test status
Simulation time 22116385 ps
CPU time 0.82 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203616 kb
Host smart-1a779844-5453-4c1f-8bf3-bad4e8fd6d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668891848 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3668891848
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.515584637
Short name T211
Test name
Test status
Simulation time 62169947 ps
CPU time 0.74 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203544 kb
Host smart-40d20302-3eee-484a-97bc-b985704f83fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515584637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.515584637
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1248615918
Short name T1441
Test name
Test status
Simulation time 16964796 ps
CPU time 0.63 seconds
Started May 12 12:45:09 PM PDT 24
Finished May 12 12:45:10 PM PDT 24
Peak memory 203444 kb
Host smart-93a1de78-e3c8-447b-815c-aa74f9b6f519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248615918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1248615918
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3748273040
Short name T95
Test name
Test status
Simulation time 256889151 ps
CPU time 1.27 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:47 PM PDT 24
Peak memory 203820 kb
Host smart-31df8fc9-097c-4e56-8c87-c8b4a0ce00d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748273040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3748273040
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3062114054
Short name T1474
Test name
Test status
Simulation time 1636649482 ps
CPU time 2.41 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203780 kb
Host smart-c2e751b9-624e-426f-9389-2948be5ace1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062114054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3062114054
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.894152674
Short name T206
Test name
Test status
Simulation time 61327430 ps
CPU time 1.41 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203828 kb
Host smart-bf8714b7-1ffe-40a4-866a-e7f7c9cd7917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894152674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.894152674
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3641295310
Short name T91
Test name
Test status
Simulation time 32137160 ps
CPU time 0.89 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 201716 kb
Host smart-f3d3ddbe-ff94-440e-ae6b-56d9a4af00e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641295310 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3641295310
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1695887525
Short name T208
Test name
Test status
Simulation time 72085213 ps
CPU time 0.73 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203796 kb
Host smart-662a4338-7c93-4ae1-9799-6942998e3eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695887525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1695887525
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2345039508
Short name T1403
Test name
Test status
Simulation time 39646296 ps
CPU time 0.68 seconds
Started May 12 12:45:02 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203812 kb
Host smart-93fa7daa-5d19-49ad-b11e-d269ecfa84eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345039508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2345039508
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1723051419
Short name T145
Test name
Test status
Simulation time 164148453 ps
CPU time 1.14 seconds
Started May 12 12:45:06 PM PDT 24
Finished May 12 12:45:08 PM PDT 24
Peak memory 203776 kb
Host smart-af320741-d93d-4aa3-bfab-35051af06252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723051419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1723051419
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.655453584
Short name T1438
Test name
Test status
Simulation time 107895987 ps
CPU time 2.92 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203800 kb
Host smart-a811c1a8-cd66-4284-bae5-af406d0e90dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655453584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.655453584
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2070909136
Short name T202
Test name
Test status
Simulation time 304494503 ps
CPU time 2.35 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203792 kb
Host smart-6c202602-230e-439d-a149-0e6d811ce6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070909136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2070909136
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3677654641
Short name T194
Test name
Test status
Simulation time 41951654 ps
CPU time 1.09 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 211732 kb
Host smart-b532200d-9371-4686-8256-2fb0a442e9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677654641 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3677654641
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1451071200
Short name T215
Test name
Test status
Simulation time 17292235 ps
CPU time 0.74 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203560 kb
Host smart-b41458ae-156d-44ff-8dd7-8597907509a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451071200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1451071200
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2183609371
Short name T1401
Test name
Test status
Simulation time 16968945 ps
CPU time 0.7 seconds
Started May 12 12:45:02 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203412 kb
Host smart-dcc70b72-2632-4c7c-88c8-b851fa0a5daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183609371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2183609371
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3821690300
Short name T1397
Test name
Test status
Simulation time 28140189 ps
CPU time 1.13 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 201924 kb
Host smart-70d7b459-5f0e-47e3-9408-76ec80787b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821690300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3821690300
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.905650386
Short name T197
Test name
Test status
Simulation time 242558650 ps
CPU time 1.64 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 204164 kb
Host smart-5125f00a-133e-4be1-959f-030b926cce69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905650386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.905650386
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1887617796
Short name T1434
Test name
Test status
Simulation time 208351440 ps
CPU time 0.79 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203668 kb
Host smart-528c09f9-0769-4782-be55-9e30f5921b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887617796 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1887617796
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3022914686
Short name T1469
Test name
Test status
Simulation time 59983570 ps
CPU time 0.79 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 201580 kb
Host smart-cf47064b-ad60-44e5-aa50-fedb62c33fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022914686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3022914686
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1564682683
Short name T1465
Test name
Test status
Simulation time 15366837 ps
CPU time 0.68 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203088 kb
Host smart-355757a2-23ff-48a2-8127-af1d206c93ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564682683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1564682683
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1944305297
Short name T1412
Test name
Test status
Simulation time 108871721 ps
CPU time 0.86 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203560 kb
Host smart-faf64b57-5224-4438-bc1f-551ea1404291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944305297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1944305297
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2441541474
Short name T1472
Test name
Test status
Simulation time 2397758321 ps
CPU time 2.6 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:18 PM PDT 24
Peak memory 203876 kb
Host smart-873f3d66-68c6-4b11-b015-761fcc6536d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441541474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2441541474
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.738625831
Short name T243
Test name
Test status
Simulation time 287510743 ps
CPU time 1.47 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203756 kb
Host smart-39088c41-248c-4c81-8ddb-90d9cd40f685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738625831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.738625831
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4196463851
Short name T1450
Test name
Test status
Simulation time 264816872 ps
CPU time 2.1 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203716 kb
Host smart-bd1cf89f-9ddb-4d18-be8d-b5dbd2a1290e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196463851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4196463851
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3561267820
Short name T217
Test name
Test status
Simulation time 1243104604 ps
CPU time 6.04 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203800 kb
Host smart-1eac4709-85cf-4954-9d2a-83c94661a6de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561267820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3561267820
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2980617849
Short name T220
Test name
Test status
Simulation time 54764376 ps
CPU time 0.76 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203580 kb
Host smart-de5a4ac4-a02b-4319-ba61-8aa2e2d00eb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980617849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2980617849
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4080104795
Short name T171
Test name
Test status
Simulation time 25148333 ps
CPU time 1.12 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203800 kb
Host smart-7ce615a6-3298-45d3-bcf1-3102af934cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080104795 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4080104795
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3892603246
Short name T216
Test name
Test status
Simulation time 25774011 ps
CPU time 0.78 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203460 kb
Host smart-8090559f-bedd-4075-b1e3-787e51b0b8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892603246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3892603246
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1030247921
Short name T1409
Test name
Test status
Simulation time 29534032 ps
CPU time 0.65 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203368 kb
Host smart-36b6ac54-2072-4c00-9444-81d643ff142c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030247921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1030247921
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1196222120
Short name T225
Test name
Test status
Simulation time 34024034 ps
CPU time 0.85 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203552 kb
Host smart-d3eaf290-a8dc-4fc5-baa1-25261703421d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196222120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1196222120
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1298352941
Short name T172
Test name
Test status
Simulation time 897308339 ps
CPU time 2.68 seconds
Started May 12 12:44:41 PM PDT 24
Finished May 12 12:44:44 PM PDT 24
Peak memory 203776 kb
Host smart-5cc2ffa5-f4db-46f3-b6c8-27d3af48e418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298352941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1298352941
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3314187964
Short name T203
Test name
Test status
Simulation time 287989011 ps
CPU time 2.18 seconds
Started May 12 12:44:45 PM PDT 24
Finished May 12 12:44:47 PM PDT 24
Peak memory 203808 kb
Host smart-53ae170a-0721-46b6-a697-9b011677b68d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314187964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3314187964
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2866404706
Short name T1377
Test name
Test status
Simulation time 18096574 ps
CPU time 0.66 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203404 kb
Host smart-0d1fef36-0a2e-4914-a5d8-5be97abd90e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866404706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2866404706
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3609398434
Short name T1459
Test name
Test status
Simulation time 47352194 ps
CPU time 0.61 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203424 kb
Host smart-0f3b92e3-aad1-4f3b-a697-c25b66b22b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609398434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3609398434
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.855038898
Short name T1410
Test name
Test status
Simulation time 16361070 ps
CPU time 0.65 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203408 kb
Host smart-113b7a8b-2d06-4065-bef8-28ed1af956cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855038898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.855038898
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2806938624
Short name T1387
Test name
Test status
Simulation time 33352667 ps
CPU time 0.62 seconds
Started May 12 12:45:07 PM PDT 24
Finished May 12 12:45:08 PM PDT 24
Peak memory 203820 kb
Host smart-ffd2ccb4-5260-4cc0-9439-f20ca9bf0e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806938624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2806938624
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2734180091
Short name T1427
Test name
Test status
Simulation time 23537393 ps
CPU time 0.64 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203420 kb
Host smart-a8803418-64ee-49c8-bfc4-f1571e08b11c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734180091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2734180091
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1769514671
Short name T1443
Test name
Test status
Simulation time 17764449 ps
CPU time 0.66 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203444 kb
Host smart-2d53c8c6-98d8-4c92-b538-f5f5313ff2dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769514671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1769514671
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.4144063466
Short name T1385
Test name
Test status
Simulation time 20845629 ps
CPU time 0.66 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203424 kb
Host smart-7d82c68d-3bb5-4144-b3dc-5d04675f68a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144063466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4144063466
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2258793107
Short name T1431
Test name
Test status
Simulation time 44821742 ps
CPU time 0.68 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203336 kb
Host smart-f830e277-54a8-4f63-846b-07f91b3d28fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258793107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2258793107
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3738099005
Short name T1372
Test name
Test status
Simulation time 18820822 ps
CPU time 0.65 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203440 kb
Host smart-58a9397e-08f1-4335-9009-c263380dd797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738099005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3738099005
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3555182160
Short name T1380
Test name
Test status
Simulation time 83251039 ps
CPU time 0.68 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203416 kb
Host smart-18a1fecc-eb84-4a47-abfd-7ac95fab2875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555182160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3555182160
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2012287195
Short name T213
Test name
Test status
Simulation time 115564490 ps
CPU time 2.17 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203704 kb
Host smart-060d57ca-04ea-4dac-90a9-3b7acb74491f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012287195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2012287195
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3747920483
Short name T1468
Test name
Test status
Simulation time 280558098 ps
CPU time 2.89 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203700 kb
Host smart-30a644f7-2c87-430d-aa1d-661903c3b17a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747920483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3747920483
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3695970541
Short name T214
Test name
Test status
Simulation time 86056677 ps
CPU time 0.75 seconds
Started May 12 12:44:40 PM PDT 24
Finished May 12 12:44:46 PM PDT 24
Peak memory 203428 kb
Host smart-203868cb-386c-471c-b5dc-735a3d4f2352
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695970541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3695970541
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.875273384
Short name T1444
Test name
Test status
Simulation time 29082601 ps
CPU time 0.84 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203660 kb
Host smart-dff94a0d-4a16-4421-945a-7f8fe339c0ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875273384 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.875273384
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2440145625
Short name T212
Test name
Test status
Simulation time 16707980 ps
CPU time 0.74 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203440 kb
Host smart-57f60dc3-ccf9-4067-bf10-0e4c7fd487ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440145625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2440145625
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.351277595
Short name T1390
Test name
Test status
Simulation time 39259445 ps
CPU time 0.7 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203380 kb
Host smart-2bb36a64-3af6-4504-9414-93f303be908e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351277595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.351277595
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1900916492
Short name T226
Test name
Test status
Simulation time 60051663 ps
CPU time 0.83 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203548 kb
Host smart-aff5fd38-9567-4b21-99de-4f9aae126436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900916492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1900916492
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1622242940
Short name T1416
Test name
Test status
Simulation time 122490939 ps
CPU time 1.79 seconds
Started May 12 12:44:42 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203716 kb
Host smart-e078ff64-72e3-46d4-bfd5-dd3d957e9c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622242940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1622242940
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4062075679
Short name T1464
Test name
Test status
Simulation time 242620167 ps
CPU time 1.43 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203708 kb
Host smart-dbb78468-018c-47de-a4fd-c3af2719e397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062075679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4062075679
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2761176785
Short name T1379
Test name
Test status
Simulation time 20132498 ps
CPU time 0.67 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203388 kb
Host smart-16646299-6d47-4ad3-9de8-833572e5b962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761176785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2761176785
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2917632399
Short name T1376
Test name
Test status
Simulation time 90377911 ps
CPU time 0.62 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:44:58 PM PDT 24
Peak memory 203296 kb
Host smart-3bbc10d7-9893-4d24-875e-6a05f80a91e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917632399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2917632399
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.4265604280
Short name T1378
Test name
Test status
Simulation time 42907701 ps
CPU time 0.62 seconds
Started May 12 12:45:17 PM PDT 24
Finished May 12 12:45:19 PM PDT 24
Peak memory 203440 kb
Host smart-dcfede32-e202-4450-8140-28cd2136ba0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265604280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4265604280
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.971680139
Short name T1406
Test name
Test status
Simulation time 46507474 ps
CPU time 0.65 seconds
Started May 12 12:45:09 PM PDT 24
Finished May 12 12:45:10 PM PDT 24
Peak memory 203440 kb
Host smart-30e8cda4-c4b4-4a24-a5a9-d2e3f5198419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971680139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.971680139
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2041890235
Short name T1399
Test name
Test status
Simulation time 15952111 ps
CPU time 0.66 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203732 kb
Host smart-08e9fa3f-33a7-43f7-bcc8-1b43f112b15d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041890235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2041890235
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.936767399
Short name T1435
Test name
Test status
Simulation time 22286933 ps
CPU time 0.67 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203396 kb
Host smart-9e98f603-726b-4fb0-8bd6-39eb7b9e1ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936767399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.936767399
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1085262108
Short name T1411
Test name
Test status
Simulation time 22111898 ps
CPU time 0.64 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203348 kb
Host smart-67e90402-65ce-4136-927a-45ecce6ea9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085262108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1085262108
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3100251127
Short name T1451
Test name
Test status
Simulation time 20049553 ps
CPU time 0.66 seconds
Started May 12 12:45:27 PM PDT 24
Finished May 12 12:45:29 PM PDT 24
Peak memory 203456 kb
Host smart-b0a5ca4f-5046-475f-86ec-58f3f7454941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100251127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3100251127
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2352539372
Short name T1402
Test name
Test status
Simulation time 43798875 ps
CPU time 0.62 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203440 kb
Host smart-985968a8-282a-4d2b-a80f-eb2454236fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352539372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2352539372
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.68285253
Short name T1370
Test name
Test status
Simulation time 44496600 ps
CPU time 0.66 seconds
Started May 12 12:45:02 PM PDT 24
Finished May 12 12:45:04 PM PDT 24
Peak memory 203420 kb
Host smart-8aeaad1f-a350-4566-bac3-b619c8870656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68285253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.68285253
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2993507058
Short name T1414
Test name
Test status
Simulation time 224160754 ps
CPU time 1.41 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203800 kb
Host smart-0c30c592-b82a-47f7-adf8-32b58874b08f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993507058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2993507058
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3148154657
Short name T1373
Test name
Test status
Simulation time 146934369 ps
CPU time 3 seconds
Started May 12 12:44:40 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203704 kb
Host smart-93e5f984-4dfc-4d8c-8790-bf8a71421b07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148154657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3148154657
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.193434172
Short name T219
Test name
Test status
Simulation time 20189207 ps
CPU time 0.72 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203512 kb
Host smart-f1f88feb-0c01-4016-8cc2-c043e2fcc8bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193434172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.193434172
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1218087956
Short name T1440
Test name
Test status
Simulation time 59302256 ps
CPU time 0.77 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203532 kb
Host smart-c63afc91-eb2c-4ada-a2c8-bcc7e78f49e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218087956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1218087956
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2880935311
Short name T1392
Test name
Test status
Simulation time 18858922 ps
CPU time 0.65 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203404 kb
Host smart-b8ed28b1-02c5-412b-bf00-123dc9323da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880935311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2880935311
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2638250251
Short name T1383
Test name
Test status
Simulation time 206493853 ps
CPU time 0.92 seconds
Started May 12 12:44:49 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203484 kb
Host smart-9cbaaeaf-b3a5-4e38-9f68-6452ec2a1600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638250251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2638250251
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.807782860
Short name T1433
Test name
Test status
Simulation time 400545507 ps
CPU time 2.21 seconds
Started May 12 12:44:45 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203760 kb
Host smart-6136275b-6518-47be-9a1d-b0f1d0f2dbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807782860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.807782860
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.34893955
Short name T198
Test name
Test status
Simulation time 97745316 ps
CPU time 2.27 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203836 kb
Host smart-475b3dd7-9efc-42b0-b2df-f3c2649c64dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.34893955
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2649266567
Short name T1449
Test name
Test status
Simulation time 16809403 ps
CPU time 0.65 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203788 kb
Host smart-f714554d-0be5-4421-9804-8f42e67f8c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649266567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2649266567
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1610701755
Short name T1460
Test name
Test status
Simulation time 30812286 ps
CPU time 0.65 seconds
Started May 12 12:45:13 PM PDT 24
Finished May 12 12:45:14 PM PDT 24
Peak memory 203436 kb
Host smart-7b448dea-2599-4b5c-8793-90e05d3b0da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610701755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1610701755
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2665734719
Short name T1457
Test name
Test status
Simulation time 30868630 ps
CPU time 0.65 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:12 PM PDT 24
Peak memory 203396 kb
Host smart-af19c146-10f5-4298-bbee-c70e8450d6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665734719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2665734719
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.175132567
Short name T1470
Test name
Test status
Simulation time 53479217 ps
CPU time 0.65 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203444 kb
Host smart-b958d7d7-fd09-4e01-bd95-bbbf241dfdce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175132567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.175132567
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1412909003
Short name T1421
Test name
Test status
Simulation time 40786364 ps
CPU time 0.64 seconds
Started May 12 12:44:50 PM PDT 24
Finished May 12 12:44:52 PM PDT 24
Peak memory 203376 kb
Host smart-e6cf15d2-3e16-470b-8b00-24b848988351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412909003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1412909003
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3999260660
Short name T1437
Test name
Test status
Simulation time 20645948 ps
CPU time 0.68 seconds
Started May 12 12:45:14 PM PDT 24
Finished May 12 12:45:16 PM PDT 24
Peak memory 203448 kb
Host smart-c94d70c5-0eaf-4759-aa52-dcb64843d180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999260660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3999260660
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2835446506
Short name T1381
Test name
Test status
Simulation time 48347927 ps
CPU time 0.69 seconds
Started May 12 12:45:25 PM PDT 24
Finished May 12 12:45:27 PM PDT 24
Peak memory 203444 kb
Host smart-6331d690-f938-40a3-8171-2390094a9f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835446506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2835446506
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1383557494
Short name T1452
Test name
Test status
Simulation time 22846169 ps
CPU time 0.69 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:02 PM PDT 24
Peak memory 203408 kb
Host smart-5eb0303e-9abb-4f84-ac93-5a4be744bb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383557494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1383557494
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1460614989
Short name T1447
Test name
Test status
Simulation time 39910986 ps
CPU time 0.63 seconds
Started May 12 12:45:03 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203392 kb
Host smart-b6c95a6a-b82c-42a8-a091-664b127a5551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460614989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1460614989
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2957154681
Short name T1391
Test name
Test status
Simulation time 68982250 ps
CPU time 0.67 seconds
Started May 12 12:45:11 PM PDT 24
Finished May 12 12:45:18 PM PDT 24
Peak memory 203440 kb
Host smart-5ad9ac37-42e7-40a5-bbfb-460bc2dd564c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957154681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2957154681
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.668360120
Short name T1430
Test name
Test status
Simulation time 213048419 ps
CPU time 0.99 seconds
Started May 12 12:45:21 PM PDT 24
Finished May 12 12:45:23 PM PDT 24
Peak memory 203608 kb
Host smart-a3a6433b-1347-4f35-997a-245d10a6dc7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668360120 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.668360120
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2032562895
Short name T1418
Test name
Test status
Simulation time 89324134 ps
CPU time 0.82 seconds
Started May 12 12:45:04 PM PDT 24
Finished May 12 12:45:06 PM PDT 24
Peak memory 203488 kb
Host smart-e19ebfc3-5874-471a-8605-8b479b26b5ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032562895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2032562895
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.962461689
Short name T1374
Test name
Test status
Simulation time 33682234 ps
CPU time 0.66 seconds
Started May 12 12:44:48 PM PDT 24
Finished May 12 12:44:50 PM PDT 24
Peak memory 203448 kb
Host smart-7c46b63c-dd49-41b7-88a1-aab129fc793b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962461689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.962461689
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4124033972
Short name T1461
Test name
Test status
Simulation time 48032279 ps
CPU time 1.09 seconds
Started May 12 12:44:54 PM PDT 24
Finished May 12 12:44:56 PM PDT 24
Peak memory 203764 kb
Host smart-3a07c3bc-3cc4-4d02-b2b8-207486b8627c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124033972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4124033972
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2453000458
Short name T1417
Test name
Test status
Simulation time 144618046 ps
CPU time 0.82 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:54 PM PDT 24
Peak memory 203572 kb
Host smart-18e70dae-958c-41c4-980c-c642308c57d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453000458 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2453000458
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1708463342
Short name T218
Test name
Test status
Simulation time 26430130 ps
CPU time 0.73 seconds
Started May 12 12:44:55 PM PDT 24
Finished May 12 12:44:57 PM PDT 24
Peak memory 203600 kb
Host smart-b6738826-1dbf-4ec1-aa98-d32be83e6864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708463342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1708463342
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1889926754
Short name T1386
Test name
Test status
Simulation time 25401228 ps
CPU time 0.64 seconds
Started May 12 12:44:57 PM PDT 24
Finished May 12 12:44:59 PM PDT 24
Peak memory 203520 kb
Host smart-1979ba70-9524-40fd-a6ff-5d9d8807aa8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889926754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1889926754
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2539910838
Short name T1404
Test name
Test status
Simulation time 179216017 ps
CPU time 0.93 seconds
Started May 12 12:44:53 PM PDT 24
Finished May 12 12:44:59 PM PDT 24
Peak memory 203508 kb
Host smart-37e7218f-c55e-44a1-bb07-29c00c52c176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539910838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2539910838
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2662371297
Short name T1462
Test name
Test status
Simulation time 270160663 ps
CPU time 1.65 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:49 PM PDT 24
Peak memory 203796 kb
Host smart-5c1c20a2-b334-494c-9d78-8d722cdcd9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662371297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2662371297
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.913181809
Short name T192
Test name
Test status
Simulation time 413099365 ps
CPU time 1.45 seconds
Started May 12 12:44:58 PM PDT 24
Finished May 12 12:45:00 PM PDT 24
Peak memory 203828 kb
Host smart-6a4091fa-150d-47e2-ac0b-c2c3159f3431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913181809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.913181809
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1849281602
Short name T1400
Test name
Test status
Simulation time 61444883 ps
CPU time 0.94 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203736 kb
Host smart-83b6497b-4d61-4e66-ab17-8e681df58c64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849281602 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1849281602
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2561659134
Short name T1384
Test name
Test status
Simulation time 25042860 ps
CPU time 0.77 seconds
Started May 12 12:45:20 PM PDT 24
Finished May 12 12:45:21 PM PDT 24
Peak memory 203464 kb
Host smart-796af96e-2a6b-4dd8-ae3c-7641b49c6530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561659134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2561659134
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2572933460
Short name T1456
Test name
Test status
Simulation time 15463110 ps
CPU time 0.59 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203264 kb
Host smart-28f5918b-cf01-46e2-8140-3c7091c465a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572933460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2572933460
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1736529442
Short name T97
Test name
Test status
Simulation time 141830651 ps
CPU time 0.89 seconds
Started May 12 12:44:56 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203628 kb
Host smart-8811ef1b-7b77-4112-8480-577a36d8784b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736529442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1736529442
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1235532965
Short name T1422
Test name
Test status
Simulation time 63387805 ps
CPU time 1.19 seconds
Started May 12 12:45:01 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203784 kb
Host smart-cc7e0302-9ce7-471b-84c3-7ace31bb2f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235532965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1235532965
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.366935763
Short name T191
Test name
Test status
Simulation time 974640666 ps
CPU time 2.54 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:03 PM PDT 24
Peak memory 203828 kb
Host smart-80254826-fdcf-49ea-87af-8f84a494578e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366935763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.366935763
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1237637474
Short name T1396
Test name
Test status
Simulation time 202943494 ps
CPU time 0.84 seconds
Started May 12 12:44:45 PM PDT 24
Finished May 12 12:44:47 PM PDT 24
Peak memory 203656 kb
Host smart-c9257b5c-69f3-45cf-89d0-77fea2baa946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237637474 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1237637474
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.804241971
Short name T1375
Test name
Test status
Simulation time 33174938 ps
CPU time 0.65 seconds
Started May 12 12:44:51 PM PDT 24
Finished May 12 12:44:53 PM PDT 24
Peak memory 203460 kb
Host smart-87ec8eb5-def1-4cce-80cd-12cee84a0849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804241971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.804241971
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.617203437
Short name T1428
Test name
Test status
Simulation time 34690778 ps
CPU time 0.65 seconds
Started May 12 12:44:59 PM PDT 24
Finished May 12 12:45:05 PM PDT 24
Peak memory 203448 kb
Host smart-4ebaec5c-70bf-441f-8add-2bec0bfeffef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617203437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.617203437
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.18569502
Short name T1382
Test name
Test status
Simulation time 100672830 ps
CPU time 1.18 seconds
Started May 12 12:45:05 PM PDT 24
Finished May 12 12:45:07 PM PDT 24
Peak memory 203864 kb
Host smart-d686acfa-4e2f-4f5d-be49-d5d1ecdc5d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outs
tanding.18569502
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2702116689
Short name T1446
Test name
Test status
Simulation time 50177896 ps
CPU time 2.35 seconds
Started May 12 12:45:07 PM PDT 24
Finished May 12 12:45:15 PM PDT 24
Peak memory 203708 kb
Host smart-5b593dee-bbdc-4e1e-9a0f-74a206b7aeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702116689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2702116689
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1688525641
Short name T188
Test name
Test status
Simulation time 136633512 ps
CPU time 2.31 seconds
Started May 12 12:44:52 PM PDT 24
Finished May 12 12:44:55 PM PDT 24
Peak memory 203760 kb
Host smart-42ba8e13-a074-4be4-ba2b-91a9d7d3be9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688525641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1688525641
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1492551954
Short name T1453
Test name
Test status
Simulation time 129863022 ps
CPU time 0.92 seconds
Started May 12 12:44:46 PM PDT 24
Finished May 12 12:44:48 PM PDT 24
Peak memory 203632 kb
Host smart-e8009902-8d73-4d7e-b24d-a8db97e11dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492551954 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1492551954
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3236448442
Short name T1436
Test name
Test status
Simulation time 28128181 ps
CPU time 0.82 seconds
Started May 12 12:44:44 PM PDT 24
Finished May 12 12:44:45 PM PDT 24
Peak memory 203424 kb
Host smart-3ba7ad8a-5bfe-4a38-9128-88fe7674936b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236448442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3236448442
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2484476059
Short name T1393
Test name
Test status
Simulation time 16172505 ps
CPU time 0.67 seconds
Started May 12 12:45:00 PM PDT 24
Finished May 12 12:45:01 PM PDT 24
Peak memory 203452 kb
Host smart-8519b11a-83cb-4310-8c67-69e7f02efdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484476059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2484476059
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2938266751
Short name T1419
Test name
Test status
Simulation time 504405209 ps
CPU time 1.92 seconds
Started May 12 12:45:19 PM PDT 24
Finished May 12 12:45:22 PM PDT 24
Peak memory 203752 kb
Host smart-85cc26f9-db38-45f6-9a27-b28072b5ddc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938266751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2938266751
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2728026122
Short name T201
Test name
Test status
Simulation time 516835208 ps
CPU time 2.55 seconds
Started May 12 12:44:47 PM PDT 24
Finished May 12 12:44:51 PM PDT 24
Peak memory 203784 kb
Host smart-148ee841-3d6c-4c25-ae19-9233dd20aa85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728026122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2728026122
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2985716125
Short name T1140
Test name
Test status
Simulation time 41321560 ps
CPU time 0.63 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 204040 kb
Host smart-420c0ab6-2c99-49f9-857d-14c8b0c14819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985716125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2985716125
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3380335480
Short name T1073
Test name
Test status
Simulation time 366950119 ps
CPU time 1.22 seconds
Started May 12 12:46:29 PM PDT 24
Finished May 12 12:46:31 PM PDT 24
Peak memory 212656 kb
Host smart-c11af7a8-c002-4998-a5ab-dca2beaa56a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380335480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3380335480
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1645616213
Short name T1256
Test name
Test status
Simulation time 325731871 ps
CPU time 15.41 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:21 PM PDT 24
Peak memory 218444 kb
Host smart-3212802e-f807-4c0b-94d4-76d925df0247
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645616213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1645616213
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2039110683
Short name T1271
Test name
Test status
Simulation time 1594716571 ps
CPU time 46.81 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:46:39 PM PDT 24
Peak memory 557096 kb
Host smart-9e6e3b3b-3b5d-4f95-96c3-986728fbc4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039110683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2039110683
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.817310789
Short name T132
Test name
Test status
Simulation time 2147655394 ps
CPU time 147.72 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:48:27 PM PDT 24
Peak memory 670524 kb
Host smart-c29d2a91-ba29-43e0-9901-ac465966df96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817310789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.817310789
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.13367461
Short name T775
Test name
Test status
Simulation time 116318352 ps
CPU time 0.96 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:23 PM PDT 24
Peak memory 204060 kb
Host smart-0d566032-d6f1-4003-9807-a0343acc2f1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.13367461
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2280560929
Short name T1185
Test name
Test status
Simulation time 628012799 ps
CPU time 3.91 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 231656 kb
Host smart-ca0b4e0d-edae-45eb-972e-ce8e81df87da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280560929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2280560929
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1038066446
Short name T104
Test name
Test status
Simulation time 12096871620 ps
CPU time 53.92 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 809144 kb
Host smart-528e78d5-ad96-4991-bbfb-706a4c8b7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038066446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1038066446
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1733958986
Short name T934
Test name
Test status
Simulation time 1912206156 ps
CPU time 11.15 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 204228 kb
Host smart-30bdd499-fb0b-4998-a638-d7a60a815a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733958986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1733958986
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3358860
Short name T1232
Test name
Test status
Simulation time 7344867756 ps
CPU time 26.38 seconds
Started May 12 12:46:08 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 283952 kb
Host smart-2786eb05-497b-4a37-bfeb-22cef230152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3358860
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2347097422
Short name T1165
Test name
Test status
Simulation time 129893972 ps
CPU time 0.66 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:25 PM PDT 24
Peak memory 204032 kb
Host smart-7743bc03-58b7-456d-a930-d4cb15b6a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347097422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2347097422
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.408210378
Short name T576
Test name
Test status
Simulation time 49214566635 ps
CPU time 139.54 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 230512 kb
Host smart-e52bcfb8-aee3-4e42-a99a-e41f121c617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408210378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.408210378
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2155873281
Short name T391
Test name
Test status
Simulation time 951373504 ps
CPU time 41.44 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:43 PM PDT 24
Peak memory 261416 kb
Host smart-ea5e52e9-0943-44b8-b89f-907a32626e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155873281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2155873281
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1623735059
Short name T168
Test name
Test status
Simulation time 181082239244 ps
CPU time 520.74 seconds
Started May 12 12:46:25 PM PDT 24
Finished May 12 12:55:07 PM PDT 24
Peak memory 1565356 kb
Host smart-85668caa-3fe3-4bb0-8480-f53407424aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623735059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1623735059
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1056990622
Short name T763
Test name
Test status
Simulation time 1417815907 ps
CPU time 11.85 seconds
Started May 12 12:46:18 PM PDT 24
Finished May 12 12:46:30 PM PDT 24
Peak memory 219668 kb
Host smart-b38e99e3-15cd-463c-aa67-d23c6fbdb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056990622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1056990622
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3126606780
Short name T646
Test name
Test status
Simulation time 679224260 ps
CPU time 3.77 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 212556 kb
Host smart-566538d0-c776-445e-9178-80c8e68c2317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126606780 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3126606780
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3343903677
Short name T927
Test name
Test status
Simulation time 10379696417 ps
CPU time 14.11 seconds
Started May 12 12:46:01 PM PDT 24
Finished May 12 12:46:16 PM PDT 24
Peak memory 278896 kb
Host smart-082f009a-545a-4b60-846c-2c7568ee21dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343903677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3343903677
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.954437043
Short name T564
Test name
Test status
Simulation time 10222201241 ps
CPU time 13.87 seconds
Started May 12 12:46:25 PM PDT 24
Finished May 12 12:46:39 PM PDT 24
Peak memory 254528 kb
Host smart-7f0b2d08-a8d8-4ccb-b5ab-4805af98a3a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954437043 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.954437043
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2929795405
Short name T922
Test name
Test status
Simulation time 437135381 ps
CPU time 2.6 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:52 PM PDT 24
Peak memory 204360 kb
Host smart-6375f7e8-b1e7-4bac-84fe-011103f676b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929795405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2929795405
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3929899767
Short name T281
Test name
Test status
Simulation time 1054037147 ps
CPU time 5.59 seconds
Started May 12 12:46:25 PM PDT 24
Finished May 12 12:46:32 PM PDT 24
Peak memory 207152 kb
Host smart-c3702a0d-e98c-475c-9839-6dd959c9dd71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929899767 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3929899767
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.452954628
Short name T478
Test name
Test status
Simulation time 16298263120 ps
CPU time 188.51 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:49:33 PM PDT 24
Peak memory 2230760 kb
Host smart-1c6e4ac7-37a2-465b-972a-227652d1524f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452954628 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.452954628
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4262608304
Short name T182
Test name
Test status
Simulation time 1639566798 ps
CPU time 32.47 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204460 kb
Host smart-d90cef1b-3698-4442-9671-fda54ef4e3a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262608304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4262608304
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3330755707
Short name T1
Test name
Test status
Simulation time 426042497 ps
CPU time 6.89 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 204268 kb
Host smart-a7ec0b54-23eb-4bca-a57c-d5d0c6a9ee25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330755707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3330755707
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1855872181
Short name T252
Test name
Test status
Simulation time 40199178133 ps
CPU time 223.63 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:50:22 PM PDT 24
Peak memory 2516152 kb
Host smart-89490957-aea8-4305-aaab-e8ce60da7aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855872181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1855872181
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.586517427
Short name T1297
Test name
Test status
Simulation time 17431308912 ps
CPU time 2958.19 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 01:35:40 PM PDT 24
Peak memory 4352400 kb
Host smart-61709a05-feb6-48c6-ba10-8c57b51ed087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586517427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.586517427
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1171558019
Short name T895
Test name
Test status
Simulation time 5081684263 ps
CPU time 6.78 seconds
Started May 12 12:45:59 PM PDT 24
Finished May 12 12:46:07 PM PDT 24
Peak memory 219192 kb
Host smart-7b5e6935-1980-4637-84b2-a2dd2ab4246f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171558019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1171558019
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3256779214
Short name T1170
Test name
Test status
Simulation time 14300405 ps
CPU time 0.62 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:13 PM PDT 24
Peak memory 203912 kb
Host smart-54b6414f-f07f-4229-99d4-a8d385848ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256779214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3256779214
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2994374423
Short name T726
Test name
Test status
Simulation time 1051968706 ps
CPU time 1.44 seconds
Started May 12 12:45:48 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 216324 kb
Host smart-e81bbe82-bf62-41c8-80a8-14813b18c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994374423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2994374423
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1672333790
Short name T165
Test name
Test status
Simulation time 654028208 ps
CPU time 14.33 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:55 PM PDT 24
Peak memory 230948 kb
Host smart-3d9244b7-b55e-4a36-889a-07a18107d6ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672333790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1672333790
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.4103149349
Short name T1295
Test name
Test status
Simulation time 5143953864 ps
CPU time 180.61 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 713452 kb
Host smart-b9044966-3082-4c38-a7c6-96c9e6e60538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103149349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.4103149349
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3404002825
Short name T420
Test name
Test status
Simulation time 2555803258 ps
CPU time 84.32 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 770880 kb
Host smart-5830db45-8949-4b1d-9a10-bd2351b086cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404002825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3404002825
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2713978440
Short name T81
Test name
Test status
Simulation time 108595474 ps
CPU time 0.85 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 204108 kb
Host smart-9b917c9f-c19d-4f9c-b3a8-a6824d751955
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713978440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2713978440
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.901279474
Short name T1196
Test name
Test status
Simulation time 752634200 ps
CPU time 9.31 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:25 PM PDT 24
Peak memory 204284 kb
Host smart-0ab53ce4-f92d-4716-a1f0-113683d99b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901279474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.901279474
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.4189214182
Short name T58
Test name
Test status
Simulation time 5913549002 ps
CPU time 73.46 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:47:24 PM PDT 24
Peak memory 864756 kb
Host smart-8f202281-b952-4aad-8c64-6a780dc11a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189214182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.4189214182
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4159080794
Short name T8
Test name
Test status
Simulation time 916081458 ps
CPU time 4.06 seconds
Started May 12 12:45:48 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 204312 kb
Host smart-f651903c-a721-4a31-8972-57483135873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159080794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4159080794
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1473191654
Short name T1131
Test name
Test status
Simulation time 1471870247 ps
CPU time 82.62 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 449664 kb
Host smart-06518ad3-eee5-434f-8833-666d739cc18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473191654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1473191654
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1734803170
Short name T968
Test name
Test status
Simulation time 1294556440 ps
CPU time 29.1 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:46 PM PDT 24
Peak memory 347868 kb
Host smart-5f82c1a7-f64d-4ba1-8bfb-9c65cc69256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734803170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1734803170
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1976582400
Short name T161
Test name
Test status
Simulation time 18039593033 ps
CPU time 787.66 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:59:19 PM PDT 24
Peak memory 2300692 kb
Host smart-4ace5d18-c51b-4adf-b08b-28331fbc21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976582400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1976582400
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2925303310
Short name T239
Test name
Test status
Simulation time 5367602410 ps
CPU time 10.99 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 220664 kb
Host smart-50bf0a3f-288d-43eb-926a-602c1b16ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925303310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2925303310
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2160748230
Short name T176
Test name
Test status
Simulation time 189719346 ps
CPU time 0.97 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 221340 kb
Host smart-502d14b5-25db-46f9-81d9-1320c1a57b45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160748230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2160748230
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.38577467
Short name T327
Test name
Test status
Simulation time 1701608021 ps
CPU time 4.38 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 212596 kb
Host smart-13835d36-9648-412b-8ec1-a29d47548b4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577467 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_bad_addr.38577467
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1465542088
Short name T427
Test name
Test status
Simulation time 10184695592 ps
CPU time 12.1 seconds
Started May 12 12:46:01 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 243248 kb
Host smart-547c986b-14bc-4f7b-8c63-16358abfd023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465542088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1465542088
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.780695299
Short name T789
Test name
Test status
Simulation time 10245172458 ps
CPU time 13.05 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 262140 kb
Host smart-7a04203f-6487-490f-a81a-6429b7babebf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780695299 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.780695299
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1377799672
Short name T23
Test name
Test status
Simulation time 1677931966 ps
CPU time 9.35 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:46:13 PM PDT 24
Peak memory 212872 kb
Host smart-7f1c15a4-7500-4a38-bffa-938af7314632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377799672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1377799672
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3140938987
Short name T26
Test name
Test status
Simulation time 1209774806 ps
CPU time 2.89 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 204348 kb
Host smart-a277824b-0922-4e9f-8dc6-b9a07ad2ea2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140938987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3140938987
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3665410106
Short name T892
Test name
Test status
Simulation time 1037567158 ps
CPU time 5.63 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 212504 kb
Host smart-5f16ee9c-3708-458f-b742-2ee11673eb90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665410106 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3665410106
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2914386200
Short name T503
Test name
Test status
Simulation time 20785359071 ps
CPU time 42.93 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:47:03 PM PDT 24
Peak memory 740924 kb
Host smart-79e9ece0-6c9a-44d1-a5c4-8788730a36e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914386200 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2914386200
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2422852418
Short name T338
Test name
Test status
Simulation time 1816091957 ps
CPU time 34.41 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:47:02 PM PDT 24
Peak memory 204300 kb
Host smart-ce17cdd3-54b6-4400-89cf-539fadc3eeca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422852418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2422852418
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.597596432
Short name T803
Test name
Test status
Simulation time 1358202869 ps
CPU time 59.99 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 205088 kb
Host smart-59a82782-f16c-479c-9be4-d07f5b7b45d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597596432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.597596432
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.150658439
Short name T278
Test name
Test status
Simulation time 11308757198 ps
CPU time 6.68 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 204344 kb
Host smart-fa6d0ed4-c33c-4d58-a223-52fdfce56407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150658439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.150658439
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.4027699470
Short name T885
Test name
Test status
Simulation time 1241923470 ps
CPU time 6.49 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:05 PM PDT 24
Peak memory 204340 kb
Host smart-6ce030b0-a755-4c86-b79c-0e8999de4f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027699470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.4027699470
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.1810374569
Short name T245
Test name
Test status
Simulation time 1855907070 ps
CPU time 5.78 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 208004 kb
Host smart-f1f746b6-220f-40a3-aef2-e56ada84c18b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810374569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.1810374569
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2109203826
Short name T1105
Test name
Test status
Simulation time 16142345 ps
CPU time 0.6 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:46:57 PM PDT 24
Peak memory 204068 kb
Host smart-475ca664-1143-40e5-a665-d353f5a48f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109203826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2109203826
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3098988866
Short name T732
Test name
Test status
Simulation time 285241741 ps
CPU time 1.49 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:46:51 PM PDT 24
Peak memory 220804 kb
Host smart-c9b878b3-a724-41b5-aab7-adae01c9876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098988866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3098988866
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3560512935
Short name T584
Test name
Test status
Simulation time 1132620614 ps
CPU time 15.33 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:47:03 PM PDT 24
Peak memory 265672 kb
Host smart-320301ec-0531-4cc3-be05-44878ba5ffc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560512935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3560512935
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1269224814
Short name T771
Test name
Test status
Simulation time 8357464626 ps
CPU time 60.12 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:47:36 PM PDT 24
Peak memory 674096 kb
Host smart-3afa38b3-e493-4536-ba22-ade67fa8deed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269224814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1269224814
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3662412664
Short name T744
Test name
Test status
Simulation time 1538597289 ps
CPU time 42.89 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:21 PM PDT 24
Peak memory 484748 kb
Host smart-d41e6799-86ec-4483-8c06-dfe4a81c802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662412664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3662412664
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1293071490
Short name T1332
Test name
Test status
Simulation time 236545425 ps
CPU time 0.97 seconds
Started May 12 12:46:50 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 204072 kb
Host smart-2043177d-cbcd-4581-bb35-990323fe0518
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293071490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1293071490
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1660903938
Short name T1126
Test name
Test status
Simulation time 9048122019 ps
CPU time 150.09 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 765464 kb
Host smart-749742ff-2d13-478f-bd6e-929c56181e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660903938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1660903938
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.684557934
Short name T676
Test name
Test status
Simulation time 13069085213 ps
CPU time 101.89 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 424108 kb
Host smart-7231df3b-bd7c-47ba-8e3a-83decbbc5a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684557934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.684557934
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.993264977
Short name T443
Test name
Test status
Simulation time 24914965 ps
CPU time 0.62 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 203992 kb
Host smart-f82e44fd-dbe8-4f53-bb00-e72d0e8712dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993264977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.993264977
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3006173961
Short name T84
Test name
Test status
Simulation time 17393865872 ps
CPU time 1723.35 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 01:15:20 PM PDT 24
Peak memory 2731680 kb
Host smart-87602b27-aa9a-491c-81f2-339a74daa59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006173961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3006173961
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1601865586
Short name T282
Test name
Test status
Simulation time 1532994975 ps
CPU time 70.87 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 325160 kb
Host smart-edfd38c9-0b51-4a75-95eb-04758479dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601865586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1601865586
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1235513545
Short name T980
Test name
Test status
Simulation time 29346828534 ps
CPU time 634.76 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:57:11 PM PDT 24
Peak memory 1073496 kb
Host smart-30ee4591-9893-44c7-ab7a-203df5526be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235513545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1235513545
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.440018068
Short name T847
Test name
Test status
Simulation time 1074435898 ps
CPU time 8.34 seconds
Started May 12 12:46:38 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 216476 kb
Host smart-7fe548cb-2460-456e-b361-8b055d57109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440018068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.440018068
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1225520589
Short name T946
Test name
Test status
Simulation time 10060204395 ps
CPU time 34.09 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:47:16 PM PDT 24
Peak memory 400172 kb
Host smart-a881b725-b5a2-4718-8747-8aba0ee60187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225520589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1225520589
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1793836947
Short name T970
Test name
Test status
Simulation time 1056507074 ps
CPU time 2.91 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:46:51 PM PDT 24
Peak memory 204232 kb
Host smart-97c0bca9-c236-42ad-9bb5-930d3fe4aae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793836947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1793836947
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1042800793
Short name T342
Test name
Test status
Simulation time 4604714250 ps
CPU time 5.51 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 212420 kb
Host smart-4813d63a-cb5c-47df-8824-6b5020626a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042800793 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1042800793
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2764414592
Short name T343
Test name
Test status
Simulation time 16146874395 ps
CPU time 27.47 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:47:02 PM PDT 24
Peak memory 599636 kb
Host smart-1782ebb3-64a1-43b8-ad9e-9bf52cda4bd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764414592 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2764414592
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1467275504
Short name T316
Test name
Test status
Simulation time 4096803201 ps
CPU time 14.98 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 204284 kb
Host smart-30c32a62-3f92-4555-b02c-ddedef012e18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467275504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1467275504
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2320666241
Short name T360
Test name
Test status
Simulation time 1265754686 ps
CPU time 25.58 seconds
Started May 12 12:46:58 PM PDT 24
Finished May 12 12:47:24 PM PDT 24
Peak memory 224928 kb
Host smart-42e798c7-459b-4045-aa34-cb92b6f5c473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320666241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2320666241
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2618532506
Short name T481
Test name
Test status
Simulation time 12982088252 ps
CPU time 26.94 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:12 PM PDT 24
Peak memory 204296 kb
Host smart-b7339701-4d9d-4df2-9691-10545f5b6466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618532506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2618532506
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2663977342
Short name T1146
Test name
Test status
Simulation time 25430025973 ps
CPU time 76.75 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 788152 kb
Host smart-e1b084f1-96b3-47cb-ad29-346f1e535ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663977342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2663977342
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.784814890
Short name T804
Test name
Test status
Simulation time 3110797240 ps
CPU time 7.77 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 212552 kb
Host smart-9688fde1-2ef2-43bc-9584-c525500c59d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784814890 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.784814890
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2549595373
Short name T1139
Test name
Test status
Simulation time 45159091 ps
CPU time 0.61 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 203984 kb
Host smart-c0f8bfda-3007-4f8f-bb93-08f671da8b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549595373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2549595373
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.284828006
Short name T1284
Test name
Test status
Simulation time 1292297892 ps
CPU time 1.62 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:07 PM PDT 24
Peak memory 212632 kb
Host smart-65127510-42bf-471c-a11c-365b54888065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284828006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.284828006
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2604774314
Short name T627
Test name
Test status
Simulation time 248278328 ps
CPU time 5.62 seconds
Started May 12 12:46:38 PM PDT 24
Finished May 12 12:46:45 PM PDT 24
Peak memory 253508 kb
Host smart-11e91551-dcdb-4f66-a022-0018f4cbad2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604774314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2604774314
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3985447943
Short name T150
Test name
Test status
Simulation time 2230682850 ps
CPU time 58.2 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 626680 kb
Host smart-2579be51-6a9f-4d5e-8164-6cc7cbb8c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985447943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3985447943
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.248649633
Short name T479
Test name
Test status
Simulation time 1713822883 ps
CPU time 116.42 seconds
Started May 12 12:46:58 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 555488 kb
Host smart-f9ca00c5-f56f-4a13-b177-d9659fea8812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248649633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.248649633
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.431700501
Short name T599
Test name
Test status
Simulation time 125432617 ps
CPU time 1.07 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:38 PM PDT 24
Peak memory 204316 kb
Host smart-e420b02b-bb9c-47de-b8ce-ecf287c8d473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431700501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.431700501
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3870384302
Short name T738
Test name
Test status
Simulation time 133733101 ps
CPU time 3.24 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 219924 kb
Host smart-54d1a4fa-dc4e-4019-b0c8-aa3bf37957b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870384302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3870384302
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3988002246
Short name T603
Test name
Test status
Simulation time 12236509901 ps
CPU time 328.51 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:52:29 PM PDT 24
Peak memory 1241072 kb
Host smart-0560901e-a753-4082-b617-54ab61bd88b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988002246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3988002246
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.558149597
Short name T518
Test name
Test status
Simulation time 2269746497 ps
CPU time 35.26 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:47:25 PM PDT 24
Peak memory 361376 kb
Host smart-f23dcac7-7d70-4f38-90ae-611e820b3c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558149597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.558149597
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.210786310
Short name T297
Test name
Test status
Simulation time 58097024 ps
CPU time 0.64 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 204032 kb
Host smart-62a1931a-ee6f-45e0-bc72-e1528e45069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210786310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.210786310
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.196682117
Short name T796
Test name
Test status
Simulation time 7554960015 ps
CPU time 100.4 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 613568 kb
Host smart-7073f863-1866-4411-b1d5-55d8f8c37888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196682117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.196682117
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.107798561
Short name T421
Test name
Test status
Simulation time 3964943632 ps
CPU time 107.55 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:48:31 PM PDT 24
Peak memory 437032 kb
Host smart-bdbe1d26-39ba-47d6-b3f8-f31cfd6dd0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107798561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.107798561
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1400472546
Short name T1171
Test name
Test status
Simulation time 15860975889 ps
CPU time 809.25 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 01:00:32 PM PDT 24
Peak memory 3261692 kb
Host smart-e191c34a-072e-4770-86c2-b842a8773927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400472546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1400472546
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3729843031
Short name T907
Test name
Test status
Simulation time 2276567338 ps
CPU time 10.14 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 212468 kb
Host smart-df2e8410-44d3-4636-a013-127b2e174a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729843031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3729843031
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1942035780
Short name T489
Test name
Test status
Simulation time 3605281612 ps
CPU time 4.03 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 204572 kb
Host smart-1bb25e5c-2dcd-47ea-b9dd-efc4332bf843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942035780 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1942035780
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1750201148
Short name T645
Test name
Test status
Simulation time 10660434301 ps
CPU time 5.29 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:46:56 PM PDT 24
Peak memory 222868 kb
Host smart-ce721bb2-6bc5-405e-a127-e57c211845be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750201148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1750201148
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2467135069
Short name T1151
Test name
Test status
Simulation time 10320370618 ps
CPU time 13.68 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 267092 kb
Host smart-4c8db9da-143c-4f3b-bd4a-37780971b3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467135069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2467135069
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3796741851
Short name T1077
Test name
Test status
Simulation time 1851713897 ps
CPU time 2.55 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:46:58 PM PDT 24
Peak memory 204284 kb
Host smart-ab8861e8-75af-4437-9ac5-6e9e3bf76487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796741851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3796741851
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2866942881
Short name T767
Test name
Test status
Simulation time 1056423191 ps
CPU time 3.67 seconds
Started May 12 12:46:51 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204276 kb
Host smart-a4eb3c56-61a9-40b2-9759-9c9593678c65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866942881 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2866942881
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.473696752
Short name T528
Test name
Test status
Simulation time 4872789158 ps
CPU time 10.02 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 204384 kb
Host smart-cc4e5eb7-3dbe-4def-a957-be5986de6c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473696752 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.473696752
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3204051754
Short name T332
Test name
Test status
Simulation time 918793083 ps
CPU time 33.99 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:47:11 PM PDT 24
Peak memory 204252 kb
Host smart-c187e4a7-1e4b-48c5-b2ff-adbbac97d74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204051754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3204051754
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2731293757
Short name T951
Test name
Test status
Simulation time 5858725291 ps
CPU time 66.09 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 207516 kb
Host smart-e2159344-b509-4562-a421-a15f4988ccc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731293757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2731293757
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1040090271
Short name T901
Test name
Test status
Simulation time 44360959684 ps
CPU time 833.77 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 01:00:43 PM PDT 24
Peak memory 6172196 kb
Host smart-5b4edb3d-354e-45d2-b592-7ec8f1c94c6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040090271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1040090271
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3959553328
Short name T765
Test name
Test status
Simulation time 23966166628 ps
CPU time 402.04 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:53:37 PM PDT 24
Peak memory 1268272 kb
Host smart-c03c80d9-4a70-460e-a3bf-10869ab2ac7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959553328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3959553328
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3870326864
Short name T621
Test name
Test status
Simulation time 4571742547 ps
CPU time 7.47 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 220544 kb
Host smart-56d2d65b-4029-4523-ae7d-4f9460ae125f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870326864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3870326864
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2109556218
Short name T896
Test name
Test status
Simulation time 18368255 ps
CPU time 0.62 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:46:58 PM PDT 24
Peak memory 203908 kb
Host smart-7282ec9e-9eb5-4aeb-a3b8-ef85a1072d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109556218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2109556218
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.749669118
Short name T52
Test name
Test status
Simulation time 188263567 ps
CPU time 1.5 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 212652 kb
Host smart-77e229ed-cc2e-4ca5-9de5-5049b2903829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749669118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.749669118
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3135920493
Short name T692
Test name
Test status
Simulation time 218180815 ps
CPU time 9.51 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 236924 kb
Host smart-e12359b8-a2b9-4873-87e1-98dff4fc7d29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135920493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3135920493
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3975364767
Short name T544
Test name
Test status
Simulation time 6046465158 ps
CPU time 51.66 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 579752 kb
Host smart-21dc8aaf-cde1-4e66-adfd-d9417076ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975364767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3975364767
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.605639637
Short name T1153
Test name
Test status
Simulation time 8024498449 ps
CPU time 62.57 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:47:39 PM PDT 24
Peak memory 723368 kb
Host smart-f7e677bd-2cca-4bce-90d8-18e3783be2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605639637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.605639637
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1200942936
Short name T1347
Test name
Test status
Simulation time 546946899 ps
CPU time 0.94 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 203980 kb
Host smart-df82babc-694e-4cee-bdc4-af9f3bc61a31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200942936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1200942936
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3675869913
Short name T232
Test name
Test status
Simulation time 387166082 ps
CPU time 5.06 seconds
Started May 12 12:47:13 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 204252 kb
Host smart-cb5f68cf-022b-493e-8fe8-1072e3ebd695
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675869913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3675869913
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.327890010
Short name T572
Test name
Test status
Simulation time 851618662 ps
CPU time 3.91 seconds
Started May 12 12:46:51 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204308 kb
Host smart-14282aa6-9852-40f5-a840-757688656152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327890010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.327890010
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.4293819719
Short name T985
Test name
Test status
Simulation time 6904296746 ps
CPU time 25.93 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:47:22 PM PDT 24
Peak memory 314544 kb
Host smart-c662753a-22a9-4ed0-889a-53cab081c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293819719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.4293819719
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3242805317
Short name T1311
Test name
Test status
Simulation time 29363317 ps
CPU time 0.67 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:03 PM PDT 24
Peak memory 203928 kb
Host smart-b5a28783-dccc-4b89-bec6-8d63d1901cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242805317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3242805317
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.163192066
Short name T1300
Test name
Test status
Simulation time 403593652 ps
CPU time 9.22 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 235944 kb
Host smart-75238950-e57c-4abc-9ba2-37e8687b0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163192066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.163192066
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.983172917
Short name T954
Test name
Test status
Simulation time 1583872569 ps
CPU time 22.73 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:47:11 PM PDT 24
Peak memory 309708 kb
Host smart-d818b5b9-9232-4b05-bf0d-c08915ed96a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983172917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.983172917
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.1738727515
Short name T1005
Test name
Test status
Simulation time 27682908710 ps
CPU time 406.36 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:53:22 PM PDT 24
Peak memory 1706912 kb
Host smart-6912338c-dc8d-4a28-8efd-4b8fbcd91849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738727515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1738727515
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1331214056
Short name T1082
Test name
Test status
Simulation time 2135372991 ps
CPU time 7.65 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:17 PM PDT 24
Peak memory 220344 kb
Host smart-256cec25-24e7-4843-9124-83aaa4ca3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331214056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1331214056
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.705193176
Short name T973
Test name
Test status
Simulation time 816249585 ps
CPU time 3.89 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 212480 kb
Host smart-42ae9b6f-f9c9-4501-b99a-16448186987c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705193176 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.705193176
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.224436117
Short name T848
Test name
Test status
Simulation time 10036330783 ps
CPU time 68.66 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 402020 kb
Host smart-91b1cecf-2268-4ed5-8d99-9c12f36f3d53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224436117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.224436117
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1658426165
Short name T1217
Test name
Test status
Simulation time 10134774742 ps
CPU time 72.21 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 528108 kb
Host smart-b9a75caa-3286-412e-852f-143ff374365b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658426165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1658426165
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.4251406573
Short name T591
Test name
Test status
Simulation time 840191269 ps
CPU time 2.59 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 204580 kb
Host smart-dd882ecb-24e7-45ae-8913-16a38cfdfd47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251406573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.4251406573
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3095866104
Short name T1090
Test name
Test status
Simulation time 1588543509 ps
CPU time 7.89 seconds
Started May 12 12:46:53 PM PDT 24
Finished May 12 12:47:01 PM PDT 24
Peak memory 220504 kb
Host smart-04d0308a-431c-41a0-807f-dd4a1d45ac76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095866104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3095866104
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.85525463
Short name T301
Test name
Test status
Simulation time 6900123797 ps
CPU time 14.68 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 204552 kb
Host smart-f4879d42-22e0-4622-84a9-86a87f853e0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85525463 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.85525463
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.699023487
Short name T486
Test name
Test status
Simulation time 2845441226 ps
CPU time 9.81 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 204344 kb
Host smart-54847f57-fdd7-474d-8112-f76dd746981f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699023487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.699023487
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3511993363
Short name T623
Test name
Test status
Simulation time 1285149300 ps
CPU time 57.98 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:44 PM PDT 24
Peak memory 205380 kb
Host smart-731fff2a-cc2d-4968-8a26-f929affe84a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511993363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3511993363
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2719589233
Short name T1093
Test name
Test status
Simulation time 53806705254 ps
CPU time 1379.34 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 01:09:56 PM PDT 24
Peak memory 8300656 kb
Host smart-8cdccbe7-267c-40e1-ac79-ea4f8bb6c129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719589233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2719589233
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1596431722
Short name T851
Test name
Test status
Simulation time 17440157880 ps
CPU time 585.07 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:56:28 PM PDT 24
Peak memory 3080600 kb
Host smart-2970e01d-c3ef-4139-9a7c-46b051d0443d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596431722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1596431722
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.426727396
Short name T511
Test name
Test status
Simulation time 1244966410 ps
CPU time 6.58 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:46:45 PM PDT 24
Peak memory 204384 kb
Host smart-b1c37161-04a2-4d39-87cf-b6088c2d789b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426727396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.426727396
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1340027147
Short name T304
Test name
Test status
Simulation time 52821632 ps
CPU time 0.62 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:10 PM PDT 24
Peak memory 204028 kb
Host smart-f3f7e3f7-c00f-4822-930f-87ce0d9941c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340027147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1340027147
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.261692887
Short name T127
Test name
Test status
Simulation time 147204380 ps
CPU time 1.41 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 212604 kb
Host smart-ac1413ea-25a3-4351-a002-2c82a9f8a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261692887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.261692887
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1277470836
Short name T467
Test name
Test status
Simulation time 666350049 ps
CPU time 5.84 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 273568 kb
Host smart-131d9a90-fe31-4372-b6e3-203fbe6241cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277470836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1277470836
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.772280502
Short name T1012
Test name
Test status
Simulation time 5140476519 ps
CPU time 80.32 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 483056 kb
Host smart-db627712-6fb7-4c11-bf53-dd7ac14895d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772280502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.772280502
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3862417966
Short name T1204
Test name
Test status
Simulation time 255480501 ps
CPU time 0.99 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 204204 kb
Host smart-9337ac0f-8acc-4903-8eb6-bb5e13179d82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862417966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3862417966
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.202978892
Short name T130
Test name
Test status
Simulation time 154625080 ps
CPU time 7.65 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 204340 kb
Host smart-d864167d-65ad-43f6-8062-70dff339957f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202978892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
202978892
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.4020728617
Short name T1142
Test name
Test status
Simulation time 12809293465 ps
CPU time 83.27 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 910040 kb
Host smart-b6d19924-ac3c-4160-b3b1-9423328707ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020728617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.4020728617
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2315745054
Short name T1035
Test name
Test status
Simulation time 895479799 ps
CPU time 6.3 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 204320 kb
Host smart-cd923b1b-7f67-4099-b086-1c45c4c6edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315745054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2315745054
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3261284489
Short name T1072
Test name
Test status
Simulation time 6473581765 ps
CPU time 36.36 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 394292 kb
Host smart-b5a8f207-660e-4e04-a518-12dab21978bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261284489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3261284489
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2328533515
Short name T1100
Test name
Test status
Simulation time 78420547 ps
CPU time 0.68 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 204000 kb
Host smart-7006a07f-f29c-416e-ae56-352e9f6e25b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328533515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2328533515
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3548058244
Short name T1252
Test name
Test status
Simulation time 777651389 ps
CPU time 9.78 seconds
Started May 12 12:46:53 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 249276 kb
Host smart-8d5ada0e-a704-4331-9fec-83b7a316f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548058244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3548058244
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3773640514
Short name T1178
Test name
Test status
Simulation time 3738262445 ps
CPU time 17.2 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:47:07 PM PDT 24
Peak memory 268416 kb
Host smart-295be18b-c154-4701-9017-62a1a6776669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773640514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3773640514
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3713945556
Short name T147
Test name
Test status
Simulation time 7950619455 ps
CPU time 149.48 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:49:06 PM PDT 24
Peak memory 599696 kb
Host smart-412c1a00-d410-46e4-85fa-8858a3918d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713945556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3713945556
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.650721408
Short name T611
Test name
Test status
Simulation time 720792865 ps
CPU time 12.18 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 219812 kb
Host smart-6ce72e7c-a2a0-43e8-97fd-6bbe2e333b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650721408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.650721408
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2618909586
Short name T701
Test name
Test status
Simulation time 1051038983 ps
CPU time 5.01 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 212896 kb
Host smart-ee983962-ac69-47ee-aaa1-adcfad7864c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618909586 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2618909586
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.234635968
Short name T1249
Test name
Test status
Simulation time 10736754539 ps
CPU time 7.56 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:13 PM PDT 24
Peak memory 236584 kb
Host smart-38f71a30-0e0b-4130-9391-ca976f7efcf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234635968 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.234635968
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.106360447
Short name T1210
Test name
Test status
Simulation time 10064232040 ps
CPU time 65.38 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:48:02 PM PDT 24
Peak memory 417176 kb
Host smart-7a28c63e-8b9f-4c10-a91a-e6258b70b64a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106360447 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.106360447
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1846830483
Short name T27
Test name
Test status
Simulation time 401998846 ps
CPU time 2.61 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:47:00 PM PDT 24
Peak memory 204216 kb
Host smart-37468a2a-756b-41fc-8c1e-635512818e4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846830483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1846830483
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3026234039
Short name T554
Test name
Test status
Simulation time 1226257496 ps
CPU time 6.13 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 215180 kb
Host smart-7a8142a7-af7f-4cb0-8596-c805293e629c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026234039 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3026234039
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1106523301
Short name T1106
Test name
Test status
Simulation time 21302021458 ps
CPU time 297.53 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:51:53 PM PDT 24
Peak memory 3790012 kb
Host smart-dddab4c7-1521-4c67-8725-c0b184ca10fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106523301 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1106523301
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.759524414
Short name T458
Test name
Test status
Simulation time 1014301260 ps
CPU time 40.67 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:47:31 PM PDT 24
Peak memory 204252 kb
Host smart-1b1804fb-0b3d-4e21-94f0-5c920dc77606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759524414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.759524414
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3124118146
Short name T752
Test name
Test status
Simulation time 488881760 ps
CPU time 20.13 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 204288 kb
Host smart-2ab36907-32ed-4d64-84d8-d24b0c2b687e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124118146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3124118146
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.581120982
Short name T938
Test name
Test status
Simulation time 47021882317 ps
CPU time 220.72 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:50:30 PM PDT 24
Peak memory 2543996 kb
Host smart-174cb264-46fd-4195-ad32-63651e18ffa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581120982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.581120982
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1714178353
Short name T1138
Test name
Test status
Simulation time 8776800805 ps
CPU time 126.33 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 1466656 kb
Host smart-cddc1f00-30e6-414b-ae95-da25d7cfddf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714178353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1714178353
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.4278151706
Short name T638
Test name
Test status
Simulation time 5443401452 ps
CPU time 7.15 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:47:00 PM PDT 24
Peak memory 212636 kb
Host smart-72349c37-26d3-4811-94fc-dbd207dbfc42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278151706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.4278151706
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.653085134
Short name T442
Test name
Test status
Simulation time 29959055 ps
CPU time 0.61 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 204076 kb
Host smart-397bfd03-e46a-4ca2-8d7a-c25d873f819f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653085134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.653085134
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3090633409
Short name T406
Test name
Test status
Simulation time 92054106 ps
CPU time 1.82 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:46:57 PM PDT 24
Peak memory 212632 kb
Host smart-fd8b764d-4cef-4860-85d6-b2dbd8c4f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090633409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3090633409
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2400645640
Short name T346
Test name
Test status
Simulation time 589614331 ps
CPU time 3.28 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 218056 kb
Host smart-cbd7b3ea-acbf-4d0c-b52c-ffdb8b01fc9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400645640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2400645640
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3616044703
Short name T1274
Test name
Test status
Simulation time 10348534326 ps
CPU time 39.88 seconds
Started May 12 12:47:06 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 447892 kb
Host smart-7f3f68ec-0f90-4767-b208-34a8cd27629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616044703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3616044703
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.444336578
Short name T288
Test name
Test status
Simulation time 8178456625 ps
CPU time 61.29 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:47:39 PM PDT 24
Peak memory 692520 kb
Host smart-09700c32-735d-4330-ae37-24afa9bde794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444336578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.444336578
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1258015871
Short name T1335
Test name
Test status
Simulation time 327384367 ps
CPU time 0.8 seconds
Started May 12 12:46:59 PM PDT 24
Finished May 12 12:47:00 PM PDT 24
Peak memory 204088 kb
Host smart-a9442123-8a60-4244-bb22-4dfe27e08039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258015871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1258015871
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1277475182
Short name T126
Test name
Test status
Simulation time 122327920 ps
CPU time 3.14 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 222544 kb
Host smart-78061bfd-918d-4cb7-bad2-263b78a9679e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277475182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1277475182
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2026909322
Short name T633
Test name
Test status
Simulation time 4550546751 ps
CPU time 160.12 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:49:38 PM PDT 24
Peak memory 793832 kb
Host smart-7851ebeb-f868-42aa-a525-c15d04464115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026909322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2026909322
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.158734597
Short name T423
Test name
Test status
Simulation time 516869049 ps
CPU time 10.36 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:08 PM PDT 24
Peak memory 204332 kb
Host smart-33db8682-de29-48bb-92f2-227772eef04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158734597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.158734597
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3900523680
Short name T755
Test name
Test status
Simulation time 6834666081 ps
CPU time 31.1 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 298772 kb
Host smart-cf79495d-fa34-4a9b-ac84-b699503f1db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900523680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3900523680
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3967154176
Short name T137
Test name
Test status
Simulation time 54004321 ps
CPU time 0.64 seconds
Started May 12 12:46:53 PM PDT 24
Finished May 12 12:46:54 PM PDT 24
Peak memory 203992 kb
Host smart-244ae5f9-aff1-4724-beb1-265ba60a9952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967154176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3967154176
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2962462329
Short name T1192
Test name
Test status
Simulation time 6062926048 ps
CPU time 30.23 seconds
Started May 12 12:46:40 PM PDT 24
Finished May 12 12:47:11 PM PDT 24
Peak memory 402540 kb
Host smart-25e21c5c-91a8-466a-a6e1-52cb6d6521b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962462329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2962462329
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.4022025802
Short name T347
Test name
Test status
Simulation time 1328177669 ps
CPU time 20.33 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:57 PM PDT 24
Peak memory 296332 kb
Host smart-b88178c8-6b51-4479-8151-5184193054b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022025802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.4022025802
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.4063632920
Short name T821
Test name
Test status
Simulation time 30309613847 ps
CPU time 166.02 seconds
Started May 12 12:46:40 PM PDT 24
Finished May 12 12:49:27 PM PDT 24
Peak memory 521036 kb
Host smart-529514e3-941b-410a-b33c-3b88c02baeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063632920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.4063632920
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3638295878
Short name T919
Test name
Test status
Simulation time 599801036 ps
CPU time 24.56 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 212484 kb
Host smart-45b5f15d-4d2c-4be9-b504-8a194aa1e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638295878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3638295878
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3776980554
Short name T1194
Test name
Test status
Simulation time 11571325485 ps
CPU time 4.73 seconds
Started May 12 12:47:04 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 212268 kb
Host smart-2baadc08-ac00-4845-a448-d479c62ed955
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776980554 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3776980554
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3692716650
Short name T388
Test name
Test status
Simulation time 10054485460 ps
CPU time 73.64 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 487512 kb
Host smart-f4ccbca6-fc32-4a43-b729-6ab5f4c29a7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692716650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3692716650
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3043305036
Short name T1080
Test name
Test status
Simulation time 10044111387 ps
CPU time 67.03 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 521080 kb
Host smart-c6d6d9d8-34f0-49e1-95f5-a24622a5eb77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043305036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3043305036
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.508757582
Short name T1183
Test name
Test status
Simulation time 1658897604 ps
CPU time 2.34 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204312 kb
Host smart-7ddf7ff6-a132-4d55-82d1-e7d21e09520d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508757582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.508757582
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2848341745
Short name T1216
Test name
Test status
Simulation time 1371537694 ps
CPU time 3.65 seconds
Started May 12 12:47:01 PM PDT 24
Finished May 12 12:47:05 PM PDT 24
Peak memory 204292 kb
Host smart-96717749-d530-4aea-b0c0-4b15df3f4b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848341745 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2848341745
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1055727952
Short name T828
Test name
Test status
Simulation time 4367621924 ps
CPU time 5.24 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:47:01 PM PDT 24
Peak memory 204432 kb
Host smart-5ce911dc-2ded-4438-a298-1c42e5906b3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055727952 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1055727952
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1473830600
Short name T872
Test name
Test status
Simulation time 3535505165 ps
CPU time 13.24 seconds
Started May 12 12:47:16 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 204248 kb
Host smart-a1369c13-8930-412d-8037-54e81e53495f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473830600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1473830600
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3552059279
Short name T656
Test name
Test status
Simulation time 1594552468 ps
CPU time 27.85 seconds
Started May 12 12:46:59 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 223620 kb
Host smart-06527e50-c50b-4f49-9245-f5649bcc949d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552059279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3552059279
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.20957776
Short name T846
Test name
Test status
Simulation time 29629846987 ps
CPU time 31.28 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 683080 kb
Host smart-2d258d28-ae87-40cc-8a27-dc4eef4e757d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20957776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stress_wr.20957776
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.601013724
Short name T708
Test name
Test status
Simulation time 5858800890 ps
CPU time 420.13 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:53:46 PM PDT 24
Peak memory 1484680 kb
Host smart-be72213b-a07d-4f13-8c8f-4f5ddc207b53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601013724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.601013724
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2217089213
Short name T1108
Test name
Test status
Simulation time 2458624419 ps
CPU time 6.94 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 210624 kb
Host smart-6cc50e51-fc89-4370-bcc5-b11adaf97be9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217089213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2217089213
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.3301292303
Short name T1026
Test name
Test status
Simulation time 2926796868 ps
CPU time 5.94 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 204380 kb
Host smart-5ffdf9fd-3d85-4d8f-a4a0-6b099a7a2be3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301292303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.3301292303
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.287068690
Short name T1081
Test name
Test status
Simulation time 18268365 ps
CPU time 0.63 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 204068 kb
Host smart-0f531d74-af1d-4cc1-b4a2-be8b3dcad92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287068690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.287068690
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3408154923
Short name T1042
Test name
Test status
Simulation time 120717435 ps
CPU time 1.68 seconds
Started May 12 12:46:59 PM PDT 24
Finished May 12 12:47:01 PM PDT 24
Peak memory 212636 kb
Host smart-492a33a3-75bd-432e-bc63-16323fc99ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408154923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3408154923
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3217115383
Short name T641
Test name
Test status
Simulation time 360007154 ps
CPU time 3.86 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 237324 kb
Host smart-ee6fd469-c931-43db-ac9a-ed5f422d3465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217115383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3217115383
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1314257973
Short name T60
Test name
Test status
Simulation time 1435787427 ps
CPU time 43 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 509000 kb
Host smart-3ead049f-c378-4163-a582-3f0f60d34be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314257973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1314257973
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2718619057
Short name T1280
Test name
Test status
Simulation time 1412721722 ps
CPU time 41.46 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 509944 kb
Host smart-7a315481-53d5-409f-a93b-f9e2cacea6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718619057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2718619057
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1023081690
Short name T43
Test name
Test status
Simulation time 109247958 ps
CPU time 0.94 seconds
Started May 12 12:47:19 PM PDT 24
Finished May 12 12:47:21 PM PDT 24
Peak memory 204004 kb
Host smart-62a78fb8-60eb-4188-a7b5-cb6ec7f6c166
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023081690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1023081690
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3905796350
Short name T858
Test name
Test status
Simulation time 1158998128 ps
CPU time 7.32 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 204220 kb
Host smart-a2beffd4-86bc-4e37-9c96-4f3525188ce8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905796350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3905796350
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1264497084
Short name T103
Test name
Test status
Simulation time 30925569032 ps
CPU time 79.76 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 1103024 kb
Host smart-289431f2-6ca7-453d-8c2c-6a1a438de269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264497084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1264497084
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2114786949
Short name T1133
Test name
Test status
Simulation time 674617284 ps
CPU time 10.77 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 204348 kb
Host smart-c42bd433-2f55-4ca8-ad05-ae296c07e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114786949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2114786949
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1332060072
Short name T75
Test name
Test status
Simulation time 5015917378 ps
CPU time 27.28 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 12:47:12 PM PDT 24
Peak memory 366460 kb
Host smart-99313f96-fc3c-412b-b530-ed01963497a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332060072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1332060072
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.84129340
Short name T141
Test name
Test status
Simulation time 108250314 ps
CPU time 0.65 seconds
Started May 12 12:46:50 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 203948 kb
Host smart-6e1059c8-fca1-434a-8464-63276e8895f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84129340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.84129340
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.4057870602
Short name T672
Test name
Test status
Simulation time 48315720330 ps
CPU time 761.72 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:59:31 PM PDT 24
Peak memory 1836652 kb
Host smart-e8dc5f4c-085d-486a-88f9-8edef133ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057870602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.4057870602
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1141568819
Short name T600
Test name
Test status
Simulation time 2820662103 ps
CPU time 66.57 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 285620 kb
Host smart-0d7bdb3d-bfbd-4bb4-8b73-72e3a2de5a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141568819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1141568819
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2530940094
Short name T121
Test name
Test status
Simulation time 53930524024 ps
CPU time 385.5 seconds
Started May 12 12:47:04 PM PDT 24
Finished May 12 12:53:30 PM PDT 24
Peak memory 1685260 kb
Host smart-8eca562a-b151-491f-98d7-53a7f6f441c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530940094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2530940094
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3545572889
Short name T779
Test name
Test status
Simulation time 2264857741 ps
CPU time 11.52 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 215188 kb
Host smart-dacc854e-92e3-4d7f-810c-026b25d16db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545572889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3545572889
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2881014534
Short name T1246
Test name
Test status
Simulation time 2884156988 ps
CPU time 3.85 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:46:51 PM PDT 24
Peak memory 204372 kb
Host smart-21c334af-08f6-4541-b56e-8b28757a1da1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881014534 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2881014534
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.339320338
Short name T1009
Test name
Test status
Simulation time 10265434444 ps
CPU time 12.49 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:47:05 PM PDT 24
Peak memory 288360 kb
Host smart-5735c71d-7e03-40a8-ade9-f7af225ff37b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339320338 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.339320338
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1215479131
Short name T1251
Test name
Test status
Simulation time 1028831824 ps
CPU time 2.87 seconds
Started May 12 12:47:00 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 204380 kb
Host smart-0f843557-f351-4e7b-8ce1-14224df2137a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215479131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1215479131
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1987831303
Short name T550
Test name
Test status
Simulation time 652538352 ps
CPU time 3.6 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 204224 kb
Host smart-2e503eee-396d-42e5-a4e0-e39f652fd399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987831303 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1987831303
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.145960465
Short name T766
Test name
Test status
Simulation time 16368661406 ps
CPU time 21.55 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:47:18 PM PDT 24
Peak memory 524456 kb
Host smart-610f65af-8626-4f8e-89b3-d44b9418225b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145960465 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.145960465
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.320616773
Short name T695
Test name
Test status
Simulation time 4410054381 ps
CPU time 9.03 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204276 kb
Host smart-b5856172-9914-4da1-8f01-7f305ce204c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320616773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.320616773
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3207440405
Short name T754
Test name
Test status
Simulation time 1847580485 ps
CPU time 26.13 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 237212 kb
Host smart-38acde9e-3dbf-46b6-92c6-8586e647f887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207440405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3207440405
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3565009912
Short name T533
Test name
Test status
Simulation time 22712049239 ps
CPU time 11.41 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 212628 kb
Host smart-1419a1d0-bb1e-4793-9f7e-630ddd763236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565009912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3565009912
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1110362077
Short name T129
Test name
Test status
Simulation time 6423394540 ps
CPU time 500.16 seconds
Started May 12 12:47:03 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 1585960 kb
Host smart-37d98de4-8e2b-4683-8afb-868c6a9682c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110362077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1110362077
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1664619125
Short name T1230
Test name
Test status
Simulation time 9424870790 ps
CPU time 6.07 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 212484 kb
Host smart-b0d6fdf5-8f62-4472-9a03-d948105856e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664619125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1664619125
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2581436657
Short name T1083
Test name
Test status
Simulation time 31075426 ps
CPU time 0.62 seconds
Started May 12 12:47:01 PM PDT 24
Finished May 12 12:47:02 PM PDT 24
Peak memory 204036 kb
Host smart-2f696304-45f4-4873-b686-345118876c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581436657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2581436657
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3816399854
Short name T399
Test name
Test status
Simulation time 195474588 ps
CPU time 1.51 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 220808 kb
Host smart-64de1142-aff2-49a4-af28-a716ff4b0d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816399854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3816399854
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.545811123
Short name T403
Test name
Test status
Simulation time 397739110 ps
CPU time 20.71 seconds
Started May 12 12:47:06 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 287016 kb
Host smart-44c1e2e7-9981-4303-a074-ac1439178b06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545811123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.545811123
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3777363125
Short name T534
Test name
Test status
Simulation time 17543740403 ps
CPU time 69.53 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 714540 kb
Host smart-fb4bc838-83f8-424d-a789-258cb48b87e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777363125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3777363125
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2103592196
Short name T405
Test name
Test status
Simulation time 1990740099 ps
CPU time 137.38 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 632852 kb
Host smart-47298243-971b-4830-8fa9-e712cc4b0563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103592196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2103592196
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.543376833
Short name T1296
Test name
Test status
Simulation time 184763698 ps
CPU time 0.85 seconds
Started May 12 12:47:06 PM PDT 24
Finished May 12 12:47:07 PM PDT 24
Peak memory 204100 kb
Host smart-1a652397-6ee4-4e7a-b78c-d0d7f6026d6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543376833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.543376833
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3525544724
Short name T157
Test name
Test status
Simulation time 157056120 ps
CPU time 8 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 230384 kb
Host smart-3727e022-6465-4ff2-b1b0-448203918957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525544724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3525544724
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3249509187
Short name T355
Test name
Test status
Simulation time 418147395 ps
CPU time 8.74 seconds
Started May 12 12:47:00 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 204244 kb
Host smart-e427d97e-857e-4d04-a05c-600bbcdc5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249509187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3249509187
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3412943920
Short name T1362
Test name
Test status
Simulation time 10791559397 ps
CPU time 31.01 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:47:22 PM PDT 24
Peak memory 322448 kb
Host smart-26c6920f-205a-44dd-a907-8049191831fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412943920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3412943920
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3098675988
Short name T688
Test name
Test status
Simulation time 52456304 ps
CPU time 0.63 seconds
Started May 12 12:47:01 PM PDT 24
Finished May 12 12:47:02 PM PDT 24
Peak memory 203960 kb
Host smart-b06ea4a8-ec4e-41f7-93e2-0783fbbd2b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098675988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3098675988
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1916177340
Short name T230
Test name
Test status
Simulation time 23299381390 ps
CPU time 89.16 seconds
Started May 12 12:46:58 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 479288 kb
Host smart-dd14c295-4a94-499e-addc-4130a0126b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916177340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1916177340
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1598977349
Short name T1205
Test name
Test status
Simulation time 3401041854 ps
CPU time 17.55 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 267864 kb
Host smart-6116d812-194d-4075-a0de-4eb29697e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598977349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1598977349
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.690796856
Short name T647
Test name
Test status
Simulation time 1688476569 ps
CPU time 16.14 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 217596 kb
Host smart-835c6f79-2eef-4056-9bac-255be95e7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690796856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.690796856
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1902027224
Short name T925
Test name
Test status
Simulation time 1783024752 ps
CPU time 2.76 seconds
Started May 12 12:47:06 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 204488 kb
Host smart-35b542f4-05be-4004-9480-5011e1e7c6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902027224 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1902027224
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3140046796
Short name T1127
Test name
Test status
Simulation time 10036755094 ps
CPU time 59.6 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 508760 kb
Host smart-82171dbf-f570-45e2-bd45-3d0f05ceacea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140046796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3140046796
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1923311108
Short name T557
Test name
Test status
Simulation time 10343017804 ps
CPU time 5.33 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:16 PM PDT 24
Peak memory 235192 kb
Host smart-e5519cbd-5673-4978-9418-7bbab9ef2288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923311108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1923311108
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.135992358
Short name T795
Test name
Test status
Simulation time 443226886 ps
CPU time 2.09 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 204284 kb
Host smart-42197e20-07be-464a-a698-4d09fe62eb81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135992358 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.135992358
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1157650178
Short name T294
Test name
Test status
Simulation time 3842259889 ps
CPU time 6.87 seconds
Started May 12 12:47:14 PM PDT 24
Finished May 12 12:47:22 PM PDT 24
Peak memory 220576 kb
Host smart-e0fe3b7f-eab5-4187-b925-6ed868da8116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157650178 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1157650178
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2975269847
Short name T386
Test name
Test status
Simulation time 13035050153 ps
CPU time 44.76 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 865372 kb
Host smart-11c747df-a05f-416a-85af-bd15300e8f56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975269847 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2975269847
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2926478870
Short name T469
Test name
Test status
Simulation time 3718979436 ps
CPU time 34.73 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 204472 kb
Host smart-39a67622-d211-4a81-b31f-d214841edf66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926478870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2926478870
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.674259082
Short name T836
Test name
Test status
Simulation time 1147672110 ps
CPU time 24.15 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 204172 kb
Host smart-23db19fc-a484-42d9-91e8-72cb5fe5a354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674259082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.674259082
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3004303060
Short name T1360
Test name
Test status
Simulation time 7691961240 ps
CPU time 8.49 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 204344 kb
Host smart-40f8fbfa-999b-4e7b-a5bb-0ed9e5b4376d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004303060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3004303060
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.4207149546
Short name T620
Test name
Test status
Simulation time 29061927128 ps
CPU time 472.23 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:55:05 PM PDT 24
Peak memory 1489372 kb
Host smart-58357129-e458-4166-a8b7-8071b1a28a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207149546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.4207149546
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.959966288
Short name T799
Test name
Test status
Simulation time 3450308280 ps
CPU time 8.1 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 220888 kb
Host smart-5ff62ae2-7ab2-4669-b680-b80bf14a77d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959966288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.959966288
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.2704950683
Short name T162
Test name
Test status
Simulation time 1052184507 ps
CPU time 7.26 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:16 PM PDT 24
Peak memory 204272 kb
Host smart-c73a22e1-b3ba-46d4-99bd-3764bb2c185a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704950683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.i2c_target_unexp_stop.2704950683
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3661402176
Short name T1259
Test name
Test status
Simulation time 17814732 ps
CPU time 0.59 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204044 kb
Host smart-8d13ddd3-886c-4e14-841b-6b98961e2a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661402176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3661402176
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1858725893
Short name T579
Test name
Test status
Simulation time 64585179 ps
CPU time 1.14 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:47:12 PM PDT 24
Peak memory 204348 kb
Host smart-d0a672d8-7a47-442c-9acc-7f4ba517bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858725893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1858725893
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3969673248
Short name T79
Test name
Test status
Simulation time 934191355 ps
CPU time 5.17 seconds
Started May 12 12:46:46 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 252196 kb
Host smart-0c6aaf5e-7fce-4b0e-9dde-556aeb2ceb2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969673248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3969673248
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3151307842
Short name T429
Test name
Test status
Simulation time 3804269333 ps
CPU time 131.02 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:49:00 PM PDT 24
Peak memory 623484 kb
Host smart-6107e356-8a0d-4fb7-afe2-9ff9abb4a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151307842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3151307842
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.862656999
Short name T585
Test name
Test status
Simulation time 1902903068 ps
CPU time 54.93 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 656016 kb
Host smart-ee47a63c-ea70-4538-8b45-b4f9e527fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862656999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.862656999
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3717722331
Short name T464
Test name
Test status
Simulation time 1016094371 ps
CPU time 1 seconds
Started May 12 12:47:19 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 204256 kb
Host smart-41166630-3bef-414d-b877-e7a3fdc5fe66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717722331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3717722331
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3969145348
Short name T376
Test name
Test status
Simulation time 163783982 ps
CPU time 3.73 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 204244 kb
Host smart-975020ab-6695-498a-904d-7717ff94e5fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969145348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3969145348
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2838295953
Short name T1363
Test name
Test status
Simulation time 7066801270 ps
CPU time 60.64 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 850616 kb
Host smart-cf2f619a-04de-451c-a130-f2d68eb4069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838295953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2838295953
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.75076228
Short name T545
Test name
Test status
Simulation time 471176845 ps
CPU time 5.96 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 204208 kb
Host smart-fa65c5de-7244-46c8-9afa-5336f09433bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75076228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.75076228
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2882641030
Short name T1163
Test name
Test status
Simulation time 4014215423 ps
CPU time 19.13 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 298576 kb
Host smart-3a53fab3-b69f-4fd9-9877-26edbaf59552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882641030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2882641030
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2353976706
Short name T1019
Test name
Test status
Simulation time 46593223 ps
CPU time 0.64 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 204020 kb
Host smart-30a69a6e-13a0-4765-a401-fc4bb79b73e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353976706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2353976706
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3716985916
Short name T845
Test name
Test status
Simulation time 299712091 ps
CPU time 5.26 seconds
Started May 12 12:46:58 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 231376 kb
Host smart-dc26e3c3-3f51-4fc1-95bf-5ee86860a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716985916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3716985916
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.642496297
Short name T508
Test name
Test status
Simulation time 4789139960 ps
CPU time 27.44 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:36 PM PDT 24
Peak memory 365124 kb
Host smart-0e615435-2f0a-4f6c-ace9-044079c9f8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642496297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.642496297
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.4011585075
Short name T1061
Test name
Test status
Simulation time 14955044245 ps
CPU time 284.6 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:51:37 PM PDT 24
Peak memory 1744264 kb
Host smart-3e6d9a46-2a14-4c65-a383-8f4a0446aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011585075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4011585075
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2688175939
Short name T867
Test name
Test status
Simulation time 4349576188 ps
CPU time 22.21 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:59 PM PDT 24
Peak memory 212536 kb
Host smart-da0f5f03-3e42-4991-8722-7ccb1e4d718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688175939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2688175939
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.4053737691
Short name T689
Test name
Test status
Simulation time 1296068874 ps
CPU time 5.56 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:11 PM PDT 24
Peak memory 220656 kb
Host smart-4f085afe-8439-4857-9b90-722e6286beb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053737691 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.4053737691
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.287021884
Short name T372
Test name
Test status
Simulation time 10200494793 ps
CPU time 11.4 seconds
Started May 12 12:46:40 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 271996 kb
Host smart-65a15cf7-d914-4cc1-b8cd-bb2b806b80af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287021884 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.287021884
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1959443935
Short name T1222
Test name
Test status
Simulation time 10135723227 ps
CPU time 46.41 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:47:31 PM PDT 24
Peak memory 372540 kb
Host smart-764708b6-7983-42ea-85c0-aa0720d93720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959443935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1959443935
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1365456430
Short name T875
Test name
Test status
Simulation time 9244969826 ps
CPU time 36.4 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 722204 kb
Host smart-781f6ab0-76af-4178-a0bc-844e18ce1eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365456430 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1365456430
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1448385021
Short name T340
Test name
Test status
Simulation time 3795152177 ps
CPU time 33.6 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 204280 kb
Host smart-71c7988a-d752-44e7-bc78-24fa32199321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448385021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1448385021
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.2498943513
Short name T814
Test name
Test status
Simulation time 49955359041 ps
CPU time 105.71 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 699840 kb
Host smart-7a5b5e1c-6929-4a18-9337-f8bc0e6a3f58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498943513 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.2498943513
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2586490985
Short name T964
Test name
Test status
Simulation time 386485038 ps
CPU time 10.06 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:16 PM PDT 24
Peak memory 204224 kb
Host smart-e0dc9225-51b1-4422-8171-648a928cd1aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586490985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2586490985
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2657098951
Short name T369
Test name
Test status
Simulation time 54131640388 ps
CPU time 1367.83 seconds
Started May 12 12:47:00 PM PDT 24
Finished May 12 01:09:49 PM PDT 24
Peak memory 8503384 kb
Host smart-47aeeed6-37a5-45e7-bf1a-d1b75ac15eb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657098951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2657098951
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3599123158
Short name T810
Test name
Test status
Simulation time 10733893889 ps
CPU time 1182.71 seconds
Started May 12 12:46:44 PM PDT 24
Finished May 12 01:06:28 PM PDT 24
Peak memory 2751772 kb
Host smart-d4b64bae-09ea-47f6-b669-2c2e84e435c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599123158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3599123158
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2506081670
Short name T485
Test name
Test status
Simulation time 1516375960 ps
CPU time 7.87 seconds
Started May 12 12:47:01 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 220632 kb
Host smart-a827a5c3-c3a3-4c50-a0ba-35e2f0238b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506081670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2506081670
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1989583580
Short name T956
Test name
Test status
Simulation time 31458340 ps
CPU time 0.62 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:47:13 PM PDT 24
Peak memory 204108 kb
Host smart-98eb5743-ec2c-445b-ac15-31d7215c730e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989583580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1989583580
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.768209528
Short name T1237
Test name
Test status
Simulation time 150908535 ps
CPU time 1.27 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 212512 kb
Host smart-870d65fb-282e-4ae6-a843-1cd693388633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768209528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.768209528
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1320012023
Short name T1056
Test name
Test status
Simulation time 856869023 ps
CPU time 5.91 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 260204 kb
Host smart-50470e79-d198-4d2b-92e1-42d6e58b86c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320012023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1320012023
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1477914028
Short name T1119
Test name
Test status
Simulation time 1186211252 ps
CPU time 72.77 seconds
Started May 12 12:47:00 PM PDT 24
Finished May 12 12:48:13 PM PDT 24
Peak memory 449560 kb
Host smart-9946eb3d-1659-4207-a101-5bac56d4825a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477914028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1477914028
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2503889684
Short name T657
Test name
Test status
Simulation time 25992541985 ps
CPU time 100.4 seconds
Started May 12 12:47:03 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 460144 kb
Host smart-3441423c-cd32-4d62-b9cd-6450ec423355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503889684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2503889684
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1852652569
Short name T864
Test name
Test status
Simulation time 308420938 ps
CPU time 1.09 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:47:01 PM PDT 24
Peak memory 204192 kb
Host smart-b71067d5-4130-48d8-bfaf-08b205fc8723
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852652569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1852652569
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.925117606
Short name T615
Test name
Test status
Simulation time 356017291 ps
CPU time 8.87 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 231848 kb
Host smart-f0433b2b-5c4e-4821-93f0-3b7ee7fd9b67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925117606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
925117606
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.4238972767
Short name T658
Test name
Test status
Simulation time 3523914276 ps
CPU time 245.33 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:51:14 PM PDT 24
Peak memory 1035068 kb
Host smart-63f9c7ba-6a83-4c21-a83c-a5692656bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238972767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.4238972767
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2119926287
Short name T1110
Test name
Test status
Simulation time 929530086 ps
CPU time 6.41 seconds
Started May 12 12:47:15 PM PDT 24
Finished May 12 12:47:22 PM PDT 24
Peak memory 204272 kb
Host smart-392edff6-5f67-4570-bc31-b374c718a6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119926287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2119926287
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1367186198
Short name T163
Test name
Test status
Simulation time 16552035926 ps
CPU time 35.05 seconds
Started May 12 12:47:25 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 403328 kb
Host smart-749b8b53-797c-4c66-bb70-74859e4ebb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367186198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1367186198
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1645439317
Short name T496
Test name
Test status
Simulation time 45172770 ps
CPU time 0.64 seconds
Started May 12 12:46:56 PM PDT 24
Finished May 12 12:46:57 PM PDT 24
Peak memory 204032 kb
Host smart-3fffd93b-d8d0-4689-9c1f-0775900c823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645439317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1645439317
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2609900329
Short name T449
Test name
Test status
Simulation time 1251434017 ps
CPU time 13.96 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:47:26 PM PDT 24
Peak memory 229732 kb
Host smart-9e576989-7242-4df5-91cf-e7a683b714e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609900329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2609900329
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3488542526
Short name T619
Test name
Test status
Simulation time 1506813522 ps
CPU time 33.44 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:44 PM PDT 24
Peak memory 399436 kb
Host smart-9222bae6-6e2a-415f-a5b3-aab6625ce9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488542526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3488542526
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.744192241
Short name T674
Test name
Test status
Simulation time 965688936 ps
CPU time 9.15 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 213508 kb
Host smart-741c6f5b-cf07-4c4e-93a5-83551389810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744192241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.744192241
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.31550848
Short name T878
Test name
Test status
Simulation time 5751885642 ps
CPU time 6.32 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:47:13 PM PDT 24
Peak memory 212580 kb
Host smart-0cc8aea0-cb55-4501-befc-5ab32be84999
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31550848 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_bad_addr.31550848
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2846068802
Short name T698
Test name
Test status
Simulation time 10383554640 ps
CPU time 6.24 seconds
Started May 12 12:47:03 PM PDT 24
Finished May 12 12:47:10 PM PDT 24
Peak memory 229144 kb
Host smart-a7dbf462-a39d-4624-9628-1d2bfe92c5c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846068802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2846068802
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.4188496271
Short name T988
Test name
Test status
Simulation time 10056555859 ps
CPU time 14.86 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:25 PM PDT 24
Peak memory 308464 kb
Host smart-0306474e-e83e-489b-9c61-52ac0e4fe271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188496271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.4188496271
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.338493393
Short name T244
Test name
Test status
Simulation time 1597899436 ps
CPU time 2.39 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 204236 kb
Host smart-818788da-a454-4e33-81e4-0bd5e73f77bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338493393 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.338493393
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.624893171
Short name T412
Test name
Test status
Simulation time 540136746 ps
CPU time 3.59 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 204288 kb
Host smart-9fd76282-10bd-469a-94c7-d23c8120f268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624893171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.624893171
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3815088430
Short name T1225
Test name
Test status
Simulation time 11533539931 ps
CPU time 9.81 seconds
Started May 12 12:46:58 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 274564 kb
Host smart-6f35bcf6-4d71-4118-a323-642421141802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815088430 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3815088430
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.4084477937
Short name T433
Test name
Test status
Simulation time 1370634806 ps
CPU time 6.62 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 204272 kb
Host smart-51105b96-dbaf-4a1b-b7fb-1935821e07e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084477937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.4084477937
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.1691904827
Short name T838
Test name
Test status
Simulation time 589558416 ps
CPU time 11.79 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 204232 kb
Host smart-ec7a8859-b641-4145-936d-720f822bfadf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691904827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.1691904827
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1949358969
Short name T1282
Test name
Test status
Simulation time 12577737380 ps
CPU time 12.48 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:10 PM PDT 24
Peak memory 204332 kb
Host smart-50bbcfa5-0f90-4ce2-85aa-622d20a5ebc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949358969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1949358969
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1641518014
Short name T826
Test name
Test status
Simulation time 10392916493 ps
CPU time 95.11 seconds
Started May 12 12:47:13 PM PDT 24
Finished May 12 12:48:49 PM PDT 24
Peak memory 574668 kb
Host smart-5f30bdfe-5cbc-4331-9fe6-7f6f90f95761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641518014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1641518014
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3618974667
Short name T1071
Test name
Test status
Simulation time 5657948494 ps
CPU time 7.39 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 218616 kb
Host smart-29f49837-7b35-4cbb-b7ca-6994b5dcb43a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618974667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3618974667
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3787122854
Short name T170
Test name
Test status
Simulation time 32066976 ps
CPU time 0.61 seconds
Started May 12 12:47:14 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 204036 kb
Host smart-96ebe718-35fe-4bc5-b4ee-4abc4d735835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787122854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3787122854
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.705636408
Short name T1242
Test name
Test status
Simulation time 111998747 ps
CPU time 1.65 seconds
Started May 12 12:47:13 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 216020 kb
Host smart-d5242864-4362-4466-801c-f48eb9599dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705636408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.705636408
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.302376069
Short name T310
Test name
Test status
Simulation time 1002952092 ps
CPU time 12.2 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 254964 kb
Host smart-89af66bd-8b47-49e2-8683-2148fbb13c35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302376069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.302376069
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.693272537
Short name T367
Test name
Test status
Simulation time 2346429498 ps
CPU time 70.87 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 763216 kb
Host smart-b9671da3-493d-45a5-b330-8f83b603173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693272537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.693272537
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.170560572
Short name T617
Test name
Test status
Simulation time 6394843766 ps
CPU time 52.53 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 585396 kb
Host smart-c0b699da-46a2-4013-8135-0cda52e0594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170560572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.170560572
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3591514490
Short name T837
Test name
Test status
Simulation time 129986098 ps
CPU time 1.05 seconds
Started May 12 12:47:07 PM PDT 24
Finished May 12 12:47:08 PM PDT 24
Peak memory 204116 kb
Host smart-e0937e84-d1ed-4097-9b34-61b425121758
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591514490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3591514490
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2553191452
Short name T1258
Test name
Test status
Simulation time 360193434 ps
CPU time 2.89 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 214656 kb
Host smart-54769974-aee1-431b-b218-8b4bf2aa754e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553191452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2553191452
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3260343620
Short name T1164
Test name
Test status
Simulation time 14526391410 ps
CPU time 91.83 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 1073384 kb
Host smart-04732fe0-3ba9-4f3b-8d77-5e5e7547f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260343620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3260343620
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3619856897
Short name T1208
Test name
Test status
Simulation time 4992704611 ps
CPU time 22.81 seconds
Started May 12 12:47:01 PM PDT 24
Finished May 12 12:47:25 PM PDT 24
Peak memory 204360 kb
Host smart-a57c4db7-b1aa-40f5-9260-44a66020f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619856897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3619856897
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1027339416
Short name T693
Test name
Test status
Simulation time 6196200605 ps
CPU time 29.25 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 348292 kb
Host smart-d98840dc-075a-4afb-9fa9-19f946ed6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027339416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1027339416
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2559361003
Short name T1346
Test name
Test status
Simulation time 102391941 ps
CPU time 0.69 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 12:47:13 PM PDT 24
Peak memory 204272 kb
Host smart-d5653bc9-0a08-4e90-a0ef-e42debb4c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559361003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2559361003
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2361477551
Short name T227
Test name
Test status
Simulation time 6725207722 ps
CPU time 68.8 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:48:26 PM PDT 24
Peak memory 235336 kb
Host smart-2b35feb8-c545-4144-b76e-df721037689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361477551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2361477551
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2026359892
Short name T609
Test name
Test status
Simulation time 4866353118 ps
CPU time 61.66 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 343120 kb
Host smart-fc248729-0823-48bf-8963-525c4469e8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026359892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2026359892
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2519871276
Short name T120
Test name
Test status
Simulation time 30868174634 ps
CPU time 384.82 seconds
Started May 12 12:46:59 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 1736492 kb
Host smart-63db4a17-35d1-4c0f-9db6-772250e92e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519871276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2519871276
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.760760409
Short name T883
Test name
Test status
Simulation time 532949271 ps
CPU time 22.56 seconds
Started May 12 12:46:54 PM PDT 24
Finished May 12 12:47:17 PM PDT 24
Peak memory 212540 kb
Host smart-430bc769-8cdb-4553-b789-922d684a4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760760409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.760760409
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3835415819
Short name T860
Test name
Test status
Simulation time 535851835 ps
CPU time 3.1 seconds
Started May 12 12:47:02 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 204344 kb
Host smart-a6a27107-fc1b-4740-9dc6-9da1d62fd336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835415819 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3835415819
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3837079338
Short name T650
Test name
Test status
Simulation time 10091675533 ps
CPU time 66.18 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 423556 kb
Host smart-f0dcaa65-d203-455c-85e4-7604f49942af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837079338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3837079338
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4104360736
Short name T598
Test name
Test status
Simulation time 384351530 ps
CPU time 2.47 seconds
Started May 12 12:46:52 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 204344 kb
Host smart-87a2832a-9b3a-4f35-b7eb-f3bac501a7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104360736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4104360736
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.633753187
Short name T880
Test name
Test status
Simulation time 1317794027 ps
CPU time 6.9 seconds
Started May 12 12:47:15 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 212496 kb
Host smart-3a8c1e25-516e-4165-8d4d-c431e2528e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633753187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.633753187
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3288622548
Short name T560
Test name
Test status
Simulation time 6595550895 ps
CPU time 66.15 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 1749872 kb
Host smart-dc67b515-6bf5-4211-9993-8540f9a7bfff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288622548 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3288622548
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3539006911
Short name T1323
Test name
Test status
Simulation time 3853491647 ps
CPU time 13.43 seconds
Started May 12 12:47:23 PM PDT 24
Finished May 12 12:47:38 PM PDT 24
Peak memory 204328 kb
Host smart-27e14d67-316b-4702-93dc-b911b6fc35a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539006911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3539006911
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3831427134
Short name T605
Test name
Test status
Simulation time 2532052077 ps
CPU time 36.99 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:10 PM PDT 24
Peak memory 204280 kb
Host smart-0f079ba5-9201-4a4d-91f7-c3d4418b7a00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831427134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3831427134
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2154665540
Short name T1174
Test name
Test status
Simulation time 21623786118 ps
CPU time 10.98 seconds
Started May 12 12:47:16 PM PDT 24
Finished May 12 12:47:28 PM PDT 24
Peak memory 204400 kb
Host smart-fd01ee1b-6bfb-4729-81a1-ba771ab028e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154665540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2154665540
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1006817611
Short name T452
Test name
Test status
Simulation time 17757532749 ps
CPU time 83.84 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 874032 kb
Host smart-83c3689b-d0dd-4e37-a683-85f8b2bc6f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006817611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1006817611
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1005895585
Short name T1043
Test name
Test status
Simulation time 1541562613 ps
CPU time 7.9 seconds
Started May 12 12:47:03 PM PDT 24
Finished May 12 12:47:12 PM PDT 24
Peak memory 220736 kb
Host smart-c47e22f2-a92b-4b9f-8cc0-e7073a3a1e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005895585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1005895585
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.2003727069
Short name T18
Test name
Test status
Simulation time 1066904272 ps
CPU time 6.87 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 204200 kb
Host smart-9c69590b-3f25-4c22-a0ef-2885d2df6e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003727069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.2003727069
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3600216104
Short name T1305
Test name
Test status
Simulation time 49684808 ps
CPU time 0.59 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:16 PM PDT 24
Peak memory 204072 kb
Host smart-02af611e-11eb-4583-b912-811592d4537f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600216104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3600216104
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1221276489
Short name T667
Test name
Test status
Simulation time 302928749 ps
CPU time 1.19 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 212676 kb
Host smart-14966f77-4335-4a94-b68a-4f3251ac4906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221276489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1221276489
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.4098304550
Short name T298
Test name
Test status
Simulation time 386062327 ps
CPU time 6 seconds
Started May 12 12:46:29 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 250756 kb
Host smart-a20cb28c-467b-41cd-9e1d-f33bc5cbb1d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098304550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.4098304550
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.514681466
Short name T835
Test name
Test status
Simulation time 1846588554 ps
CPU time 44.66 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:47:21 PM PDT 24
Peak memory 478292 kb
Host smart-b8146384-248d-477d-8229-ad5e1165e0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514681466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.514681466
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1064068116
Short name T377
Test name
Test status
Simulation time 1311573129 ps
CPU time 32.06 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 308096 kb
Host smart-dc62d9ec-a2b2-4ac7-ba23-22f4835ba784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064068116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1064068116
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3336254597
Short name T1187
Test name
Test status
Simulation time 669782401 ps
CPU time 1.21 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:02 PM PDT 24
Peak memory 204252 kb
Host smart-031f7614-d595-4d99-b5f6-2d375177addb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336254597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3336254597
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2773661979
Short name T419
Test name
Test status
Simulation time 731655035 ps
CPU time 5.49 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:46:28 PM PDT 24
Peak memory 238224 kb
Host smart-e705f94c-6271-417b-a33c-d9b0714651d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773661979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2773661979
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.4190939627
Short name T509
Test name
Test status
Simulation time 18715068609 ps
CPU time 193.2 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:49:29 PM PDT 24
Peak memory 901876 kb
Host smart-d4eabe8e-c369-42f8-922f-591588b809c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190939627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.4190939627
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3431306063
Short name T541
Test name
Test status
Simulation time 358705008 ps
CPU time 14.74 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:28 PM PDT 24
Peak memory 204384 kb
Host smart-6d8911bc-168c-4f5b-b9c9-9dd630105cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431306063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3431306063
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1336616595
Short name T484
Test name
Test status
Simulation time 12300432331 ps
CPU time 18.62 seconds
Started May 12 12:45:54 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 326412 kb
Host smart-b56a7d9c-a4d5-459c-a42a-8c427a911d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336616595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1336616595
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1659478306
Short name T595
Test name
Test status
Simulation time 273209501 ps
CPU time 0.68 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:45 PM PDT 24
Peak memory 204020 kb
Host smart-810ce149-8420-4fc5-b52a-361a7502980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659478306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1659478306
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3232124977
Short name T229
Test name
Test status
Simulation time 4342042584 ps
CPU time 46.99 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:46 PM PDT 24
Peak memory 232008 kb
Host smart-5ac3b5c7-7605-4f8d-94f3-677997612fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232124977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3232124977
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1158960479
Short name T630
Test name
Test status
Simulation time 6883595438 ps
CPU time 31.38 seconds
Started May 12 12:46:18 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 316692 kb
Host smart-8d25bfd0-7457-4d7c-b304-ec08589dc008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158960479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1158960479
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.289420696
Short name T686
Test name
Test status
Simulation time 482375126 ps
CPU time 8.14 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:32 PM PDT 24
Peak memory 213692 kb
Host smart-0d667776-b8c8-481d-b065-5ab4f48bc3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289420696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.289420696
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3603785600
Short name T177
Test name
Test status
Simulation time 125198878 ps
CPU time 0.85 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 221340 kb
Host smart-d0a2ed73-91a0-4e36-839b-a63636cc0a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603785600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3603785600
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3101045527
Short name T737
Test name
Test status
Simulation time 848690339 ps
CPU time 3.1 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:19 PM PDT 24
Peak memory 204300 kb
Host smart-69f5d1da-b2dc-4288-833b-68cef5e42ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101045527 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3101045527
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.777877354
Short name T855
Test name
Test status
Simulation time 10088712782 ps
CPU time 66.4 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:47:17 PM PDT 24
Peak memory 434528 kb
Host smart-a6920db3-7f58-4512-b306-f44c8d0ab4f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777877354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.777877354
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3780691521
Short name T757
Test name
Test status
Simulation time 10083536716 ps
CPU time 55.71 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 417656 kb
Host smart-827695ff-4571-4e39-a8af-2ddd685c468e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780691521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3780691521
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1915092147
Short name T1155
Test name
Test status
Simulation time 1386313169 ps
CPU time 2.19 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 204236 kb
Host smart-af30b235-a547-4d9f-9cf1-ed66f6f067f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915092147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1915092147
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.274979350
Short name T941
Test name
Test status
Simulation time 3535303531 ps
CPU time 4.61 seconds
Started May 12 12:45:48 PM PDT 24
Finished May 12 12:45:55 PM PDT 24
Peak memory 204264 kb
Host smart-952a767b-ba9a-4927-8ec6-0a10d79691ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274979350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.274979350
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1439128427
Short name T734
Test name
Test status
Simulation time 9895474517 ps
CPU time 161.98 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 2499704 kb
Host smart-b7ea3193-957a-43eb-9484-b1f35905b3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439128427 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1439128427
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3498516680
Short name T762
Test name
Test status
Simulation time 1071182090 ps
CPU time 18.06 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:31 PM PDT 24
Peak memory 204280 kb
Host smart-57a40fb0-56ca-4391-9d51-0d159ad46369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498516680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3498516680
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3066289837
Short name T777
Test name
Test status
Simulation time 40520336602 ps
CPU time 122.47 seconds
Started May 12 12:46:07 PM PDT 24
Finished May 12 12:48:15 PM PDT 24
Peak memory 1296648 kb
Host smart-c2049ef3-35d0-43c4-a737-256d19ff3b80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066289837 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3066289837
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2381077059
Short name T1054
Test name
Test status
Simulation time 9027113419 ps
CPU time 25.69 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 204268 kb
Host smart-921533a0-f9c1-4795-a89d-0b46322f37e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381077059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2381077059
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3670202214
Short name T397
Test name
Test status
Simulation time 27663759319 ps
CPU time 24.75 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:30 PM PDT 24
Peak memory 553052 kb
Host smart-1c47524a-ebd7-477f-88fe-78a0cbb4ed5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670202214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3670202214
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1904718161
Short name T1113
Test name
Test status
Simulation time 6844196445 ps
CPU time 424.53 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:53:19 PM PDT 24
Peak memory 1508244 kb
Host smart-ebdfd2b9-9be8-42c7-b327-c5da3440e97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904718161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1904718161
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2545758307
Short name T1023
Test name
Test status
Simulation time 2846726677 ps
CPU time 7.37 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:46:11 PM PDT 24
Peak memory 216840 kb
Host smart-d6319176-cb49-4752-8638-5e5012bacf68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545758307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2545758307
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.148573283
Short name T160
Test name
Test status
Simulation time 16717296 ps
CPU time 0.61 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 204028 kb
Host smart-169d9024-bb89-44fb-8b98-583548c1b033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148573283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.148573283
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2073433432
Short name T1207
Test name
Test status
Simulation time 186653589 ps
CPU time 1.58 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:12 PM PDT 24
Peak memory 212680 kb
Host smart-61c11087-e1a8-4d79-b491-4f12247318ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073433432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2073433432
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2047344237
Short name T283
Test name
Test status
Simulation time 254603787 ps
CPU time 6.06 seconds
Started May 12 12:47:22 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 257868 kb
Host smart-d40352df-443e-4f5e-a7a3-e9852e3b6929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047344237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2047344237
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3925296579
Short name T716
Test name
Test status
Simulation time 8007491668 ps
CPU time 70.8 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:48:35 PM PDT 24
Peak memory 682072 kb
Host smart-6487a52a-1d05-487e-a957-47d6b58711c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925296579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3925296579
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2592882047
Short name T414
Test name
Test status
Simulation time 4866966287 ps
CPU time 83.9 seconds
Started May 12 12:47:13 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 505492 kb
Host smart-d782d89e-d2b6-4b6e-a402-d34575984bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592882047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2592882047
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.344179436
Short name T413
Test name
Test status
Simulation time 127525037 ps
CPU time 1.12 seconds
Started May 12 12:47:19 PM PDT 24
Finished May 12 12:47:21 PM PDT 24
Peak memory 204372 kb
Host smart-185c4d53-843c-423b-b3ad-17e737a6775f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344179436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.344179436
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1556375877
Short name T1011
Test name
Test status
Simulation time 449156772 ps
CPU time 6.43 seconds
Started May 12 12:47:20 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 221448 kb
Host smart-3b8d7c72-9add-4d7f-adda-58a10f73becb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556375877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1556375877
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3972412880
Short name T105
Test name
Test status
Simulation time 4034486442 ps
CPU time 90.72 seconds
Started May 12 12:47:22 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 1108580 kb
Host smart-d34f2723-27cf-4a05-bee4-2c25182a1d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972412880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3972412880
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.846151315
Short name T1144
Test name
Test status
Simulation time 1066854327 ps
CPU time 4.42 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:38 PM PDT 24
Peak memory 204376 kb
Host smart-50049140-8b49-4ea4-946b-6b3de49ebf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846151315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.846151315
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3076835356
Short name T435
Test name
Test status
Simulation time 8615250373 ps
CPU time 43.91 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 12:47:54 PM PDT 24
Peak memory 480420 kb
Host smart-a30423e8-82b7-41a0-8dca-16eb4e98cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076835356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3076835356
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3206466871
Short name T822
Test name
Test status
Simulation time 17687141 ps
CPU time 0.63 seconds
Started May 12 12:47:15 PM PDT 24
Finished May 12 12:47:16 PM PDT 24
Peak memory 203900 kb
Host smart-dfc449f7-9353-49a9-acd6-b2a661722575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206466871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3206466871
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.843561232
Short name T495
Test name
Test status
Simulation time 3529676793 ps
CPU time 23.48 seconds
Started May 12 12:47:08 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 425268 kb
Host smart-ee38bb79-0969-4bc7-9674-29fdd2997a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843561232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.843561232
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.263582697
Short name T1017
Test name
Test status
Simulation time 1747258626 ps
CPU time 16.18 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 334200 kb
Host smart-029b19d5-c8e5-46f8-9a31-fbb32bae50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263582697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.263582697
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.420366041
Short name T1116
Test name
Test status
Simulation time 11766184832 ps
CPU time 612.45 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 2668808 kb
Host smart-003be8a6-3e2a-4a49-be12-1f635ead0013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420366041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.420366041
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2446050443
Short name T668
Test name
Test status
Simulation time 489434470 ps
CPU time 8.92 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 212540 kb
Host smart-87c4193c-e9d0-4bd4-955c-c19ded54ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446050443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2446050443
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1740833397
Short name T1212
Test name
Test status
Simulation time 736776304 ps
CPU time 3.65 seconds
Started May 12 12:47:16 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 204272 kb
Host smart-45d8fa61-bd90-460e-a9fb-33ee09114e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740833397 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1740833397
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3649887559
Short name T1315
Test name
Test status
Simulation time 10056551370 ps
CPU time 78.18 seconds
Started May 12 12:47:16 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 530600 kb
Host smart-cfc455b5-71fa-4448-99dd-6e9772fbae7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649887559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3649887559
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.624443454
Short name T33
Test name
Test status
Simulation time 10282150205 ps
CPU time 15.8 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 301900 kb
Host smart-c612c0bd-3200-4495-9b0d-16ff576aac00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624443454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.624443454
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2160267437
Short name T13
Test name
Test status
Simulation time 368325295 ps
CPU time 2.04 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 204244 kb
Host smart-245281f6-ba77-4810-9cf3-b41063ffa045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160267437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2160267437
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1709295114
Short name T487
Test name
Test status
Simulation time 3340516734 ps
CPU time 4.37 seconds
Started May 12 12:47:13 PM PDT 24
Finished May 12 12:47:18 PM PDT 24
Peak memory 204356 kb
Host smart-e6753790-4280-4d3e-8da0-c0c37946b04e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709295114 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1709295114
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3356413977
Short name T635
Test name
Test status
Simulation time 15994935523 ps
CPU time 327.8 seconds
Started May 12 12:47:06 PM PDT 24
Finished May 12 12:52:34 PM PDT 24
Peak memory 3957700 kb
Host smart-466a2433-2952-4012-9f57-31506ff4a333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356413977 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3356413977
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3572057064
Short name T330
Test name
Test status
Simulation time 1166817110 ps
CPU time 44.33 seconds
Started May 12 12:47:09 PM PDT 24
Finished May 12 12:47:54 PM PDT 24
Peak memory 204248 kb
Host smart-a65bf1dd-179d-4d0c-95bb-4bea367411e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572057064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3572057064
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3166274127
Short name T725
Test name
Test status
Simulation time 697794831 ps
CPU time 29.49 seconds
Started May 12 12:47:11 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 204204 kb
Host smart-32a35b4d-04bb-4251-8403-2da3cc3d9cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166274127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3166274127
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1995237665
Short name T1218
Test name
Test status
Simulation time 33059175938 ps
CPU time 358.09 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:53:09 PM PDT 24
Peak memory 3282688 kb
Host smart-2afa24d1-8c7c-4d4b-ad35-b3aeff564258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995237665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1995237665
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2208416087
Short name T318
Test name
Test status
Simulation time 16346396156 ps
CPU time 292.53 seconds
Started May 12 12:47:15 PM PDT 24
Finished May 12 12:52:08 PM PDT 24
Peak memory 1966864 kb
Host smart-7580c754-3a48-46e4-9ecc-0535aa48e5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208416087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2208416087
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1864253402
Short name T47
Test name
Test status
Simulation time 6037107868 ps
CPU time 7.76 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 212224 kb
Host smart-40525e61-190d-4c77-8122-fa655c23aebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864253402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1864253402
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1971628417
Short name T17
Test name
Test status
Simulation time 5325804377 ps
CPU time 7.35 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 218064 kb
Host smart-4cb65938-37b0-4522-8c87-786c8c5c90cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971628417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1971628417
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.18197651
Short name T1121
Test name
Test status
Simulation time 40434736 ps
CPU time 0.63 seconds
Started May 12 12:47:23 PM PDT 24
Finished May 12 12:47:24 PM PDT 24
Peak memory 204224 kb
Host smart-4708a2a6-668e-475c-affd-0ce87d6137b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18197651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.18197651
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2181004410
Short name T302
Test name
Test status
Simulation time 145589875 ps
CPU time 1.23 seconds
Started May 12 12:47:18 PM PDT 24
Finished May 12 12:47:20 PM PDT 24
Peak memory 220936 kb
Host smart-b37ea0cc-342f-4b82-a726-15e52b60c922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181004410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2181004410
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2072621655
Short name T505
Test name
Test status
Simulation time 196827633 ps
CPU time 3.7 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:36 PM PDT 24
Peak memory 241388 kb
Host smart-8d194492-664f-4ab9-8557-01d8d98e9db6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072621655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2072621655
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3120638893
Short name T504
Test name
Test status
Simulation time 1455695389 ps
CPU time 42.39 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 562616 kb
Host smart-1227180f-658a-46bf-a8c3-a48765463346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120638893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3120638893
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3333990805
Short name T472
Test name
Test status
Simulation time 1630815525 ps
CPU time 51.46 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 571972 kb
Host smart-395468f7-81e4-4570-bc52-bcf672162e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333990805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3333990805
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1276352505
Short name T979
Test name
Test status
Simulation time 400326310 ps
CPU time 0.94 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 203984 kb
Host smart-88dcfaa3-0712-4bd4-bdc6-691e6d48d130
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276352505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1276352505
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2411469248
Short name T923
Test name
Test status
Simulation time 172761069 ps
CPU time 8.47 seconds
Started May 12 12:47:10 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 204384 kb
Host smart-682d9968-b735-4c14-aa83-fddb664c33a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411469248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2411469248
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1327436156
Short name T786
Test name
Test status
Simulation time 3703675611 ps
CPU time 84.09 seconds
Started May 12 12:47:14 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 1077564 kb
Host smart-3fceb799-420b-4795-bc41-427d0357ae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327436156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1327436156
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.4028376442
Short name T975
Test name
Test status
Simulation time 432047736 ps
CPU time 5.54 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 204252 kb
Host smart-491a3ddc-824d-4d4d-8c3b-2d7fa649e366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028376442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.4028376442
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.2736840341
Short name T135
Test name
Test status
Simulation time 207007663 ps
CPU time 0.64 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 204032 kb
Host smart-3bcf31bc-f4e1-4ecd-b83d-88d7e2e38db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736840341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2736840341
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2294202372
Short name T995
Test name
Test status
Simulation time 3763829598 ps
CPU time 30.65 seconds
Started May 12 12:47:23 PM PDT 24
Finished May 12 12:47:54 PM PDT 24
Peak memory 216672 kb
Host smart-08b4db52-aea4-49a3-9e93-5d0683729690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294202372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2294202372
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2420864502
Short name T903
Test name
Test status
Simulation time 907617692 ps
CPU time 11.62 seconds
Started May 12 12:47:18 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 244268 kb
Host smart-c6aae551-2ca6-4764-955d-0b5d691aa329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420864502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2420864502
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2449704070
Short name T1261
Test name
Test status
Simulation time 166729926335 ps
CPU time 691.38 seconds
Started May 12 12:47:25 PM PDT 24
Finished May 12 12:58:57 PM PDT 24
Peak memory 2624648 kb
Host smart-943f6d0f-5082-4712-b1a4-0f0529b44b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449704070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2449704070
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.601860534
Short name T1179
Test name
Test status
Simulation time 546868064 ps
CPU time 24.47 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 212556 kb
Host smart-15927588-eb0d-4228-91a7-d93e5159f5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601860534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.601860534
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.828028886
Short name T1345
Test name
Test status
Simulation time 3522420782 ps
CPU time 4.29 seconds
Started May 12 12:47:21 PM PDT 24
Finished May 12 12:47:26 PM PDT 24
Peak memory 212560 kb
Host smart-4077325d-da01-4b56-b10f-e0353f119a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828028886 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.828028886
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1357741889
Short name T151
Test name
Test status
Simulation time 10390933868 ps
CPU time 14.01 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 276624 kb
Host smart-6fb28750-922c-4e11-a6cc-f1d770790637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357741889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1357741889
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.705331618
Short name T274
Test name
Test status
Simulation time 10464735369 ps
CPU time 14.92 seconds
Started May 12 12:47:17 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 294496 kb
Host smart-e49985fd-1e82-474f-b3a4-8474b4689947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705331618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.705331618
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.508990683
Short name T430
Test name
Test status
Simulation time 1676776603 ps
CPU time 2.75 seconds
Started May 12 12:47:15 PM PDT 24
Finished May 12 12:47:18 PM PDT 24
Peak memory 204276 kb
Host smart-45744823-93d5-4327-aa47-260e844377ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508990683 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.508990683
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2002702838
Short name T661
Test name
Test status
Simulation time 1249901028 ps
CPU time 6.02 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 214608 kb
Host smart-4e6a825c-6133-4a0e-b073-ae7a75427b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002702838 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2002702838
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1160321216
Short name T865
Test name
Test status
Simulation time 10362794890 ps
CPU time 181.33 seconds
Started May 12 12:47:25 PM PDT 24
Finished May 12 12:50:27 PM PDT 24
Peak memory 2638064 kb
Host smart-133d5be9-f9ee-4f83-b5db-cc8bb265ca85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160321216 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1160321216
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1356210290
Short name T1299
Test name
Test status
Simulation time 22528079062 ps
CPU time 45.18 seconds
Started May 12 12:47:34 PM PDT 24
Finished May 12 12:48:20 PM PDT 24
Peak memory 204324 kb
Host smart-6f3669f6-8304-4c8e-bffe-f0b905300447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356210290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1356210290
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2960278362
Short name T928
Test name
Test status
Simulation time 453361095 ps
CPU time 3.6 seconds
Started May 12 12:47:19 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 204300 kb
Host smart-bd616797-ef7d-48d0-957c-7a161fce59de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960278362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2960278362
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4285160735
Short name T521
Test name
Test status
Simulation time 15888340485 ps
CPU time 9.6 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:39 PM PDT 24
Peak memory 204364 kb
Host smart-a855c6e1-e1c9-43ea-87e3-90c8e1255457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285160735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4285160735
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.3903970448
Short name T994
Test name
Test status
Simulation time 8981384499 ps
CPU time 780.83 seconds
Started May 12 12:47:12 PM PDT 24
Finished May 12 01:00:13 PM PDT 24
Peak memory 2165280 kb
Host smart-51f7cebd-95f5-4e9d-9293-c15668549971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903970448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.3903970448
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1274514037
Short name T548
Test name
Test status
Simulation time 11141285261 ps
CPU time 6.5 seconds
Started May 12 12:47:14 PM PDT 24
Finished May 12 12:47:21 PM PDT 24
Peak memory 219036 kb
Host smart-0d609786-79ff-48c6-b62d-8dda5813b236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274514037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1274514037
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2021924026
Short name T1228
Test name
Test status
Simulation time 93798761 ps
CPU time 0.57 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:31 PM PDT 24
Peak memory 204104 kb
Host smart-ca5ae6d5-4cbd-42a9-95fb-5c9ecf29877e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021924026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2021924026
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1380716345
Short name T992
Test name
Test status
Simulation time 65792728 ps
CPU time 1.64 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 212956 kb
Host smart-0364451b-5a8e-4bab-ae8c-9a83b06f0278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380716345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1380716345
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2680854151
Short name T788
Test name
Test status
Simulation time 203359380 ps
CPU time 3.93 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:36 PM PDT 24
Peak memory 241224 kb
Host smart-23e6804c-8fe9-44fa-8c96-5ba92d80df7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680854151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.2680854151
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.133002667
Short name T675
Test name
Test status
Simulation time 7959733065 ps
CPU time 61.25 seconds
Started May 12 12:47:22 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 640004 kb
Host smart-008e5230-0a5e-4918-9f54-929e289a9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133002667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.133002667
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.44195229
Short name T1094
Test name
Test status
Simulation time 1620742040 ps
CPU time 46.09 seconds
Started May 12 12:47:25 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 590708 kb
Host smart-c3687b27-24c7-409f-bb49-ac65117fcdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44195229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.44195229
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3307692224
Short name T1089
Test name
Test status
Simulation time 114238553 ps
CPU time 1.03 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 204316 kb
Host smart-33232a97-a205-429a-b9d3-38e091978bd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307692224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3307692224
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.907916182
Short name T774
Test name
Test status
Simulation time 278796936 ps
CPU time 7.01 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 224508 kb
Host smart-2745b0e8-db8b-4dad-b5ac-90c7293bf558
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907916182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
907916182
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2522135074
Short name T792
Test name
Test status
Simulation time 3454643892 ps
CPU time 259.98 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:51:48 PM PDT 24
Peak memory 1019392 kb
Host smart-21950fe1-b9ba-48ac-8e0e-44b8101fd00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522135074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2522135074
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.1857809700
Short name T944
Test name
Test status
Simulation time 1909157059 ps
CPU time 16.92 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 204424 kb
Host smart-6bce475f-f9ba-498f-af20-cdf5ca1d537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857809700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.1857809700
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2514325096
Short name T568
Test name
Test status
Simulation time 6511647591 ps
CPU time 77.81 seconds
Started May 12 12:47:25 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 318000 kb
Host smart-d668a515-5803-47ee-a648-c1c11af109de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514325096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2514325096
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.4113622309
Short name T1338
Test name
Test status
Simulation time 19542772 ps
CPU time 0.65 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:28 PM PDT 24
Peak memory 203964 kb
Host smart-0ae44805-7e98-479d-84c2-81ca3ec11f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113622309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.4113622309
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2859991411
Short name T1145
Test name
Test status
Simulation time 50076568565 ps
CPU time 416.92 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:54:25 PM PDT 24
Peak memory 212636 kb
Host smart-7ddd0efe-88f8-45d6-a0ab-d3656f5dbbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859991411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2859991411
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3272623667
Short name T513
Test name
Test status
Simulation time 1451679516 ps
CPU time 59.13 seconds
Started May 12 12:47:22 PM PDT 24
Finished May 12 12:48:21 PM PDT 24
Peak memory 302004 kb
Host smart-7f62543d-5e57-403d-a8bd-78b2998cc7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272623667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3272623667
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3118463168
Short name T843
Test name
Test status
Simulation time 65047646344 ps
CPU time 568 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:56:56 PM PDT 24
Peak memory 1098892 kb
Host smart-84efd6f5-af7b-426f-969a-99f941bba4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118463168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3118463168
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2351635293
Short name T769
Test name
Test status
Simulation time 1702790394 ps
CPU time 21.2 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 212480 kb
Host smart-4642328a-9870-427e-a3b2-7a4f4e2574c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351635293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2351635293
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2428970391
Short name T1067
Test name
Test status
Simulation time 1161046133 ps
CPU time 5.26 seconds
Started May 12 12:47:36 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 204324 kb
Host smart-aecee5b3-6404-4e49-af22-bc825ff19eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428970391 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2428970391
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2995305648
Short name T569
Test name
Test status
Simulation time 10324514151 ps
CPU time 14.81 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 274908 kb
Host smart-96e2889b-bb75-4d37-a5ca-1f91f32f9b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995305648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2995305648
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3060737953
Short name T525
Test name
Test status
Simulation time 10042234843 ps
CPU time 86.06 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 539804 kb
Host smart-48570e2b-5ba2-425f-ad4f-e91d06fdca06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060737953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3060737953
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1977281282
Short name T745
Test name
Test status
Simulation time 1262232799 ps
CPU time 5.1 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 204860 kb
Host smart-d1d2128f-e5db-498d-829c-6eddc63fef10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977281282 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1977281282
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2564520165
Short name T918
Test name
Test status
Simulation time 15837135427 ps
CPU time 14.82 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 483648 kb
Host smart-b816e8a5-4fcc-44b7-8733-c89d01edc46b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564520165 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2564520165
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.417960989
Short name T1307
Test name
Test status
Simulation time 799532767 ps
CPU time 30.65 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:56 PM PDT 24
Peak memory 204316 kb
Host smart-e9badb24-5650-426d-8c9a-a3af925138b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417960989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.417960989
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2297347367
Short name T477
Test name
Test status
Simulation time 7640659059 ps
CPU time 60.99 seconds
Started May 12 12:47:20 PM PDT 24
Finished May 12 12:48:21 PM PDT 24
Peak memory 208060 kb
Host smart-e43af5a6-fcd1-4108-af0b-1d70e5218d6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297347367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2297347367
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3115649056
Short name T723
Test name
Test status
Simulation time 8912059579 ps
CPU time 5.86 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:38 PM PDT 24
Peak memory 204644 kb
Host smart-a06e24bb-2c8c-4d95-9973-74810b51cdaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115649056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3115649056
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2743528239
Short name T1278
Test name
Test status
Simulation time 6621021517 ps
CPU time 166.68 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:50:15 PM PDT 24
Peak memory 1726268 kb
Host smart-4f3f0e6a-6b09-4cdf-8c3d-6212371b8b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743528239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2743528239
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.640939259
Short name T587
Test name
Test status
Simulation time 3184935607 ps
CPU time 6.66 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 212472 kb
Host smart-ea5bd49c-1bfe-4a1f-9f49-73a3f9a07d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640939259 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.640939259
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3919581501
Short name T1236
Test name
Test status
Simulation time 37403824 ps
CPU time 0.62 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 204100 kb
Host smart-2e5fefb6-5d60-44d4-a9ac-7ef19bb2a99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919581501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3919581501
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1115871757
Short name T743
Test name
Test status
Simulation time 397774924 ps
CPU time 1.3 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:29 PM PDT 24
Peak memory 212604 kb
Host smart-9d95942b-def2-4df9-ac1a-193bb2c334f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115871757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1115871757
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2333547948
Short name T329
Test name
Test status
Simulation time 5422771697 ps
CPU time 17.32 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:50 PM PDT 24
Peak memory 275660 kb
Host smart-dc1652dc-6fe4-4261-b196-04a51720d5e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333547948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2333547948
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3334942397
Short name T989
Test name
Test status
Simulation time 11987875419 ps
CPU time 32.66 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:05 PM PDT 24
Peak memory 360708 kb
Host smart-3817ef54-7d0c-4ab2-bfe4-afd79183b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334942397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3334942397
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3949160766
Short name T1175
Test name
Test status
Simulation time 1124787797 ps
CPU time 34.5 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 471748 kb
Host smart-4370a5b1-da33-41c1-94f9-51ec2a7fc27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949160766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3949160766
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1541262089
Short name T1324
Test name
Test status
Simulation time 156794959 ps
CPU time 0.84 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:28 PM PDT 24
Peak memory 204016 kb
Host smart-ef9d9dcd-4a0a-43ad-ace8-4acbc298dfd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541262089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1541262089
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3716333527
Short name T740
Test name
Test status
Simulation time 540809128 ps
CPU time 6.59 seconds
Started May 12 12:47:16 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 204380 kb
Host smart-d91d3469-0f9e-430c-a174-8c722fae3ef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716333527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3716333527
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1584956286
Short name T142
Test name
Test status
Simulation time 3914396944 ps
CPU time 211.76 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:51:03 PM PDT 24
Peak memory 952440 kb
Host smart-b1094559-9a1f-4453-bbf7-09935333ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584956286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1584956286
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.3142223923
Short name T1354
Test name
Test status
Simulation time 715241682 ps
CPU time 8.34 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 204312 kb
Host smart-5f282591-9042-46b8-8d8a-c0c3c9470df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142223923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3142223923
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.240155844
Short name T1086
Test name
Test status
Simulation time 2272454864 ps
CPU time 18.43 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:50 PM PDT 24
Peak memory 277208 kb
Host smart-bb47ab74-9284-437d-8551-65f70046aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240155844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.240155844
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2063242872
Short name T1317
Test name
Test status
Simulation time 32254513 ps
CPU time 0.66 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 203908 kb
Host smart-d951130c-b2ed-46ae-9088-871fb717283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063242872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2063242872
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2812099860
Short name T73
Test name
Test status
Simulation time 12368681264 ps
CPU time 212.96 seconds
Started May 12 12:47:36 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 1374732 kb
Host smart-3f1853b1-ad3d-4d1d-a0e2-4487e5db1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812099860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2812099860
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1172634489
Short name T287
Test name
Test status
Simulation time 1081375297 ps
CPU time 50.27 seconds
Started May 12 12:47:21 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 326108 kb
Host smart-a6ed01a4-1ede-4301-a773-e449b752e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172634489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1172634489
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.840051191
Short name T886
Test name
Test status
Simulation time 818670000 ps
CPU time 19.16 seconds
Started May 12 12:47:21 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 212492 kb
Host smart-d547040c-c1aa-439f-9852-3fe2b7cba6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840051191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.840051191
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2584682499
Short name T395
Test name
Test status
Simulation time 2383039824 ps
CPU time 3.22 seconds
Started May 12 12:47:36 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204408 kb
Host smart-21641cc8-e744-4ced-80a6-7de221cbc5e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584682499 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2584682499
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.737199836
Short name T753
Test name
Test status
Simulation time 10245468820 ps
CPU time 30.88 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 361324 kb
Host smart-278afd06-4228-4174-8275-c9f30fcf8f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737199836 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.737199836
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1256471025
Short name T1000
Test name
Test status
Simulation time 10152149939 ps
CPU time 17.56 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 264224 kb
Host smart-fde73b3a-dfa1-4588-822d-5a9d72ad86c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256471025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1256471025
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1500343297
Short name T724
Test name
Test status
Simulation time 1618687005 ps
CPU time 2.59 seconds
Started May 12 12:47:23 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 204308 kb
Host smart-d68b0c92-e3d7-4430-ab13-9b517e2d4690
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500343297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1500343297
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2360086734
Short name T820
Test name
Test status
Simulation time 938261055 ps
CPU time 2.91 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 204332 kb
Host smart-0a4fcde9-bfdc-437f-9cca-ff606ad88406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360086734 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2360086734
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.4072539756
Short name T735
Test name
Test status
Simulation time 19924119271 ps
CPU time 70.13 seconds
Started May 12 12:47:35 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 1352540 kb
Host smart-395f420a-2f45-4505-992c-78bcee8d3651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072539756 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.4072539756
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3623160141
Short name T1292
Test name
Test status
Simulation time 3926415274 ps
CPU time 30.5 seconds
Started May 12 12:47:35 PM PDT 24
Finished May 12 12:48:06 PM PDT 24
Peak memory 204372 kb
Host smart-2da83499-e49c-48af-9216-60b2a9f0301d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623160141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3623160141
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1710416224
Short name T776
Test name
Test status
Simulation time 2087449930 ps
CPU time 18.6 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 217400 kb
Host smart-4f87d032-d1a6-4c15-b2ca-c26c6128a8e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710416224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1710416224
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1038013791
Short name T417
Test name
Test status
Simulation time 33072817719 ps
CPU time 169.15 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:50:23 PM PDT 24
Peak memory 2212188 kb
Host smart-065bad6f-074d-4f83-9f69-42f6eab92898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038013791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1038013791
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2973810665
Short name T669
Test name
Test status
Simulation time 3614796720 ps
CPU time 84.55 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 987700 kb
Host smart-a81036aa-664a-4c8c-8782-77445c604e85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973810665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2973810665
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2910118381
Short name T832
Test name
Test status
Simulation time 1425418157 ps
CPU time 7.69 seconds
Started May 12 12:47:24 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 212560 kb
Host smart-c720de40-d4af-4b8e-bcf6-9f80a676f309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910118381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2910118381
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.1061060192
Short name T780
Test name
Test status
Simulation time 2863885611 ps
CPU time 4.18 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 204360 kb
Host smart-70bcbdd4-324d-4d4a-90ba-f57ec59bfebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061060192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.1061060192
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.30399797
Short name T1132
Test name
Test status
Simulation time 569093302 ps
CPU time 1.44 seconds
Started May 12 12:47:35 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 212636 kb
Host smart-72fc2e64-d2a9-4e2a-a7f8-ef8c15ae7f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30399797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.30399797
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2198179608
Short name T808
Test name
Test status
Simulation time 1556985833 ps
CPU time 5.78 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:36 PM PDT 24
Peak memory 257556 kb
Host smart-5c736d2d-faf9-46a8-9700-afcb2833699c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198179608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2198179608
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.304111698
Short name T69
Test name
Test status
Simulation time 3376217417 ps
CPU time 117.61 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:49:31 PM PDT 24
Peak memory 616332 kb
Host smart-a66c0e68-6e55-4808-89b2-be2b07e92df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304111698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.304111698
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.4091194999
Short name T404
Test name
Test status
Simulation time 9495813003 ps
CPU time 86.73 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 771880 kb
Host smart-f260d032-514f-4850-923b-52ec421d2810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091194999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.4091194999
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1325736713
Short name T1025
Test name
Test status
Simulation time 99234967 ps
CPU time 0.98 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204040 kb
Host smart-49a74870-a12d-4b2a-8a4a-e9d50575f10d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325736713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1325736713
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1387904178
Short name T1075
Test name
Test status
Simulation time 113758016 ps
CPU time 6.44 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 222060 kb
Host smart-bf779bf6-d862-407d-9a00-b78642aec61d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387904178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1387904178
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3160656049
Short name T720
Test name
Test status
Simulation time 18896078746 ps
CPU time 135.53 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:49:57 PM PDT 24
Peak memory 1216420 kb
Host smart-f7135335-c0bb-4baf-aa39-506fe1cc126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160656049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3160656049
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2117513960
Short name T1203
Test name
Test status
Simulation time 1786996956 ps
CPU time 17.91 seconds
Started May 12 12:47:26 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 204276 kb
Host smart-1ef528e1-134a-4e05-b326-482f3ae1837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117513960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2117513960
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.779685869
Short name T416
Test name
Test status
Simulation time 3396993838 ps
CPU time 36.43 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:20 PM PDT 24
Peak memory 294676 kb
Host smart-0e797d91-42e8-4bb0-95d4-147db4d06e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779685869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.779685869
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3514744363
Short name T1055
Test name
Test status
Simulation time 87256687 ps
CPU time 0.67 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204000 kb
Host smart-5fe53805-ed69-4f58-91cc-dd48c5adf6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514744363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3514744363
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.601450451
Short name T1269
Test name
Test status
Simulation time 31321891128 ps
CPU time 133.96 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:49:58 PM PDT 24
Peak memory 214292 kb
Host smart-056ebef8-5936-4d1c-8fca-41948645fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601450451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.601450451
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1619234655
Short name T158
Test name
Test status
Simulation time 807151625 ps
CPU time 14.43 seconds
Started May 12 12:47:36 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 287796 kb
Host smart-856104ff-8d07-45af-a31b-9e07621191c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619234655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1619234655
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2665069189
Short name T535
Test name
Test status
Simulation time 595141001 ps
CPU time 3.11 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 204312 kb
Host smart-7de1bc29-3cfe-487d-afe6-899a7f03bdfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665069189 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2665069189
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.4094288232
Short name T254
Test name
Test status
Simulation time 10044313439 ps
CPU time 13.32 seconds
Started May 12 12:47:27 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 267424 kb
Host smart-810d0748-fa16-4082-b642-739803531ed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094288232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.4094288232
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.403597229
Short name T1206
Test name
Test status
Simulation time 10069692941 ps
CPU time 26.75 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 350204 kb
Host smart-4592560d-5e8e-4205-bd37-52669f2faf35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403597229 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.403597229
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4038749083
Short name T1020
Test name
Test status
Simulation time 401622143 ps
CPU time 2.7 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 204304 kb
Host smart-5737d126-7f3a-48bf-9d52-4bc71b788f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038749083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4038749083
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1561267871
Short name T538
Test name
Test status
Simulation time 1240496406 ps
CPU time 7.03 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 220500 kb
Host smart-93811e03-ca1d-4f45-a77b-4f66106abffb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561267871 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1561267871
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.636447483
Short name T751
Test name
Test status
Simulation time 19497361231 ps
CPU time 325.33 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:53:00 PM PDT 24
Peak memory 3173516 kb
Host smart-ae7ca594-b6b1-4276-82c8-ca5572203bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636447483 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.636447483
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3377984721
Short name T1368
Test name
Test status
Simulation time 8108548248 ps
CPU time 13.58 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 204328 kb
Host smart-9ae5112e-c90d-4f26-9731-48f2af088ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377984721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3377984721
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3115129714
Short name T1314
Test name
Test status
Simulation time 1356008483 ps
CPU time 6.08 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204264 kb
Host smart-4c447743-346e-4951-98f6-898897207474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115129714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3115129714
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3149727138
Short name T742
Test name
Test status
Simulation time 12125755810 ps
CPU time 12.54 seconds
Started May 12 12:47:34 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 204296 kb
Host smart-032c613f-5133-4492-a0fb-0aba691debb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149727138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3149727138
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2175979093
Short name T871
Test name
Test status
Simulation time 32023948719 ps
CPU time 2446.33 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 01:28:21 PM PDT 24
Peak memory 3755320 kb
Host smart-603aed82-aa0d-41f5-9f9a-ff158ce93ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175979093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2175979093
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2651432869
Short name T681
Test name
Test status
Simulation time 2766847054 ps
CPU time 7.16 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 218796 kb
Host smart-54cca5b9-896e-4d87-9b6b-fe746120aa7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651432869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2651432869
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3944556481
Short name T984
Test name
Test status
Simulation time 18266327 ps
CPU time 0.63 seconds
Started May 12 12:47:58 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 204308 kb
Host smart-a6387e1a-beab-4939-b0a8-c53a8a34a75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944556481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3944556481
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3853615908
Short name T546
Test name
Test status
Simulation time 255284301 ps
CPU time 1.4 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 212628 kb
Host smart-7555319b-1c29-44f5-b465-85c642ad1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853615908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3853615908
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3071471474
Short name T733
Test name
Test status
Simulation time 283789483 ps
CPU time 6.48 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 265096 kb
Host smart-57340089-319b-4a29-8e99-a0f0d88458e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071471474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3071471474
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3408560999
Short name T1033
Test name
Test status
Simulation time 1501920551 ps
CPU time 42.43 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 532736 kb
Host smart-431ee12b-196b-4533-8096-48cb004f48e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408560999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3408560999
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2919527716
Short name T401
Test name
Test status
Simulation time 1382879657 ps
CPU time 41.03 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:25 PM PDT 24
Peak memory 485536 kb
Host smart-99b356d0-1e93-4cb4-9e1e-b4daca3327de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919527716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2919527716
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2665497234
Short name T778
Test name
Test status
Simulation time 650479300 ps
CPU time 1.17 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 204228 kb
Host smart-09e06cec-2641-42b9-bded-a4c977b4dbc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665497234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2665497234
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2047211210
Short name T185
Test name
Test status
Simulation time 177100179 ps
CPU time 3.89 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 226432 kb
Host smart-03126d01-aee8-4947-866c-3ab4b5a966fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047211210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2047211210
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3957195436
Short name T169
Test name
Test status
Simulation time 14595519558 ps
CPU time 117.07 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:49:38 PM PDT 24
Peak memory 1113916 kb
Host smart-eefad3a4-0c8d-4c01-9e6a-9e3a25eff3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957195436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3957195436
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2527114832
Short name T1199
Test name
Test status
Simulation time 220410349 ps
CPU time 8.06 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 204276 kb
Host smart-45a085ed-3d81-4005-aa73-5e561e0a69ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527114832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2527114832
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3348395873
Short name T1037
Test name
Test status
Simulation time 8731234014 ps
CPU time 27.41 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:48:00 PM PDT 24
Peak memory 342392 kb
Host smart-9679cab2-27cf-43a7-9297-7e6dc95fcfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348395873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3348395873
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3689470439
Short name T408
Test name
Test status
Simulation time 33947919 ps
CPU time 0.67 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 204084 kb
Host smart-04aa1598-113f-4aeb-a8d7-036817f5cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689470439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3689470439
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.538139331
Short name T552
Test name
Test status
Simulation time 2927735167 ps
CPU time 42.8 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:48:25 PM PDT 24
Peak memory 267124 kb
Host smart-025134a6-5f2b-4695-a4de-f8a889ef2a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538139331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.538139331
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3986976149
Short name T876
Test name
Test status
Simulation time 1220996159 ps
CPU time 63.49 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 354736 kb
Host smart-ac0f16f8-9a36-4449-affb-e96bdee13d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986976149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3986976149
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2218695886
Short name T1365
Test name
Test status
Simulation time 9994327477 ps
CPU time 851.43 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 01:01:54 PM PDT 24
Peak memory 1608196 kb
Host smart-c7dfed52-4b91-4e53-98e9-b898b70b29d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218695886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2218695886
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.577652958
Short name T759
Test name
Test status
Simulation time 4754950070 ps
CPU time 10.31 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 220872 kb
Host smart-114c749f-09c2-4995-882f-80a386a08e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577652958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.577652958
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3757250656
Short name T473
Test name
Test status
Simulation time 1985261028 ps
CPU time 4.32 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 212616 kb
Host smart-1d9165c3-5449-4a41-b0a4-bd7410484140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757250656 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3757250656
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1173621539
Short name T963
Test name
Test status
Simulation time 10171329359 ps
CPU time 13.57 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 268256 kb
Host smart-cd5e31b0-c3ab-41ad-a0fe-d41951644168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173621539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1173621539
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1013385019
Short name T1337
Test name
Test status
Simulation time 10072703053 ps
CPU time 69.46 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:48:50 PM PDT 24
Peak memory 547200 kb
Host smart-4904aadb-f5ce-4562-918d-a460cda45334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013385019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1013385019
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.516921973
Short name T446
Test name
Test status
Simulation time 390073283 ps
CPU time 2.51 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 204220 kb
Host smart-fdbf077a-12a9-4aaa-8b7d-90e57b0afcd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516921973 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.516921973
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3741494080
Short name T382
Test name
Test status
Simulation time 7830866383 ps
CPU time 4.12 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 204328 kb
Host smart-8e9a4524-1da6-43d2-a470-fb2c9acec41f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741494080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3741494080
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3333262885
Short name T11
Test name
Test status
Simulation time 15687553612 ps
CPU time 309.06 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:52:39 PM PDT 24
Peak memory 3681632 kb
Host smart-4e64b0c4-1c5c-4b0e-93b3-104eb654fb66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333262885 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3333262885
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.682749702
Short name T818
Test name
Test status
Simulation time 919890696 ps
CPU time 32.93 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 204440 kb
Host smart-3a9b5f9e-5eff-44cf-8237-eda315bc1d20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682749702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.682749702
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2540499536
Short name T1180
Test name
Test status
Simulation time 1062058626 ps
CPU time 18.76 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 216176 kb
Host smart-31c2d683-47f8-422a-97c8-3a2d47a37a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540499536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2540499536
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1807897088
Short name T680
Test name
Test status
Simulation time 8260055219 ps
CPU time 5.27 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 204236 kb
Host smart-b5724eff-d5f7-4c56-b0f0-245db8c62a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807897088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1807897088
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3557984249
Short name T6
Test name
Test status
Simulation time 12374335035 ps
CPU time 155.62 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:50:08 PM PDT 24
Peak memory 705252 kb
Host smart-3d87e60b-283a-42be-8178-4c4afb8d2678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557984249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3557984249
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2167030898
Short name T1200
Test name
Test status
Simulation time 1119808084 ps
CPU time 6.32 seconds
Started May 12 12:47:35 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 212672 kb
Host smart-dad24832-72bf-470f-98b8-71ce5560c10c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167030898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2167030898
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1181066270
Short name T470
Test name
Test status
Simulation time 45756853 ps
CPU time 0.62 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 204068 kb
Host smart-0b4990fa-daae-42e3-8f9b-15bc612032bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181066270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1181066270
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4249285420
Short name T942
Test name
Test status
Simulation time 95242136 ps
CPU time 1.76 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 212528 kb
Host smart-880401c7-6219-4538-b8bd-aaff73d20ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249285420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4249285420
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2998058150
Short name T974
Test name
Test status
Simulation time 273732980 ps
CPU time 4.96 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:39 PM PDT 24
Peak memory 260940 kb
Host smart-39e0780f-2b49-45cc-8254-c9c07a668b2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998058150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2998058150
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3572368017
Short name T263
Test name
Test status
Simulation time 24174462899 ps
CPU time 193.54 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:50:56 PM PDT 24
Peak memory 805260 kb
Host smart-5f96db35-595c-4c67-879e-6a87a6b6fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572368017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3572368017
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2935142605
Short name T900
Test name
Test status
Simulation time 7143085945 ps
CPU time 54.82 seconds
Started May 12 12:47:46 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 564620 kb
Host smart-a500587c-db44-4962-9bb7-0bb1f62b48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935142605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2935142605
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2739907114
Short name T348
Test name
Test status
Simulation time 104006422 ps
CPU time 0.9 seconds
Started May 12 12:47:38 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204020 kb
Host smart-1a015ff5-89fa-46de-9a35-f5ad6787746e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739907114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2739907114
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.814706177
Short name T1117
Test name
Test status
Simulation time 241035963 ps
CPU time 6.25 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204364 kb
Host smart-10cbfd06-24f2-41b8-8d67-8ac81aa79e4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814706177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
814706177
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2564894841
Short name T1135
Test name
Test status
Simulation time 3459172174 ps
CPU time 85.99 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 1062580 kb
Host smart-1b560461-7be7-4bb6-b673-f82077828c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564894841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2564894841
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.2319240602
Short name T77
Test name
Test status
Simulation time 302669499 ps
CPU time 11.84 seconds
Started May 12 12:47:38 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 204304 kb
Host smart-d2900cab-e437-4368-a932-cf0b846877ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319240602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2319240602
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2515128544
Short name T873
Test name
Test status
Simulation time 7979552017 ps
CPU time 72.57 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 312744 kb
Host smart-792d428a-c1d9-4a91-ab2a-c68dcba0b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515128544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2515128544
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1753394519
Short name T140
Test name
Test status
Simulation time 86423132 ps
CPU time 0.68 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 203996 kb
Host smart-e2d74127-820c-48cd-97f3-4c23676995ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753394519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1753394519
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3904453989
Short name T498
Test name
Test status
Simulation time 4938154447 ps
CPU time 200.97 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:51:01 PM PDT 24
Peak memory 229024 kb
Host smart-e0b0958e-e687-4b6e-ba71-e274fbc58d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904453989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3904453989
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1261054689
Short name T682
Test name
Test status
Simulation time 972638449 ps
CPU time 43.43 seconds
Started May 12 12:47:29 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 268448 kb
Host smart-48b062b1-cde1-4b64-8810-ea6898a4d456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261054689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1261054689
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.349706653
Short name T268
Test name
Test status
Simulation time 21985734096 ps
CPU time 1237.45 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 01:08:07 PM PDT 24
Peak memory 3202932 kb
Host smart-63723eb4-0341-4182-bd7e-b1a861b1c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349706653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.349706653
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2795424186
Short name T314
Test name
Test status
Simulation time 1625359884 ps
CPU time 15.46 seconds
Started May 12 12:47:36 PM PDT 24
Finished May 12 12:47:52 PM PDT 24
Peak memory 212484 kb
Host smart-92d85d09-2262-44c7-b8f9-46e7499b0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795424186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2795424186
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.929122835
Short name T303
Test name
Test status
Simulation time 3683200871 ps
CPU time 4.03 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 212624 kb
Host smart-d96d7a2d-a356-4a13-b844-ec4a89f4b1e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929122835 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.929122835
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.719228349
Short name T457
Test name
Test status
Simulation time 10027045309 ps
CPU time 78.89 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 429416 kb
Host smart-4e30c004-29f2-4789-acca-57c39f5c7b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719228349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.719228349
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1630063389
Short name T749
Test name
Test status
Simulation time 10159185485 ps
CPU time 16.26 seconds
Started May 12 12:47:47 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 291128 kb
Host smart-39a23925-201c-42e2-9888-831d646a33d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630063389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1630063389
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1028687982
Short name T1010
Test name
Test status
Simulation time 481813037 ps
CPU time 1.98 seconds
Started May 12 12:47:57 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 204384 kb
Host smart-7f09b08d-4824-4ddd-8daa-1a44adbd717f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028687982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1028687982
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.37944358
Short name T890
Test name
Test status
Simulation time 578584038 ps
CPU time 3.57 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 204412 kb
Host smart-ea7880a7-288b-4487-bbd5-672a2ac3ad42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944358 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.37944358
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.801766407
Short name T782
Test name
Test status
Simulation time 21601390567 ps
CPU time 55.62 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 1207136 kb
Host smart-15ed743a-6c82-4f9b-ab3b-c3710eaac1d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801766407 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.801766407
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2292524897
Short name T364
Test name
Test status
Simulation time 3716714618 ps
CPU time 11.95 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 204352 kb
Host smart-63a697d8-8cd3-4329-bc6d-77e1edcef6f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292524897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2292524897
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3212737842
Short name T1310
Test name
Test status
Simulation time 1422163229 ps
CPU time 25.82 seconds
Started May 12 12:47:34 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 223052 kb
Host smart-ba3577cf-a69b-4eea-8232-b91efe40c9fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212737842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3212737842
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1880578015
Short name T296
Test name
Test status
Simulation time 7416206322 ps
CPU time 13.28 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 204208 kb
Host smart-6471b584-b00d-4aec-b4b6-7d42509a1dbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880578015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1880578015
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.949710359
Short name T613
Test name
Test status
Simulation time 17754871078 ps
CPU time 253.97 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:51:48 PM PDT 24
Peak memory 980908 kb
Host smart-c47629dc-709d-4521-9000-89236889ee1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949710359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.949710359
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.4242610444
Short name T1359
Test name
Test status
Simulation time 5937368058 ps
CPU time 6.73 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 212560 kb
Host smart-b63a2592-cc83-4e8b-af24-9f44124fe92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242610444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.4242610444
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.4110294158
Short name T715
Test name
Test status
Simulation time 19697678 ps
CPU time 0.56 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 203900 kb
Host smart-6ebc3481-8ea3-4c2b-99e8-84ab2767b87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110294158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4110294158
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.776277074
Short name T888
Test name
Test status
Simulation time 862152400 ps
CPU time 1.36 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 220788 kb
Host smart-72b7d2f9-fc98-4df2-bd2d-5ff025fc9b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776277074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.776277074
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2128839930
Short name T800
Test name
Test status
Simulation time 1301394290 ps
CPU time 5.93 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 270824 kb
Host smart-0dd54716-0967-40b9-bb1f-6ac5e9eb4828
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128839930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2128839930
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.4234729137
Short name T148
Test name
Test status
Simulation time 1812610285 ps
CPU time 130.51 seconds
Started May 12 12:47:55 PM PDT 24
Finished May 12 12:50:06 PM PDT 24
Peak memory 645788 kb
Host smart-161882ec-6f34-478b-9552-c55577445c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234729137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.4234729137
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3566543447
Short name T696
Test name
Test status
Simulation time 3222061785 ps
CPU time 112.12 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 588012 kb
Host smart-ea14ab6b-f2cc-4741-b4ca-ca36fe0bd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566543447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3566543447
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1963515301
Short name T815
Test name
Test status
Simulation time 550747197 ps
CPU time 1 seconds
Started May 12 12:47:28 PM PDT 24
Finished May 12 12:47:30 PM PDT 24
Peak memory 204048 kb
Host smart-a03a632c-e125-4fd4-8232-64cef44974ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963515301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1963515301
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.465162225
Short name T730
Test name
Test status
Simulation time 629441419 ps
CPU time 10.15 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 235164 kb
Host smart-d0617094-ea75-41b9-9cd1-53e63b1d771b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465162225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
465162225
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3099016980
Short name T100
Test name
Test status
Simulation time 22615966699 ps
CPU time 75.51 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 990496 kb
Host smart-c9fc1d4a-430e-44c6-8577-0db20ff4e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099016980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3099016980
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2474129810
Short name T1309
Test name
Test status
Simulation time 759809646 ps
CPU time 7.37 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 204608 kb
Host smart-a72a2346-934a-46f8-ae0e-017dfd1e749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474129810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2474129810
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2817749355
Short name T731
Test name
Test status
Simulation time 8025685199 ps
CPU time 43.44 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 422672 kb
Host smart-d03c9f5c-55c4-4389-9ff1-911cd74b9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817749355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2817749355
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.4216559699
Short name T51
Test name
Test status
Simulation time 52484834 ps
CPU time 0.64 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 203944 kb
Host smart-3d16cd3f-894b-448e-9612-d8ae7488df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216559699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4216559699
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.298526489
Short name T773
Test name
Test status
Simulation time 27410027226 ps
CPU time 926.78 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 01:03:27 PM PDT 24
Peak memory 2513780 kb
Host smart-5253284d-9f40-4ad1-a3f3-5ab675e1fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298526489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.298526489
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4068656752
Short name T270
Test name
Test status
Simulation time 7188273345 ps
CPU time 83.35 seconds
Started May 12 12:47:58 PM PDT 24
Finished May 12 12:49:22 PM PDT 24
Peak memory 334664 kb
Host smart-981a0b1f-f5b3-46e3-836c-d032a7f24154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068656752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4068656752
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3192307681
Short name T910
Test name
Test status
Simulation time 10648681855 ps
CPU time 10.84 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 212520 kb
Host smart-08460d1e-5c4c-4a0e-ae27-794bf93a8a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192307681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3192307681
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3735349150
Short name T553
Test name
Test status
Simulation time 1181062230 ps
CPU time 3.07 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:47:41 PM PDT 24
Peak memory 204308 kb
Host smart-04354245-d85b-4c0e-aa34-67f0f3bbcf11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735349150 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3735349150
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3879148668
Short name T67
Test name
Test status
Simulation time 10116900403 ps
CPU time 13.76 seconds
Started May 12 12:47:57 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 284724 kb
Host smart-7e41654b-ec82-4777-b6a4-ffeda0df2f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879148668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3879148668
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3043738113
Short name T1302
Test name
Test status
Simulation time 10166159006 ps
CPU time 29.11 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:13 PM PDT 24
Peak memory 339528 kb
Host smart-0f8907bb-ff90-4fed-861c-e50343982c18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043738113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3043738113
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.4027229211
Short name T1340
Test name
Test status
Simulation time 509012745 ps
CPU time 3.19 seconds
Started May 12 12:47:32 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 204276 kb
Host smart-d45b96f8-c60a-4980-9280-2307ff325017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027229211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.4027229211
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1344482741
Short name T728
Test name
Test status
Simulation time 5402749640 ps
CPU time 4.82 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 204636 kb
Host smart-13063104-34f4-4b95-9c3b-ad17669b4db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344482741 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1344482741
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.701212326
Short name T21
Test name
Test status
Simulation time 10948027101 ps
CPU time 49.59 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:48:27 PM PDT 24
Peak memory 943516 kb
Host smart-a2e46725-c039-4040-84c5-3b8a4a293667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701212326 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.701212326
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3353799965
Short name T363
Test name
Test status
Simulation time 1195500997 ps
CPU time 16.38 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:48:03 PM PDT 24
Peak memory 204336 kb
Host smart-ddfed771-8f24-485b-b744-4170431999b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353799965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3353799965
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.691408739
Short name T933
Test name
Test status
Simulation time 24032471253 ps
CPU time 26.58 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 223840 kb
Host smart-3acc8956-6c44-4401-9b94-1a0f7c81a9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691408739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.691408739
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1117532741
Short name T289
Test name
Test status
Simulation time 64270320380 ps
CPU time 809.05 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 01:01:16 PM PDT 24
Peak memory 5705684 kb
Host smart-a3316de8-5687-4121-93e2-ccafd8fb8d53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117532741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1117532741
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3553091696
Short name T111
Test name
Test status
Simulation time 29855328561 ps
CPU time 1762.7 seconds
Started May 12 12:47:34 PM PDT 24
Finished May 12 01:16:58 PM PDT 24
Peak memory 3398488 kb
Host smart-6cf16b8f-ff69-4952-9d2d-01d9d3172dbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553091696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3553091696
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2761877197
Short name T580
Test name
Test status
Simulation time 1503575245 ps
CPU time 8.51 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 220548 kb
Host smart-a95d66e0-26da-4011-b596-b9e6a7dc7338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761877197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2761877197
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3793047383
Short name T1001
Test name
Test status
Simulation time 36198228 ps
CPU time 0.63 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:47:46 PM PDT 24
Peak memory 204096 kb
Host smart-8b70a262-28b6-4560-a9dd-b5df6af34318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793047383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3793047383
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2233152036
Short name T756
Test name
Test status
Simulation time 479768211 ps
CPU time 1.55 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 216008 kb
Host smart-0027de81-22a2-402c-8c83-986d6416129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233152036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2233152036
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2471712825
Short name T610
Test name
Test status
Simulation time 1193793114 ps
CPU time 15.66 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 267776 kb
Host smart-e4d25046-8528-4b68-b13e-8d19af4138fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471712825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2471712825
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.1781801097
Short name T957
Test name
Test status
Simulation time 2378089958 ps
CPU time 73.59 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 458240 kb
Host smart-d578fd84-2cad-4994-abc6-40977021b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781801097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1781801097
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3826464349
Short name T306
Test name
Test status
Simulation time 2537058438 ps
CPU time 81.44 seconds
Started May 12 12:47:31 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 464228 kb
Host smart-06631453-127f-4770-b0d9-32f152735748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826464349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3826464349
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1073400014
Short name T639
Test name
Test status
Simulation time 399428981 ps
CPU time 0.92 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 204092 kb
Host smart-72e67636-ce3e-4c57-80ba-6f14c43e65d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073400014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1073400014
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.870237523
Short name T679
Test name
Test status
Simulation time 117883803 ps
CPU time 5.77 seconds
Started May 12 12:47:30 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 204380 kb
Host smart-dcdedfd0-e527-4047-899b-56b055a93847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870237523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
870237523
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4227631809
Short name T261
Test name
Test status
Simulation time 3850347106 ps
CPU time 302.94 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:52:47 PM PDT 24
Peak memory 1162480 kb
Host smart-6859cd0f-1267-4c81-8c24-dfb396a4520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227631809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4227631809
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2088169344
Short name T1234
Test name
Test status
Simulation time 1205563192 ps
CPU time 14.32 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 204308 kb
Host smart-838f02aa-932b-4601-9e22-76462e0a965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088169344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2088169344
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.353831685
Short name T750
Test name
Test status
Simulation time 1350546095 ps
CPU time 26.87 seconds
Started May 12 12:47:46 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 325848 kb
Host smart-3402455b-9466-4be2-a146-26ada257ca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353831685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.353831685
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1121670107
Short name T184
Test name
Test status
Simulation time 31395739 ps
CPU time 0.72 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 204328 kb
Host smart-aed30f85-16c2-44d4-a327-b336378419e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121670107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1121670107
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1836037228
Short name T1308
Test name
Test status
Simulation time 12410619048 ps
CPU time 47.42 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 244992 kb
Host smart-7f4ab8ab-ff0d-4036-ad91-1078bc364c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836037228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1836037228
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1193378578
Short name T1264
Test name
Test status
Simulation time 3011471956 ps
CPU time 28.88 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 292792 kb
Host smart-4f542a15-82d7-43e4-9a2b-232c1be95ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193378578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1193378578
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.955474187
Short name T983
Test name
Test status
Simulation time 32306012174 ps
CPU time 1701.96 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 01:16:00 PM PDT 24
Peak memory 1275000 kb
Host smart-9c0a5c21-6074-4637-80ad-d8d8bcfaf484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955474187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.955474187
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2063195990
Short name T186
Test name
Test status
Simulation time 1071621144 ps
CPU time 10.58 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:47:56 PM PDT 24
Peak memory 212520 kb
Host smart-baa99403-c981-4bb5-bc77-42ca08efda6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063195990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2063195990
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2956708300
Short name T362
Test name
Test status
Simulation time 1034322188 ps
CPU time 5.16 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:47:56 PM PDT 24
Peak memory 204340 kb
Host smart-41eb5c37-306a-47f2-b72f-221266c57786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956708300 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2956708300
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.313153577
Short name T948
Test name
Test status
Simulation time 10581900930 ps
CPU time 9.87 seconds
Started May 12 12:47:40 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 248416 kb
Host smart-c987590f-3905-4f26-8fdb-97ade897abef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313153577 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.313153577
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.4273301846
Short name T1053
Test name
Test status
Simulation time 10123162596 ps
CPU time 65.43 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 423944 kb
Host smart-85a89ccd-9a2d-4e4f-854b-c9183204ca63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273301846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.4273301846
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2484481131
Short name T713
Test name
Test status
Simulation time 821441994 ps
CPU time 2.61 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:03 PM PDT 24
Peak memory 204368 kb
Host smart-9ce8a065-97dc-4730-95f7-6efcc7da5ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484481131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2484481131
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3461590104
Short name T1202
Test name
Test status
Simulation time 2110930449 ps
CPU time 6.29 seconds
Started May 12 12:47:42 PM PDT 24
Finished May 12 12:47:50 PM PDT 24
Peak memory 212372 kb
Host smart-7c60b647-b4ae-478c-97f6-3dc4d87db865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461590104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3461590104
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.882302461
Short name T1047
Test name
Test status
Simulation time 23808784381 ps
CPU time 196.25 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:51:01 PM PDT 24
Peak memory 2871600 kb
Host smart-21809b06-9b0c-4f23-b488-53e9c59849c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882302461 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.882302461
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1280300205
Short name T1353
Test name
Test status
Simulation time 4695703926 ps
CPU time 18.68 seconds
Started May 12 12:47:46 PM PDT 24
Finished May 12 12:48:10 PM PDT 24
Peak memory 204396 kb
Host smart-3b469c59-fd1f-41eb-90e5-66760794c355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280300205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1280300205
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1441957726
Short name T335
Test name
Test status
Simulation time 1835553462 ps
CPU time 21.08 seconds
Started May 12 12:47:37 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 204308 kb
Host smart-3dd2210c-2bdf-4339-8ac8-b61e601941cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441957726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1441957726
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.99237463
Short name T1287
Test name
Test status
Simulation time 11786843396 ps
CPU time 21.34 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:48:07 PM PDT 24
Peak memory 204376 kb
Host smart-15f4b7b8-2852-4549-8338-367a1abd7a9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99237463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stress_wr.99237463
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2869221743
Short name T1188
Test name
Test status
Simulation time 28986901865 ps
CPU time 257.91 seconds
Started May 12 12:47:33 PM PDT 24
Finished May 12 12:51:53 PM PDT 24
Peak memory 1801824 kb
Host smart-a0a43df3-c1b1-4265-bcb2-06a353d4dc67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869221743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2869221743
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3846063887
Short name T930
Test name
Test status
Simulation time 1379231828 ps
CPU time 6.89 seconds
Started May 12 12:47:57 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 211728 kb
Host smart-f3ba5750-cad2-4ccc-84f5-9d0b42a9e890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846063887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3846063887
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1751755995
Short name T986
Test name
Test status
Simulation time 38072749 ps
CPU time 0.6 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 203960 kb
Host smart-8f63d2f6-754e-4486-9234-289846303ddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751755995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1751755995
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3579363896
Short name T691
Test name
Test status
Simulation time 95856624 ps
CPU time 1.61 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 212584 kb
Host smart-dd603639-ca4e-4774-8a7e-1ce9ff069b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579363896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3579363896
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3511454255
Short name T1029
Test name
Test status
Simulation time 6642417484 ps
CPU time 21.93 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 296032 kb
Host smart-d215cd22-2ee4-4d9b-a891-2ddd9a05e5fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511454255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3511454255
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3944810502
Short name T453
Test name
Test status
Simulation time 1360806239 ps
CPU time 42.87 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:48:27 PM PDT 24
Peak memory 498172 kb
Host smart-54b8deb2-2338-4c57-98d6-8db53ad75512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944810502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3944810502
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3896755501
Short name T54
Test name
Test status
Simulation time 1943348899 ps
CPU time 138 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:50:05 PM PDT 24
Peak memory 632204 kb
Host smart-edfa3555-cc67-4b01-9348-20524bffb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896755501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3896755501
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1383761167
Short name T466
Test name
Test status
Simulation time 107390100 ps
CPU time 0.91 seconds
Started May 12 12:47:39 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 204080 kb
Host smart-eeb92464-a7d2-4b38-8039-ef595c36e987
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383761167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1383761167
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.296908651
Short name T714
Test name
Test status
Simulation time 115239512 ps
CPU time 3.35 seconds
Started May 12 12:47:47 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 221164 kb
Host smart-40a1b61b-6c57-42ec-af48-bfbded08de02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296908651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
296908651
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3803948618
Short name T1104
Test name
Test status
Simulation time 10351076361 ps
CPU time 163.92 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:50:29 PM PDT 24
Peak memory 798284 kb
Host smart-d6171b27-8025-4576-ba4b-b55a7c9b1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803948618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3803948618
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.987691919
Short name T566
Test name
Test status
Simulation time 2318075807 ps
CPU time 3.86 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:47:55 PM PDT 24
Peak memory 204420 kb
Host smart-f398f28a-d3a4-439d-b1ac-7f539b20ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987691919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.987691919
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1557321505
Short name T758
Test name
Test status
Simulation time 1203880924 ps
CPU time 56.83 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:48:47 PM PDT 24
Peak memory 299236 kb
Host smart-c11faa0f-be08-4b9a-b622-3ffff0e3926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557321505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1557321505
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.540329413
Short name T655
Test name
Test status
Simulation time 20985555 ps
CPU time 0.63 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 204032 kb
Host smart-5cccb973-e145-46f2-b756-3f7db8cf616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540329413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.540329413
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.783798039
Short name T768
Test name
Test status
Simulation time 6938643436 ps
CPU time 88.09 seconds
Started May 12 12:47:48 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 213916 kb
Host smart-6ba17d48-0ffc-4bf6-9ce0-0d451f218183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783798039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.783798039
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1851999787
Short name T1172
Test name
Test status
Simulation time 1919110263 ps
CPU time 41.52 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 269292 kb
Host smart-bcf61723-930d-401b-a08d-080de5ac62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851999787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1851999787
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3516233282
Short name T586
Test name
Test status
Simulation time 4110387945 ps
CPU time 96.26 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 686300 kb
Host smart-0b38cbe1-21a2-465a-8c48-54cb049ecd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516233282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3516233282
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2649825006
Short name T1048
Test name
Test status
Simulation time 678344660 ps
CPU time 13.79 seconds
Started May 12 12:47:51 PM PDT 24
Finished May 12 12:48:05 PM PDT 24
Peak memory 212484 kb
Host smart-f445d274-fabd-4b06-a2ac-5a92b25fea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649825006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2649825006
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1790268792
Short name T987
Test name
Test status
Simulation time 4640773991 ps
CPU time 3.18 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 204536 kb
Host smart-7dde679b-c541-4704-a64e-89c958d9636e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790268792 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1790268792
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.4270884033
Short name T1027
Test name
Test status
Simulation time 10327963383 ps
CPU time 15.8 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:18 PM PDT 24
Peak memory 256440 kb
Host smart-2f959dde-48da-4bf8-b90c-5b1f832810bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270884033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.4270884033
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3795169504
Short name T353
Test name
Test status
Simulation time 11323288092 ps
CPU time 8.31 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 258080 kb
Host smart-c4c81135-a395-4a2e-8713-0b1559725c14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795169504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3795169504
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2045388988
Short name T866
Test name
Test status
Simulation time 3965543998 ps
CPU time 3.5 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:47:50 PM PDT 24
Peak memory 204408 kb
Host smart-9aa96847-2731-4af9-a773-b0776758a577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045388988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2045388988
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1884838232
Short name T1367
Test name
Test status
Simulation time 2342242039 ps
CPU time 4.85 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 204436 kb
Host smart-964008f4-3b7a-43ec-a5df-c51b7cfd79a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884838232 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1884838232
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.4108709168
Short name T1357
Test name
Test status
Simulation time 16015232140 ps
CPU time 103.25 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 1925704 kb
Host smart-db0c5841-4f2f-4806-b8cc-c37e032716ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108709168 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.4108709168
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2542935278
Short name T1134
Test name
Test status
Simulation time 1051803165 ps
CPU time 38.93 seconds
Started May 12 12:47:41 PM PDT 24
Finished May 12 12:48:21 PM PDT 24
Peak memory 204272 kb
Host smart-504674bc-8846-4acf-b151-93fae3d406ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542935278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2542935278
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1672312135
Short name T312
Test name
Test status
Simulation time 12205138804 ps
CPU time 64.86 seconds
Started May 12 12:47:44 PM PDT 24
Finished May 12 12:48:50 PM PDT 24
Peak memory 208512 kb
Host smart-359d9e81-c904-4004-9104-21a1edfe85b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672312135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1672312135
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2407296241
Short name T507
Test name
Test status
Simulation time 16164587239 ps
CPU time 9.59 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 204408 kb
Host smart-0f6231d4-1ec2-4ec1-a09e-81d64abd8a82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407296241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2407296241
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1336087241
Short name T827
Test name
Test status
Simulation time 30124101580 ps
CPU time 1955.56 seconds
Started May 12 12:47:38 PM PDT 24
Finished May 12 01:20:15 PM PDT 24
Peak memory 7300704 kb
Host smart-33f50c45-9895-4a63-b2f4-53490f07258a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336087241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1336087241
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.94595927
Short name T718
Test name
Test status
Simulation time 1337635059 ps
CPU time 7.33 seconds
Started May 12 12:47:58 PM PDT 24
Finished May 12 12:48:06 PM PDT 24
Peak memory 212468 kb
Host smart-a51afe57-18b2-4277-b907-514bc3059a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94595927 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_timeout.94595927
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1948092347
Short name T491
Test name
Test status
Simulation time 16492086 ps
CPU time 0.7 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:46:11 PM PDT 24
Peak memory 203960 kb
Host smart-b93495b8-489f-443a-907f-897e928ec045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948092347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1948092347
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3419063992
Short name T512
Test name
Test status
Simulation time 353203649 ps
CPU time 1.76 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 216840 kb
Host smart-02c8ecf3-2b6e-40a8-aded-1787da75956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419063992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3419063992
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1392404373
Short name T616
Test name
Test status
Simulation time 208141493 ps
CPU time 3.84 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:21 PM PDT 24
Peak memory 238320 kb
Host smart-3f49d9a8-2f56-4323-a658-cd665029d3a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392404373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1392404373
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.321074012
Short name T180
Test name
Test status
Simulation time 8512290346 ps
CPU time 84.85 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:47:35 PM PDT 24
Peak memory 776020 kb
Host smart-9dd4e18a-b419-4ffb-a841-518abd4c8a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321074012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.321074012
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1825354233
Short name T441
Test name
Test status
Simulation time 7777721661 ps
CPU time 66.74 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:47:27 PM PDT 24
Peak memory 662332 kb
Host smart-3cdcf0ef-679a-407f-a3e2-71688a9e2b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825354233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1825354233
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.191704846
Short name T1085
Test name
Test status
Simulation time 472332387 ps
CPU time 1.03 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:46:32 PM PDT 24
Peak memory 204232 kb
Host smart-951bf711-72ea-417c-9d62-fe73192e9636
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191704846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.191704846
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.4051426514
Short name T384
Test name
Test status
Simulation time 218405402 ps
CPU time 4.27 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 204228 kb
Host smart-8407d27d-8df0-48e5-83dc-ed86fc895f80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051426514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
4051426514
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1478683642
Short name T257
Test name
Test status
Simulation time 18226647598 ps
CPU time 135.56 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 1292092 kb
Host smart-643b2128-cfea-4a67-8d6a-03ea318cbdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478683642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1478683642
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3508132277
Short name T242
Test name
Test status
Simulation time 886587589 ps
CPU time 6.22 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 204296 kb
Host smart-987de001-73aa-4aa6-b91e-e02c87a2ea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508132277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3508132277
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.3512300338
Short name T134
Test name
Test status
Simulation time 55103904 ps
CPU time 0.65 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:13 PM PDT 24
Peak memory 203952 kb
Host smart-09f87de2-5d70-4e04-97a5-03f95ea625dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512300338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3512300338
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1870090800
Short name T719
Test name
Test status
Simulation time 24090539192 ps
CPU time 123.12 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 212936 kb
Host smart-9d19a936-cb03-4f8e-963a-63f9e04857ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870090800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1870090800
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1820718199
Short name T465
Test name
Test status
Simulation time 1330465724 ps
CPU time 60.08 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 313692 kb
Host smart-ddc71299-4919-400a-b111-533dcb8f4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820718199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1820718199
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3177444561
Short name T1275
Test name
Test status
Simulation time 9586248994 ps
CPU time 268.44 seconds
Started May 12 12:46:07 PM PDT 24
Finished May 12 12:50:36 PM PDT 24
Peak memory 507400 kb
Host smart-2a14b38c-a319-4c20-9201-223b47f106ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177444561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3177444561
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.162908270
Short name T967
Test name
Test status
Simulation time 6200523786 ps
CPU time 11.29 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 228868 kb
Host smart-1508fe3b-206b-4443-bbc8-4b855a82c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162908270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.162908270
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3396349126
Short name T174
Test name
Test status
Simulation time 509281591 ps
CPU time 0.91 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:25 PM PDT 24
Peak memory 222056 kb
Host smart-07012a87-9f1e-4c9a-88fe-d967ef1ea81e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396349126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3396349126
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2066213584
Short name T1268
Test name
Test status
Simulation time 692483516 ps
CPU time 4 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 204412 kb
Host smart-59d953b0-f94a-4021-889a-cf5be1f9f376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066213584 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2066213584
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1503520121
Short name T71
Test name
Test status
Simulation time 10226408441 ps
CPU time 14.61 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 251408 kb
Host smart-3bff9742-8e74-44eb-bcb9-7fa9509af863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503520121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1503520121
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2634492334
Short name T849
Test name
Test status
Simulation time 10028658414 ps
CPU time 73.17 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 424216 kb
Host smart-387c24a8-d130-4123-a77e-7f41a1e7aeb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634492334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2634492334
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3762280712
Short name T14
Test name
Test status
Simulation time 447443277 ps
CPU time 2.76 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:17 PM PDT 24
Peak memory 204376 kb
Host smart-9e6a1b21-53a7-4b94-aa2f-2e6af20a5d75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762280712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3762280712
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1952968010
Short name T915
Test name
Test status
Simulation time 1503734575 ps
CPU time 4.56 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 204316 kb
Host smart-a80c11fa-50ea-44ff-aa8f-7206e697b71a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952968010 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1952968010
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.840189891
Short name T1066
Test name
Test status
Simulation time 11556379862 ps
CPU time 71.03 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:47:37 PM PDT 24
Peak memory 1254808 kb
Host smart-68a8de9f-c585-4e9b-8e64-ebc4caf58085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840189891 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.840189891
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2425067105
Short name T1031
Test name
Test status
Simulation time 990160313 ps
CPU time 12.36 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 204400 kb
Host smart-9535a69f-aba2-45f0-a7d9-90ea21b82b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425067105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2425067105
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1991139707
Short name T998
Test name
Test status
Simulation time 1212140020 ps
CPU time 51.59 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:47:05 PM PDT 24
Peak memory 205152 kb
Host smart-44de533c-ce29-4c56-a22c-0ee297c73021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991139707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1991139707
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.580624579
Short name T893
Test name
Test status
Simulation time 26157366319 ps
CPU time 111.85 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:48:06 PM PDT 24
Peak memory 1666524 kb
Host smart-2e6ff08f-f846-43c4-9488-9cb21c57fff2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580624579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.580624579
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2187065660
Short name T1260
Test name
Test status
Simulation time 24863653904 ps
CPU time 188.11 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:49:26 PM PDT 24
Peak memory 1586672 kb
Host smart-83a69ca4-5ebf-48ae-b622-4016998b6041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187065660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2187065660
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.433503095
Short name T1219
Test name
Test status
Simulation time 1743002353 ps
CPU time 6.77 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:24 PM PDT 24
Peak memory 214568 kb
Host smart-cb3c9fc2-07f6-4baf-b4ca-14427b73a0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433503095 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.433503095
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.3952199563
Short name T1301
Test name
Test status
Simulation time 2433243479 ps
CPU time 4.17 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 204296 kb
Host smart-39683b8c-4557-4897-9326-3f7442ffc4cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952199563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.3952199563
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2231156617
Short name T523
Test name
Test status
Simulation time 90900423 ps
CPU time 0.64 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 204040 kb
Host smart-7ba1fa62-abc4-41fb-a1e8-b15ca35ce1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231156617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2231156617
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.4252028002
Short name T520
Test name
Test status
Simulation time 344113583 ps
CPU time 1.25 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:01 PM PDT 24
Peak memory 212548 kb
Host smart-a8e2a516-08f8-49fc-8a8d-0b106f62a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252028002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.4252028002
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.342016845
Short name T183
Test name
Test status
Simulation time 1993222272 ps
CPU time 15.49 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:48:06 PM PDT 24
Peak memory 265680 kb
Host smart-1bf51aa7-f470-45ef-a8f6-c624910501f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342016845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.342016845
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.687853307
Short name T791
Test name
Test status
Simulation time 1173676612 ps
CPU time 31.76 seconds
Started May 12 12:47:52 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 493144 kb
Host smart-906711b3-f9fb-46dd-9381-d12937c42927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687853307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.687853307
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.775186
Short name T1270
Test name
Test status
Simulation time 1083875698 ps
CPU time 64.66 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 350744 kb
Host smart-d8c37edd-988c-4b72-a4c4-35de9bd04acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.775186
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.379271441
Short name T1293
Test name
Test status
Simulation time 208111763 ps
CPU time 7.18 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 225044 kb
Host smart-efc96e1e-f90f-4656-a759-40052d0fcec4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379271441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
379271441
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.24552461
Short name T783
Test name
Test status
Simulation time 4922820868 ps
CPU time 65.62 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 756440 kb
Host smart-5531d0d8-97fa-43ef-b6f5-c89f34f73341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24552461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.24552461
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3377985150
Short name T852
Test name
Test status
Simulation time 805924787 ps
CPU time 6.74 seconds
Started May 12 12:47:51 PM PDT 24
Finished May 12 12:47:58 PM PDT 24
Peak memory 204360 kb
Host smart-d40e1523-7651-4065-a709-1672466c705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377985150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3377985150
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.2055747846
Short name T1063
Test name
Test status
Simulation time 8010674307 ps
CPU time 39.23 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 452992 kb
Host smart-3f685de0-262f-4aa7-9dff-aa1a43a35ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055747846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2055747846
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3269048447
Short name T604
Test name
Test status
Simulation time 42967303 ps
CPU time 0.63 seconds
Started May 12 12:47:43 PM PDT 24
Finished May 12 12:47:45 PM PDT 24
Peak memory 203944 kb
Host smart-580e6b27-a737-43e0-9126-3560ce75ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269048447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3269048447
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3272533759
Short name T488
Test name
Test status
Simulation time 7558520504 ps
CPU time 56.97 seconds
Started May 12 12:47:48 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 245240 kb
Host smart-10586ff1-951e-446e-a5de-1927d2cd318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272533759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3272533759
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2768255300
Short name T1057
Test name
Test status
Simulation time 3117063592 ps
CPU time 33.67 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:36 PM PDT 24
Peak memory 363924 kb
Host smart-03fb4d26-7e6c-4c54-a999-ef51a13eb9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768255300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2768255300
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3301405900
Short name T233
Test name
Test status
Simulation time 19608730634 ps
CPU time 320.98 seconds
Started May 12 12:47:46 PM PDT 24
Finished May 12 12:53:08 PM PDT 24
Peak memory 1649408 kb
Host smart-67e9f6ba-cf11-4103-b24f-a63f009ff0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301405900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3301405900
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2413939399
Short name T1173
Test name
Test status
Simulation time 1140870246 ps
CPU time 9.12 seconds
Started May 12 12:47:58 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 214588 kb
Host smart-5c463960-e986-41e7-a6ac-e1785c1ba229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413939399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2413939399
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2949927348
Short name T722
Test name
Test status
Simulation time 440034704 ps
CPU time 2.67 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 204276 kb
Host smart-df5688bd-35a6-4d54-b035-930e7287f6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949927348 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2949927348
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1314027975
Short name T911
Test name
Test status
Simulation time 10334736557 ps
CPU time 19.68 seconds
Started May 12 12:47:47 PM PDT 24
Finished May 12 12:48:07 PM PDT 24
Peak memory 300852 kb
Host smart-b8090a3c-2b25-4fcc-99b0-91096e2d5d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314027975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1314027975
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.531107063
Short name T1169
Test name
Test status
Simulation time 10145249406 ps
CPU time 13.19 seconds
Started May 12 12:47:51 PM PDT 24
Finished May 12 12:48:05 PM PDT 24
Peak memory 285120 kb
Host smart-423485e2-fe8b-414c-a19e-f59687763b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531107063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.531107063
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3407011979
Short name T1329
Test name
Test status
Simulation time 510222047 ps
CPU time 2.93 seconds
Started May 12 12:47:49 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 204304 kb
Host smart-3ead827c-79be-4984-a952-b16dc83bbcc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407011979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3407011979
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2259544493
Short name T991
Test name
Test status
Simulation time 4151382809 ps
CPU time 6.77 seconds
Started May 12 12:48:04 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 204304 kb
Host smart-89a59a9b-36a3-4144-8e8d-ea8cd05a5e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259544493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2259544493
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1787858939
Short name T772
Test name
Test status
Simulation time 3043174154 ps
CPU time 26.03 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:26 PM PDT 24
Peak memory 881240 kb
Host smart-14ef6e85-6d0e-4479-8415-2a629c3e3ebb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787858939 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1787858939
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.385503427
Short name T337
Test name
Test status
Simulation time 2559536169 ps
CPU time 20.41 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:22 PM PDT 24
Peak memory 204412 kb
Host smart-ee4ff982-7412-473f-b920-2684ac64d8d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385503427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.385503427
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3780167130
Short name T798
Test name
Test status
Simulation time 4288809192 ps
CPU time 15.14 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:18 PM PDT 24
Peak memory 224832 kb
Host smart-04296efd-992d-4519-bd0a-79cf029bd827
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780167130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3780167130
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2876112816
Short name T882
Test name
Test status
Simulation time 12068708191 ps
CPU time 4.21 seconds
Started May 12 12:47:49 PM PDT 24
Finished May 12 12:47:54 PM PDT 24
Peak memory 204316 kb
Host smart-2e0decf5-3de7-4366-a429-e5947bc1eef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876112816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2876112816
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2068176499
Short name T1088
Test name
Test status
Simulation time 29364422778 ps
CPU time 2142.36 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 01:23:42 PM PDT 24
Peak memory 7287788 kb
Host smart-8d4d96bd-23bf-4644-b1b5-e7f668187822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068176499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2068176499
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1640139738
Short name T356
Test name
Test status
Simulation time 5293073956 ps
CPU time 7.03 seconds
Started May 12 12:47:59 PM PDT 24
Finished May 12 12:48:06 PM PDT 24
Peak memory 204460 kb
Host smart-f6e1173e-6ffa-44a6-872c-70dd29d1fcd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640139738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1640139738
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.885194453
Short name T1191
Test name
Test status
Simulation time 16558839 ps
CPU time 0.64 seconds
Started May 12 12:48:10 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 204088 kb
Host smart-c5556946-00f1-4ab8-9541-3e0264a71830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885194453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.885194453
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2782634358
Short name T1342
Test name
Test status
Simulation time 383480878 ps
CPU time 1.59 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 212748 kb
Host smart-75df06c7-db3d-4385-993a-9c4d2370bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782634358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2782634358
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.856513230
Short name T284
Test name
Test status
Simulation time 1693352108 ps
CPU time 9.92 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 298608 kb
Host smart-3643f945-4848-4674-a6e9-133d54e835a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856513230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.856513230
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2805864815
Short name T624
Test name
Test status
Simulation time 1465091808 ps
CPU time 94.42 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:49:38 PM PDT 24
Peak memory 554632 kb
Host smart-0d128069-127a-4c28-a79a-ccd714d89456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805864815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2805864815
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1350109348
Short name T500
Test name
Test status
Simulation time 7739032222 ps
CPU time 147.42 seconds
Started May 12 12:47:50 PM PDT 24
Finished May 12 12:50:18 PM PDT 24
Peak memory 687396 kb
Host smart-f6387ee5-aa20-4352-bee5-cc7338df16b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350109348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1350109348
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1222256746
Short name T982
Test name
Test status
Simulation time 169728975 ps
CPU time 1.2 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:48:20 PM PDT 24
Peak memory 204232 kb
Host smart-e49240f2-57eb-4b12-a110-21f5d0ff70a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222256746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1222256746
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3917141626
Short name T1114
Test name
Test status
Simulation time 103194585 ps
CPU time 2.45 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 204296 kb
Host smart-d154d1f1-7439-4403-bb92-93d10075fbbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917141626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3917141626
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1094897527
Short name T659
Test name
Test status
Simulation time 16571511504 ps
CPU time 283.74 seconds
Started May 12 12:47:49 PM PDT 24
Finished May 12 12:52:33 PM PDT 24
Peak memory 1031392 kb
Host smart-f84dc0a2-9a55-4aea-b34c-608645c6b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094897527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1094897527
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.180682989
Short name T1118
Test name
Test status
Simulation time 435906858 ps
CPU time 17.49 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 204320 kb
Host smart-4aa41aa6-b242-46bb-a0b4-d3789e0c4283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180682989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.180682989
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1554570189
Short name T460
Test name
Test status
Simulation time 955756588 ps
CPU time 42.13 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 252796 kb
Host smart-afe63cd4-0c1b-43bc-97ba-91102e597ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554570189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1554570189
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2133690398
Short name T50
Test name
Test status
Simulation time 80465568 ps
CPU time 0.64 seconds
Started May 12 12:47:45 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 203956 kb
Host smart-a8c1904c-884c-430c-af48-94dcc8c475ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133690398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2133690398
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1576190449
Short name T440
Test name
Test status
Simulation time 6919211617 ps
CPU time 35.83 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 212528 kb
Host smart-a564dfe3-9707-4b6a-99e4-695eac1f1fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576190449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1576190449
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2223885091
Short name T359
Test name
Test status
Simulation time 1203801524 ps
CPU time 20.1 seconds
Started May 12 12:47:48 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 313948 kb
Host smart-96ae8b61-a3f9-46a3-af4c-94d7d715548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223885091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2223885091
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.4182576286
Short name T63
Test name
Test status
Simulation time 22589493217 ps
CPU time 1006.59 seconds
Started May 12 12:47:54 PM PDT 24
Finished May 12 01:04:41 PM PDT 24
Peak memory 971764 kb
Host smart-749128cc-f3b9-4117-8f1a-48be76bb73c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182576286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.4182576286
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.399210670
Short name T902
Test name
Test status
Simulation time 1053189901 ps
CPU time 10.13 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 214036 kb
Host smart-d3f1da2c-876c-40f9-96ea-c27176f8a844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399210670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.399210670
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.286021207
Short name T1318
Test name
Test status
Simulation time 890768268 ps
CPU time 4.79 seconds
Started May 12 12:47:57 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 212488 kb
Host smart-25162a4c-d744-4c3a-8a4f-de6cfdd2822c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286021207 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.286021207
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2421375420
Short name T34
Test name
Test status
Simulation time 10241378839 ps
CPU time 13.43 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 253948 kb
Host smart-bb65d590-a2e1-462e-9a23-653576dfd21d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421375420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2421375420
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.332411948
Short name T841
Test name
Test status
Simulation time 10113407855 ps
CPU time 68.53 seconds
Started May 12 12:47:51 PM PDT 24
Finished May 12 12:49:00 PM PDT 24
Peak memory 553212 kb
Host smart-0cdf7737-d58f-48f1-82b2-3f53e4add4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332411948 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.332411948
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.324836227
Short name T653
Test name
Test status
Simulation time 487234338 ps
CPU time 2.92 seconds
Started May 12 12:48:01 PM PDT 24
Finished May 12 12:48:05 PM PDT 24
Peak memory 204352 kb
Host smart-c5374291-dcef-493a-b560-3b1dea6b2ae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324836227 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.324836227
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3951876149
Short name T1348
Test name
Test status
Simulation time 5070961659 ps
CPU time 4.43 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 204956 kb
Host smart-250e1ea4-d45f-47de-bd98-ec307c56a802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951876149 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3951876149
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2856725619
Short name T797
Test name
Test status
Simulation time 3311716970 ps
CPU time 6.68 seconds
Started May 12 12:48:04 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 204244 kb
Host smart-ae44c2e6-0d7e-4e76-94fd-3e092e97580d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856725619 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2856725619
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3315640111
Short name T1224
Test name
Test status
Simulation time 673892715 ps
CPU time 10.71 seconds
Started May 12 12:47:51 PM PDT 24
Finished May 12 12:48:02 PM PDT 24
Peak memory 204248 kb
Host smart-754c6933-2930-4f1a-a397-3b9640881dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315640111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3315640111
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1070572588
Short name T1079
Test name
Test status
Simulation time 1208711724 ps
CPU time 53.73 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 204628 kb
Host smart-d95e454b-fec8-4cfd-a67b-f4a11fad5d20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070572588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1070572588
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2482141516
Short name T727
Test name
Test status
Simulation time 24825088066 ps
CPU time 16.97 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:18 PM PDT 24
Peak memory 349032 kb
Host smart-49f174f6-5ab0-4f58-b2d9-710eaffa39e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482141516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2482141516
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2123967131
Short name T48
Test name
Test status
Simulation time 2936894782 ps
CPU time 7.39 seconds
Started May 12 12:48:04 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 212632 kb
Host smart-e456c6f9-75d2-4d6d-83c7-6a372bc7047f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123967131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2123967131
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.801293516
Short name T1123
Test name
Test status
Simulation time 2158304247 ps
CPU time 3.93 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 204304 kb
Host smart-63f43cd6-a0d3-4164-9f86-551258eae576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801293516 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_unexp_stop.801293516
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.26110772
Short name T1097
Test name
Test status
Simulation time 70764637 ps
CPU time 0.6 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:11 PM PDT 24
Peak memory 203968 kb
Host smart-0ae1366c-400d-4c60-a96d-e70af9ba4fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26110772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.26110772
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1585052242
Short name T444
Test name
Test status
Simulation time 83061132 ps
CPU time 1.61 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 212404 kb
Host smart-631c8387-184a-4fc3-8957-dab672a46712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585052242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1585052242
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2702580442
Short name T295
Test name
Test status
Simulation time 577751198 ps
CPU time 7.28 seconds
Started May 12 12:47:55 PM PDT 24
Finished May 12 12:48:02 PM PDT 24
Peak memory 229648 kb
Host smart-ecc0d112-2b47-458c-8c11-09965aaf1b84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702580442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2702580442
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4212678905
Short name T577
Test name
Test status
Simulation time 2551862939 ps
CPU time 189.53 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:51:13 PM PDT 24
Peak memory 813920 kb
Host smart-a2c712eb-227d-4872-8c95-86f4c69c4a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212678905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4212678905
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3215304908
Short name T468
Test name
Test status
Simulation time 1384966205 ps
CPU time 98.58 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:49:42 PM PDT 24
Peak memory 547968 kb
Host smart-993b5c2d-5393-43a6-9010-aab231d287ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215304908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3215304908
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2550443073
Short name T1162
Test name
Test status
Simulation time 884663749 ps
CPU time 0.89 seconds
Started May 12 12:47:55 PM PDT 24
Finished May 12 12:47:56 PM PDT 24
Peak memory 204084 kb
Host smart-f609b7cd-694e-4c5e-865e-4b4266f41a63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550443073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2550443073
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3121215349
Short name T1122
Test name
Test status
Simulation time 1826901460 ps
CPU time 3.28 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:48:22 PM PDT 24
Peak memory 204352 kb
Host smart-7987f303-1f47-423a-b958-b494f18fcc77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121215349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3121215349
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2625398431
Short name T99
Test name
Test status
Simulation time 6179539660 ps
CPU time 87.96 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 1082596 kb
Host smart-81493101-8afd-4773-83bb-5905169efb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625398431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2625398431
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3612753852
Short name T969
Test name
Test status
Simulation time 1129539029 ps
CPU time 5.29 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 204384 kb
Host smart-33b40089-1bbe-4b85-abca-7879a76afe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612753852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3612753852
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3399586824
Short name T115
Test name
Test status
Simulation time 23127064357 ps
CPU time 25.5 seconds
Started May 12 12:47:56 PM PDT 24
Finished May 12 12:48:22 PM PDT 24
Peak memory 345636 kb
Host smart-821703b7-b713-4dae-8a30-0bd756a82e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399586824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3399586824
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3805037847
Short name T1283
Test name
Test status
Simulation time 579948984 ps
CPU time 3.76 seconds
Started May 12 12:47:53 PM PDT 24
Finished May 12 12:47:58 PM PDT 24
Peak memory 231292 kb
Host smart-ada4a269-8ad2-4380-938f-1d261c3a6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805037847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3805037847
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4200225025
Short name T807
Test name
Test status
Simulation time 2021246304 ps
CPU time 19.78 seconds
Started May 12 12:47:49 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 297572 kb
Host smart-0baddf2a-5c7b-43cc-9879-0f3ae1ecf62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200225025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4200225025
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.4186944388
Short name T238
Test name
Test status
Simulation time 35103851904 ps
CPU time 1054.33 seconds
Started May 12 12:48:05 PM PDT 24
Finished May 12 01:05:41 PM PDT 24
Peak memory 3012000 kb
Host smart-3be4abca-267e-4f10-a723-d61faea5b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186944388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.4186944388
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2853013323
Short name T383
Test name
Test status
Simulation time 1909897580 ps
CPU time 23.74 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 212796 kb
Host smart-a8985207-f4ef-4f42-80f8-966a60accd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853013323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2853013323
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.353895450
Short name T1189
Test name
Test status
Simulation time 2152129092 ps
CPU time 3.08 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:10 PM PDT 24
Peak memory 204376 kb
Host smart-d9758258-ac0d-4216-b6f4-9cb6317b130b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353895450 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.353895450
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1510625229
Short name T913
Test name
Test status
Simulation time 10178774258 ps
CPU time 33.54 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 339336 kb
Host smart-85e533b7-de34-4103-aaa0-89259f7d8fab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510625229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1510625229
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1954437704
Short name T729
Test name
Test status
Simulation time 10076687063 ps
CPU time 73.4 seconds
Started May 12 12:48:05 PM PDT 24
Finished May 12 12:49:19 PM PDT 24
Peak memory 477772 kb
Host smart-2628ca21-91a9-428c-8cf0-d5330dddf239
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954437704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1954437704
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.384737785
Short name T25
Test name
Test status
Simulation time 1662887399 ps
CPU time 2.7 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:05 PM PDT 24
Peak memory 204284 kb
Host smart-06020cb3-5c59-4e76-b43f-4b1d38a4833e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384737785 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.384737785
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2096002316
Short name T542
Test name
Test status
Simulation time 4310333397 ps
CPU time 5.31 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:08 PM PDT 24
Peak memory 212596 kb
Host smart-d4d21dd0-2a8c-48f2-9d1c-5f6793a88a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096002316 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2096002316
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2992966632
Short name T1003
Test name
Test status
Simulation time 15517184987 ps
CPU time 288.82 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:52:50 PM PDT 24
Peak memory 3642904 kb
Host smart-1e062a46-44d4-4f04-914c-e5dc2cb87895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992966632 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2992966632
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3114220332
Short name T618
Test name
Test status
Simulation time 1350430111 ps
CPU time 21.24 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 204272 kb
Host smart-d19b468b-b19f-45c3-9c2d-f30683c0c7fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114220332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3114220332
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.804111702
Short name T1336
Test name
Test status
Simulation time 5589350695 ps
CPU time 44.46 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:49 PM PDT 24
Peak memory 204532 kb
Host smart-fb6ef23a-f064-441f-938e-7722898a539f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804111702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.804111702
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.275399773
Short name T1084
Test name
Test status
Simulation time 11484265016 ps
CPU time 6.99 seconds
Started May 12 12:48:00 PM PDT 24
Finished May 12 12:48:07 PM PDT 24
Peak memory 204380 kb
Host smart-c06eb1b4-c3de-4dd0-881e-4e6218e3605d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275399773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.275399773
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2430611142
Short name T861
Test name
Test status
Simulation time 3109795590 ps
CPU time 7.39 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 212552 kb
Host smart-78db3579-588c-4600-a79f-ee1259585536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430611142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2430611142
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2893445474
Short name T299
Test name
Test status
Simulation time 33877926 ps
CPU time 0.61 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:03 PM PDT 24
Peak memory 204072 kb
Host smart-b9b8da9d-1cb4-4671-8211-0039bec34f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893445474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2893445474
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.335713674
Short name T116
Test name
Test status
Simulation time 221663982 ps
CPU time 1.26 seconds
Started May 12 12:48:14 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 212768 kb
Host smart-b81ae79b-0bc0-4270-bab2-2810b9e74d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335713674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.335713674
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.396556212
Short name T1198
Test name
Test status
Simulation time 1606857840 ps
CPU time 7.75 seconds
Started May 12 12:48:11 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 289820 kb
Host smart-33027949-109c-45b2-8a8d-e476069668f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396556212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.396556212
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3404626005
Short name T905
Test name
Test status
Simulation time 6464492640 ps
CPU time 84.63 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 212596 kb
Host smart-6f003148-c4a0-44d3-8006-51ad23b3a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404626005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3404626005
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2715356171
Short name T634
Test name
Test status
Simulation time 8300665728 ps
CPU time 72.75 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 670484 kb
Host smart-2fc76ab6-34a3-43d8-a11a-d707a81dd2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715356171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2715356171
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.97899449
Short name T1220
Test name
Test status
Simulation time 534191697 ps
CPU time 1.02 seconds
Started May 12 12:48:13 PM PDT 24
Finished May 12 12:48:15 PM PDT 24
Peak memory 204004 kb
Host smart-091982b1-653c-415a-bac2-db89cab0e883
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97899449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt
.97899449
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.159811629
Short name T407
Test name
Test status
Simulation time 126329343 ps
CPU time 6.42 seconds
Started May 12 12:48:08 PM PDT 24
Finished May 12 12:48:15 PM PDT 24
Peak memory 222356 kb
Host smart-3bee4180-3c49-43ee-84c6-d68aca31f271
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159811629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
159811629
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1192609020
Short name T265
Test name
Test status
Simulation time 4408522456 ps
CPU time 141.76 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:50:38 PM PDT 24
Peak memory 1301588 kb
Host smart-eae5d2f6-cc95-4270-80e8-116277edb52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192609020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1192609020
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1621201062
Short name T381
Test name
Test status
Simulation time 1905321518 ps
CPU time 8.02 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:14 PM PDT 24
Peak memory 204236 kb
Host smart-9de52c2b-dcf1-4542-a1ed-48b905bf8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621201062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1621201062
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1571116101
Short name T697
Test name
Test status
Simulation time 2243851509 ps
CPU time 21.18 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 350544 kb
Host smart-9da618ed-f607-459e-bc00-9cde64e32e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571116101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1571116101
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.1067635526
Short name T601
Test name
Test status
Simulation time 49054109 ps
CPU time 0.68 seconds
Started May 12 12:48:02 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 203852 kb
Host smart-d01a957a-92c4-44a5-a407-f5a503654838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067635526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1067635526
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.635663042
Short name T527
Test name
Test status
Simulation time 2539845476 ps
CPU time 26.45 seconds
Started May 12 12:48:11 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 226528 kb
Host smart-71b38eb5-006b-4c2f-b605-f1004c4cf861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635663042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.635663042
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1844011639
Short name T921
Test name
Test status
Simulation time 5984425236 ps
CPU time 26.93 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:31 PM PDT 24
Peak memory 347240 kb
Host smart-5c71fd13-3d97-4b67-8f85-5790cd757fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844011639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1844011639
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2968144622
Short name T1156
Test name
Test status
Simulation time 76088315932 ps
CPU time 1623.89 seconds
Started May 12 12:48:04 PM PDT 24
Finished May 12 01:15:09 PM PDT 24
Peak memory 3851168 kb
Host smart-c2a13b52-780f-477a-83a8-1f38be1042a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968144622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2968144622
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.4034021820
Short name T642
Test name
Test status
Simulation time 1732268959 ps
CPU time 20.39 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:25 PM PDT 24
Peak memory 212412 kb
Host smart-e924051a-f868-4209-90a6-c89dd5185791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034021820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.4034021820
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3842461576
Short name T461
Test name
Test status
Simulation time 2216784495 ps
CPU time 2.3 seconds
Started May 12 12:48:07 PM PDT 24
Finished May 12 12:48:10 PM PDT 24
Peak memory 204512 kb
Host smart-d29ca67e-727e-4e2b-beb2-fe103bb3e2a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842461576 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3842461576
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.849261416
Short name T70
Test name
Test status
Simulation time 10107180334 ps
CPU time 73.2 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 491596 kb
Host smart-44bdb6e6-a0ed-4742-9754-3270dab9764c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849261416 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.849261416
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2591346624
Short name T1177
Test name
Test status
Simulation time 10041661170 ps
CPU time 83.61 seconds
Started May 12 12:48:05 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 504612 kb
Host smart-1b78431e-3a10-4cab-b617-f33fba3802df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591346624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2591346624
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1122966635
Short name T899
Test name
Test status
Simulation time 553523860 ps
CPU time 2.72 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:25 PM PDT 24
Peak memory 204296 kb
Host smart-a73cbc0e-818f-47a7-8067-9d47e09b8f2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122966635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1122966635
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4111474752
Short name T863
Test name
Test status
Simulation time 2885340208 ps
CPU time 3.81 seconds
Started May 12 12:48:11 PM PDT 24
Finished May 12 12:48:15 PM PDT 24
Peak memory 204336 kb
Host smart-b139ac7d-5c99-49da-8421-438409edbdc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111474752 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4111474752
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.835900285
Short name T1062
Test name
Test status
Simulation time 19338047991 ps
CPU time 44.31 seconds
Started May 12 12:48:15 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 1081232 kb
Host smart-d9db7e7c-0926-4ec7-bbc1-0302efc59d7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835900285 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.835900285
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2479017046
Short name T1190
Test name
Test status
Simulation time 1124420657 ps
CPU time 11.31 seconds
Started May 12 12:48:03 PM PDT 24
Finished May 12 12:48:15 PM PDT 24
Peak memory 204084 kb
Host smart-de5b00fc-70c8-4053-9168-14aad1ce2362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479017046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2479017046
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3621860965
Short name T812
Test name
Test status
Simulation time 1766491152 ps
CPU time 15.96 seconds
Started May 12 12:48:07 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 204292 kb
Host smart-c3877b37-4b4f-40cb-8717-25cf3e8e25ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621860965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3621860965
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.602897331
Short name T662
Test name
Test status
Simulation time 23586354346 ps
CPU time 15.46 seconds
Started May 12 12:48:08 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 280284 kb
Host smart-b4fe31e4-e16d-4389-b99c-1c023a72ac41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602897331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.602897331
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.133682081
Short name T418
Test name
Test status
Simulation time 5253253026 ps
CPU time 31.57 seconds
Started May 12 12:48:20 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 314800 kb
Host smart-f1c8ccac-d0be-47b1-b9b6-9a119a863cd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133682081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.133682081
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1242368556
Short name T664
Test name
Test status
Simulation time 3187081052 ps
CPU time 7.73 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 218764 kb
Host smart-c0fc79a3-3274-4d50-9f42-43647ea76213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242368556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1242368556
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1069281772
Short name T884
Test name
Test status
Simulation time 173475000 ps
CPU time 0.64 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 204100 kb
Host smart-ac9bb7ee-4734-4176-b4c1-a79ad1f78928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069281772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1069281772
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3489068426
Short name T590
Test name
Test status
Simulation time 108558197 ps
CPU time 1.64 seconds
Started May 12 12:48:14 PM PDT 24
Finished May 12 12:48:16 PM PDT 24
Peak memory 212640 kb
Host smart-f5eef0bc-6b5a-4025-b6e1-9b8787b63118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489068426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3489068426
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3190796926
Short name T1046
Test name
Test status
Simulation time 1477566092 ps
CPU time 6.7 seconds
Started May 12 12:48:10 PM PDT 24
Finished May 12 12:48:17 PM PDT 24
Peak memory 267584 kb
Host smart-dc84ae19-58c0-4f7e-ad60-34e4a7d00729
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190796926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3190796926
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2539077983
Short name T1352
Test name
Test status
Simulation time 10002860433 ps
CPU time 88.12 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:49:38 PM PDT 24
Peak memory 649540 kb
Host smart-19ea9fb4-bfae-4087-a48c-bda43d51b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539077983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2539077983
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1019498421
Short name T344
Test name
Test status
Simulation time 17003373282 ps
CPU time 30.14 seconds
Started May 12 12:48:11 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 443412 kb
Host smart-673f26bf-a086-47e3-9e10-7d0c2126cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019498421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1019498421
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3193627027
Short name T606
Test name
Test status
Simulation time 230792711 ps
CPU time 0.85 seconds
Started May 12 12:48:07 PM PDT 24
Finished May 12 12:48:09 PM PDT 24
Peak memory 204040 kb
Host smart-e54ad6af-4090-469f-bede-6a002c762e8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193627027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3193627027
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.4033739195
Short name T1069
Test name
Test status
Simulation time 520773241 ps
CPU time 6.61 seconds
Started May 12 12:48:12 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 204376 kb
Host smart-4bb7edab-a5c7-450b-84b4-c6af80b037a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033739195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.4033739195
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.352856967
Short name T1143
Test name
Test status
Simulation time 9251445755 ps
CPU time 44.23 seconds
Started May 12 12:48:06 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 663128 kb
Host smart-bf835f2f-8cd7-40ed-8ae4-003fa971b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352856967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.352856967
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1163163474
Short name T813
Test name
Test status
Simulation time 981609388 ps
CPU time 27.08 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 204376 kb
Host smart-567d151f-f150-40f0-bb39-804448928bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163163474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1163163474
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2104230461
Short name T42
Test name
Test status
Simulation time 5126606033 ps
CPU time 41.53 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:49:00 PM PDT 24
Peak memory 378996 kb
Host smart-a5cc7704-d201-4c4a-810a-b59bedb02d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104230461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2104230461
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3320873966
Short name T844
Test name
Test status
Simulation time 109591577 ps
CPU time 0.65 seconds
Started May 12 12:48:12 PM PDT 24
Finished May 12 12:48:13 PM PDT 24
Peak memory 203908 kb
Host smart-5840c167-2bd8-4896-b7b6-c552f18d2d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320873966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3320873966
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3988834159
Short name T516
Test name
Test status
Simulation time 11516385245 ps
CPU time 168.33 seconds
Started May 12 12:48:07 PM PDT 24
Finished May 12 12:50:56 PM PDT 24
Peak memory 606540 kb
Host smart-d9aac723-bf76-4c0b-8529-bceefe967ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988834159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3988834159
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3065430211
Short name T476
Test name
Test status
Simulation time 7046117430 ps
CPU time 32.97 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:48:49 PM PDT 24
Peak memory 385156 kb
Host smart-4efaea4a-4ba4-4053-a828-a445ced4ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065430211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3065430211
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2370920540
Short name T123
Test name
Test status
Simulation time 9282321793 ps
CPU time 296.75 seconds
Started May 12 12:48:11 PM PDT 24
Finished May 12 12:53:08 PM PDT 24
Peak memory 1768472 kb
Host smart-1c43a2a4-0124-4405-8db3-a2ad75d2e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370920540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2370920540
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2798090009
Short name T1197
Test name
Test status
Simulation time 5172175105 ps
CPU time 16.99 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:27 PM PDT 24
Peak memory 218644 kb
Host smart-e1c2b45e-bc69-4a1e-945c-5fe53f265467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798090009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2798090009
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2728732054
Short name T428
Test name
Test status
Simulation time 2044666812 ps
CPU time 4.84 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 204356 kb
Host smart-08d9cd86-3b02-494a-8140-b0f3def14c13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728732054 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2728732054
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3828435153
Short name T308
Test name
Test status
Simulation time 10061457445 ps
CPU time 75.85 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:49:41 PM PDT 24
Peak memory 466220 kb
Host smart-4faa954d-3ed2-4a4c-9755-e1f6511bb500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828435153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3828435153
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1101700553
Short name T271
Test name
Test status
Simulation time 10207884977 ps
CPU time 26.52 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 306820 kb
Host smart-322d6792-5998-49b5-add9-8cd196f88ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101700553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1101700553
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2688597815
Short name T1355
Test name
Test status
Simulation time 549094024 ps
CPU time 3.18 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:26 PM PDT 24
Peak memory 204256 kb
Host smart-61d4176a-124e-4d22-a32f-1d96edfe60f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688597815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2688597815
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.292120512
Short name T1213
Test name
Test status
Simulation time 1618878885 ps
CPU time 2.5 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 204360 kb
Host smart-823aa2ff-a7a6-4397-a353-c920b47f4626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292120512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.292120512
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.4149145695
Short name T456
Test name
Test status
Simulation time 13328907022 ps
CPU time 16.87 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 419800 kb
Host smart-a527fd3d-8271-43e8-86f5-402fdd863d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149145695 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.4149145695
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2135411348
Short name T1238
Test name
Test status
Simulation time 8049503558 ps
CPU time 20.58 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 204352 kb
Host smart-0bcd7911-4ce8-4390-8130-d9b88fff35c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135411348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2135411348
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3283741578
Short name T526
Test name
Test status
Simulation time 1083030483 ps
CPU time 19.62 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 217932 kb
Host smart-716ded39-4d08-4187-ba9b-dcc5a377046a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283741578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3283741578
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1787867803
Short name T999
Test name
Test status
Simulation time 16780857100 ps
CPU time 9.23 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:19 PM PDT 24
Peak memory 204324 kb
Host smart-0ba3aea4-1588-4742-a1cd-ed788c9b1d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787867803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1787867803
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3504380215
Short name T787
Test name
Test status
Simulation time 9296881125 ps
CPU time 110.76 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:50:10 PM PDT 24
Peak memory 575464 kb
Host smart-1e18e274-99da-4649-9552-2b79b066a5dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504380215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3504380215
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.106521940
Short name T997
Test name
Test status
Simulation time 4186989427 ps
CPU time 6.52 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 220284 kb
Host smart-35761436-d5e7-4690-9377-af988f197152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106521940 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.106521940
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3757088195
Short name T436
Test name
Test status
Simulation time 26857362 ps
CPU time 0.6 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 204100 kb
Host smart-be08b077-1537-44a9-8728-94b0ddf4adc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757088195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3757088195
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.49377683
Short name T276
Test name
Test status
Simulation time 893778330 ps
CPU time 1.67 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:25 PM PDT 24
Peak memory 204400 kb
Host smart-7c098145-ecca-4d9b-ace7-bda6c2fcd4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49377683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.49377683
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2664916291
Short name T480
Test name
Test status
Simulation time 270381233 ps
CPU time 6.26 seconds
Started May 12 12:48:15 PM PDT 24
Finished May 12 12:48:22 PM PDT 24
Peak memory 261128 kb
Host smart-211726f5-f3aa-4e06-880f-ede0d56285c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664916291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2664916291
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.662779757
Short name T663
Test name
Test status
Simulation time 4694931555 ps
CPU time 28.46 seconds
Started May 12 12:48:16 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 403460 kb
Host smart-dc921a68-66d4-4ef9-aa2d-79b52aea3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662779757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.662779757
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.4038066167
Short name T502
Test name
Test status
Simulation time 1345690809 ps
CPU time 87.55 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:49:52 PM PDT 24
Peak memory 488880 kb
Host smart-a69fdcb4-fe66-434a-809c-51a904b0fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038066167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.4038066167
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1941407507
Short name T1279
Test name
Test status
Simulation time 72765054 ps
CPU time 0.76 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:48:21 PM PDT 24
Peak memory 204076 kb
Host smart-26c21306-4594-4b58-aa31-6d3aac159e1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941407507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1941407507
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1845811246
Short name T1201
Test name
Test status
Simulation time 118590660 ps
CPU time 6.23 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 220116 kb
Host smart-2f268c58-6b92-46b5-bde8-1fb70ad6409b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845811246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1845811246
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3704508088
Short name T1096
Test name
Test status
Simulation time 15753505425 ps
CPU time 120.16 seconds
Started May 12 12:48:13 PM PDT 24
Finished May 12 12:50:13 PM PDT 24
Peak memory 1144292 kb
Host smart-85c20110-bd14-4885-b54d-1efbb49f13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704508088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3704508088
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2686702164
Short name T240
Test name
Test status
Simulation time 400931840 ps
CPU time 5.14 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 204320 kb
Host smart-80238ef0-b069-4641-ad89-b1a1b2b37538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686702164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2686702164
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2366966186
Short name T246
Test name
Test status
Simulation time 6689900023 ps
CPU time 27.62 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 349364 kb
Host smart-ba427b62-1370-4ab9-9fc3-a59866ee3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366966186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2366966186
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1950965445
Short name T1257
Test name
Test status
Simulation time 56598479 ps
CPU time 0.65 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:48:20 PM PDT 24
Peak memory 204144 kb
Host smart-c48cfdd4-4584-4c38-9ec0-991acb378ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950965445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1950965445
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.929481262
Short name T802
Test name
Test status
Simulation time 13304179466 ps
CPU time 103.28 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:50:16 PM PDT 24
Peak memory 731092 kb
Host smart-52839932-524f-485f-a3b1-811c5035f8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929481262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.929481262
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3896658955
Short name T936
Test name
Test status
Simulation time 8846262098 ps
CPU time 18.11 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 293768 kb
Host smart-7562ddc5-46df-4c20-b044-e111aa005aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896658955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3896658955
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1562266733
Short name T1044
Test name
Test status
Simulation time 16841309526 ps
CPU time 548.36 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 1800780 kb
Host smart-2e5b6a0d-25d7-4e9e-87a3-a6bfcff6e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562266733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1562266733
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1102110105
Short name T179
Test name
Test status
Simulation time 1112852754 ps
CPU time 9.9 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 220704 kb
Host smart-bdd87d7b-1c2e-4d5f-8f8c-fe5aaa5247c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102110105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1102110105
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.207538087
Short name T784
Test name
Test status
Simulation time 975578517 ps
CPU time 4.69 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:27 PM PDT 24
Peak memory 212468 kb
Host smart-ac6abbca-43a8-49fd-aaa3-91264ac04a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207538087 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.207538087
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2520832693
Short name T415
Test name
Test status
Simulation time 10153323770 ps
CPU time 32.49 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:49:03 PM PDT 24
Peak memory 377900 kb
Host smart-1b3692bf-ef98-4d46-bb3f-3cc61165b2a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520832693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2520832693
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3416462434
Short name T588
Test name
Test status
Simulation time 10219823809 ps
CPU time 11.94 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 277284 kb
Host smart-70b70dc7-a64b-4ddb-9737-f957f5ec7c61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416462434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3416462434
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.190074929
Short name T1007
Test name
Test status
Simulation time 2389420967 ps
CPU time 3.23 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 204428 kb
Host smart-b8676582-8b6a-4618-8425-884b35556a8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190074929 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.190074929
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1790262085
Short name T1235
Test name
Test status
Simulation time 9758020469 ps
CPU time 5.1 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 212480 kb
Host smart-463c32e5-becb-482e-b6ee-7429efc0cbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790262085 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1790262085
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1464569688
Short name T912
Test name
Test status
Simulation time 27088692140 ps
CPU time 69.08 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 1516112 kb
Host smart-3246f559-f7ff-4c9c-973a-2740e4681177
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464569688 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1464569688
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.912144492
Short name T463
Test name
Test status
Simulation time 4510586768 ps
CPU time 19.49 seconds
Started May 12 12:48:20 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 204428 kb
Host smart-29465a68-2037-476f-9f2f-b68686f34350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912144492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.912144492
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2502218749
Short name T1008
Test name
Test status
Simulation time 4776639956 ps
CPU time 16.08 seconds
Started May 12 12:48:09 PM PDT 24
Finished May 12 12:48:26 PM PDT 24
Peak memory 228696 kb
Host smart-f33a832a-2a36-46ca-a5f6-71133b0cf9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502218749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2502218749
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1919842727
Short name T581
Test name
Test status
Simulation time 64930854079 ps
CPU time 2323.19 seconds
Started May 12 12:48:10 PM PDT 24
Finished May 12 01:26:54 PM PDT 24
Peak memory 11334448 kb
Host smart-1f084e7d-d3b8-4c64-bcb6-6ce06a6c0721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919842727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1919842727
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1771706491
Short name T272
Test name
Test status
Simulation time 27028951600 ps
CPU time 180.34 seconds
Started May 12 12:48:10 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 1564420 kb
Host smart-f39274ec-d222-462c-8b7f-d9c393c90163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771706491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1771706491
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.971724924
Short name T597
Test name
Test status
Simulation time 1297444151 ps
CPU time 7.13 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 219140 kb
Host smart-0fe37dc2-3843-414c-9bfe-3db75263d9d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971724924 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.971724924
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1561651358
Short name T736
Test name
Test status
Simulation time 18400097 ps
CPU time 0.64 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 204396 kb
Host smart-a2d3b857-410f-44e4-b970-4cab2b676fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561651358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1561651358
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.4133356476
Short name T625
Test name
Test status
Simulation time 275350806 ps
CPU time 1.24 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:23 PM PDT 24
Peak memory 212696 kb
Host smart-a2970dfa-c83c-4e4e-877a-b9e55d1d28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133356476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.4133356476
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3305014283
Short name T794
Test name
Test status
Simulation time 1869313115 ps
CPU time 7.28 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 271908 kb
Host smart-ddb9bfc9-7d59-4932-8c53-f1f2834d0fdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305014283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3305014283
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.3482790384
Short name T1150
Test name
Test status
Simulation time 9891537167 ps
CPU time 65.07 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 603696 kb
Host smart-e83b6752-2829-4903-8986-0b24b57e36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482790384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.3482790384
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1531019781
Short name T402
Test name
Test status
Simulation time 5432922820 ps
CPU time 66.8 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 448568 kb
Host smart-ebc030ad-1764-4559-878b-9290ad924595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531019781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1531019781
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1810680890
Short name T673
Test name
Test status
Simulation time 275589329 ps
CPU time 1.05 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 204144 kb
Host smart-cb2a41a6-d008-4480-9460-0c70223745c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810680890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1810680890
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.562146793
Short name T328
Test name
Test status
Simulation time 143819366 ps
CPU time 7.04 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 204316 kb
Host smart-dc25783d-2822-4ed2-923e-c41883b18da4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562146793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
562146793
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1825384710
Short name T102
Test name
Test status
Simulation time 19267099997 ps
CPU time 123.42 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:50:27 PM PDT 24
Peak memory 1357000 kb
Host smart-8d366898-2d59-4985-af69-ac35f8fbf52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825384710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1825384710
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.260016118
Short name T717
Test name
Test status
Simulation time 977652618 ps
CPU time 10.1 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 204084 kb
Host smart-70c5e676-60a3-4b2f-94fc-46a984e25c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260016118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.260016118
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.490077957
Short name T37
Test name
Test status
Simulation time 6908523297 ps
CPU time 81.03 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:49:59 PM PDT 24
Peak memory 366160 kb
Host smart-6711eb72-9921-457d-a6bb-a7da2c953396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490077957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.490077957
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.4223254103
Short name T1286
Test name
Test status
Simulation time 35453716 ps
CPU time 0.68 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:22 PM PDT 24
Peak memory 204036 kb
Host smart-a50c244a-6a9e-400c-8fd3-618fbce3bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223254103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.4223254103
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1169885986
Short name T40
Test name
Test status
Simulation time 2714291764 ps
CPU time 38.16 seconds
Started May 12 12:48:25 PM PDT 24
Finished May 12 12:49:05 PM PDT 24
Peak memory 234344 kb
Host smart-d9e1c0b6-0501-47a2-9964-15d249fa705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169885986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1169885986
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2822811331
Short name T1168
Test name
Test status
Simulation time 1502512586 ps
CPU time 27.24 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:56 PM PDT 24
Peak memory 351136 kb
Host smart-c4e7a4a7-4d67-4205-9861-f6aa76ce16f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822811331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2822811331
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1361114972
Short name T1327
Test name
Test status
Simulation time 27597917540 ps
CPU time 813.71 seconds
Started May 12 12:48:25 PM PDT 24
Finished May 12 01:02:01 PM PDT 24
Peak memory 1397944 kb
Host smart-bd218902-3411-4f71-8e70-c255e55524d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361114972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1361114972
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3910320805
Short name T1050
Test name
Test status
Simulation time 874999506 ps
CPU time 8.46 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 212772 kb
Host smart-484e671d-5b42-426f-8897-d1772776f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910320805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3910320805
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1029147784
Short name T351
Test name
Test status
Simulation time 1034931856 ps
CPU time 4.44 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 212488 kb
Host smart-fe846349-457a-4d33-abd5-2987187b5c11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029147784 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1029147784
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3710396097
Short name T454
Test name
Test status
Simulation time 10043798493 ps
CPU time 70.27 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:49:41 PM PDT 24
Peak memory 485244 kb
Host smart-87c0a501-f273-4477-8361-952edadb62db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710396097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3710396097
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2924372911
Short name T1098
Test name
Test status
Simulation time 10076256537 ps
CPU time 17.57 seconds
Started May 12 12:48:20 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 309384 kb
Host smart-0deb9829-d810-4105-b47b-c148ce51c9cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924372911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2924372911
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.313881950
Short name T1328
Test name
Test status
Simulation time 2105388814 ps
CPU time 2.9 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 204484 kb
Host smart-abadcb3b-705e-4662-a0e5-2f1482115e9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313881950 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.313881950
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1152953098
Short name T702
Test name
Test status
Simulation time 1193487024 ps
CPU time 6.31 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:48:35 PM PDT 24
Peak memory 214312 kb
Host smart-0ea5d354-fe3b-4ff3-a216-7aa1792ec04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152953098 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1152953098
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4268580798
Short name T573
Test name
Test status
Simulation time 13551272714 ps
CPU time 14.67 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 377528 kb
Host smart-031a8968-529a-4540-ada7-be7f27f2cef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268580798 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4268580798
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.350170685
Short name T1041
Test name
Test status
Simulation time 2226153595 ps
CPU time 16.42 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 204308 kb
Host smart-2a6c0873-28ca-43ce-8e18-75fd545ef973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350170685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.350170685
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2582613832
Short name T887
Test name
Test status
Simulation time 700157674 ps
CPU time 30.54 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 204248 kb
Host smart-2f7d6ceb-8c6a-4d2e-9ee3-c72a0be7ee93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582613832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2582613832
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3897376328
Short name T917
Test name
Test status
Simulation time 15285392744 ps
CPU time 28.47 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 204308 kb
Host smart-4cba63cc-1704-46f5-83e5-bde00676466e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897376328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3897376328
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2647406543
Short name T683
Test name
Test status
Simulation time 17767076972 ps
CPU time 1270.31 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 01:09:38 PM PDT 24
Peak memory 4413292 kb
Host smart-b80e1700-a987-40b4-8a7b-f9214c99ed39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647406543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2647406543
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2748889444
Short name T961
Test name
Test status
Simulation time 5024113163 ps
CPU time 6.79 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 220620 kb
Host smart-698830d7-9d9a-405a-aad7-641ec099bebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748889444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2748889444
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.831736254
Short name T694
Test name
Test status
Simulation time 18260032 ps
CPU time 0.62 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 204092 kb
Host smart-bc04aab4-5b1f-49ce-a4ef-b6d45cc7fa4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831736254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.831736254
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2132316773
Short name T1181
Test name
Test status
Simulation time 122581224 ps
CPU time 1.65 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 212572 kb
Host smart-04d12e94-f036-43e4-9642-ec9cf04f141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132316773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2132316773
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3320191485
Short name T345
Test name
Test status
Simulation time 396490639 ps
CPU time 19.83 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 288120 kb
Host smart-90a0ad56-5329-4229-8eca-a2d03e020d75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320191485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3320191485
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.538541457
Short name T785
Test name
Test status
Simulation time 2145732316 ps
CPU time 71.74 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:49:34 PM PDT 24
Peak memory 666044 kb
Host smart-568d3811-7d95-48e5-b490-e72af38a6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538541457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.538541457
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3644517239
Short name T517
Test name
Test status
Simulation time 8052854614 ps
CPU time 133.24 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:50:40 PM PDT 24
Peak memory 554272 kb
Host smart-1de68bcf-de81-4d09-9be8-7e6511fd03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644517239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3644517239
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2619845538
Short name T567
Test name
Test status
Simulation time 917318411 ps
CPU time 1.13 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 204612 kb
Host smart-8384a07b-8f9c-4406-a05f-c95bd6110cfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619845538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2619845538
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2971543500
Short name T424
Test name
Test status
Simulation time 169865175 ps
CPU time 4.01 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 232760 kb
Host smart-bb12561c-1616-4b0c-8bd9-d9032b0ffa8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971543500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2971543500
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3578528955
Short name T529
Test name
Test status
Simulation time 7786492837 ps
CPU time 82.21 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:49:53 PM PDT 24
Peak memory 919892 kb
Host smart-3cf27c4f-3aca-43a3-9d8b-dfcad0936db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578528955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3578528955
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1207297648
Short name T490
Test name
Test status
Simulation time 2882268953 ps
CPU time 6.92 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 204352 kb
Host smart-9cc90154-0acd-44fc-8786-a5a3e828975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207297648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1207297648
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.574927522
Short name T1272
Test name
Test status
Simulation time 1291822994 ps
CPU time 24.63 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 289468 kb
Host smart-e90b817b-8334-4c8e-befe-cd7fbb1401fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574927522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.574927522
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4214717139
Short name T990
Test name
Test status
Simulation time 35227093 ps
CPU time 0.63 seconds
Started May 12 12:48:25 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 203956 kb
Host smart-76d43def-4e14-41e9-a69e-f9a286115894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214717139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4214717139
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2521847258
Short name T1214
Test name
Test status
Simulation time 6421798538 ps
CPU time 605.83 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:58:29 PM PDT 24
Peak memory 1628172 kb
Host smart-7b5c4e2f-3000-40ac-9557-e5598ad61a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521847258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2521847258
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1688702638
Short name T898
Test name
Test status
Simulation time 11718748796 ps
CPU time 20.59 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 301552 kb
Host smart-bd7ea102-8c40-40e9-9d30-1757011e693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688702638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1688702638
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.4069333367
Short name T570
Test name
Test status
Simulation time 716239095 ps
CPU time 34.61 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 212544 kb
Host smart-7853b99b-8836-4fec-93fd-9eebe83fd55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069333367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4069333367
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2983144456
Short name T29
Test name
Test status
Simulation time 1187262278 ps
CPU time 3.03 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 204304 kb
Host smart-8fd5d173-4db0-426e-a980-c24d15e4128e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983144456 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2983144456
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2463588120
Short name T937
Test name
Test status
Simulation time 10608627101 ps
CPU time 15.11 seconds
Started May 12 12:48:20 PM PDT 24
Finished May 12 12:48:36 PM PDT 24
Peak memory 247416 kb
Host smart-bd4b7dae-4c63-4118-bc49-582b13bfc2f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463588120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2463588120
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3382420154
Short name T65
Test name
Test status
Simulation time 10049749701 ps
CPU time 73.64 seconds
Started May 12 12:48:18 PM PDT 24
Finished May 12 12:49:33 PM PDT 24
Peak memory 557304 kb
Host smart-71c41d3e-9a8b-439b-aa4b-f6ea6b252ef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382420154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3382420154
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.394882098
Short name T649
Test name
Test status
Simulation time 605316852 ps
CPU time 3.41 seconds
Started May 12 12:48:25 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 204408 kb
Host smart-f3babe99-3ef5-4811-a315-28b2779cae4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394882098 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.394882098
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.242141406
Short name T482
Test name
Test status
Simulation time 2297217807 ps
CPU time 5.89 seconds
Started May 12 12:48:30 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 205264 kb
Host smart-aac66205-c6fd-47a4-9108-cd43a45b89a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242141406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.242141406
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2350128113
Short name T1313
Test name
Test status
Simulation time 14152540089 ps
CPU time 256.87 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 3448812 kb
Host smart-e0187d72-6d8c-4216-a55c-3b26715b445d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350128113 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2350128113
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1506658595
Short name T1358
Test name
Test status
Simulation time 1439496644 ps
CPU time 9.6 seconds
Started May 12 12:48:19 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 204164 kb
Host smart-a36053de-949a-4272-9795-2c8a5942ca5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506658595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1506658595
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.4006869315
Short name T1262
Test name
Test status
Simulation time 9217967812 ps
CPU time 23.43 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 231944 kb
Host smart-75ae82ea-795f-47ce-9ecd-92a16d8ab3cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006869315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.4006869315
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4102005931
Short name T1064
Test name
Test status
Simulation time 28037040667 ps
CPU time 12.3 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 341672 kb
Host smart-ae254a6e-7d2e-46c7-b8f0-4b94c4a93c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102005931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4102005931
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.945561450
Short name T629
Test name
Test status
Simulation time 7748947957 ps
CPU time 462.65 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:56:11 PM PDT 24
Peak memory 1581508 kb
Host smart-5456055f-ad00-4bf0-a0ed-cbebf37fd629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945561450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.945561450
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1167945597
Short name T462
Test name
Test status
Simulation time 5491107157 ps
CPU time 7.01 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 212912 kb
Host smart-edd7c163-2eb8-40ed-b83d-1bd440fa6042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167945597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1167945597
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1805800240
Short name T1209
Test name
Test status
Simulation time 39738679 ps
CPU time 0.61 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 204392 kb
Host smart-51849de3-d3c3-4557-b964-56694c9e19c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805800240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1805800240
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3147444941
Short name T1321
Test name
Test status
Simulation time 262263041 ps
CPU time 1.54 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 212652 kb
Host smart-fdadccc1-8d1e-42fa-abd5-70452ccdb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147444941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3147444941
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1691373056
Short name T1331
Test name
Test status
Simulation time 667900954 ps
CPU time 6.29 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 275556 kb
Host smart-9e1729f3-60f1-4c07-ab49-7deaefaecfc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691373056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1691373056
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3641521844
Short name T204
Test name
Test status
Simulation time 1336562751 ps
CPU time 24.71 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:49:01 PM PDT 24
Peak memory 213540 kb
Host smart-089f5387-0952-43a2-970a-c2d0d6ac2241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641521844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3641521844
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2652022275
Short name T56
Test name
Test status
Simulation time 2446322223 ps
CPU time 66.81 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:49:29 PM PDT 24
Peak memory 725868 kb
Host smart-e15288db-f4a2-4cfa-8608-59e925e80f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652022275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2652022275
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3873245282
Short name T439
Test name
Test status
Simulation time 104710769 ps
CPU time 0.87 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:48:35 PM PDT 24
Peak memory 204052 kb
Host smart-bf8fd146-659a-4a93-89f7-411cf62d836e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873245282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3873245282
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3979264026
Short name T631
Test name
Test status
Simulation time 112879840 ps
CPU time 2.81 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:28 PM PDT 24
Peak memory 204256 kb
Host smart-34f93f28-56ba-4350-942c-643df9da3c38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979264026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3979264026
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.752289708
Short name T816
Test name
Test status
Simulation time 71648409258 ps
CPU time 253.03 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:52:51 PM PDT 24
Peak memory 1034240 kb
Host smart-f4da2d54-a410-4238-a66e-953b597c2e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752289708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.752289708
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3156228637
Short name T1334
Test name
Test status
Simulation time 5269551763 ps
CPU time 10.64 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:49 PM PDT 24
Peak memory 204368 kb
Host smart-eb24e50c-94b1-476c-bac4-443ab7487aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156228637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3156228637
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2486264678
Short name T801
Test name
Test status
Simulation time 1647500632 ps
CPU time 25.71 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:50 PM PDT 24
Peak memory 261368 kb
Host smart-ced17728-a146-46c8-bf60-570240b23bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486264678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2486264678
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1014118919
Short name T325
Test name
Test status
Simulation time 45948443 ps
CPU time 0.71 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 204088 kb
Host smart-9f3dfd7b-0a3c-4252-a5fa-00cce7addc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014118919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1014118919
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3229357380
Short name T1161
Test name
Test status
Simulation time 1458540966 ps
CPU time 11.88 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 236216 kb
Host smart-3655c9e1-a558-4d97-9c31-d277c87680cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229357380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3229357380
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4263017279
Short name T806
Test name
Test status
Simulation time 5018297453 ps
CPU time 24.25 seconds
Started May 12 12:48:28 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 300644 kb
Host smart-d352e5f5-abfb-437d-80e2-a3564d92bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263017279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4263017279
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2961946036
Short name T122
Test name
Test status
Simulation time 69738727237 ps
CPU time 435.04 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 968880 kb
Host smart-9af3e099-a2f7-4c91-861e-780cba19cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961946036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2961946036
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.4269462645
Short name T114
Test name
Test status
Simulation time 719414677 ps
CPU time 13.56 seconds
Started May 12 12:48:22 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 216972 kb
Host smart-087ebac7-3e5f-4ddb-ae85-1d476e451837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269462645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.4269462645
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3655537802
Short name T746
Test name
Test status
Simulation time 564436055 ps
CPU time 3.25 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 212544 kb
Host smart-fa0e6fe7-0b38-4d13-a366-e19fec51383d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655537802 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3655537802
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1171531876
Short name T1266
Test name
Test status
Simulation time 10130263261 ps
CPU time 31.39 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 328140 kb
Host smart-f1b32129-26c6-44d2-bb9e-7bb6798cde60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171531876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1171531876
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3483589760
Short name T739
Test name
Test status
Simulation time 925698870 ps
CPU time 2.75 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 204300 kb
Host smart-c1de67ef-bb3e-43a6-9467-8d26cf48a81f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483589760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3483589760
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3510458997
Short name T1148
Test name
Test status
Simulation time 1290920855 ps
CPU time 6.7 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 212536 kb
Host smart-4fe7ee8a-9165-47d1-a06c-2fff3f5e4745
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510458997 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3510458997
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2586778648
Short name T451
Test name
Test status
Simulation time 14394614956 ps
CPU time 16.73 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 419708 kb
Host smart-cd41276b-6428-4bd9-b48b-8767da7ab40b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586778648 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2586778648
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2968259653
Short name T1253
Test name
Test status
Simulation time 5120772158 ps
CPU time 14.55 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 204272 kb
Host smart-b8fc8b44-f639-437a-949c-ff241505750e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968259653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2968259653
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.4051080124
Short name T279
Test name
Test status
Simulation time 4844229155 ps
CPU time 21.45 seconds
Started May 12 12:48:21 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 216388 kb
Host smart-6a4c13b0-79f6-44d4-9934-e3a557338a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051080124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.4051080124
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1835789127
Short name T1267
Test name
Test status
Simulation time 25140993449 ps
CPU time 94.24 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:49:59 PM PDT 24
Peak memory 1326500 kb
Host smart-b9d51900-a399-427a-924a-aa1510f8535e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835789127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1835789127
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1708620615
Short name T32
Test name
Test status
Simulation time 15897495347 ps
CPU time 109.63 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:50:20 PM PDT 24
Peak memory 983092 kb
Host smart-f3159e09-eec9-49cd-9c39-8b62fad90bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708620615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1708620615
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1492535174
Short name T582
Test name
Test status
Simulation time 1286619582 ps
CPU time 7.21 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 217884 kb
Host smart-0495e112-931d-4d07-99f8-bebd5185f206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492535174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1492535174
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.982790499
Short name T637
Test name
Test status
Simulation time 44057836 ps
CPU time 0.6 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:35 PM PDT 24
Peak memory 204092 kb
Host smart-9fd314cd-7d26-4ac0-ac1c-5587e8fe2948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982790499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.982790499
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3810402555
Short name T349
Test name
Test status
Simulation time 127589692 ps
CPU time 1.19 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 215068 kb
Host smart-211c1792-3e2c-4101-8c3c-64667777fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810402555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3810402555
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.661703663
Short name T1087
Test name
Test status
Simulation time 285701959 ps
CPU time 11.69 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:49 PM PDT 24
Peak memory 246012 kb
Host smart-03d95636-e9ba-4c30-ad6d-5b24103c3f9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661703663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.661703663
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.358938498
Short name T704
Test name
Test status
Simulation time 1477732897 ps
CPU time 75.9 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:49:48 PM PDT 24
Peak memory 288468 kb
Host smart-8f316945-7070-4d49-a9e3-6b8ee5225829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358938498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.358938498
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3551455860
Short name T333
Test name
Test status
Simulation time 8084017053 ps
CPU time 51.87 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:49:29 PM PDT 24
Peak memory 558016 kb
Host smart-48fb2393-b52b-47ea-80c9-58fa17e2f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551455860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3551455860
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3093823924
Short name T108
Test name
Test status
Simulation time 201987063 ps
CPU time 0.9 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:48:33 PM PDT 24
Peak memory 203980 kb
Host smart-7d2dcc96-b828-434a-b31d-c11e367e904b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093823924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3093823924
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.699758406
Short name T131
Test name
Test status
Simulation time 175783113 ps
CPU time 5.22 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 235384 kb
Host smart-fddd8882-d6ad-4919-810f-d7bebcd618df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699758406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
699758406
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1400881339
Short name T107
Test name
Test status
Simulation time 4836516206 ps
CPU time 119.74 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:50:30 PM PDT 24
Peak memory 1359924 kb
Host smart-cc511027-99ae-41a6-ae42-fbc493ad6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400881339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1400881339
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3679055983
Short name T1002
Test name
Test status
Simulation time 1169946111 ps
CPU time 20.98 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 204328 kb
Host smart-53cf82d7-f87e-4e14-92ed-b5635841598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679055983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3679055983
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3933544963
Short name T392
Test name
Test status
Simulation time 1541798552 ps
CPU time 30.29 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:49:08 PM PDT 24
Peak memory 355340 kb
Host smart-d297131f-6814-4615-acea-c30134d2bac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933544963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3933544963
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.4262929017
Short name T1229
Test name
Test status
Simulation time 42128731 ps
CPU time 0.67 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:29 PM PDT 24
Peak memory 203972 kb
Host smart-4d18381e-2dd8-4c72-826a-accbe0fcc8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262929017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.4262929017
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1524845842
Short name T823
Test name
Test status
Simulation time 1441866844 ps
CPU time 31.74 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 269296 kb
Host smart-e6ecca5c-8b07-45cb-8163-05ed13fd69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524845842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1524845842
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3478897966
Short name T497
Test name
Test status
Simulation time 1292068421 ps
CPU time 10.31 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:48:38 PM PDT 24
Peak memory 219148 kb
Host smart-1545d980-b5f5-472b-92bf-1d3a773b6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478897966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3478897966
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2802759355
Short name T908
Test name
Test status
Simulation time 2266963160 ps
CPU time 3.31 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 12:48:31 PM PDT 24
Peak memory 204364 kb
Host smart-2f48dac4-80aa-4615-ac27-1513e179582d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802759355 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2802759355
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.435256102
Short name T431
Test name
Test status
Simulation time 10204485651 ps
CPU time 15.16 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 280820 kb
Host smart-941d4060-6d31-4a22-a21f-7befe8a773d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435256102 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.435256102
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3526675676
Short name T916
Test name
Test status
Simulation time 10217890478 ps
CPU time 18.75 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:56 PM PDT 24
Peak memory 307660 kb
Host smart-f34e385a-202f-4bec-8825-5aac51e69e2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526675676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3526675676
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2223218234
Short name T1250
Test name
Test status
Simulation time 1096532642 ps
CPU time 2.2 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:31 PM PDT 24
Peak memory 204360 kb
Host smart-549b9009-63a7-4356-9e88-742d06eb7b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223218234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2223218234
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3200612015
Short name T311
Test name
Test status
Simulation time 2309538496 ps
CPU time 5.82 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 220772 kb
Host smart-052672ea-ce8c-4280-b530-9285b77cbb15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200612015 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3200612015
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2178407166
Short name T519
Test name
Test status
Simulation time 19952714970 ps
CPU time 350.91 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 3381420 kb
Host smart-28aaa824-bca2-41a1-966f-251a6514af42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178407166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2178407166
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1715655833
Short name T167
Test name
Test status
Simulation time 6851052813 ps
CPU time 13.7 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 204316 kb
Host smart-de81edee-c505-4f12-b1df-5149980011f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715655833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1715655833
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2360623767
Short name T1349
Test name
Test status
Simulation time 44518639744 ps
CPU time 646.47 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:59:23 PM PDT 24
Peak memory 5159892 kb
Host smart-617e0b05-0bdd-4e96-84b1-78b7a83ace40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360623767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2360623767
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1745799972
Short name T510
Test name
Test status
Simulation time 30278788326 ps
CPU time 2067.85 seconds
Started May 12 12:48:26 PM PDT 24
Finished May 12 01:22:56 PM PDT 24
Peak memory 7257356 kb
Host smart-f2a2f560-4560-414a-8d67-68fb4b9ea31d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745799972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1745799972
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3590858541
Short name T1223
Test name
Test status
Simulation time 980042332 ps
CPU time 6.69 seconds
Started May 12 12:48:28 PM PDT 24
Finished May 12 12:48:36 PM PDT 24
Peak memory 212596 kb
Host smart-b57727de-c618-43c1-a458-2cc57668061a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590858541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3590858541
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.136586567
Short name T1241
Test name
Test status
Simulation time 238514198 ps
CPU time 0.62 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 204000 kb
Host smart-c35e0215-8ea2-40c1-b800-0fd8b989226c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136586567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.136586567
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.594550837
Short name T1036
Test name
Test status
Simulation time 220064063 ps
CPU time 1.28 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:25 PM PDT 24
Peak memory 212876 kb
Host smart-c5801305-be35-4707-b3cd-b909a606e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594550837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.594550837
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2215796913
Short name T1320
Test name
Test status
Simulation time 182704515 ps
CPU time 8.63 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 235580 kb
Host smart-ab9cb312-302c-4dd8-b0d7-079c3637a4ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215796913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2215796913
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2109597578
Short name T2
Test name
Test status
Simulation time 2122672176 ps
CPU time 120.84 seconds
Started May 12 12:46:30 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 455268 kb
Host smart-8d8432b0-3917-4594-8ff7-e708b8d1b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109597578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2109597578
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3323019118
Short name T648
Test name
Test status
Simulation time 2222764442 ps
CPU time 73.28 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:47:40 PM PDT 24
Peak memory 701300 kb
Host smart-d8e1c687-f22f-4b82-8c07-2a7423db826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323019118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3323019118
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.605943694
Short name T943
Test name
Test status
Simulation time 98985053 ps
CPU time 0.94 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:46:11 PM PDT 24
Peak memory 204104 kb
Host smart-98a1219d-2701-4da9-9d93-6f0d985345ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605943694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.605943694
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.799706043
Short name T1136
Test name
Test status
Simulation time 121405752 ps
CPU time 3.42 seconds
Started May 12 12:46:29 PM PDT 24
Finished May 12 12:46:38 PM PDT 24
Peak memory 204308 kb
Host smart-4ef44dcb-77c7-46a3-a6eb-956d2be81699
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799706043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.799706043
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.878979069
Short name T87
Test name
Test status
Simulation time 4494298115 ps
CPU time 143.47 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:49:08 PM PDT 24
Peak memory 1286828 kb
Host smart-399f7c02-4f6e-4404-b66b-2b565b4ad6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878979069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.878979069
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2687682417
Short name T805
Test name
Test status
Simulation time 285288411 ps
CPU time 3.64 seconds
Started May 12 12:46:02 PM PDT 24
Finished May 12 12:46:06 PM PDT 24
Peak memory 204344 kb
Host smart-9fe01032-0db0-47b1-8bac-ba5bf358ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687682417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2687682417
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.683881833
Short name T1344
Test name
Test status
Simulation time 4456559058 ps
CPU time 43.13 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 351716 kb
Host smart-c36c3580-5cd3-4d1b-8b48-472704a3d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683881833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.683881833
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2241838388
Short name T138
Test name
Test status
Simulation time 50438335 ps
CPU time 0.69 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 203908 kb
Host smart-2ecf4c80-f96c-498f-b250-1f24ebc7770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241838388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2241838388
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3595223842
Short name T499
Test name
Test status
Simulation time 5179062487 ps
CPU time 28.45 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 215328 kb
Host smart-25f6f962-14bd-43c6-8729-4a295cebeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595223842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3595223842
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1137976332
Short name T1022
Test name
Test status
Simulation time 12720177687 ps
CPU time 58.36 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 328612 kb
Host smart-3ff978cc-e04e-4f40-98e4-223bd4be1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137976332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1137976332
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2198327831
Short name T72
Test name
Test status
Simulation time 8827140170 ps
CPU time 1096.46 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 01:04:32 PM PDT 24
Peak memory 2096904 kb
Host smart-3548d63a-32ae-4148-b022-41998652edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198327831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2198327831
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3050225650
Short name T1167
Test name
Test status
Simulation time 1106328251 ps
CPU time 8.61 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 213504 kb
Host smart-98515667-3f52-4bac-9594-028709760e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050225650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3050225650
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2535157151
Short name T175
Test name
Test status
Simulation time 78422498 ps
CPU time 0.94 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:37 PM PDT 24
Peak memory 222364 kb
Host smart-611d37e8-90a7-4199-874a-a1cf68b93d07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535157151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2535157151
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1246243177
Short name T1240
Test name
Test status
Simulation time 4440322799 ps
CPU time 5.04 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:27 PM PDT 24
Peak memory 212564 kb
Host smart-9fa97ad0-a910-4627-b242-c77a9fe53021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246243177 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1246243177
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1160434389
Short name T1006
Test name
Test status
Simulation time 10055355728 ps
CPU time 33.51 seconds
Started May 12 12:46:05 PM PDT 24
Finished May 12 12:46:39 PM PDT 24
Peak memory 318600 kb
Host smart-a2ded7b3-accf-46aa-a8f4-fa11a2eb3d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160434389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1160434389
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1955918598
Short name T770
Test name
Test status
Simulation time 10043119041 ps
CPU time 89 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:47:53 PM PDT 24
Peak memory 563716 kb
Host smart-46bd882d-cf66-4cfb-8751-9dff3807dff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955918598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1955918598
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1405383168
Short name T1333
Test name
Test status
Simulation time 2008517025 ps
CPU time 2.63 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:24 PM PDT 24
Peak memory 204324 kb
Host smart-896351da-9d2c-4770-89df-54ff4553a78d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405383168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1405383168
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2671205764
Short name T255
Test name
Test status
Simulation time 749496372 ps
CPU time 4.39 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 204516 kb
Host smart-16c560cf-5703-4c47-bca8-fee34123b11c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671205764 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2671205764
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2786523405
Short name T1254
Test name
Test status
Simulation time 9881749565 ps
CPU time 47.9 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 1173060 kb
Host smart-6fa061db-c7ce-4f48-a111-067bb3bc9da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786523405 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2786523405
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.4120455452
Short name T710
Test name
Test status
Simulation time 4943647928 ps
CPU time 25.52 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:46:43 PM PDT 24
Peak memory 204600 kb
Host smart-eda9f4ab-6211-4169-ad66-3ee761d6d823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120455452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.4120455452
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.264166982
Short name T1107
Test name
Test status
Simulation time 1861720649 ps
CPU time 33.58 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 228564 kb
Host smart-eb4674a2-4976-413c-accf-1c334fb33772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264166982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.264166982
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2923756142
Short name T652
Test name
Test status
Simulation time 41108524095 ps
CPU time 19.92 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 513496 kb
Host smart-6e2dd442-f970-4004-a7f4-33d92bbb0914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923756142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2923756142
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.1337055743
Short name T357
Test name
Test status
Simulation time 25204354533 ps
CPU time 198.63 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:49:35 PM PDT 24
Peak memory 1525632 kb
Host smart-3b6bcea7-0377-4f85-8ff7-f58fa18b1a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337055743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.1337055743
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.903386707
Short name T350
Test name
Test status
Simulation time 7227703966 ps
CPU time 7.44 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:30 PM PDT 24
Peak memory 218680 kb
Host smart-5a84fbc5-97b3-4c65-bfd3-1e2a12e90037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903386707 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.903386707
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3343448237
Short name T1128
Test name
Test status
Simulation time 15142886 ps
CPU time 0.62 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 203992 kb
Host smart-203bd08d-5490-4a4c-b5d3-78efd80d534d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343448237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3343448237
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3466085561
Short name T628
Test name
Test status
Simulation time 350189139 ps
CPU time 1.62 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:48:41 PM PDT 24
Peak memory 212628 kb
Host smart-035b5b29-a404-4d70-973e-b2897a833140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466085561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3466085561
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3333634564
Short name T561
Test name
Test status
Simulation time 2035252869 ps
CPU time 6.3 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 251744 kb
Host smart-e305796c-10c6-4f8f-ae1b-38812cf37363
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333634564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3333634564
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2974252847
Short name T1049
Test name
Test status
Simulation time 16013427926 ps
CPU time 113.2 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:50:29 PM PDT 24
Peak memory 602220 kb
Host smart-68a7da35-5729-4879-bc94-42554820212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974252847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2974252847
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.322615490
Short name T1247
Test name
Test status
Simulation time 8157992649 ps
CPU time 148.93 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:50:57 PM PDT 24
Peak memory 688996 kb
Host smart-fbf39887-3e40-4aa6-9f02-e432be395f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322615490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.322615490
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3839956887
Short name T1076
Test name
Test status
Simulation time 96988808 ps
CPU time 0.83 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 204024 kb
Host smart-b1e9cd19-984e-419a-8c92-9ef41b5efd4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839956887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3839956887
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1534315744
Short name T829
Test name
Test status
Simulation time 345679620 ps
CPU time 5.42 seconds
Started May 12 12:48:27 PM PDT 24
Finished May 12 12:48:34 PM PDT 24
Peak memory 238396 kb
Host smart-05e2dc6d-fe13-4b4b-ac2d-16bece515e8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534315744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1534315744
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3641310917
Short name T1115
Test name
Test status
Simulation time 5220257156 ps
CPU time 173.04 seconds
Started May 12 12:48:24 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 854788 kb
Host smart-b988ee69-c8a5-43bf-a331-058e5ba73514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641310917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3641310917
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2341571567
Short name T1158
Test name
Test status
Simulation time 1146610592 ps
CPU time 20.2 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 204300 kb
Host smart-de198813-08cd-4ed7-bdfc-f19e63b3d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341571567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2341571567
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1201782787
Short name T614
Test name
Test status
Simulation time 5302773210 ps
CPU time 23.83 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 316220 kb
Host smart-9b30174c-58b1-4cb1-ac4f-aecc20b71802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201782787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1201782787
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.442693012
Short name T136
Test name
Test status
Simulation time 59225184 ps
CPU time 0.62 seconds
Started May 12 12:48:23 PM PDT 24
Finished May 12 12:48:24 PM PDT 24
Peak memory 203948 kb
Host smart-590f77c5-e9c8-42a4-adcc-db3992e00539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442693012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.442693012
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.192674341
Short name T57
Test name
Test status
Simulation time 810284393 ps
CPU time 3.42 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 230688 kb
Host smart-0977127c-4ec3-4ee4-b200-e8dff1d86934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192674341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.192674341
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.891260309
Short name T269
Test name
Test status
Simulation time 9377376237 ps
CPU time 19.58 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:50 PM PDT 24
Peak memory 301936 kb
Host smart-4e8812c5-3b8a-4207-b4f4-fb84131a8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891260309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.891260309
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2660222048
Short name T267
Test name
Test status
Simulation time 14850901137 ps
CPU time 1834.96 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 01:19:12 PM PDT 24
Peak memory 2547844 kb
Host smart-80310813-0364-4b4f-8162-512080cc6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660222048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2660222048
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2230583219
Short name T445
Test name
Test status
Simulation time 369889546 ps
CPU time 16.39 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 212452 kb
Host smart-2a2b27e2-1733-4bb3-bf59-d4da8267e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230583219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2230583219
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2868071543
Short name T1024
Test name
Test status
Simulation time 1138292488 ps
CPU time 5.22 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:48:45 PM PDT 24
Peak memory 212552 kb
Host smart-82c46790-9172-4287-9c6b-b98699308958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868071543 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2868071543
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2028501883
Short name T1070
Test name
Test status
Simulation time 10233554515 ps
CPU time 25.82 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:49:01 PM PDT 24
Peak memory 287004 kb
Host smart-711698a5-6cd4-463f-bf40-b044e92eea66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028501883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2028501883
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1292999953
Short name T315
Test name
Test status
Simulation time 10070854019 ps
CPU time 33.44 seconds
Started May 12 12:48:42 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 328984 kb
Host smart-2ab7e134-9eb9-41c7-80be-c20ca55ecf5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292999953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1292999953
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2268955417
Short name T706
Test name
Test status
Simulation time 888366280 ps
CPU time 2.89 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:41 PM PDT 24
Peak memory 204228 kb
Host smart-553f5ac5-ed1f-4303-b22b-3321415faf55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268955417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2268955417
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2839918943
Short name T1074
Test name
Test status
Simulation time 10465343528 ps
CPU time 4.77 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:43 PM PDT 24
Peak memory 204232 kb
Host smart-86a19136-e518-4c25-b2e2-d6d7a81590e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839918943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2839918943
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.820438727
Short name T253
Test name
Test status
Simulation time 18543384211 ps
CPU time 136.26 seconds
Started May 12 12:48:40 PM PDT 24
Finished May 12 12:50:57 PM PDT 24
Peak memory 1522096 kb
Host smart-082f1f92-de1e-4746-b71e-d9480938f786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820438727 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.820438727
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2803093746
Short name T273
Test name
Test status
Simulation time 3864784268 ps
CPU time 35.18 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 204348 kb
Host smart-353d7e81-6892-4db6-a149-0fbc117537c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803093746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2803093746
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.4059347748
Short name T1211
Test name
Test status
Simulation time 2981605894 ps
CPU time 19.7 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 212148 kb
Host smart-5f5f3170-5a0d-4747-8f3e-542ae9093e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059347748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.4059347748
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1794393729
Short name T1112
Test name
Test status
Simulation time 8375194649 ps
CPU time 5.15 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:48:47 PM PDT 24
Peak memory 204408 kb
Host smart-3490f53e-a7a6-45d6-8b51-76b57f13b237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794393729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1794393729
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2183378994
Short name T1291
Test name
Test status
Simulation time 50708778043 ps
CPU time 39.9 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:49:15 PM PDT 24
Peak memory 492424 kb
Host smart-c5d92bcf-0b65-416b-ac7d-6285c39d561e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183378994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2183378994
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3416722950
Short name T811
Test name
Test status
Simulation time 7433631340 ps
CPU time 7.26 seconds
Started May 12 12:48:31 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 220564 kb
Host smart-118e41bf-e37b-438c-9dfb-f2ce659e8dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416722950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3416722950
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1733407580
Short name T834
Test name
Test status
Simulation time 91295306 ps
CPU time 0.61 seconds
Started May 12 12:48:40 PM PDT 24
Finished May 12 12:48:41 PM PDT 24
Peak memory 204064 kb
Host smart-9be44954-2955-4e58-9d48-bb5693f806ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733407580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1733407580
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.854927554
Short name T665
Test name
Test status
Simulation time 304467516 ps
CPU time 1.32 seconds
Started May 12 12:48:29 PM PDT 24
Finished May 12 12:48:32 PM PDT 24
Peak memory 212520 kb
Host smart-fb572b92-dae3-47ce-a33a-15c98ceb8aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854927554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.854927554
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.4046590020
Short name T850
Test name
Test status
Simulation time 764482206 ps
CPU time 7.26 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 286812 kb
Host smart-d472cc0a-3678-4609-86aa-139d6b4b8c45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046590020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.4046590020
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.980224449
Short name T154
Test name
Test status
Simulation time 2048883229 ps
CPU time 44.54 seconds
Started May 12 12:48:40 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 512256 kb
Host smart-b799e02d-8ae2-4e60-81f1-95e0e1724f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980224449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.980224449
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2145049019
Short name T643
Test name
Test status
Simulation time 1998263490 ps
CPU time 152.89 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 701404 kb
Host smart-6a0c2fc3-8ace-48e4-8926-6ece78ab6312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145049019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2145049019
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2896327513
Short name T924
Test name
Test status
Simulation time 263516558 ps
CPU time 0.8 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 204052 kb
Host smart-4fbf0b65-f76a-41bd-bd7c-023515a41867
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896327513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2896327513
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4170863840
Short name T859
Test name
Test status
Simulation time 251148479 ps
CPU time 4.96 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 235352 kb
Host smart-20108a3d-a571-4a78-b414-576f753147bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170863840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4170863840
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.299341921
Short name T260
Test name
Test status
Simulation time 2748167235 ps
CPU time 56.44 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:49:31 PM PDT 24
Peak memory 780364 kb
Host smart-7dce2795-a010-45d4-ac17-9a1abee6315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299341921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.299341921
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.356833550
Short name T389
Test name
Test status
Simulation time 1289924002 ps
CPU time 4.81 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 204248 kb
Host smart-924c372a-c70c-435b-8c6d-b1c7103d0071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356833550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.356833550
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1446214563
Short name T906
Test name
Test status
Simulation time 1293081294 ps
CPU time 58.23 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:50:05 PM PDT 24
Peak memory 318204 kb
Host smart-ffd6e41f-6115-45e7-ae7c-9caaa32b409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446214563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1446214563
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1324051675
Short name T322
Test name
Test status
Simulation time 38828726 ps
CPU time 0.68 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:36 PM PDT 24
Peak memory 204148 kb
Host smart-0827ae34-0492-41f4-83e8-b99902f97a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324051675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1324051675
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2627651187
Short name T74
Test name
Test status
Simulation time 3471397642 ps
CPU time 14.02 seconds
Started May 12 12:48:39 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 219512 kb
Host smart-ea48409b-48da-4439-a5cb-216daa5917fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627651187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2627651187
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.548714291
Short name T559
Test name
Test status
Simulation time 5471189760 ps
CPU time 63.14 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:49:36 PM PDT 24
Peak memory 307608 kb
Host smart-adada726-0dbf-42c9-b707-e4950bac1e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548714291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.548714291
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2047600064
Short name T118
Test name
Test status
Simulation time 21165037141 ps
CPU time 1415.09 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 01:12:11 PM PDT 24
Peak memory 2859756 kb
Host smart-0d941456-0360-4698-8a4a-288679e283d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047600064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2047600064
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3834175918
Short name T1125
Test name
Test status
Simulation time 1510819799 ps
CPU time 15.49 seconds
Started May 12 12:48:39 PM PDT 24
Finished May 12 12:48:56 PM PDT 24
Peak memory 220684 kb
Host smart-f861fb5d-d026-4300-97e0-33374c249c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834175918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3834175918
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.282244911
Short name T687
Test name
Test status
Simulation time 1047421107 ps
CPU time 5.03 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 212556 kb
Host smart-9657aa4f-bb43-47f0-a523-23e583bd909d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282244911 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.282244911
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.244075414
Short name T705
Test name
Test status
Simulation time 10078253495 ps
CPU time 68.9 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:49:46 PM PDT 24
Peak memory 528448 kb
Host smart-05a1a9fa-10e2-4dd8-9388-1fadd5ce3d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244075414 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.244075414
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.15208247
Short name T543
Test name
Test status
Simulation time 10149710528 ps
CPU time 34.21 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:49:13 PM PDT 24
Peak memory 383452 kb
Host smart-20512edd-c8b8-4511-beaa-066d40523b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208247 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_fifo_reset_tx.15208247
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2457439457
Short name T15
Test name
Test status
Simulation time 376393023 ps
CPU time 2.43 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 204288 kb
Host smart-1f050b9c-2067-465e-af96-4c56277f5d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457439457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2457439457
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1043327979
Short name T862
Test name
Test status
Simulation time 5525775231 ps
CPU time 3.62 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:48:37 PM PDT 24
Peak memory 204404 kb
Host smart-330a2ff6-fd15-4bb2-932a-1a221ddccfc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043327979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1043327979
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3002442827
Short name T1068
Test name
Test status
Simulation time 10336018675 ps
CPU time 49.78 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 12:49:23 PM PDT 24
Peak memory 1201764 kb
Host smart-de2e35ef-786e-4001-82c6-953d32100ee2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002442827 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3002442827
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3639165855
Short name T1059
Test name
Test status
Simulation time 8808701380 ps
CPU time 13.11 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 203752 kb
Host smart-71f601b4-7259-4bb6-b600-2bb11b12397e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639165855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3639165855
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3344627935
Short name T932
Test name
Test status
Simulation time 1445330990 ps
CPU time 59.26 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:49:37 PM PDT 24
Peak memory 207672 kb
Host smart-0297b651-821c-4bf4-9dd9-93cb7a2565e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344627935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3344627935
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3208295130
Short name T575
Test name
Test status
Simulation time 44350672344 ps
CPU time 846.71 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 01:02:48 PM PDT 24
Peak memory 5957896 kb
Host smart-73cfc8a5-8d8b-4c39-8d1a-bdd27f63e2ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208295130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3208295130
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1691605380
Short name T320
Test name
Test status
Simulation time 15738097466 ps
CPU time 999.72 seconds
Started May 12 12:48:32 PM PDT 24
Finished May 12 01:05:13 PM PDT 24
Peak memory 3796512 kb
Host smart-fbc89499-2235-44aa-b524-4faa4cb2b009
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691605380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1691605380
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1599607503
Short name T868
Test name
Test status
Simulation time 4209682352 ps
CPU time 7.51 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 220596 kb
Host smart-0aac5aa5-587f-4460-ad96-098d9bb9d3a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599607503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1599607503
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2068287189
Short name T1226
Test name
Test status
Simulation time 39826065 ps
CPU time 0.62 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 204308 kb
Host smart-35ee5531-5397-4529-8be9-92e18ee32cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068287189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2068287189
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3028746438
Short name T699
Test name
Test status
Simulation time 298214297 ps
CPU time 1.96 seconds
Started May 12 12:48:33 PM PDT 24
Finished May 12 12:48:36 PM PDT 24
Peak memory 212628 kb
Host smart-308ebf27-38d4-4a9a-98fc-0c28c247b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028746438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3028746438
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.419396284
Short name T1051
Test name
Test status
Simulation time 1225533612 ps
CPU time 16.27 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 269316 kb
Host smart-6354fae9-34e1-4f6a-9511-e486e028f3f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419396284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.419396284
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2934486449
Short name T1014
Test name
Test status
Simulation time 2632209317 ps
CPU time 70.11 seconds
Started May 12 12:48:50 PM PDT 24
Finished May 12 12:50:01 PM PDT 24
Peak memory 275780 kb
Host smart-283c410c-9bdc-46c6-9ef1-3108aeea851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934486449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2934486449
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3369568870
Short name T589
Test name
Test status
Simulation time 7054460856 ps
CPU time 62 seconds
Started May 12 12:48:35 PM PDT 24
Finished May 12 12:49:40 PM PDT 24
Peak memory 662704 kb
Host smart-e9449444-49f1-4445-9c8d-70d986bed4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369568870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3369568870
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1958450234
Short name T1312
Test name
Test status
Simulation time 721855001 ps
CPU time 1.17 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:40 PM PDT 24
Peak memory 204344 kb
Host smart-de39f00b-106c-4091-ace0-794ca384fd06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958450234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1958450234
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3052819930
Short name T833
Test name
Test status
Simulation time 207938347 ps
CPU time 9.98 seconds
Started May 12 12:48:34 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 204228 kb
Host smart-075deaf6-6c09-491f-b076-ad9383b449d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052819930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3052819930
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2946702944
Short name T712
Test name
Test status
Simulation time 14132668452 ps
CPU time 299.44 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:53:39 PM PDT 24
Peak memory 1140976 kb
Host smart-8de78570-c63f-4095-bf1d-7c85338e4a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946702944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2946702944
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2422876155
Short name T593
Test name
Test status
Simulation time 389444925 ps
CPU time 5.8 seconds
Started May 12 12:49:02 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 204316 kb
Host smart-53c61563-bbfe-4010-bdb3-7c788300b861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422876155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2422876155
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2505015847
Short name T1013
Test name
Test status
Simulation time 5269375224 ps
CPU time 62.4 seconds
Started May 12 12:48:53 PM PDT 24
Finished May 12 12:49:56 PM PDT 24
Peak memory 314884 kb
Host smart-c8eb7c03-6608-4408-b13e-e8336fc969ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505015847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2505015847
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2028906749
Short name T955
Test name
Test status
Simulation time 21380988 ps
CPU time 0.67 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:39 PM PDT 24
Peak memory 203968 kb
Host smart-c8b38c91-375b-4d89-819b-7d617a673564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028906749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2028906749
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1953161461
Short name T1038
Test name
Test status
Simulation time 50060666192 ps
CPU time 1536.43 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 01:14:15 PM PDT 24
Peak memory 3434644 kb
Host smart-09959d23-e153-4c14-adf8-92dd5b396d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953161461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1953161461
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4201803246
Short name T375
Test name
Test status
Simulation time 11875360321 ps
CPU time 51.89 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:49:31 PM PDT 24
Peak memory 331832 kb
Host smart-75ece1f8-50d0-4a7e-a5a3-9510c5eea8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201803246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4201803246
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3040639528
Short name T259
Test name
Test status
Simulation time 13535464517 ps
CPU time 636.22 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:59:16 PM PDT 24
Peak memory 1298048 kb
Host smart-86c1df4e-1a1f-4f26-88fe-6fd117d6178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040639528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3040639528
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3110578974
Short name T1159
Test name
Test status
Simulation time 1504254250 ps
CPU time 12.96 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 212484 kb
Host smart-9914aa7c-edbd-4ce4-8beb-41570ebf6f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110578974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3110578974
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3175164711
Short name T366
Test name
Test status
Simulation time 2594439824 ps
CPU time 3.53 seconds
Started May 12 12:48:39 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 204384 kb
Host smart-ccc1487c-ebf5-4ec6-abab-991bfb1ab867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175164711 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3175164711
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.4071609710
Short name T1099
Test name
Test status
Simulation time 10042386211 ps
CPU time 69.74 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:49:51 PM PDT 24
Peak memory 521416 kb
Host smart-a6202a3c-97a7-4112-8524-e8f0d88355e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071609710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.4071609710
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.230178628
Short name T839
Test name
Test status
Simulation time 10185445974 ps
CPU time 14.32 seconds
Started May 12 12:48:36 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 302768 kb
Host smart-92ec53fd-9f65-40d5-9b90-8191475d4de2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230178628 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.230178628
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3472213949
Short name T285
Test name
Test status
Simulation time 1494816427 ps
CPU time 2.26 seconds
Started May 12 12:48:45 PM PDT 24
Finished May 12 12:48:47 PM PDT 24
Peak memory 204336 kb
Host smart-86bb115b-b95d-438c-83c0-1f394d2d49e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472213949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3472213949
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2777752834
Short name T1141
Test name
Test status
Simulation time 17652241738 ps
CPU time 4.88 seconds
Started May 12 12:48:47 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 204388 kb
Host smart-c145e01e-494c-442a-88d0-1f465c1368b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777752834 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2777752834
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2383511808
Short name T379
Test name
Test status
Simulation time 4134615780 ps
CPU time 8.73 seconds
Started May 12 12:48:38 PM PDT 24
Finished May 12 12:48:48 PM PDT 24
Peak memory 204456 kb
Host smart-4a80df9f-26ff-463e-8e81-fcec43ab33ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383511808 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2383511808
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1767369286
Short name T300
Test name
Test status
Simulation time 3400002440 ps
CPU time 9.17 seconds
Started May 12 12:48:37 PM PDT 24
Finished May 12 12:48:48 PM PDT 24
Peak memory 204432 kb
Host smart-c0dbcb19-1554-41b4-9161-28b7336565bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767369286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1767369286
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.518876965
Short name T966
Test name
Test status
Simulation time 3607372811 ps
CPU time 21.9 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:18 PM PDT 24
Peak memory 223704 kb
Host smart-d604d5b9-4ca5-4770-9ab0-c8cc9b846267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518876965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.518876965
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2678051677
Short name T594
Test name
Test status
Simulation time 40691981337 ps
CPU time 638.8 seconds
Started May 12 12:48:40 PM PDT 24
Finished May 12 12:59:20 PM PDT 24
Peak memory 5029680 kb
Host smart-7bd7d588-c6f7-4794-afb3-a14c34d2c42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678051677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2678051677
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2065438031
Short name T602
Test name
Test status
Simulation time 6976915193 ps
CPU time 30.21 seconds
Started May 12 12:48:49 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 554532 kb
Host smart-970d7534-6c93-4526-ae79-aabd09a401b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065438031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2065438031
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1897333414
Short name T574
Test name
Test status
Simulation time 11228271535 ps
CPU time 7.45 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:03 PM PDT 24
Peak memory 217632 kb
Host smart-f8c8cc29-ca96-4942-a6ec-a16fd1837f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897333414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1897333414
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.52118830
Short name T4
Test name
Test status
Simulation time 51002257 ps
CPU time 0.62 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 204100 kb
Host smart-902d04c9-fd9d-48a6-8941-69d2696b0b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52118830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.52118830
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.988356354
Short name T949
Test name
Test status
Simulation time 427255667 ps
CPU time 1.5 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 212544 kb
Host smart-49c8cf21-21a3-480b-a770-ff46610605f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988356354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.988356354
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1013767320
Short name T1248
Test name
Test status
Simulation time 1485577945 ps
CPU time 20.3 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 284868 kb
Host smart-ca9e790a-4240-4f29-bd38-47c8e2d21957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013767320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1013767320
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.855528291
Short name T434
Test name
Test status
Simulation time 1436415830 ps
CPU time 68.67 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:49:50 PM PDT 24
Peak memory 212456 kb
Host smart-3c5f2210-9b36-480e-b83f-5a89acc4984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855528291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.855528291
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2443382478
Short name T721
Test name
Test status
Simulation time 17360558864 ps
CPU time 48.05 seconds
Started May 12 12:48:44 PM PDT 24
Finished May 12 12:49:32 PM PDT 24
Peak memory 592680 kb
Host smart-66848f84-29cc-4ea7-8863-0b3a10a71723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443382478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2443382478
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3162127901
Short name T666
Test name
Test status
Simulation time 308830012 ps
CPU time 0.95 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:48:42 PM PDT 24
Peak memory 204076 kb
Host smart-37598492-e28c-4cf5-94c9-7a1430d86bb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162127901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3162127901
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.211259360
Short name T1030
Test name
Test status
Simulation time 141239907 ps
CPU time 2.98 seconds
Started May 12 12:48:42 PM PDT 24
Finished May 12 12:48:46 PM PDT 24
Peak memory 204272 kb
Host smart-04f83f48-bda4-4cb4-8f8e-ce134afd6cd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211259360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
211259360
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3231865772
Short name T636
Test name
Test status
Simulation time 3666462258 ps
CPU time 287.68 seconds
Started May 12 12:48:56 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 1107832 kb
Host smart-e4325614-58f9-4ffc-8b84-3c156d7ae2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231865772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3231865772
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1985903831
Short name T164
Test name
Test status
Simulation time 1237733155 ps
CPU time 9.99 seconds
Started May 12 12:48:54 PM PDT 24
Finished May 12 12:49:05 PM PDT 24
Peak memory 204268 kb
Host smart-9948e53a-d367-4390-94af-e4f79b6cfc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985903831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1985903831
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3953156954
Short name T1120
Test name
Test status
Simulation time 2501435948 ps
CPU time 26.1 seconds
Started May 12 12:48:47 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 378836 kb
Host smart-7cd13700-91d0-412e-a2b4-c0e38856da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953156954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3953156954
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3260212878
Short name T365
Test name
Test status
Simulation time 18582723 ps
CPU time 0.65 seconds
Started May 12 12:48:51 PM PDT 24
Finished May 12 12:48:52 PM PDT 24
Peak memory 203996 kb
Host smart-d1637436-4a8a-4004-a59b-e610ea4605af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260212878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3260212878
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1278808640
Short name T85
Test name
Test status
Simulation time 27444351776 ps
CPU time 154.83 seconds
Started May 12 12:48:41 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 212548 kb
Host smart-6d205c84-b67f-4bf2-9ecd-f1d13555f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278808640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1278808640
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3220920545
Short name T361
Test name
Test status
Simulation time 2390992909 ps
CPU time 59.75 seconds
Started May 12 12:48:39 PM PDT 24
Finished May 12 12:49:40 PM PDT 24
Peak memory 285516 kb
Host smart-89cfaf63-e49e-4233-b96e-89a1d5401908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220920545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3220920545
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1966883926
Short name T228
Test name
Test status
Simulation time 8680246824 ps
CPU time 755.68 seconds
Started May 12 12:48:45 PM PDT 24
Finished May 12 01:01:21 PM PDT 24
Peak memory 1479304 kb
Host smart-f7a7b081-7b2d-473d-89b8-762b48b9e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966883926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1966883926
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1260896132
Short name T471
Test name
Test status
Simulation time 2232968558 ps
CPU time 28.14 seconds
Started May 12 12:48:42 PM PDT 24
Finished May 12 12:49:11 PM PDT 24
Peak memory 212616 kb
Host smart-e2de6686-5688-4334-96f8-f60da25710cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260896132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1260896132
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3428119597
Short name T380
Test name
Test status
Simulation time 906747779 ps
CPU time 4.59 seconds
Started May 12 12:48:50 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 212460 kb
Host smart-39c04070-9da1-4394-88c4-8df0b0947199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428119597 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3428119597
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.219444995
Short name T977
Test name
Test status
Simulation time 10117744271 ps
CPU time 64.59 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:50:09 PM PDT 24
Peak memory 480116 kb
Host smart-cd07dfb7-ecf3-494e-8674-a979d8a3e840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219444995 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.219444995
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.4098910649
Short name T671
Test name
Test status
Simulation time 10056297739 ps
CPU time 86.12 seconds
Started May 12 12:48:58 PM PDT 24
Finished May 12 12:50:25 PM PDT 24
Peak memory 480056 kb
Host smart-ab5120bb-f891-4b70-b699-316a5616cfea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098910649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.4098910649
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3030417687
Short name T291
Test name
Test status
Simulation time 1239582405 ps
CPU time 2.65 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 204520 kb
Host smart-dce99502-2c99-4c11-8de8-d1f9ac1eb922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030417687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3030417687
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.228855253
Short name T1078
Test name
Test status
Simulation time 4696686433 ps
CPU time 5.7 seconds
Started May 12 12:48:54 PM PDT 24
Finished May 12 12:49:00 PM PDT 24
Peak memory 212560 kb
Host smart-71eb2b6a-7b55-4774-9d60-71686bbd7b7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228855253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.228855253
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2233823962
Short name T1092
Test name
Test status
Simulation time 23576834829 ps
CPU time 63.12 seconds
Started May 12 12:49:02 PM PDT 24
Finished May 12 12:50:05 PM PDT 24
Peak memory 1314904 kb
Host smart-c0cf063e-786a-4b62-ada6-d7449b8ce041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233823962 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2233823962
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2906767216
Short name T1316
Test name
Test status
Simulation time 1112516068 ps
CPU time 17.4 seconds
Started May 12 12:48:49 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 204320 kb
Host smart-369eb208-05a3-499a-8e2b-83bcb0821066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906767216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2906767216
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1048680867
Short name T1102
Test name
Test status
Simulation time 745078195 ps
CPU time 31.27 seconds
Started May 12 12:48:49 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 204232 kb
Host smart-92755a28-f314-423b-b2d3-923dd53249dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048680867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1048680867
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2252222058
Short name T110
Test name
Test status
Simulation time 30189600534 ps
CPU time 41.71 seconds
Started May 12 12:48:43 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 831128 kb
Host smart-a2db14ba-0eb0-4e18-bd0c-e00373fbd9d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252222058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2252222058
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.4293248104
Short name T660
Test name
Test status
Simulation time 4030575155 ps
CPU time 34 seconds
Started May 12 12:48:53 PM PDT 24
Finished May 12 12:49:28 PM PDT 24
Peak memory 477664 kb
Host smart-861b7fc1-710c-43e2-a9bb-d9018d799d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293248104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.4293248104
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.981022677
Short name T651
Test name
Test status
Simulation time 1135997431 ps
CPU time 6.71 seconds
Started May 12 12:48:47 PM PDT 24
Finished May 12 12:48:54 PM PDT 24
Peak memory 204316 kb
Host smart-340a9d99-c6a1-439e-bb36-fc7f4765962a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981022677 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.981022677
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.907109904
Short name T133
Test name
Test status
Simulation time 22751888 ps
CPU time 0.61 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:48:53 PM PDT 24
Peak memory 204004 kb
Host smart-7ef81a0a-582c-416e-8c80-8816bcff2efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907109904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.907109904
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2654952702
Short name T677
Test name
Test status
Simulation time 353498900 ps
CPU time 1.38 seconds
Started May 12 12:48:59 PM PDT 24
Finished May 12 12:49:01 PM PDT 24
Peak memory 212516 kb
Host smart-e52864e5-50af-4aaa-8ab5-7a97c774135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654952702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2654952702
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.134510447
Short name T371
Test name
Test status
Simulation time 379026892 ps
CPU time 7.02 seconds
Started May 12 12:48:50 PM PDT 24
Finished May 12 12:48:57 PM PDT 24
Peak memory 283460 kb
Host smart-041c8d95-01e1-49f4-859d-72d2ef500ce4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134510447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.134510447
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3782014318
Short name T1290
Test name
Test status
Simulation time 8954206786 ps
CPU time 73.77 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:50:23 PM PDT 24
Peak memory 732796 kb
Host smart-22891120-232f-4454-820d-cb554c79d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782014318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3782014318
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.764875416
Short name T411
Test name
Test status
Simulation time 1117066873 ps
CPU time 72.68 seconds
Started May 12 12:48:45 PM PDT 24
Finished May 12 12:49:58 PM PDT 24
Peak memory 452620 kb
Host smart-bca59e39-d1d7-4b70-af95-99b46586b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764875416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.764875416
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3329161110
Short name T237
Test name
Test status
Simulation time 116136365 ps
CPU time 1.09 seconds
Started May 12 12:48:42 PM PDT 24
Finished May 12 12:48:44 PM PDT 24
Peak memory 204340 kb
Host smart-e6e78ab9-0853-46de-84aa-b5a47e29e3c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329161110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3329161110
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3246940913
Short name T1285
Test name
Test status
Simulation time 159893722 ps
CPU time 9.14 seconds
Started May 12 12:48:56 PM PDT 24
Finished May 12 12:49:06 PM PDT 24
Peak memory 233948 kb
Host smart-1c434730-f700-46cf-b32e-cf929a4905a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246940913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3246940913
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2718128087
Short name T1265
Test name
Test status
Simulation time 42401866855 ps
CPU time 121.3 seconds
Started May 12 12:48:53 PM PDT 24
Finished May 12 12:50:55 PM PDT 24
Peak memory 1156020 kb
Host smart-5badb208-f5b7-4a53-8340-9a73a14aa270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718128087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2718128087
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.4256791794
Short name T1149
Test name
Test status
Simulation time 856490249 ps
CPU time 15.65 seconds
Started May 12 12:48:51 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 204224 kb
Host smart-088f20a2-bc50-44e4-94fd-b8c1be1de639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256791794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.4256791794
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1618388287
Short name T36
Test name
Test status
Simulation time 5815443149 ps
CPU time 17.9 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 253220 kb
Host smart-bc9cfbfb-1559-48a3-8972-39d56950b42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618388287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1618388287
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3906775083
Short name T139
Test name
Test status
Simulation time 21402305 ps
CPU time 0.65 seconds
Started May 12 12:48:47 PM PDT 24
Finished May 12 12:48:48 PM PDT 24
Peak memory 203992 kb
Host smart-484d73b0-ef79-4f73-81dc-764862a18366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906775083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3906775083
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3273282853
Short name T1052
Test name
Test status
Simulation time 2932252738 ps
CPU time 10.2 seconds
Started May 12 12:48:51 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 221200 kb
Host smart-f0ea04e7-64da-475e-a591-7f3dce3eeafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273282853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3273282853
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1692539044
Short name T1166
Test name
Test status
Simulation time 1436883729 ps
CPU time 14.62 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 278292 kb
Host smart-f0a2d45c-ccc8-452b-a511-1b3a26f077c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692539044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1692539044
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1142438355
Short name T247
Test name
Test status
Simulation time 40564564266 ps
CPU time 732.52 seconds
Started May 12 12:48:58 PM PDT 24
Finished May 12 01:01:11 PM PDT 24
Peak memory 1006408 kb
Host smart-2c279576-8fad-4d2e-8326-2a15bae9136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142438355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1142438355
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.4271385890
Short name T935
Test name
Test status
Simulation time 7011905319 ps
CPU time 16.68 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 212572 kb
Host smart-5485f3ac-436f-4fac-a12b-dd4269bfc55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271385890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.4271385890
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3876697774
Short name T1366
Test name
Test status
Simulation time 2504534329 ps
CPU time 5.01 seconds
Started May 12 12:48:50 PM PDT 24
Finished May 12 12:48:55 PM PDT 24
Peak memory 213620 kb
Host smart-fa50e6a2-6d3f-4aa1-9e97-1b480a9e93fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876697774 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3876697774
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2584070506
Short name T981
Test name
Test status
Simulation time 10083558741 ps
CPU time 55.37 seconds
Started May 12 12:48:58 PM PDT 24
Finished May 12 12:49:53 PM PDT 24
Peak memory 434072 kb
Host smart-d86ae651-87dd-4678-80ee-71bbd083077c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584070506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2584070506
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1047969339
Short name T536
Test name
Test status
Simulation time 10305568602 ps
CPU time 7.58 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 264392 kb
Host smart-5a7973ec-14af-4807-8297-afb52cebdf08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047969339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1047969339
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.606166675
Short name T319
Test name
Test status
Simulation time 478583918 ps
CPU time 2.69 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:48:59 PM PDT 24
Peak memory 204284 kb
Host smart-a17802db-79ab-493e-bc54-388bf1210a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606166675 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.606166675
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3267804439
Short name T1021
Test name
Test status
Simulation time 2152500505 ps
CPU time 5.93 seconds
Started May 12 12:48:46 PM PDT 24
Finished May 12 12:49:03 PM PDT 24
Peak memory 212644 kb
Host smart-7b5383d7-154b-4238-bd71-6737ffc1fd34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267804439 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3267804439
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3000083696
Short name T532
Test name
Test status
Simulation time 21358276767 ps
CPU time 624.46 seconds
Started May 12 12:48:54 PM PDT 24
Finished May 12 12:59:19 PM PDT 24
Peak memory 5249240 kb
Host smart-f204a4b6-3051-4200-a37a-6208539ee779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000083696 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3000083696
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3555127865
Short name T761
Test name
Test status
Simulation time 2755856832 ps
CPU time 24.84 seconds
Started May 12 12:48:52 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 204404 kb
Host smart-de2f3db1-02ab-47ed-971a-63c5b30bda07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555127865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3555127865
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.708402390
Short name T1277
Test name
Test status
Simulation time 621999781 ps
CPU time 12.15 seconds
Started May 12 12:48:56 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 205228 kb
Host smart-7abd9178-8650-4310-8e47-9474968488fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708402390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.708402390
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2626969456
Short name T891
Test name
Test status
Simulation time 26593636977 ps
CPU time 45.42 seconds
Started May 12 12:48:59 PM PDT 24
Finished May 12 12:49:45 PM PDT 24
Peak memory 885920 kb
Host smart-13658f1f-c0fd-44fd-814b-d0616cf77112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626969456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2626969456
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2617001120
Short name T612
Test name
Test status
Simulation time 9389020612 ps
CPU time 54.4 seconds
Started May 12 12:48:50 PM PDT 24
Finished May 12 12:49:45 PM PDT 24
Peak memory 663324 kb
Host smart-9db9de88-b249-4eca-9e18-f023d7749f3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617001120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2617001120
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.4206121595
Short name T881
Test name
Test status
Simulation time 1223683469 ps
CPU time 6.3 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 212416 kb
Host smart-8667f641-8f7c-4dcf-91d1-1c31e9cc3714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206121595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.4206121595
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1698745845
Short name T370
Test name
Test status
Simulation time 22444746 ps
CPU time 0.62 seconds
Started May 12 12:48:57 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 204112 kb
Host smart-0c545b11-be9d-402f-9024-12f8d1e44193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698745845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1698745845
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3953120205
Short name T323
Test name
Test status
Simulation time 112765496 ps
CPU time 1.81 seconds
Started May 12 12:48:56 PM PDT 24
Finished May 12 12:48:58 PM PDT 24
Peak memory 212628 kb
Host smart-b6af667d-cb5d-4b15-b240-a5e8b9202435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953120205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3953120205
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2645712196
Short name T286
Test name
Test status
Simulation time 303828113 ps
CPU time 5.44 seconds
Started May 12 12:48:56 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 257740 kb
Host smart-4d2660a9-4304-4623-9dd6-39c7803aa1f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645712196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2645712196
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2566929400
Short name T869
Test name
Test status
Simulation time 1892925894 ps
CPU time 46.26 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:42 PM PDT 24
Peak memory 461688 kb
Host smart-7adee17f-78b1-43e9-82ff-576e35c4220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566929400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2566929400
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1199379108
Short name T374
Test name
Test status
Simulation time 2337669908 ps
CPU time 65.54 seconds
Started May 12 12:48:53 PM PDT 24
Finished May 12 12:49:59 PM PDT 24
Peak memory 667276 kb
Host smart-e528e797-8c59-42c7-b0a1-f46c42f96666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199379108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1199379108
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2847383429
Short name T971
Test name
Test status
Simulation time 1117389697 ps
CPU time 1.2 seconds
Started May 12 12:48:48 PM PDT 24
Finished May 12 12:48:50 PM PDT 24
Peak memory 204192 kb
Host smart-7a0c95b9-6549-46ef-a19e-b27f52a6dc85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847383429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2847383429
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.569049677
Short name T819
Test name
Test status
Simulation time 2252057697 ps
CPU time 7.66 seconds
Started May 12 12:48:54 PM PDT 24
Finished May 12 12:49:03 PM PDT 24
Peak memory 204404 kb
Host smart-2a08cb6e-7417-4bda-b165-2e3075a39e5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569049677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
569049677
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1780455985
Short name T98
Test name
Test status
Simulation time 29182581893 ps
CPU time 73.49 seconds
Started May 12 12:48:51 PM PDT 24
Finished May 12 12:50:06 PM PDT 24
Peak memory 930008 kb
Host smart-13ef9b6a-1075-47c4-9536-a2c75ee7fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780455985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1780455985
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1302272995
Short name T1255
Test name
Test status
Simulation time 1726154582 ps
CPU time 23.6 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 204268 kb
Host smart-577d3a10-bf61-44ae-8dde-a9a7de2d7e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302272995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1302272995
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.628325883
Short name T425
Test name
Test status
Simulation time 11586652362 ps
CPU time 27.99 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:49:35 PM PDT 24
Peak memory 329312 kb
Host smart-44fe0cad-d5d5-4afc-84ee-fbe43bf7b96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628325883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.628325883
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.4101410622
Short name T53
Test name
Test status
Simulation time 17571160 ps
CPU time 0.65 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:48:56 PM PDT 24
Peak memory 203924 kb
Host smart-54013d14-b4ba-46c8-b0e4-14ec189cf2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101410622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.4101410622
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2364897133
Short name T857
Test name
Test status
Simulation time 49332134577 ps
CPU time 561.1 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:58:34 PM PDT 24
Peak memory 1644452 kb
Host smart-01e67dc8-0fdf-42c5-9817-4490afd569eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364897133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2364897133
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3573845327
Short name T931
Test name
Test status
Simulation time 4610723283 ps
CPU time 23.7 seconds
Started May 12 12:48:53 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 377896 kb
Host smart-4285ae6d-4694-416f-a206-ba4febe4d75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573845327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3573845327
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1892050366
Short name T514
Test name
Test status
Simulation time 6213361408 ps
CPU time 522.29 seconds
Started May 12 12:49:03 PM PDT 24
Finished May 12 12:57:46 PM PDT 24
Peak memory 1125312 kb
Host smart-76c75f67-347d-4f7c-8d4e-c8ef1adeb060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892050366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1892050366
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3269100584
Short name T793
Test name
Test status
Simulation time 1002490677 ps
CPU time 22.34 seconds
Started May 12 12:48:55 PM PDT 24
Finished May 12 12:49:18 PM PDT 24
Peak memory 212472 kb
Host smart-4c56b2bc-20b8-4bf3-afaa-08e10d05096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269100584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3269100584
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.40282125
Short name T1103
Test name
Test status
Simulation time 1133722277 ps
CPU time 4.7 seconds
Started May 12 12:48:57 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 204360 kb
Host smart-88f5c270-aa8e-4ae7-bdf9-4e9893fdadca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40282125 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_bad_addr.40282125
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1656703052
Short name T339
Test name
Test status
Simulation time 10148211080 ps
CPU time 18.14 seconds
Started May 12 12:49:01 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 271600 kb
Host smart-994a69c4-d669-4e83-8e28-d79ed63e8a69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656703052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1656703052
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1010747874
Short name T324
Test name
Test status
Simulation time 10061977722 ps
CPU time 35.55 seconds
Started May 12 12:48:57 PM PDT 24
Finished May 12 12:49:33 PM PDT 24
Peak memory 369812 kb
Host smart-e0257cf6-9c3d-4ead-bbeb-09e9bb45d07f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010747874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1010747874
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1015913513
Short name T277
Test name
Test status
Simulation time 252394125 ps
CPU time 1.76 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 204184 kb
Host smart-8e781b23-390f-4e00-9ff4-fe827df73f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015913513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1015913513
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3855548881
Short name T854
Test name
Test status
Simulation time 3669136542 ps
CPU time 4.81 seconds
Started May 12 12:49:00 PM PDT 24
Finished May 12 12:49:05 PM PDT 24
Peak memory 204312 kb
Host smart-4f3f39fb-4f7b-47c5-976e-020635bb0479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855548881 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3855548881
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1601325196
Short name T707
Test name
Test status
Simulation time 21390083723 ps
CPU time 50.23 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 12:50:04 PM PDT 24
Peak memory 787204 kb
Host smart-daa3535a-0bce-452c-9086-be5a98b7d981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601325196 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1601325196
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2040454749
Short name T156
Test name
Test status
Simulation time 995891887 ps
CPU time 35.87 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:49:43 PM PDT 24
Peak memory 204320 kb
Host smart-cc67e77d-cc57-4c3f-9eb1-bb261bfa1af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040454749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2040454749
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1099808782
Short name T960
Test name
Test status
Simulation time 582756165 ps
CPU time 8.6 seconds
Started May 12 12:48:57 PM PDT 24
Finished May 12 12:49:06 PM PDT 24
Peak memory 208736 kb
Host smart-63b3be06-fb0b-45fb-820b-7617b1c261d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099808782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1099808782
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3680495938
Short name T20
Test name
Test status
Simulation time 56410911906 ps
CPU time 221.46 seconds
Started May 12 12:49:00 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 2371400 kb
Host smart-8e3f7aab-0ee1-4a76-8d69-83a1cd4245f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680495938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3680495938
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.635096682
Short name T1364
Test name
Test status
Simulation time 1391222647 ps
CPU time 7.07 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:15 PM PDT 24
Peak memory 220556 kb
Host smart-89629a12-8fa5-4fdd-86e6-aa78a7990da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635096682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.635096682
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.420503609
Short name T459
Test name
Test status
Simulation time 15063395 ps
CPU time 0.68 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:49:12 PM PDT 24
Peak memory 204100 kb
Host smart-7b290c7f-eef4-4c9a-ac14-5ab02a9359ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420503609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.420503609
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1484204324
Short name T368
Test name
Test status
Simulation time 106942052 ps
CPU time 1.47 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 212652 kb
Host smart-2992dd6c-f767-431b-bb6e-2f2a06e1c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484204324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1484204324
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2630468996
Short name T904
Test name
Test status
Simulation time 1065842162 ps
CPU time 13.52 seconds
Started May 12 12:48:57 PM PDT 24
Finished May 12 12:49:11 PM PDT 24
Peak memory 252284 kb
Host smart-9def4ad2-8cca-4489-8334-2ad902deb6a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630468996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2630468996
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1241808409
Short name T155
Test name
Test status
Simulation time 9667824587 ps
CPU time 90.23 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:50:41 PM PDT 24
Peak memory 748076 kb
Host smart-54c80a30-588c-4bcb-814a-8eff96957138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241808409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1241808409
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.988036581
Short name T1182
Test name
Test status
Simulation time 1772959389 ps
CPU time 49.88 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 12:50:03 PM PDT 24
Peak memory 623180 kb
Host smart-20ecb6b7-c573-4440-87cb-47dd6d93309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988036581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.988036581
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3271348631
Short name T965
Test name
Test status
Simulation time 543056622 ps
CPU time 1.06 seconds
Started May 12 12:49:14 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 204068 kb
Host smart-df7691e0-e471-434c-87b9-ef60a72a9943
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271348631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3271348631
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2203182369
Short name T914
Test name
Test status
Simulation time 697150354 ps
CPU time 4.46 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 236116 kb
Host smart-bbe2afe5-1eec-4200-ba6e-981e99505336
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203182369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2203182369
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1338627792
Short name T953
Test name
Test status
Simulation time 5492977005 ps
CPU time 106.88 seconds
Started May 12 12:49:01 PM PDT 24
Finished May 12 12:50:49 PM PDT 24
Peak memory 1257756 kb
Host smart-2f439d13-a68a-4b00-8a99-f3f9d16363fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338627792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1338627792
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3887417578
Short name T1243
Test name
Test status
Simulation time 312076688 ps
CPU time 3.85 seconds
Started May 12 12:49:08 PM PDT 24
Finished May 12 12:49:13 PM PDT 24
Peak memory 204300 kb
Host smart-9a2354d1-ceba-42f0-9a98-0d3184f331b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887417578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3887417578
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.2016116980
Short name T831
Test name
Test status
Simulation time 3667122625 ps
CPU time 36.15 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:49:47 PM PDT 24
Peak memory 350124 kb
Host smart-9eef79d9-3014-479a-8d01-b68b71522d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016116980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.2016116980
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2815961557
Short name T336
Test name
Test status
Simulation time 371911991 ps
CPU time 0.66 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:13 PM PDT 24
Peak memory 203996 kb
Host smart-f2e9b625-3c65-451c-967c-294459f45085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815961557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2815961557
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1564350463
Short name T996
Test name
Test status
Simulation time 13186336732 ps
CPU time 145.84 seconds
Started May 12 12:48:59 PM PDT 24
Finished May 12 12:51:25 PM PDT 24
Peak memory 859368 kb
Host smart-590d7f2b-1506-49de-9a2e-9ee7f858fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564350463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1564350463
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1572580550
Short name T1322
Test name
Test status
Simulation time 1892180533 ps
CPU time 45.18 seconds
Started May 12 12:49:05 PM PDT 24
Finished May 12 12:49:51 PM PDT 24
Peak memory 294828 kb
Host smart-a46a8d7e-b4d1-464a-8579-d092b442df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572580550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1572580550
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1281272079
Short name T124
Test name
Test status
Simulation time 12745854617 ps
CPU time 570.09 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:58:37 PM PDT 24
Peak memory 1615700 kb
Host smart-9fbbcc95-57b9-4c58-b800-3a2b0739e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281272079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1281272079
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3812543631
Short name T262
Test name
Test status
Simulation time 1834151545 ps
CPU time 7.06 seconds
Started May 12 12:49:00 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 212476 kb
Host smart-94f99430-9208-408d-8e11-6ee01c5ed578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812543631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3812543631
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1104220693
Short name T1330
Test name
Test status
Simulation time 2385785671 ps
CPU time 3.19 seconds
Started May 12 12:48:59 PM PDT 24
Finished May 12 12:49:03 PM PDT 24
Peak memory 204428 kb
Host smart-7fc860f8-a407-4127-bc38-d599bb4df445
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104220693 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1104220693
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1921034010
Short name T945
Test name
Test status
Simulation time 10068833866 ps
CPU time 68.49 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:50:20 PM PDT 24
Peak memory 464752 kb
Host smart-690df171-50dd-4167-b972-84775bada6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921034010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1921034010
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.895265660
Short name T894
Test name
Test status
Simulation time 10122988255 ps
CPU time 69.79 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 12:50:23 PM PDT 24
Peak memory 449656 kb
Host smart-755e04dc-dba7-48de-aa2d-c7309b95769e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895265660 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.895265660
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.299516475
Short name T293
Test name
Test status
Simulation time 796909759 ps
CPU time 4.67 seconds
Started May 12 12:49:17 PM PDT 24
Finished May 12 12:49:23 PM PDT 24
Peak memory 204188 kb
Host smart-7cdc682b-1701-45f3-ab57-c35e5fd6d3cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299516475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.299516475
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1030506183
Short name T920
Test name
Test status
Simulation time 17930690238 ps
CPU time 266.19 seconds
Started May 12 12:49:00 PM PDT 24
Finished May 12 12:53:27 PM PDT 24
Peak memory 2783756 kb
Host smart-1d324b36-cd7e-4108-9530-d97ac7f84e72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030506183 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1030506183
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2281911513
Short name T608
Test name
Test status
Simulation time 4470609343 ps
CPU time 42.1 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:50 PM PDT 24
Peak memory 204404 kb
Host smart-1193d806-dd24-459b-af91-5bdcf6d5076a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281911513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2281911513
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1260553332
Short name T251
Test name
Test status
Simulation time 5572973953 ps
CPU time 22.57 seconds
Started May 12 12:49:16 PM PDT 24
Finished May 12 12:49:39 PM PDT 24
Peak memory 235800 kb
Host smart-6aa21d54-6cd1-482c-b8c2-e62ae2f33589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260553332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1260553332
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1154491088
Short name T1195
Test name
Test status
Simulation time 15411966591 ps
CPU time 30.4 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:49:35 PM PDT 24
Peak memory 204272 kb
Host smart-d93267c9-3730-49f0-ad7f-e3ba26948b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154491088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1154491088
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1136662427
Short name T632
Test name
Test status
Simulation time 8083521854 ps
CPU time 177.13 seconds
Started May 12 12:49:16 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 1533964 kb
Host smart-1d074302-189d-4ac0-b05b-54b73e54eedd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136662427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1136662427
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3349433854
Short name T455
Test name
Test status
Simulation time 2478076676 ps
CPU time 7.4 seconds
Started May 12 12:49:01 PM PDT 24
Finished May 12 12:49:09 PM PDT 24
Peak memory 220748 kb
Host smart-c2db896b-00ca-4e4b-a52b-7a7513abb9d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349433854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3349433854
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3629900883
Short name T354
Test name
Test status
Simulation time 16843160 ps
CPU time 0.62 seconds
Started May 12 12:49:23 PM PDT 24
Finished May 12 12:49:24 PM PDT 24
Peak memory 204056 kb
Host smart-7600c4c0-c936-435e-b006-40c1060e1cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629900883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3629900883
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2973735226
Short name T1032
Test name
Test status
Simulation time 94588671 ps
CPU time 1.26 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 212468 kb
Host smart-9e7e40b9-65a1-4979-8a27-560ff15af074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973735226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2973735226
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3430744090
Short name T909
Test name
Test status
Simulation time 454578423 ps
CPU time 9.52 seconds
Started May 12 12:49:06 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 297068 kb
Host smart-5cc1725c-e19b-4f9b-b75f-474832ad2fd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430744090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3430744090
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1695363117
Short name T583
Test name
Test status
Simulation time 9793931382 ps
CPU time 88.18 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:50:39 PM PDT 24
Peak memory 816540 kb
Host smart-5c1c8278-93d8-47f0-ac71-2daf7a9e8f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695363117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1695363117
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3122919860
Short name T447
Test name
Test status
Simulation time 3058813283 ps
CPU time 44.79 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:57 PM PDT 24
Peak memory 585568 kb
Host smart-a9d43af7-9775-41e0-9136-e65616f1ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122919860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3122919860
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3976748895
Short name T1339
Test name
Test status
Simulation time 174577582 ps
CPU time 0.82 seconds
Started May 12 12:49:15 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 204084 kb
Host smart-5f0f8b06-9ec9-4db2-9e82-42cb864dd840
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976748895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3976748895
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1706641621
Short name T1361
Test name
Test status
Simulation time 121089486 ps
CPU time 2.97 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 219528 kb
Host smart-ea5bfa53-ad34-401d-8f94-f0646a09f4ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706641621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1706641621
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1199404612
Short name T400
Test name
Test status
Simulation time 23095758566 ps
CPU time 353.26 seconds
Started May 12 12:49:14 PM PDT 24
Finished May 12 12:55:08 PM PDT 24
Peak memory 1296108 kb
Host smart-db2ff863-1da8-4732-bcfd-63616dc85b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199404612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1199404612
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1713358895
Short name T897
Test name
Test status
Simulation time 1153982126 ps
CPU time 11.34 seconds
Started May 12 12:49:19 PM PDT 24
Finished May 12 12:49:31 PM PDT 24
Peak memory 204296 kb
Host smart-af317353-c482-4250-b274-1c22801f2a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713358895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1713358895
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3174167782
Short name T592
Test name
Test status
Simulation time 859512314 ps
CPU time 37.66 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:49:56 PM PDT 24
Peak memory 301932 kb
Host smart-1649676c-d9a8-4a5a-a003-b6097d8c1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174167782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3174167782
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.898622794
Short name T565
Test name
Test status
Simulation time 142665824 ps
CPU time 0.68 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:49:19 PM PDT 24
Peak memory 204108 kb
Host smart-078dac93-3632-44da-9436-fef1a3885f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898622794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.898622794
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1586463898
Short name T524
Test name
Test status
Simulation time 26164770967 ps
CPU time 517.7 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:57:56 PM PDT 24
Peak memory 221864 kb
Host smart-d2c0cf6d-8e20-460c-85d3-a8abe7651eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586463898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1586463898
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1783098810
Short name T506
Test name
Test status
Simulation time 4419418467 ps
CPU time 56.59 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:50:08 PM PDT 24
Peak memory 300400 kb
Host smart-74006b6e-15f0-4bd9-b50b-cf4c990e2b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783098810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1783098810
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3464349343
Short name T1045
Test name
Test status
Simulation time 18642442763 ps
CPU time 1244.73 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 01:09:57 PM PDT 24
Peak memory 3593436 kb
Host smart-9f3d6b45-4a48-4023-a491-bb084bb46045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464349343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3464349343
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2003285216
Short name T654
Test name
Test status
Simulation time 755457846 ps
CPU time 14.03 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:22 PM PDT 24
Peak memory 219820 kb
Host smart-0911db3e-33fd-43c8-ada8-0dc08806c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003285216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2003285216
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2444938733
Short name T1351
Test name
Test status
Simulation time 5613842771 ps
CPU time 4.76 seconds
Started May 12 12:49:23 PM PDT 24
Finished May 12 12:49:29 PM PDT 24
Peak memory 215268 kb
Host smart-424e9fb4-a625-420c-ab73-0f6f62898343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444938733 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2444938733
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3705752967
Short name T31
Test name
Test status
Simulation time 10718662343 ps
CPU time 6.06 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 12:49:19 PM PDT 24
Peak memory 227708 kb
Host smart-0b5f8e45-a449-4df4-99e0-bbc09aed9cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705752967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3705752967
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1150726342
Short name T817
Test name
Test status
Simulation time 10124963219 ps
CPU time 49.16 seconds
Started May 12 12:49:23 PM PDT 24
Finished May 12 12:50:12 PM PDT 24
Peak memory 446312 kb
Host smart-2a77913a-6689-410c-a299-bd54351559b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150726342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1150726342
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1153522152
Short name T747
Test name
Test status
Simulation time 5299066440 ps
CPU time 2.91 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:49:07 PM PDT 24
Peak memory 204400 kb
Host smart-d109fc73-8f54-4316-83b2-af524d70a1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153522152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1153522152
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3069114532
Short name T393
Test name
Test status
Simulation time 2807773938 ps
CPU time 5.47 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 204380 kb
Host smart-c6444ab6-613f-4294-a940-846f69f4d213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069114532 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3069114532
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1194971391
Short name T358
Test name
Test status
Simulation time 5696983971 ps
CPU time 24.86 seconds
Started May 12 12:49:27 PM PDT 24
Finished May 12 12:49:53 PM PDT 24
Peak memory 800440 kb
Host smart-841aa586-1559-4143-a41b-6fecc212b11d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194971391 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1194971391
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1705297325
Short name T494
Test name
Test status
Simulation time 876454573 ps
CPU time 30.38 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:42 PM PDT 24
Peak memory 204316 kb
Host smart-a684cb1c-7879-4e9f-80a2-cc7cb05bd446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705297325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1705297325
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1566423853
Short name T940
Test name
Test status
Simulation time 904124348 ps
CPU time 14.13 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 219336 kb
Host smart-77e962cf-1ebf-416c-a923-bc949b6518a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566423853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1566423853
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2494011039
Short name T290
Test name
Test status
Simulation time 15103505952 ps
CPU time 8.69 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 204372 kb
Host smart-b5ffb18c-9d73-4562-b710-da73ee1233a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494011039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2494011039
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1804704987
Short name T1193
Test name
Test status
Simulation time 31366257354 ps
CPU time 2075.9 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 01:23:49 PM PDT 24
Peak memory 7521640 kb
Host smart-44209105-2013-424a-a241-a01433462a88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804704987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1804704987
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.4012086280
Short name T409
Test name
Test status
Simulation time 3509237080 ps
CPU time 8.71 seconds
Started May 12 12:49:19 PM PDT 24
Finished May 12 12:49:29 PM PDT 24
Peak memory 215116 kb
Host smart-1945cbb1-5d7d-401d-b376-48e58bd245e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012086280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.4012086280
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2135116561
Short name T9
Test name
Test status
Simulation time 27427777 ps
CPU time 0.6 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:11 PM PDT 24
Peak memory 203856 kb
Host smart-01b2947d-11f2-4697-8e63-5f8d96e5d75d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135116561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2135116561
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1662052638
Short name T450
Test name
Test status
Simulation time 192138482 ps
CPU time 1.33 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:11 PM PDT 24
Peak memory 212656 kb
Host smart-74acf52d-a9bb-4c03-9e4c-f39b2ece0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662052638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1662052638
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1751863781
Short name T556
Test name
Test status
Simulation time 415961899 ps
CPU time 7.76 seconds
Started May 12 12:49:08 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 294452 kb
Host smart-f2cfc61c-7465-4e3a-8226-0932bbca92bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751863781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1751863781
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4239767704
Short name T385
Test name
Test status
Simulation time 1782945157 ps
CPU time 48.89 seconds
Started May 12 12:49:08 PM PDT 24
Finished May 12 12:49:58 PM PDT 24
Peak memory 558676 kb
Host smart-356c0928-a70b-4086-a024-21a887aded37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239767704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4239767704
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.4009228190
Short name T978
Test name
Test status
Simulation time 4015452075 ps
CPU time 64.05 seconds
Started May 12 12:49:17 PM PDT 24
Finished May 12 12:50:22 PM PDT 24
Peak memory 665284 kb
Host smart-396a70f8-37dc-4019-b6bb-4e01b6879de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009228190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.4009228190
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2706748161
Short name T959
Test name
Test status
Simulation time 85725111 ps
CPU time 0.85 seconds
Started May 12 12:49:14 PM PDT 24
Finished May 12 12:49:15 PM PDT 24
Peak memory 204200 kb
Host smart-b75731e0-d855-4c35-b46c-2aef9f091c43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706748161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2706748161
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3212264648
Short name T438
Test name
Test status
Simulation time 872994177 ps
CPU time 7.8 seconds
Started May 12 12:49:21 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 226144 kb
Host smart-4b482622-7895-4039-904d-d03cf055eed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212264648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3212264648
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.441028004
Short name T1350
Test name
Test status
Simulation time 4298034930 ps
CPU time 337.61 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:54:42 PM PDT 24
Peak memory 1260644 kb
Host smart-6f1b5240-c91f-43e3-8dc9-36ccb6ba3d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441028004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.441028004
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2502748186
Short name T684
Test name
Test status
Simulation time 958644436 ps
CPU time 21.14 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:32 PM PDT 24
Peak memory 204560 kb
Host smart-9f13755d-f4f1-46b4-a0cc-256c3b22407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502748186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2502748186
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1109796573
Short name T483
Test name
Test status
Simulation time 13067869369 ps
CPU time 21.93 seconds
Started May 12 12:49:08 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 294016 kb
Host smart-eb93888e-e028-4e09-9907-2c0209188571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109796573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1109796573
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_perf.70733860
Short name T578
Test name
Test status
Simulation time 1304047600 ps
CPU time 6.1 seconds
Started May 12 12:49:07 PM PDT 24
Finished May 12 12:49:14 PM PDT 24
Peak memory 212828 kb
Host smart-91f6e025-3827-4e29-9668-5acc5883331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70733860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.70733860
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2284478439
Short name T1326
Test name
Test status
Simulation time 6666575537 ps
CPU time 32.66 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:43 PM PDT 24
Peak memory 344924 kb
Host smart-44fd4dc8-1879-4567-81ca-01550bc0775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284478439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2284478439
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1402144270
Short name T1091
Test name
Test status
Simulation time 588752310 ps
CPU time 11.45 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:22 PM PDT 24
Peak memory 212592 kb
Host smart-c560b0c2-1a04-46c6-8f96-6e8dc502d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402144270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1402144270
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3355278986
Short name T690
Test name
Test status
Simulation time 4365499135 ps
CPU time 4.81 seconds
Started May 12 12:49:25 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 213132 kb
Host smart-253358cd-5692-42f3-b261-f8087808d6c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355278986 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3355278986
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2687697370
Short name T396
Test name
Test status
Simulation time 10080889523 ps
CPU time 62.7 seconds
Started May 12 12:49:02 PM PDT 24
Finished May 12 12:50:05 PM PDT 24
Peak memory 479064 kb
Host smart-afc582cd-ecd9-40bd-ab01-8969a0470e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687697370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2687697370
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3877406858
Short name T547
Test name
Test status
Simulation time 10143276981 ps
CPU time 73.02 seconds
Started May 12 12:49:28 PM PDT 24
Finished May 12 12:50:42 PM PDT 24
Peak memory 457524 kb
Host smart-86e003c9-2a64-4124-94f5-dd964306a8ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877406858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3877406858
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1745871317
Short name T741
Test name
Test status
Simulation time 337597477 ps
CPU time 2.1 seconds
Started May 12 12:49:27 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 204240 kb
Host smart-9c3305f8-8d60-4810-bd73-e4789f42a7ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745871317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1745871317
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2734484619
Short name T280
Test name
Test status
Simulation time 1148125287 ps
CPU time 6.16 seconds
Started May 12 12:49:19 PM PDT 24
Finished May 12 12:49:26 PM PDT 24
Peak memory 212496 kb
Host smart-49c7122a-a61a-4da5-aeac-b524ae0f6f0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734484619 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2734484619
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.857678378
Short name T1147
Test name
Test status
Simulation time 27439413215 ps
CPU time 79.69 seconds
Started May 12 12:49:03 PM PDT 24
Finished May 12 12:50:23 PM PDT 24
Peak memory 1463988 kb
Host smart-75efc944-7e75-4b48-98a5-b6591261c9ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857678378 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.857678378
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.4023695536
Short name T410
Test name
Test status
Simulation time 1808341896 ps
CPU time 30.79 seconds
Started May 12 12:49:04 PM PDT 24
Finished May 12 12:49:35 PM PDT 24
Peak memory 204396 kb
Host smart-89575974-153a-4df8-8d58-f0b6b8916a4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023695536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.4023695536
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.760490098
Short name T1356
Test name
Test status
Simulation time 2657585652 ps
CPU time 29.29 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:42 PM PDT 24
Peak memory 204404 kb
Host smart-519f914d-e2bf-4ab6-ae58-8577a61b691d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760490098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.760490098
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1370326661
Short name T128
Test name
Test status
Simulation time 23388167106 ps
CPU time 69.9 seconds
Started May 12 12:49:15 PM PDT 24
Finished May 12 12:50:25 PM PDT 24
Peak memory 960160 kb
Host smart-9d8fa92c-d8f2-4f56-833f-14ac355289b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370326661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1370326661
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.152679724
Short name T1028
Test name
Test status
Simulation time 16107502444 ps
CPU time 234.86 seconds
Started May 12 12:49:20 PM PDT 24
Finished May 12 12:53:16 PM PDT 24
Peak memory 1944012 kb
Host smart-1bb16e4e-67b6-4f32-b93c-e5f003140ab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152679724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.152679724
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3477587505
Short name T426
Test name
Test status
Simulation time 2764022097 ps
CPU time 7.57 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:20 PM PDT 24
Peak memory 220556 kb
Host smart-07685861-fb46-4e45-b4d8-d884c48e8187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477587505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3477587505
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4243262135
Short name T1137
Test name
Test status
Simulation time 18003070 ps
CPU time 0.65 seconds
Started May 12 12:49:11 PM PDT 24
Finished May 12 12:49:13 PM PDT 24
Peak memory 204024 kb
Host smart-79258619-eb6e-4818-9a1f-84a7b0869d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243262135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4243262135
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.960950489
Short name T341
Test name
Test status
Simulation time 320356125 ps
CPU time 1.7 seconds
Started May 12 12:49:10 PM PDT 24
Finished May 12 12:49:13 PM PDT 24
Peak memory 212652 kb
Host smart-c370dd4f-768f-4d45-b5dc-b48cc3e65d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960950489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.960950489
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4151781281
Short name T1319
Test name
Test status
Simulation time 200396312 ps
CPU time 4.29 seconds
Started May 12 12:49:26 PM PDT 24
Finished May 12 12:49:32 PM PDT 24
Peak memory 239692 kb
Host smart-59114222-8b65-4099-821d-982fe0bbdb38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151781281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.4151781281
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2989908553
Short name T1184
Test name
Test status
Simulation time 8238527391 ps
CPU time 38.06 seconds
Started May 12 12:49:27 PM PDT 24
Finished May 12 12:50:06 PM PDT 24
Peak memory 531480 kb
Host smart-c9b8f60d-eaec-4de4-b511-7fde673b2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989908553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2989908553
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3294361936
Short name T1040
Test name
Test status
Simulation time 38412684484 ps
CPU time 86.44 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:50:36 PM PDT 24
Peak memory 778456 kb
Host smart-7bd9ae5b-bc02-4c23-8db1-19f9803596aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294361936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3294361936
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2876661602
Short name T236
Test name
Test status
Simulation time 584518027 ps
CPU time 1.1 seconds
Started May 12 12:49:28 PM PDT 24
Finished May 12 12:49:30 PM PDT 24
Peak memory 204236 kb
Host smart-126cc29d-52ba-4fbb-a0a8-b52a2895bcc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876661602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2876661602
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2272763853
Short name T1154
Test name
Test status
Simulation time 556521550 ps
CPU time 5.87 seconds
Started May 12 12:49:08 PM PDT 24
Finished May 12 12:49:15 PM PDT 24
Peak memory 204352 kb
Host smart-ba72ef1b-25f2-4414-8f1c-0010aefa72f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272763853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2272763853
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2464571170
Short name T80
Test name
Test status
Simulation time 2180683222 ps
CPU time 126.35 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 661980 kb
Host smart-4084a025-12d9-4332-9710-fad3a490d1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464571170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2464571170
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1609068188
Short name T1015
Test name
Test status
Simulation time 3732137136 ps
CPU time 9.11 seconds
Started May 12 12:49:13 PM PDT 24
Finished May 12 12:49:23 PM PDT 24
Peak memory 204444 kb
Host smart-e6f6f323-9b91-4bd8-9b69-bd0b2af80873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609068188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1609068188
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.30422654
Short name T644
Test name
Test status
Simulation time 3334851307 ps
CPU time 30.83 seconds
Started May 12 12:49:24 PM PDT 24
Finished May 12 12:49:55 PM PDT 24
Peak memory 344888 kb
Host smart-8e9b26e2-5df5-41d9-8b4b-84fe45c081f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30422654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.30422654
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.2980459074
Short name T1186
Test name
Test status
Simulation time 46818229 ps
CPU time 0.68 seconds
Started May 12 12:49:15 PM PDT 24
Finished May 12 12:49:16 PM PDT 24
Peak memory 204016 kb
Host smart-b58dac1b-40ab-419d-adfb-9b1f84f214bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980459074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2980459074
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1270325802
Short name T853
Test name
Test status
Simulation time 48860801117 ps
CPU time 2599.28 seconds
Started May 12 12:49:27 PM PDT 24
Finished May 12 01:32:48 PM PDT 24
Peak memory 4448216 kb
Host smart-c8dabc69-2f3e-480b-b190-cd678bfce675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270325802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1270325802
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1315366245
Short name T492
Test name
Test status
Simulation time 1484727950 ps
CPU time 65.59 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:50:16 PM PDT 24
Peak memory 244684 kb
Host smart-71f688e4-73db-415d-b95b-bfd5336eb9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315366245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1315366245
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2252266394
Short name T475
Test name
Test status
Simulation time 53097670954 ps
CPU time 2005.88 seconds
Started May 12 12:49:26 PM PDT 24
Finished May 12 01:22:52 PM PDT 24
Peak memory 2930220 kb
Host smart-2c57571a-edd3-4cde-8b62-7a5d3312e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252266394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2252266394
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4241488566
Short name T390
Test name
Test status
Simulation time 2454247846 ps
CPU time 24.84 seconds
Started May 12 12:49:14 PM PDT 24
Finished May 12 12:49:40 PM PDT 24
Peak memory 212548 kb
Host smart-70666779-183e-4a27-b505-8250eb700798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241488566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4241488566
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1367074253
Short name T1239
Test name
Test status
Simulation time 648967374 ps
CPU time 2.99 seconds
Started May 12 12:49:19 PM PDT 24
Finished May 12 12:49:23 PM PDT 24
Peak memory 204388 kb
Host smart-d11080df-55d5-41ca-a698-574f460f966b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367074253 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1367074253
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1451018368
Short name T153
Test name
Test status
Simulation time 10258803618 ps
CPU time 15.97 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 254996 kb
Host smart-8381a3ea-76d4-40eb-955d-2244b4d8c691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451018368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1451018368
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2710937541
Short name T378
Test name
Test status
Simulation time 10767291123 ps
CPU time 10.93 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:21 PM PDT 24
Peak memory 274464 kb
Host smart-935e30c8-5d7f-4624-944e-cfd8799dc129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710937541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2710937541
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2295414665
Short name T539
Test name
Test status
Simulation time 1725071066 ps
CPU time 2.43 seconds
Started May 12 12:49:14 PM PDT 24
Finished May 12 12:49:17 PM PDT 24
Peak memory 204300 kb
Host smart-6a5a27dd-fb2f-4bf7-9c6c-43a7a5890cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295414665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2295414665
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1962663332
Short name T1111
Test name
Test status
Simulation time 1470570767 ps
CPU time 7.22 seconds
Started May 12 12:49:28 PM PDT 24
Finished May 12 12:49:36 PM PDT 24
Peak memory 212472 kb
Host smart-a4b863b8-40b3-403c-b354-5a7f80a1daa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962663332 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1962663332
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.1504375057
Short name T474
Test name
Test status
Simulation time 851350634 ps
CPU time 32.57 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:49:51 PM PDT 24
Peak memory 204256 kb
Host smart-5ab4aead-060d-436a-8deb-daf38ec7fe22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504375057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.1504375057
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2879659271
Short name T387
Test name
Test status
Simulation time 11809601016 ps
CPU time 22.76 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:49:33 PM PDT 24
Peak memory 218136 kb
Host smart-8374f733-ba51-4b6d-8392-171591f44091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879659271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2879659271
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.4110611540
Short name T305
Test name
Test status
Simulation time 54326794403 ps
CPU time 174.66 seconds
Started May 12 12:49:12 PM PDT 24
Finished May 12 12:52:08 PM PDT 24
Peak memory 2135824 kb
Host smart-07d6228f-c91a-4654-b675-71a65df46a5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110611540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.4110611540
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2559487829
Short name T313
Test name
Test status
Simulation time 13574120333 ps
CPU time 211.42 seconds
Started May 12 12:49:09 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 880312 kb
Host smart-1e3d6b00-0ff5-48c3-a2a8-94a3ca5f60ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559487829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2559487829
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.637674310
Short name T870
Test name
Test status
Simulation time 1370542764 ps
CPU time 6.8 seconds
Started May 12 12:49:18 PM PDT 24
Finished May 12 12:49:25 PM PDT 24
Peak memory 210808 kb
Host smart-d87e9232-6e30-49c0-9e85-b408de693466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637674310 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.637674310
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2300530507
Short name T709
Test name
Test status
Simulation time 1683390155 ps
CPU time 5.13 seconds
Started May 12 12:49:30 PM PDT 24
Finished May 12 12:49:36 PM PDT 24
Peak memory 204264 kb
Host smart-58fcd8b1-9c18-4753-99e1-17f3e3f4f6f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300530507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2300530507
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2605103469
Short name T711
Test name
Test status
Simulation time 15691017 ps
CPU time 0.63 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 203928 kb
Host smart-c80335cf-b96e-4cf7-8abb-7747def5ae06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605103469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2605103469
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3963608122
Short name T1341
Test name
Test status
Simulation time 619680131 ps
CPU time 1.26 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 212608 kb
Host smart-fb739d08-ded5-4ffc-a49f-b3df235cbd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963608122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3963608122
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1382852487
Short name T1176
Test name
Test status
Simulation time 1193970809 ps
CPU time 7.16 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:46:28 PM PDT 24
Peak memory 270100 kb
Host smart-9554365b-8854-43c3-b96f-abf5dc88ecd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382852487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1382852487
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2473611299
Short name T59
Test name
Test status
Simulation time 9388866481 ps
CPU time 59.19 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:47:14 PM PDT 24
Peak memory 654828 kb
Host smart-7e5323a2-d33f-41dd-b018-fa9aad41dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473611299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2473611299
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.499694984
Short name T760
Test name
Test status
Simulation time 1852159221 ps
CPU time 61.02 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:47:19 PM PDT 24
Peak memory 643780 kb
Host smart-241993d1-2890-4f4c-ab81-f8ede4a5df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499694984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.499694984
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1424247160
Short name T962
Test name
Test status
Simulation time 120116707 ps
CPU time 1.11 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 204312 kb
Host smart-261a6500-cf81-4b01-95a9-b253f478e3bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424247160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1424247160
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.723600542
Short name T947
Test name
Test status
Simulation time 122774438 ps
CPU time 3.42 seconds
Started May 12 12:46:18 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 221320 kb
Host smart-92dab92b-4ec4-46bf-8918-808bc112939e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723600542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.723600542
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.661897243
Short name T159
Test name
Test status
Simulation time 3598076240 ps
CPU time 267.12 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:50:40 PM PDT 24
Peak memory 1052228 kb
Host smart-831874bb-5c1f-4277-8a6e-61003e581364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661897243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.661897243
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3042606140
Short name T1130
Test name
Test status
Simulation time 501816397 ps
CPU time 20.57 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:58 PM PDT 24
Peak memory 204456 kb
Host smart-6707446c-404c-4976-9c36-d680fedb2f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042606140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3042606140
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1816434949
Short name T432
Test name
Test status
Simulation time 2357110590 ps
CPU time 72.51 seconds
Started May 12 12:46:02 PM PDT 24
Finished May 12 12:47:15 PM PDT 24
Peak memory 373628 kb
Host smart-f0988765-e7ac-4571-808a-20eedf3315ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816434949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1816434949
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.930718054
Short name T607
Test name
Test status
Simulation time 85684428 ps
CPU time 0.72 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 204024 kb
Host smart-34df1673-744b-4929-b21e-6689862f9159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930718054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.930718054
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.947941810
Short name T1215
Test name
Test status
Simulation time 2621286013 ps
CPU time 55.79 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:47:09 PM PDT 24
Peak memory 216896 kb
Host smart-2b40b639-2f74-4491-bc88-b8625b9c4227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947941810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.947941810
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2267209429
Short name T1227
Test name
Test status
Simulation time 1079793842 ps
CPU time 17.1 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:46:31 PM PDT 24
Peak memory 284096 kb
Host smart-dd3db481-9722-4016-b8f6-679a110daa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267209429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2267209429
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1706544432
Short name T531
Test name
Test status
Simulation time 855866619 ps
CPU time 16.77 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 218584 kb
Host smart-429b440f-833e-4560-8179-c2887b9da296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706544432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1706544432
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.931896800
Short name T1039
Test name
Test status
Simulation time 3323221905 ps
CPU time 4.79 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:20 PM PDT 24
Peak memory 212560 kb
Host smart-78fab6a3-92e8-4ed4-a34d-d203d2290e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931896800 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.931896800
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3427012195
Short name T152
Test name
Test status
Simulation time 10227917581 ps
CPU time 12.05 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 268096 kb
Host smart-c6717cf4-9d02-4625-8879-17dd9b2b7812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427012195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3427012195
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.335294246
Short name T64
Test name
Test status
Simulation time 10115913139 ps
CPU time 76.12 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:47:44 PM PDT 24
Peak memory 584740 kb
Host smart-ed341e29-d67c-417e-a706-0070e2ba496e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335294246 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.335294246
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.220406847
Short name T522
Test name
Test status
Simulation time 774745970 ps
CPU time 2.77 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 204300 kb
Host smart-ed3629cb-a516-4ac0-b921-90a04f272d08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220406847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.220406847
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2481125466
Short name T877
Test name
Test status
Simulation time 3662476322 ps
CPU time 5.08 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 207828 kb
Host smart-cde431d4-74f3-4076-8143-70390e4942bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481125466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2481125466
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.421487960
Short name T1273
Test name
Test status
Simulation time 33404295094 ps
CPU time 56.95 seconds
Started May 12 12:46:05 PM PDT 24
Finished May 12 12:47:08 PM PDT 24
Peak memory 1103444 kb
Host smart-9023d7cd-a47a-44c6-a829-de73f0201e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421487960 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.421487960
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1120960357
Short name T824
Test name
Test status
Simulation time 6186829616 ps
CPU time 25.75 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:54 PM PDT 24
Peak memory 204420 kb
Host smart-1f1df91d-f13a-4c2d-ade6-8f5e4f968f6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120960357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1120960357
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3329210920
Short name T249
Test name
Test status
Simulation time 10495351258 ps
CPU time 32.99 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 232772 kb
Host smart-168af887-3053-4a47-8def-d7f1a93075a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329210920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3329210920
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1809133691
Short name T1004
Test name
Test status
Simulation time 44478961093 ps
CPU time 826.22 seconds
Started May 12 12:46:18 PM PDT 24
Finished May 12 01:00:05 PM PDT 24
Peak memory 6159408 kb
Host smart-33b7ae3e-bcfd-4991-8c07-8d3e9fabda73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809133691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1809133691
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.5955228
Short name T530
Test name
Test status
Simulation time 38976212990 ps
CPU time 2171.88 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 01:22:47 PM PDT 24
Peak memory 7218264 kb
Host smart-c193b4cb-c709-4765-a5c4-5a01a6dcc554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5955228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_stretch.5955228
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3805849513
Short name T1306
Test name
Test status
Simulation time 2288289648 ps
CPU time 6.75 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:46:32 PM PDT 24
Peak memory 210960 kb
Host smart-cf94f714-7d3d-46c8-a22d-b70774c122c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805849513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3805849513
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.991906313
Short name T326
Test name
Test status
Simulation time 22584284 ps
CPU time 0.59 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 204064 kb
Host smart-0ac4ab96-b668-4c3b-9f54-948637448ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991906313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.991906313
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2177886325
Short name T926
Test name
Test status
Simulation time 91349173 ps
CPU time 1.48 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 212624 kb
Host smart-b368ca58-2c7d-4cba-841e-17d54d46ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177886325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2177886325
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3053375834
Short name T764
Test name
Test status
Simulation time 394756573 ps
CPU time 4.29 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 240784 kb
Host smart-7bef09c4-4896-4a6e-9272-9f6fa1b91f8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053375834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3053375834
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2472328405
Short name T149
Test name
Test status
Simulation time 9028059562 ps
CPU time 66.73 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:47:33 PM PDT 24
Peak memory 670232 kb
Host smart-4705d0c3-f342-479d-97ca-33c20a5ee8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472328405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2472328405
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1936281108
Short name T1233
Test name
Test status
Simulation time 3595875504 ps
CPU time 74.29 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:47:47 PM PDT 24
Peak memory 778380 kb
Host smart-7a6dfd99-1e1f-4f59-9e10-d919dfa1a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936281108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1936281108
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3813172468
Short name T113
Test name
Test status
Simulation time 475169748 ps
CPU time 5.77 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 218580 kb
Host smart-47fdf670-70d0-4b15-bb8f-6872caeece8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813172468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3813172468
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.146978363
Short name T830
Test name
Test status
Simulation time 6284078063 ps
CPU time 229.99 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:50:17 PM PDT 24
Peak memory 984708 kb
Host smart-b3617d71-d6bb-42f1-a1f9-bc9fd460d828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146978363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.146978363
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3503717379
Short name T874
Test name
Test status
Simulation time 1992074991 ps
CPU time 20.55 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:54 PM PDT 24
Peak memory 204320 kb
Host smart-1c455da0-c544-4d5a-b2b2-3e3a5a757fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503717379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3503717379
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.460540091
Short name T879
Test name
Test status
Simulation time 3255777061 ps
CPU time 33.13 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:47:06 PM PDT 24
Peak memory 328864 kb
Host smart-cd624a1a-b611-463f-930c-494bad2e8ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460540091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.460540091
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.931126646
Short name T563
Test name
Test status
Simulation time 88583943 ps
CPU time 0.65 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:46:26 PM PDT 24
Peak memory 203940 kb
Host smart-5567802e-2164-4773-9a34-bc6aa7e5f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931126646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.931126646
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1275031229
Short name T972
Test name
Test status
Simulation time 6411948829 ps
CPU time 233.74 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:50:19 PM PDT 24
Peak memory 958508 kb
Host smart-1640f591-8139-452b-af0e-702e6f54af70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275031229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1275031229
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3879500463
Short name T1157
Test name
Test status
Simulation time 2236680648 ps
CPU time 17.99 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 296760 kb
Host smart-c2fcddb6-a71d-4751-bb56-e19b99a79e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879500463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3879500463
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2205995598
Short name T537
Test name
Test status
Simulation time 1423723124 ps
CPU time 29.26 seconds
Started May 12 12:46:16 PM PDT 24
Finished May 12 12:46:51 PM PDT 24
Peak memory 212572 kb
Host smart-3fcae5c1-185a-4a67-a273-ce00647f11dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205995598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2205995598
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4197623416
Short name T493
Test name
Test status
Simulation time 11839677803 ps
CPU time 4.04 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:37 PM PDT 24
Peak memory 204416 kb
Host smart-c070afa1-60db-43d1-aca7-8305f62ef443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197623416 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4197623416
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.700023279
Short name T373
Test name
Test status
Simulation time 10403233978 ps
CPU time 9.38 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:38 PM PDT 24
Peak memory 239068 kb
Host smart-bc9e1b82-d34d-4c72-b07d-e48e768ffae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700023279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.700023279
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3229235303
Short name T181
Test name
Test status
Simulation time 10153405603 ps
CPU time 82.83 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 576908 kb
Host smart-22e10e91-f8be-4734-ae5c-62753304ec62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229235303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3229235303
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1051071608
Short name T678
Test name
Test status
Simulation time 2766419176 ps
CPU time 2.69 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:38 PM PDT 24
Peak memory 204408 kb
Host smart-0ef9b7cf-f4dd-466d-8b07-c951f8d94851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051071608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1051071608
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3486094502
Short name T1289
Test name
Test status
Simulation time 4309787551 ps
CPU time 6.15 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 220696 kb
Host smart-55505e91-3054-41d6-a156-c60dfdcbba51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486094502 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3486094502
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2883885067
Short name T398
Test name
Test status
Simulation time 10715657611 ps
CPU time 59.53 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 1113172 kb
Host smart-55f6d14b-9405-4eb5-b543-8cd1ec36c8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883885067 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2883885067
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3420263583
Short name T166
Test name
Test status
Simulation time 868920515 ps
CPU time 30.77 seconds
Started May 12 12:46:25 PM PDT 24
Finished May 12 12:46:56 PM PDT 24
Peak memory 204324 kb
Host smart-b0ca1a14-e8cd-4582-9c25-ee6d40b67f2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420263583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3420263583
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2425430867
Short name T1244
Test name
Test status
Simulation time 2549947129 ps
CPU time 24.35 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:46:56 PM PDT 24
Peak memory 219056 kb
Host smart-509deea9-ba21-40b8-b657-46888c683b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425430867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2425430867
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.4235627933
Short name T307
Test name
Test status
Simulation time 25226614132 ps
CPU time 96.33 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:47:57 PM PDT 24
Peak memory 1448536 kb
Host smart-74715c1a-833d-4f12-825b-7fef8bdfa452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235627933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.4235627933
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.19728155
Short name T5
Test name
Test status
Simulation time 8194859580 ps
CPU time 91.82 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:48:04 PM PDT 24
Peak memory 556488 kb
Host smart-97634051-e10d-43cb-9661-317defef8b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19728155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_stretch.19728155
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2325433791
Short name T1065
Test name
Test status
Simulation time 2901132149 ps
CPU time 7.09 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 220604 kb
Host smart-16eccce1-f965-43d4-b3e8-cbd3e7f00565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325433791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2325433791
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2496547730
Short name T1058
Test name
Test status
Simulation time 26546789 ps
CPU time 0.61 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:46:43 PM PDT 24
Peak memory 204096 kb
Host smart-131f90e6-45ee-4129-9722-f309b01cf74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496547730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2496547730
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1450235881
Short name T840
Test name
Test status
Simulation time 204607497 ps
CPU time 1.33 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:46:28 PM PDT 24
Peak memory 212676 kb
Host smart-fdec54e9-3471-40bb-8405-eb8e0dc591da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450235881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1450235881
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.172031922
Short name T571
Test name
Test status
Simulation time 318075704 ps
CPU time 3.59 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 232372 kb
Host smart-48f57119-14eb-4cf5-a34d-45002757358d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172031922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.172031922
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3524722797
Short name T1298
Test name
Test status
Simulation time 23396077118 ps
CPU time 168.4 seconds
Started May 12 12:46:29 PM PDT 24
Finished May 12 12:49:18 PM PDT 24
Peak memory 731244 kb
Host smart-ab6ebe1f-d000-44c5-81cf-70dc7d9f511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524722797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3524722797
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.633493946
Short name T809
Test name
Test status
Simulation time 1086906372 ps
CPU time 67.61 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:47:48 PM PDT 24
Peak memory 437356 kb
Host smart-2bb47382-610c-4c52-a52f-6cd9ff49af0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633493946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.633493946
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.25058447
Short name T234
Test name
Test status
Simulation time 253922450 ps
CPU time 1.07 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 204280 kb
Host smart-c9e73b1d-08ba-4da1-9d4f-0fc8c1ee52c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.25058447
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3689924496
Short name T562
Test name
Test status
Simulation time 952877272 ps
CPU time 4.29 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 204296 kb
Host smart-e29398c3-b73c-466c-bc3a-2eaaa9808b41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689924496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3689924496
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2059848201
Short name T856
Test name
Test status
Simulation time 23489758304 ps
CPU time 63.21 seconds
Started May 12 12:46:30 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 787664 kb
Host smart-6637a6ac-e6e7-4a88-94c8-7a218addf08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059848201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2059848201
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.971398263
Short name T558
Test name
Test status
Simulation time 1325351008 ps
CPU time 10.9 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 204268 kb
Host smart-cf369d42-a0e1-4827-ab29-ff0586fa6bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971398263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.971398263
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.4200928982
Short name T958
Test name
Test status
Simulation time 1162657251 ps
CPU time 21.44 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:56 PM PDT 24
Peak memory 275716 kb
Host smart-963acc60-5e0f-4c7c-b3e5-fec463959dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200928982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.4200928982
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3345052815
Short name T125
Test name
Test status
Simulation time 20243492 ps
CPU time 0.67 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:23 PM PDT 24
Peak memory 203964 kb
Host smart-4b206ccb-3482-45be-bbe3-bc0f9ac1a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345052815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3345052815
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2299732056
Short name T748
Test name
Test status
Simulation time 17595906061 ps
CPU time 958.91 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 01:02:37 PM PDT 24
Peak memory 3299468 kb
Host smart-6e803f4d-ca01-498f-b494-e260dd2af898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299732056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2299732056
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.57301524
Short name T950
Test name
Test status
Simulation time 1757858519 ps
CPU time 17.52 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:41 PM PDT 24
Peak memory 317024 kb
Host smart-d413cf88-8c7c-40fa-9e04-f18867992f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57301524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.57301524
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1158897796
Short name T173
Test name
Test status
Simulation time 57188278259 ps
CPU time 1460.59 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 01:10:44 PM PDT 24
Peak memory 2484552 kb
Host smart-b964000b-9eac-4481-b0ec-6438cde6de55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158897796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1158897796
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2625849014
Short name T112
Test name
Test status
Simulation time 840099158 ps
CPU time 32.37 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:10 PM PDT 24
Peak memory 220544 kb
Host smart-ef452893-f5a5-4120-9638-a6115123906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625849014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2625849014
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.789552155
Short name T309
Test name
Test status
Simulation time 1973483057 ps
CPU time 4.01 seconds
Started May 12 12:46:43 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 212528 kb
Host smart-aa8b74c9-dd00-45fc-97ce-afa2fddb9df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789552155 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.789552155
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1105335028
Short name T596
Test name
Test status
Simulation time 10153479154 ps
CPU time 45.12 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:23 PM PDT 24
Peak memory 435092 kb
Host smart-24380e67-1c20-4b84-9356-dce47a89131c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105335028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1105335028
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2936899576
Short name T939
Test name
Test status
Simulation time 10405845817 ps
CPU time 14.12 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 283292 kb
Host smart-e49cc78a-a728-4c88-aa21-e0b77f5ee59e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936899576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2936899576
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2898854443
Short name T24
Test name
Test status
Simulation time 250542420 ps
CPU time 2.04 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:46:43 PM PDT 24
Peak memory 204452 kb
Host smart-2b147a6a-5d83-4636-8757-c5c59eac2865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898854443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2898854443
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.641071390
Short name T670
Test name
Test status
Simulation time 4383512947 ps
CPU time 5.56 seconds
Started May 12 12:46:26 PM PDT 24
Finished May 12 12:46:32 PM PDT 24
Peak memory 212600 kb
Host smart-19fd9c4f-dd36-45f6-ad02-e2bb182b5c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641071390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.641071390
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.915762692
Short name T1060
Test name
Test status
Simulation time 3372438793 ps
CPU time 8.85 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 456200 kb
Host smart-b6025d44-8dba-4d02-9958-a83cac4e9853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915762692 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.915762692
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2737799683
Short name T394
Test name
Test status
Simulation time 821516767 ps
CPU time 29.72 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 204192 kb
Host smart-b51e4ddc-3385-45cc-a421-91afe8732bec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737799683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2737799683
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.4085027601
Short name T540
Test name
Test status
Simulation time 3532013476 ps
CPU time 37.43 seconds
Started May 12 12:46:30 PM PDT 24
Finished May 12 12:47:07 PM PDT 24
Peak memory 204424 kb
Host smart-fefaa61d-bf15-42f5-b97e-f461143e30cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085027601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.4085027601
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3822626945
Short name T1129
Test name
Test status
Simulation time 40251032318 ps
CPU time 74.09 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:47:43 PM PDT 24
Peak memory 1189072 kb
Host smart-5f936b1b-372a-47b0-b4d3-ab3bb737c76c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822626945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3822626945
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3764111261
Short name T1231
Test name
Test status
Simulation time 18514113394 ps
CPU time 1000.08 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 01:03:16 PM PDT 24
Peak memory 2364400 kb
Host smart-c391edeb-2e9b-453c-960d-37a20dc2fa6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764111261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3764111261
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.533881071
Short name T46
Test name
Test status
Simulation time 1391812832 ps
CPU time 7.44 seconds
Started May 12 12:46:29 PM PDT 24
Finished May 12 12:46:37 PM PDT 24
Peak memory 212640 kb
Host smart-84d45ef7-15a1-479e-91cf-1a61cac6bcf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533881071 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.533881071
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.4096140988
Short name T10
Test name
Test status
Simulation time 16549703 ps
CPU time 0.63 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 204116 kb
Host smart-09f9c87d-d08e-402e-b204-cbe93f8aa5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096140988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.4096140988
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1406070544
Short name T952
Test name
Test status
Simulation time 275165415 ps
CPU time 1.26 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 220924 kb
Host smart-571994a5-a54f-4562-96b7-16f47fe30fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406070544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1406070544
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1733470197
Short name T1109
Test name
Test status
Simulation time 1103008225 ps
CPU time 30.5 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:17 PM PDT 24
Peak memory 316480 kb
Host smart-e75292e4-ae26-4cee-ba4e-9424f26351e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733470197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1733470197
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3764626204
Short name T993
Test name
Test status
Simulation time 3513101189 ps
CPU time 117.33 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:48:30 PM PDT 24
Peak memory 616224 kb
Host smart-9e9f3cd1-066f-4583-b8f3-9ec51d76082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764626204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3764626204
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.4008123473
Short name T551
Test name
Test status
Simulation time 3930358758 ps
CPU time 60.85 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:47:34 PM PDT 24
Peak memory 633484 kb
Host smart-90535863-d31f-4c5c-a4e2-90151020b701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008123473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4008123473
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3094937220
Short name T1095
Test name
Test status
Simulation time 78829863 ps
CPU time 0.84 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:39 PM PDT 24
Peak memory 204108 kb
Host smart-48931fcf-8ea9-4096-b898-e8ee14d1f358
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094937220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3094937220
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.671722528
Short name T1221
Test name
Test status
Simulation time 758300232 ps
CPU time 10.33 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 240916 kb
Host smart-2c3d021f-30db-45af-871a-dcac76b47138
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671722528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.671722528
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2505460096
Short name T640
Test name
Test status
Simulation time 12048733614 ps
CPU time 79.67 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:47:49 PM PDT 24
Peak memory 922580 kb
Host smart-2187361b-c34e-4f14-a5cf-768c070a0938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505460096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2505460096
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1511812279
Short name T889
Test name
Test status
Simulation time 3119183090 ps
CPU time 6.16 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 204428 kb
Host smart-5b964c40-ef4a-4483-8ce6-21b021edad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511812279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1511812279
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1762567321
Short name T321
Test name
Test status
Simulation time 2807602180 ps
CPU time 18.97 seconds
Started May 12 12:46:38 PM PDT 24
Finished May 12 12:46:58 PM PDT 24
Peak memory 289084 kb
Host smart-a4001883-b316-473d-8a2c-025585f74603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762567321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1762567321
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2625486051
Short name T1034
Test name
Test status
Simulation time 16662515 ps
CPU time 0.66 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 204144 kb
Host smart-3503b648-9933-4984-b011-fd25ac47c596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625486051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2625486051
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1280634182
Short name T83
Test name
Test status
Simulation time 17773117619 ps
CPU time 708.44 seconds
Started May 12 12:46:55 PM PDT 24
Finished May 12 12:58:44 PM PDT 24
Peak memory 212664 kb
Host smart-8e970cf6-b82a-4b67-bfa7-7143ad28154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280634182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1280634182
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1454777789
Short name T292
Test name
Test status
Simulation time 3931499674 ps
CPU time 17.44 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 277528 kb
Host smart-2da5ebc9-5171-41b5-987e-07df2f359d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454777789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1454777789
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1437528782
Short name T1294
Test name
Test status
Simulation time 84763663854 ps
CPU time 1028.32 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 01:03:46 PM PDT 24
Peak memory 1869508 kb
Host smart-5dbaee6d-331b-4c83-848d-6cd7628d5a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437528782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1437528782
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3346311883
Short name T703
Test name
Test status
Simulation time 2738342786 ps
CPU time 26.78 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:47:04 PM PDT 24
Peak memory 213684 kb
Host smart-286330ec-60c7-4144-929c-e79aff164744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346311883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3346311883
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1542390185
Short name T30
Test name
Test status
Simulation time 4485805045 ps
CPU time 2.44 seconds
Started May 12 12:46:49 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 204384 kb
Host smart-67cd8fba-97f6-45bf-89d4-da853af3f87f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542390185 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1542390185
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.364678325
Short name T437
Test name
Test status
Simulation time 10085805023 ps
CPU time 66.46 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:47:38 PM PDT 24
Peak memory 410140 kb
Host smart-c8993b97-36a4-40eb-8103-09058836610d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364678325 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.364678325
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2111753312
Short name T1288
Test name
Test status
Simulation time 10032568170 ps
CPU time 69.42 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:47:59 PM PDT 24
Peak memory 463688 kb
Host smart-922e6205-ef28-48b1-8b0f-ad4cc50865e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111753312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2111753312
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.453343060
Short name T929
Test name
Test status
Simulation time 310601477 ps
CPU time 2.13 seconds
Started May 12 12:46:57 PM PDT 24
Finished May 12 12:47:00 PM PDT 24
Peak memory 204312 kb
Host smart-dcfc307c-5d99-4e5b-b4f0-1c285265e31c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453343060 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.453343060
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2936070064
Short name T1343
Test name
Test status
Simulation time 1344129938 ps
CPU time 6.85 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 12:46:40 PM PDT 24
Peak memory 212464 kb
Host smart-0db32dfe-dd56-472c-8caa-19697aff87df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936070064 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2936070064
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3444477676
Short name T109
Test name
Test status
Simulation time 2766683998 ps
CPU time 6.21 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 204376 kb
Host smart-f33c083c-a844-4504-8942-e1b883d0023f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444477676 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3444477676
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1477316496
Short name T352
Test name
Test status
Simulation time 12544129731 ps
CPU time 36.94 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:46:57 PM PDT 24
Peak memory 204312 kb
Host smart-65bd807f-6542-40d6-b1bd-bff474e46d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477316496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1477316496
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2741546184
Short name T317
Test name
Test status
Simulation time 1955274410 ps
CPU time 16.69 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:53 PM PDT 24
Peak memory 218248 kb
Host smart-35b84b07-9aff-4f96-9d79-5c4bdc1eefc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741546184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2741546184
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1826601819
Short name T1018
Test name
Test status
Simulation time 36844986800 ps
CPU time 21.53 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:50 PM PDT 24
Peak memory 483952 kb
Host smart-fbd25b7e-b4c4-4d8a-b43d-6e5ea13933f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826601819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1826601819
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2724145948
Short name T1325
Test name
Test status
Simulation time 14703017694 ps
CPU time 2550.15 seconds
Started May 12 12:46:32 PM PDT 24
Finished May 12 01:29:03 PM PDT 24
Peak memory 3627680 kb
Host smart-98549480-5a5e-4bbc-ad5e-3cfbc44a9f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724145948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2724145948
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.845819582
Short name T1303
Test name
Test status
Simulation time 11014355046 ps
CPU time 6.51 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 218048 kb
Host smart-a9e9bde3-8213-47b7-8f62-3942d2146a6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845819582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.845819582
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.776766808
Short name T1160
Test name
Test status
Simulation time 17001010 ps
CPU time 0.59 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 204060 kb
Host smart-d065dddc-0c7f-459a-9979-1c038d926b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776766808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.776766808
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3167277855
Short name T685
Test name
Test status
Simulation time 242271134 ps
CPU time 1.26 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:46:51 PM PDT 24
Peak memory 212620 kb
Host smart-d44993bc-66f5-4199-b016-2cd5b4e5172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167277855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3167277855
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1665940422
Short name T501
Test name
Test status
Simulation time 564864615 ps
CPU time 6.4 seconds
Started May 12 12:46:30 PM PDT 24
Finished May 12 12:46:36 PM PDT 24
Peak memory 263088 kb
Host smart-61e1c17a-1de2-42b4-b182-bfac1dd74935
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665940422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1665940422
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1764506964
Short name T62
Test name
Test status
Simulation time 1241007971 ps
CPU time 82.76 seconds
Started May 12 12:46:47 PM PDT 24
Finished May 12 12:48:12 PM PDT 24
Peak memory 511808 kb
Host smart-5f9c71e6-4d90-44a8-97cc-7bd6c29db36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764506964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1764506964
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1437126326
Short name T331
Test name
Test status
Simulation time 7921573081 ps
CPU time 142.43 seconds
Started May 12 12:46:39 PM PDT 24
Finished May 12 12:49:02 PM PDT 24
Peak memory 650684 kb
Host smart-ed729a82-32ab-42ff-8cfa-edde90454eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437126326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1437126326
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3920363667
Short name T976
Test name
Test status
Simulation time 121636032 ps
CPU time 0.86 seconds
Started May 12 12:47:05 PM PDT 24
Finished May 12 12:47:07 PM PDT 24
Peak memory 204020 kb
Host smart-e828829c-43d8-4012-ba7f-c01b077a1a18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920363667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3920363667
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1517045675
Short name T1304
Test name
Test status
Simulation time 156424088 ps
CPU time 7.43 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:46:46 PM PDT 24
Peak memory 204336 kb
Host smart-b0bbc8cc-deb1-4730-9ab1-ec23c4ebab4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517045675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1517045675
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1834055677
Short name T101
Test name
Test status
Simulation time 13176077241 ps
CPU time 67.47 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:47:42 PM PDT 24
Peak memory 903308 kb
Host smart-6daa8745-b362-40ed-b1bb-e3a5c0e3064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834055677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1834055677
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.251007254
Short name T842
Test name
Test status
Simulation time 1913785288 ps
CPU time 19.14 seconds
Started May 12 12:46:35 PM PDT 24
Finished May 12 12:46:56 PM PDT 24
Peak memory 204216 kb
Host smart-bd1832a0-8a3f-40c6-b9f8-3e6df2f2b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251007254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.251007254
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1960494857
Short name T1016
Test name
Test status
Simulation time 5989889479 ps
CPU time 15.27 seconds
Started May 12 12:46:31 PM PDT 24
Finished May 12 12:46:47 PM PDT 24
Peak memory 268528 kb
Host smart-d032639c-a97f-4a18-94d7-7bab8c66fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960494857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1960494857
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1878218300
Short name T825
Test name
Test status
Simulation time 46459795 ps
CPU time 0.68 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:46:44 PM PDT 24
Peak memory 204028 kb
Host smart-091539a9-f078-4395-aa36-8bd8f79c508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878218300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1878218300
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1467257943
Short name T1281
Test name
Test status
Simulation time 7047524212 ps
CPU time 143.36 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:48:51 PM PDT 24
Peak memory 204336 kb
Host smart-2f24e835-631d-4d61-9df7-98d21dc75b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467257943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1467257943
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.593140417
Short name T781
Test name
Test status
Simulation time 1488766065 ps
CPU time 73.18 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:47:51 PM PDT 24
Peak memory 326424 kb
Host smart-7ff59452-701f-45e6-ad1d-631500edf33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593140417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.593140417
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3866396198
Short name T256
Test name
Test status
Simulation time 20963049432 ps
CPU time 1144.91 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 01:05:44 PM PDT 24
Peak memory 3288844 kb
Host smart-76ef5b2c-6f0d-4e1d-b609-49d3d19bec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866396198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3866396198
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.165233886
Short name T422
Test name
Test status
Simulation time 507701275 ps
CPU time 9.81 seconds
Started May 12 12:46:37 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 212480 kb
Host smart-6fba0dae-b1a8-4c32-a9d3-07caa5dbb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165233886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.165233886
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2100764150
Short name T448
Test name
Test status
Simulation time 781419229 ps
CPU time 3.9 seconds
Started May 12 12:46:51 PM PDT 24
Finished May 12 12:46:55 PM PDT 24
Peak memory 212340 kb
Host smart-961c511e-8c43-46cb-820f-7628dd4ed86a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100764150 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2100764150
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3440219746
Short name T626
Test name
Test status
Simulation time 10038546677 ps
CPU time 75.85 seconds
Started May 12 12:46:50 PM PDT 24
Finished May 12 12:48:07 PM PDT 24
Peak memory 417592 kb
Host smart-5c142e68-aa2f-4d13-ae04-41ffd84c8548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440219746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3440219746
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.401002346
Short name T1245
Test name
Test status
Simulation time 10095564247 ps
CPU time 77.79 seconds
Started May 12 12:46:36 PM PDT 24
Finished May 12 12:47:56 PM PDT 24
Peak memory 579292 kb
Host smart-ec2ae9de-4b66-4dd1-b1cb-8b79b9cde14a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401002346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.401002346
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2140612528
Short name T1263
Test name
Test status
Simulation time 1684454444 ps
CPU time 2.56 seconds
Started May 12 12:46:48 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 204192 kb
Host smart-86aca41e-f233-48d5-a4d6-3ffe27dc72ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140612528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2140612528
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.496711671
Short name T1276
Test name
Test status
Simulation time 780362721 ps
CPU time 4.01 seconds
Started May 12 12:46:45 PM PDT 24
Finished May 12 12:47:00 PM PDT 24
Peak memory 206548 kb
Host smart-fc5afa40-77ae-4597-a1b0-8f2ce2278866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496711671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.496711671
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3319047084
Short name T622
Test name
Test status
Simulation time 7770918747 ps
CPU time 9.52 seconds
Started May 12 12:46:38 PM PDT 24
Finished May 12 12:46:49 PM PDT 24
Peak memory 204328 kb
Host smart-68f54012-bcec-416b-a593-e2cb7acf0970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319047084 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3319047084
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2216926896
Short name T515
Test name
Test status
Simulation time 3528191817 ps
CPU time 43.08 seconds
Started May 12 12:46:42 PM PDT 24
Finished May 12 12:47:26 PM PDT 24
Peak memory 204272 kb
Host smart-de83cf41-dcd1-4f08-80cb-d6059cd09c13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216926896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2216926896
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2171143090
Short name T549
Test name
Test status
Simulation time 7801682500 ps
CPU time 51.48 seconds
Started May 12 12:46:40 PM PDT 24
Finished May 12 12:47:32 PM PDT 24
Peak memory 208008 kb
Host smart-f7911f7d-8d6f-4f17-82ea-dc9d0f6fb673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171143090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2171143090
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.50827345
Short name T555
Test name
Test status
Simulation time 11578944009 ps
CPU time 16.24 seconds
Started May 12 12:46:34 PM PDT 24
Finished May 12 12:46:52 PM PDT 24
Peak memory 204376 kb
Host smart-bdd5c42f-fc25-4c3d-aad8-626a1e30ef4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50827345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stress_wr.50827345
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2827672127
Short name T1124
Test name
Test status
Simulation time 19262090251 ps
CPU time 102.86 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:48:17 PM PDT 24
Peak memory 1006212 kb
Host smart-1ae99a98-576a-4a9f-91d2-9765645651a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827672127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2827672127
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2919174521
Short name T700
Test name
Test status
Simulation time 1317101482 ps
CPU time 6.49 seconds
Started May 12 12:46:41 PM PDT 24
Finished May 12 12:46:48 PM PDT 24
Peak memory 211260 kb
Host smart-0cb0191e-4238-495f-a486-c2e0885491d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919174521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2919174521
Directory /workspace/9.i2c_target_timeout/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%