Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	9	51	85.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	9	51	85.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	930648	1			T1	3		T2	2		T3	3
all_values[1]	930648	1			T1	3		T2	2		T3	3
all_values[2]	930648	1			T1	3		T2	2		T3	3
all_values[3]	930648	1			T1	3		T2	2		T3	3
all_values[4]	930648	1			T1	3		T2	2		T3	3
all_values[5]	930648	1			T1	3		T2	2		T3	3
all_values[6]	930648	1			T1	3		T2	2		T3	3
all_values[7]	930648	1			T1	3		T2	2		T3	3
all_values[8]	930648	1			T1	3		T2	2		T3	3
all_values[9]	930648	1			T1	3		T2	2		T3	3
all_values[10]	930648	1			T1	3		T2	2		T3	3
all_values[11]	930648	1			T1	3		T2	2		T3	3
all_values[12]	930648	1			T1	3		T2	2		T3	3
all_values[13]	930648	1			T1	3		T2	2		T3	3
all_values[14]	930648	1			T1	3		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11420379

1

T1

38

T2

26

T3

38

auto[1]

2539341

1

T1

7

T2

4

T3

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12383182

1

T1

45

T2

30

T3

45

auto[1]

1576538

1

T39

5982

T37

228141

T149

642735

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	9	51	85.00	9

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83077	1			T5	1050		T18	1		T19	1
all_values[0]	auto[0]	auto[1]	11019	1			T39	24		T37	205		T149	4407
all_values[0]	auto[1]	auto[0]	738587	1			T1	3		T2	2		T3	3
all_values[0]	auto[1]	auto[1]	97965	1			T39	403		T37	15005		T149	39448
all_values[1]	auto[0]	auto[0]	836850	1			T1	3		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	93280	1			T39	425		T37	15203		T149	28741
all_values[1]	auto[1]	auto[0]	295	1			T33	1		T67	1		T58	1
all_values[1]	auto[1]	auto[1]	223	1			T39	1		T37	7		T149	29
all_values[2]	auto[0]	auto[0]	822743	1			T1	3		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	107732	1			T39	423		T37	15203		T149	43848
all_values[2]	auto[1]	auto[1]	173	1			T39	3		T37	7		T149	6
all_values[3]	auto[0]	auto[0]	829377	1			T1	3		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	101052	1			T39	423		T37	15201		T149	43846
all_values[3]	auto[1]	auto[1]	219	1			T39	5		T37	8		T149	9
all_values[4]	auto[0]	auto[0]	822262	1			T1	3		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	108191	1			T39	425		T37	15204		T149	43851
all_values[4]	auto[1]	auto[0]	17	1			T237	1		T238	2		T239	1
all_values[4]	auto[1]	auto[1]	178	1			T39	3		T37	6		T149	4
all_values[5]	auto[0]	auto[0]	826691	1			T1	3		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	103776	1			T39	422		T37	15204		T149	43845
all_values[5]	auto[1]	auto[1]	181	1			T39	4		T37	6		T149	10
all_values[6]	auto[0]	auto[0]	824444	1			T1	3		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	106003	1			T37	15203		T149	43847		T45	6580
all_values[6]	auto[1]	auto[1]	201	1			T37	7		T149	8		T45	5
all_values[7]	auto[0]	auto[0]	793827	1			T1	3		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	105789	1			T39	340		T37	15034		T149	43261
all_values[7]	auto[1]	auto[0]	27910	1			T5	247		T18	1		T33	99
all_values[7]	auto[1]	auto[1]	3122	1			T39	88		T37	173		T149	593
all_values[8]	auto[0]	auto[0]	822345	1			T1	3		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	108104	1			T39	426		T37	15206		T149	43845
all_values[8]	auto[1]	auto[1]	199	1			T39	2		T37	4		T149	10
all_values[9]	auto[0]	auto[0]	166569	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	22144	1			T39	393		T37	2792		T149	3902
all_values[9]	auto[1]	auto[0]	659457	1			T1	1		T3	1		T5	1
all_values[9]	auto[1]	auto[1]	82478	1			T39	33		T37	12416		T149	39952
all_values[10]	auto[0]	auto[0]	821642	1			T1	3		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	108833	1			T39	424		T37	15202		T149	43849
all_values[10]	auto[1]	auto[1]	173	1			T39	3		T37	8		T149	6
all_values[11]	auto[0]	auto[0]	2824	1			T5	2		T18	1		T19	1
all_values[11]	auto[0]	auto[1]	474	1			T39	24		T37	22		T149	42
all_values[11]	auto[1]	auto[0]	818845	1			T1	3		T2	2		T3	3
all_values[11]	auto[1]	auto[1]	108505	1			T39	404		T37	15187		T149	43813
all_values[12]	auto[0]	auto[0]	821662	1			T1	3		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	108812	1			T39	426		T37	15202		T149	43848
all_values[12]	auto[1]	auto[1]	174	1			T39	2		T37	8		T149	7
all_values[13]	auto[0]	auto[0]	821624	1			T1	3		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	108807	1			T39	425		T37	15204		T149	43848
all_values[13]	auto[1]	auto[1]	217	1			T39	3		T37	6		T149	5
all_values[14]	auto[0]	auto[0]	842134	1			T1	3		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	88292	1			T39	427		T37	15205		T149	43845
all_values[14]	auto[1]	auto[1]	222	1			T39	1		T37	3		T149	10