Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	930648	1			T1	3		T2	2		T3	3
all_pins[1]	930648	1			T1	3		T2	2		T3	3
all_pins[2]	930648	1			T1	3		T2	2		T3	3
all_pins[3]	930648	1			T1	3		T2	2		T3	3
all_pins[4]	930648	1			T1	3		T2	2		T3	3
all_pins[5]	930648	1			T1	3		T2	2		T3	3
all_pins[6]	930648	1			T1	3		T2	2		T3	3
all_pins[7]	930648	1			T1	3		T2	2		T3	3
all_pins[8]	930648	1			T1	3		T2	2		T3	3
all_pins[9]	930648	1			T1	3		T2	2		T3	3
all_pins[10]	930648	1			T1	3		T2	2		T3	3
all_pins[11]	930648	1			T1	3		T2	2		T3	3
all_pins[12]	930648	1			T1	3		T2	2		T3	3
all_pins[13]	930648	1			T1	3		T2	2		T3	3
all_pins[14]	930648	1			T1	3		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11426060	1			T1	38		T2	26		T3	38
values[0x1]	2533660	1			T1	7		T2	4		T3	7
transitions[0x0=>0x1]	2532921	1			T1	7		T2	4		T3	7
transitions[0x1=>0x0]	2531902	1			T1	6		T2	3		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97689	1			T5	1050		T18	1		T19	1
all_pins[0]	values[0x1]	832959	1			T1	3		T2	2		T3	3
all_pins[0]	transitions[0x0=>0x1]	832573	1			T1	3		T2	2		T3	3
all_pins[0]	transitions[0x1=>0x0]	110	1			T37	3		T149	4		T45	1
all_pins[1]	values[0x0]	930152	1			T1	3		T2	2		T3	3
all_pins[1]	values[0x1]	496	1			T33	1		T67	2		T58	2
all_pins[1]	transitions[0x0=>0x1]	468	1			T33	1		T67	2		T58	2
all_pins[1]	transitions[0x1=>0x0]	69	1			T39	2		T37	3		T149	3
all_pins[2]	values[0x0]	930551	1			T1	3		T2	2		T3	3
all_pins[2]	values[0x1]	97	1			T39	2		T37	6		T149	4
all_pins[2]	transitions[0x0=>0x1]	73	1			T37	6		T149	3		T45	2
all_pins[2]	transitions[0x1=>0x0]	81	1			T39	3		T37	5		T149	4
all_pins[3]	values[0x0]	930543	1			T1	3		T2	2		T3	3
all_pins[3]	values[0x1]	105	1			T39	5		T37	5		T149	5
all_pins[3]	transitions[0x0=>0x1]	74	1			T39	5		T37	3		T149	5
all_pins[3]	transitions[0x1=>0x0]	82	1			T43	1		T37	1		T149	1
all_pins[4]	values[0x0]	930535	1			T1	3		T2	2		T3	3
all_pins[4]	values[0x1]	113	1			T43	1		T37	3		T149	1
all_pins[4]	transitions[0x0=>0x1]	91	1			T43	1		T37	1		T45	1
all_pins[4]	transitions[0x1=>0x0]	71	1			T39	2		T37	2		T149	7
all_pins[5]	values[0x0]	930555	1			T1	3		T2	2		T3	3
all_pins[5]	values[0x1]	93	1			T39	2		T37	4		T149	8
all_pins[5]	transitions[0x0=>0x1]	66	1			T39	2		T37	2		T149	6
all_pins[5]	transitions[0x1=>0x0]	74	1			T37	3		T149	1		T45	3
all_pins[6]	values[0x0]	930547	1			T1	3		T2	2		T3	3
all_pins[6]	values[0x1]	101	1			T37	5		T149	3		T45	3
all_pins[6]	transitions[0x0=>0x1]	73	1			T37	4		T149	2		T45	1
all_pins[6]	transitions[0x1=>0x0]	33999	1			T5	249		T18	1		T33	110
all_pins[7]	values[0x0]	896621	1			T1	3		T2	2		T3	3
all_pins[7]	values[0x1]	34027	1			T5	249		T18	1		T33	110
all_pins[7]	transitions[0x0=>0x1]	34000	1			T5	249		T18	1		T33	110
all_pins[7]	transitions[0x1=>0x0]	65	1			T37	3		T149	4		T45	1
all_pins[8]	values[0x0]	930556	1			T1	3		T2	2		T3	3
all_pins[8]	values[0x1]	92	1			T39	1		T37	3		T149	4
all_pins[8]	transitions[0x0=>0x1]	72	1			T39	1		T37	3		T149	2
all_pins[8]	transitions[0x1=>0x0]	741843	1			T1	1		T3	1		T5	1
all_pins[9]	values[0x0]	188785	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	741863	1			T1	1		T3	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	741842	1			T1	1		T3	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	69	1			T39	1		T37	3		T149	1
all_pins[10]	values[0x0]	930558	1			T1	3		T2	2		T3	3
all_pins[10]	values[0x1]	90	1			T39	2		T37	3		T149	3
all_pins[10]	transitions[0x0=>0x1]	70	1			T39	2		T37	2		T149	2
all_pins[10]	transitions[0x1=>0x0]	923288	1			T1	3		T2	2		T3	3
all_pins[11]	values[0x0]	7340	1			T5	2		T18	1		T19	1
all_pins[11]	values[0x1]	923308	1			T1	3		T2	2		T3	3
all_pins[11]	transitions[0x0=>0x1]	923286	1			T1	3		T2	2		T3	3
all_pins[11]	transitions[0x1=>0x0]	72	1			T39	1		T37	2		T149	2
all_pins[12]	values[0x0]	930554	1			T1	3		T2	2		T3	3
all_pins[12]	values[0x1]	94	1			T39	2		T37	4		T149	3
all_pins[12]	transitions[0x0=>0x1]	77	1			T39	2		T37	4		T149	2
all_pins[12]	transitions[0x1=>0x0]	83	1			T39	1		T37	2		T149	3
all_pins[13]	values[0x0]	930548	1			T1	3		T2	2		T3	3
all_pins[13]	values[0x1]	100	1			T39	1		T37	2		T149	4
all_pins[13]	transitions[0x0=>0x1]	72	1			T39	1		T37	2		T149	2
all_pins[13]	transitions[0x1=>0x0]	94	1			T149	4		T45	3		T102	3
all_pins[14]	values[0x0]	930526	1			T1	3		T2	2		T3	3
all_pins[14]	values[0x1]	122	1			T149	6		T45	3		T102	4
all_pins[14]	transitions[0x0=>0x1]	84	1			T149	4		T45	3		T102	2
all_pins[14]	transitions[0x1=>0x0]	831902	1			T1	2		T2	1		T3	2