Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	446	1			T39	7		T37	14		T149	15
all_values[1]	446	1			T39	7		T37	14		T149	15
all_values[2]	446	1			T39	7		T37	14		T149	15
all_values[3]	446	1			T39	7		T37	14		T149	15
all_values[4]	446	1			T39	7		T37	14		T149	15
all_values[5]	446	1			T39	7		T37	14		T149	15
all_values[6]	446	1			T39	7		T37	14		T149	15
all_values[7]	446	1			T39	7		T37	14		T149	15
all_values[8]	446	1			T39	7		T37	14		T149	15
all_values[9]	446	1			T39	7		T37	14		T149	15
all_values[10]	446	1			T39	7		T37	14		T149	15
all_values[11]	446	1			T39	7		T37	14		T149	15
all_values[12]	446	1			T39	7		T37	14		T149	15
all_values[13]	446	1			T39	7		T37	14		T149	15
all_values[14]	446	1			T39	7		T37	14		T149	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3429

1

T39

53

T37

94

T149

99

auto[1]

3261

1

T39

52

T37

116

T149

126

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T39

17

T37

9

T149

10

auto[1]

5539

1

T39

88

T37

201

T149

215

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3977

1

T39

66

T37

117

T149

131

auto[1]

2713

1

T39

39

T37

93

T149

94

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	51	1			T39	1		T251	1		T259	3
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T39	3		T37	3		T149	5
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T251	1		T260	1		T122	1
all_values[0]	auto[0]	auto[1]	auto[1]	93	1			T39	2		T37	4		T149	5
all_values[0]	auto[1]	auto[0]	auto[1]	87	1			T37	1		T149	2		T45	3
all_values[0]	auto[1]	auto[1]	auto[1]	92	1			T39	1		T37	6		T149	3
all_values[1]	auto[0]	auto[0]	auto[0]	48	1			T39	1		T149	2		T45	2
all_values[1]	auto[0]	auto[0]	auto[1]	96	1			T39	3		T37	4		T149	2
all_values[1]	auto[0]	auto[1]	auto[0]	35	1			T39	1		T149	3		T45	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T39	1		T37	3		T149	2
all_values[1]	auto[1]	auto[0]	auto[1]	96	1			T39	1		T45	1		T102	1
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T37	7		T149	6		T102	4
all_values[2]	auto[0]	auto[0]	auto[0]	48	1			T149	1		T261	4		T119	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T39	1		T37	3		T149	5
all_values[2]	auto[0]	auto[1]	auto[0]	37	1			T39	2		T259	1		T262	4
all_values[2]	auto[0]	auto[1]	auto[1]	106	1			T39	1		T37	4		T149	3
all_values[2]	auto[1]	auto[0]	auto[1]	85	1			T39	1		T37	3		T149	3
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T39	2		T37	4		T149	3
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T45	1		T262	2		T120	2
all_values[3]	auto[0]	auto[0]	auto[1]	99	1			T39	1		T37	2		T149	5
all_values[3]	auto[0]	auto[1]	auto[0]	38	1			T37	1		T261	1		T251	1
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T39	1		T37	2		T149	3
all_values[3]	auto[1]	auto[0]	auto[1]	105	1			T39	3		T37	2		T149	1
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T39	2		T37	7		T149	6
all_values[4]	auto[0]	auto[0]	auto[0]	32	1			T263	3		T120	1		T81	1
all_values[4]	auto[0]	auto[0]	auto[1]	104	1			T39	3		T37	6		T149	5
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T251	1		T262	2		T263	1
all_values[4]	auto[0]	auto[1]	auto[1]	101	1			T39	1		T37	2		T149	6
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T39	3		T37	2		T149	3
all_values[4]	auto[1]	auto[1]	auto[1]	88	1			T37	4		T149	1		T45	2
all_values[5]	auto[0]	auto[0]	auto[0]	48	1			T39	1		T261	2		T119	3
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T39	1		T149	2		T45	4
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T39	1		T251	1		T119	1
all_values[5]	auto[0]	auto[1]	auto[1]	95	1			T39	2		T37	7		T149	4
all_values[5]	auto[1]	auto[0]	auto[1]	86	1			T39	2		T37	2		T149	1
all_values[5]	auto[1]	auto[1]	auto[1]	94	1			T37	5		T149	8		T45	2
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T39	4		T259	1		T119	1
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T37	7		T149	6		T45	2
all_values[6]	auto[0]	auto[1]	auto[0]	38	1			T39	3		T261	1		T251	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T37	2		T149	3		T45	1
all_values[6]	auto[1]	auto[0]	auto[1]	94	1			T37	1		T149	3		T45	2
all_values[6]	auto[1]	auto[1]	auto[1]	76	1			T37	4		T149	3		T45	3
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T37	2		T102	1		T251	1
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T39	3		T37	3		T149	2
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T37	1		T149	1		T251	1
all_values[7]	auto[0]	auto[1]	auto[1]	105	1			T39	2		T37	3		T149	6
all_values[7]	auto[1]	auto[0]	auto[1]	98	1			T39	1		T37	2		T149	4
all_values[7]	auto[1]	auto[1]	auto[1]	79	1			T39	1		T37	3		T149	2
all_values[8]	auto[0]	auto[0]	auto[0]	49	1			T102	1		T261	2		T119	1
all_values[8]	auto[0]	auto[0]	auto[1]	93	1			T37	4		T149	3		T45	1
all_values[8]	auto[0]	auto[1]	auto[0]	37	1			T45	1		T261	2		T251	1
all_values[8]	auto[0]	auto[1]	auto[1]	89	1			T39	2		T37	6		T149	5
all_values[8]	auto[1]	auto[0]	auto[1]	97	1			T39	2		T37	2		T149	3
all_values[8]	auto[1]	auto[1]	auto[1]	81	1			T39	3		T37	2		T149	4
all_values[9]	auto[0]	auto[0]	auto[0]	39	1			T39	1		T37	2		T45	1
all_values[9]	auto[0]	auto[0]	auto[1]	95	1			T39	2		T37	5		T149	3
all_values[9]	auto[0]	auto[1]	auto[0]	41	1			T39	1		T149	1		T45	1
all_values[9]	auto[0]	auto[1]	auto[1]	101	1			T37	3		T149	4		T45	1
all_values[9]	auto[1]	auto[0]	auto[1]	88	1			T39	1		T37	3		T149	5
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T39	2		T37	1		T149	2
all_values[10]	auto[0]	auto[0]	auto[0]	36	1			T120	2		T121	1		T124	1
all_values[10]	auto[0]	auto[0]	auto[1]	95	1			T39	1		T37	3		T149	3
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T39	1		T45	1		T261	1
all_values[10]	auto[0]	auto[1]	auto[1]	114	1			T39	2		T37	3		T149	6
all_values[10]	auto[1]	auto[0]	auto[1]	86	1			T39	1		T37	5		T149	3
all_values[10]	auto[1]	auto[1]	auto[1]	87	1			T39	2		T37	3		T149	3
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T251	1		T259	1		T119	1
all_values[11]	auto[0]	auto[0]	auto[1]	89	1			T39	3		T37	2		T149	5
all_values[11]	auto[0]	auto[1]	auto[0]	37	1			T37	1		T261	1		T251	1
all_values[11]	auto[0]	auto[1]	auto[1]	93	1			T39	1		T37	6		T149	3
all_values[11]	auto[1]	auto[0]	auto[1]	100	1			T39	2		T37	4		T149	2
all_values[11]	auto[1]	auto[1]	auto[1]	79	1			T39	1		T37	1		T149	5
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T45	2		T259	2		T52	2
all_values[12]	auto[0]	auto[0]	auto[1]	83	1			T39	2		T37	3		T149	4
all_values[12]	auto[0]	auto[1]	auto[0]	39	1			T45	3		T251	2		T259	3
all_values[12]	auto[0]	auto[1]	auto[1]	107	1			T39	3		T37	3		T149	4
all_values[12]	auto[1]	auto[0]	auto[1]	83	1			T37	5		T149	3		T45	1
all_values[12]	auto[1]	auto[1]	auto[1]	91	1			T39	2		T37	3		T149	4
all_values[13]	auto[0]	auto[0]	auto[0]	29	1			T149	1		T119	1		T260	1
all_values[13]	auto[0]	auto[0]	auto[1]	111	1			T39	1		T37	4		T149	3
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T149	1		T259	1		T260	1
all_values[13]	auto[0]	auto[1]	auto[1]	91	1			T39	4		T37	3		T149	5
all_values[13]	auto[1]	auto[0]	auto[1]	106	1			T39	2		T37	3		T149	2
all_values[13]	auto[1]	auto[1]	auto[1]	90	1			T37	4		T149	3		T102	1
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T37	1		T102	1		T251	1
all_values[14]	auto[0]	auto[0]	auto[1]	86	1			T39	1		T37	3		T149	3
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T37	1		T45	1		T261	1
all_values[14]	auto[0]	auto[1]	auto[1]	95	1			T39	2		T37	5		T149	6
all_values[14]	auto[1]	auto[0]	auto[1]	100	1			T39	1		T37	2		T149	4
all_values[14]	auto[1]	auto[1]	auto[1]	104	1			T39	3		T37	2		T149	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal