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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.85 96.56 89.70 97.67 69.64 93.55 98.44 90.42


Total test records in report: 1451
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T1310 /workspace/coverage/default/31.i2c_host_may_nack.2074213519 May 16 12:47:43 PM PDT 24 May 16 12:48:11 PM PDT 24 520646719 ps
T1311 /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2657518356 May 16 12:47:38 PM PDT 24 May 16 12:48:11 PM PDT 24 191429469 ps
T1312 /workspace/coverage/default/5.i2c_host_may_nack.2227353139 May 16 12:44:48 PM PDT 24 May 16 12:45:17 PM PDT 24 257817117 ps
T1313 /workspace/coverage/default/24.i2c_target_hrst.2630468183 May 16 12:46:51 PM PDT 24 May 16 12:47:20 PM PDT 24 5025117696 ps
T1314 /workspace/coverage/default/15.i2c_host_fifo_watermark.2872980485 May 16 12:45:36 PM PDT 24 May 16 12:50:35 PM PDT 24 16536579930 ps
T169 /workspace/coverage/default/41.i2c_host_fifo_full.3327066359 May 16 12:48:43 PM PDT 24 May 16 12:50:47 PM PDT 24 1568234472 ps
T1315 /workspace/coverage/default/49.i2c_target_stretch.677179543 May 16 12:49:44 PM PDT 24 May 16 01:16:53 PM PDT 24 13191042752 ps
T1316 /workspace/coverage/default/44.i2c_target_smoke.2853588926 May 16 12:49:05 PM PDT 24 May 16 12:49:42 PM PDT 24 1337415301 ps
T1317 /workspace/coverage/default/33.i2c_host_fifo_watermark.2860821479 May 16 12:47:51 PM PDT 24 May 16 12:50:11 PM PDT 24 4695359504 ps
T1318 /workspace/coverage/default/27.i2c_host_error_intr.2185133469 May 16 12:47:12 PM PDT 24 May 16 12:47:42 PM PDT 24 227843861 ps
T1319 /workspace/coverage/default/12.i2c_target_intr_stress_wr.1096904163 May 16 12:45:12 PM PDT 24 May 16 12:46:05 PM PDT 24 3198545469 ps
T1320 /workspace/coverage/default/43.i2c_target_stretch.2987915225 May 16 12:49:04 PM PDT 24 May 16 01:10:39 PM PDT 24 15364247183 ps
T1321 /workspace/coverage/default/13.i2c_target_hrst.1390468808 May 16 12:45:22 PM PDT 24 May 16 12:45:51 PM PDT 24 1670914062 ps
T1322 /workspace/coverage/default/28.i2c_target_bad_addr.3603924840 May 16 12:47:10 PM PDT 24 May 16 12:47:40 PM PDT 24 2589944046 ps
T1323 /workspace/coverage/default/11.i2c_host_fifo_watermark.3118425671 May 16 12:45:06 PM PDT 24 May 16 12:47:28 PM PDT 24 3967294189 ps
T1324 /workspace/coverage/default/38.i2c_host_smoke.1877508917 May 16 12:48:20 PM PDT 24 May 16 12:49:12 PM PDT 24 6063708092 ps
T1325 /workspace/coverage/default/43.i2c_target_intr_smoke.197106711 May 16 12:49:02 PM PDT 24 May 16 12:49:27 PM PDT 24 1533352319 ps
T1326 /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1288426537 May 16 12:48:23 PM PDT 24 May 16 12:48:49 PM PDT 24 359973460 ps
T1327 /workspace/coverage/default/22.i2c_target_timeout.2489859997 May 16 12:46:30 PM PDT 24 May 16 12:47:04 PM PDT 24 2467263398 ps
T1328 /workspace/coverage/default/3.i2c_host_stress_all.1264713737 May 16 12:44:39 PM PDT 24 May 16 12:54:46 PM PDT 24 39050242717 ps
T1329 /workspace/coverage/default/16.i2c_host_override.2224667417 May 16 12:45:45 PM PDT 24 May 16 12:46:08 PM PDT 24 49334512 ps
T1330 /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2971808705 May 16 12:48:53 PM PDT 24 May 16 12:49:37 PM PDT 24 5982883410 ps
T1331 /workspace/coverage/default/25.i2c_host_fifo_overflow.842000516 May 16 12:46:44 PM PDT 24 May 16 12:48:06 PM PDT 24 9069236484 ps
T1332 /workspace/coverage/default/16.i2c_target_intr_stress_wr.1999140119 May 16 12:45:53 PM PDT 24 May 16 12:46:24 PM PDT 24 3885130164 ps
T177 /workspace/coverage/default/3.i2c_sec_cm.1680541293 May 16 12:44:40 PM PDT 24 May 16 12:44:58 PM PDT 24 83731910 ps
T1333 /workspace/coverage/default/35.i2c_host_perf.4162108845 May 16 12:47:59 PM PDT 24 May 16 12:48:30 PM PDT 24 2363914457 ps
T1334 /workspace/coverage/default/9.i2c_host_fifo_full.3179386162 May 16 12:44:59 PM PDT 24 May 16 12:46:30 PM PDT 24 17526526201 ps
T1335 /workspace/coverage/default/34.i2c_host_override.4256298549 May 16 12:47:51 PM PDT 24 May 16 12:48:16 PM PDT 24 70042052 ps
T1336 /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3096229181 May 16 12:46:34 PM PDT 24 May 16 12:47:10 PM PDT 24 692899864 ps
T1337 /workspace/coverage/default/37.i2c_host_perf.1627462165 May 16 12:48:11 PM PDT 24 May 16 12:49:20 PM PDT 24 5215634472 ps
T1338 /workspace/coverage/default/2.i2c_target_hrst.1924307817 May 16 12:44:36 PM PDT 24 May 16 12:44:54 PM PDT 24 1735291099 ps
T1339 /workspace/coverage/default/38.i2c_host_fifo_overflow.1756901193 May 16 12:48:22 PM PDT 24 May 16 12:50:09 PM PDT 24 2680144014 ps
T1340 /workspace/coverage/default/33.i2c_target_stretch.1569236486 May 16 12:47:49 PM PDT 24 May 16 12:50:37 PM PDT 24 14108833198 ps
T1341 /workspace/coverage/default/49.i2c_target_intr_stress_wr.1322786088 May 16 12:49:43 PM PDT 24 May 16 12:53:45 PM PDT 24 12763677509 ps
T1342 /workspace/coverage/default/47.i2c_host_fifo_full.2214043968 May 16 12:49:37 PM PDT 24 May 16 12:51:27 PM PDT 24 2484563802 ps
T1343 /workspace/coverage/default/36.i2c_target_stretch.2172242297 May 16 12:48:10 PM PDT 24 May 16 12:50:35 PM PDT 24 5691680960 ps
T1344 /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3727471531 May 16 12:46:07 PM PDT 24 May 16 12:46:32 PM PDT 24 426980903 ps
T1345 /workspace/coverage/default/31.i2c_target_bad_addr.2798497553 May 16 12:47:40 PM PDT 24 May 16 12:48:06 PM PDT 24 2513472868 ps
T1346 /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3332235644 May 16 12:45:13 PM PDT 24 May 16 12:45:42 PM PDT 24 805104932 ps
T1347 /workspace/coverage/default/47.i2c_target_hrst.3153706851 May 16 12:49:34 PM PDT 24 May 16 12:49:53 PM PDT 24 1679857507 ps
T1348 /workspace/coverage/default/30.i2c_target_intr_smoke.750445669 May 16 12:47:38 PM PDT 24 May 16 12:48:04 PM PDT 24 592924376 ps
T1349 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3309509021 May 16 12:31:49 PM PDT 24 May 16 12:33:48 PM PDT 24 18545153 ps
T1350 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2918627732 May 16 12:31:48 PM PDT 24 May 16 12:33:32 PM PDT 24 29139829 ps
T1351 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1002152188 May 16 12:31:45 PM PDT 24 May 16 12:33:27 PM PDT 24 45527223 ps
T147 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3108001233 May 16 12:31:35 PM PDT 24 May 16 12:33:06 PM PDT 24 93398361 ps
T1352 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2583834017 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 38930915 ps
T125 /workspace/coverage/cover_reg_top/1.i2c_intr_test.2299191222 May 16 12:32:18 PM PDT 24 May 16 12:34:04 PM PDT 24 51262486 ps
T148 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2530986434 May 16 12:31:35 PM PDT 24 May 16 12:33:06 PM PDT 24 1023563738 ps
T92 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2307102175 May 16 12:32:41 PM PDT 24 May 16 12:34:22 PM PDT 24 76879586 ps
T210 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1926338046 May 16 12:31:18 PM PDT 24 May 16 12:32:18 PM PDT 24 166326086 ps
T93 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1604204415 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 109302254 ps
T94 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3126526796 May 16 12:31:37 PM PDT 24 May 16 12:33:09 PM PDT 24 34219594 ps
T218 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.4261830942 May 16 12:31:53 PM PDT 24 May 16 12:33:41 PM PDT 24 65403794 ps
T236 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.248686056 May 16 12:31:24 PM PDT 24 May 16 12:32:43 PM PDT 24 29998093 ps
T202 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.781772158 May 16 12:31:32 PM PDT 24 May 16 12:32:57 PM PDT 24 16492033 ps
T203 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3172725940 May 16 12:31:38 PM PDT 24 May 16 12:33:12 PM PDT 24 52693424 ps
T95 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3034407254 May 16 12:31:29 PM PDT 24 May 16 12:32:53 PM PDT 24 75750313 ps
T96 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3520881045 May 16 12:31:27 PM PDT 24 May 16 12:32:47 PM PDT 24 36482949 ps
T1353 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3444105770 May 16 12:31:25 PM PDT 24 May 16 12:32:46 PM PDT 24 48187696 ps
T1354 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1697295044 May 16 12:31:33 PM PDT 24 May 16 12:33:00 PM PDT 24 47055984 ps
T204 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2068883592 May 16 12:31:33 PM PDT 24 May 16 12:33:01 PM PDT 24 31284268 ps
T1355 /workspace/coverage/cover_reg_top/24.i2c_intr_test.463667030 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 35401367 ps
T97 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3365018159 May 16 12:31:39 PM PDT 24 May 16 12:33:34 PM PDT 24 230899607 ps
T1356 /workspace/coverage/cover_reg_top/22.i2c_intr_test.618848516 May 16 12:31:49 PM PDT 24 May 16 12:33:48 PM PDT 24 16211454 ps
T183 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.877583161 May 16 12:31:25 PM PDT 24 May 16 12:32:44 PM PDT 24 77744376 ps
T219 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.294942829 May 16 12:31:44 PM PDT 24 May 16 12:33:34 PM PDT 24 82195257 ps
T1357 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1867677075 May 16 12:31:36 PM PDT 24 May 16 12:33:06 PM PDT 24 17022296 ps
T220 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1039855906 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 99847855 ps
T98 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4191291258 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 108564215 ps
T118 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3704041701 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 154742301 ps
T184 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1737221307 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 92325143 ps
T1358 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3282947035 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 34483506 ps
T99 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3032402953 May 16 12:31:35 PM PDT 24 May 16 12:33:04 PM PDT 24 39430125 ps
T269 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2338377080 May 16 12:31:18 PM PDT 24 May 16 12:32:16 PM PDT 24 41647597 ps
T100 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.514784877 May 16 12:31:39 PM PDT 24 May 16 12:33:36 PM PDT 24 610400249 ps
T1359 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2224683403 May 16 12:31:29 PM PDT 24 May 16 12:32:53 PM PDT 24 114047958 ps
T101 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3139722057 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 256905281 ps
T185 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.332066309 May 16 12:31:42 PM PDT 24 May 16 12:33:30 PM PDT 24 145139731 ps
T1360 /workspace/coverage/cover_reg_top/25.i2c_intr_test.937254049 May 16 12:31:48 PM PDT 24 May 16 12:33:43 PM PDT 24 38717917 ps
T1361 /workspace/coverage/cover_reg_top/19.i2c_intr_test.391362867 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 44434742 ps
T221 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.260306217 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 23401625 ps
T145 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1989672377 May 16 12:31:34 PM PDT 24 May 16 12:33:03 PM PDT 24 30109217 ps
T1362 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1440001033 May 16 12:31:45 PM PDT 24 May 16 12:33:27 PM PDT 24 20300758 ps
T1363 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1782088599 May 16 12:31:33 PM PDT 24 May 16 12:33:00 PM PDT 24 25545513 ps
T186 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.417032249 May 16 12:31:44 PM PDT 24 May 16 12:33:36 PM PDT 24 143551298 ps
T222 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.772592813 May 16 12:31:45 PM PDT 24 May 16 12:33:27 PM PDT 24 130355908 ps
T1364 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1602542753 May 16 12:31:29 PM PDT 24 May 16 12:32:54 PM PDT 24 23783794 ps
T146 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3826731192 May 16 12:31:36 PM PDT 24 May 16 12:33:06 PM PDT 24 239296949 ps
T200 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.716731305 May 16 12:31:30 PM PDT 24 May 16 12:32:55 PM PDT 24 25120246 ps
T201 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3118110950 May 16 12:31:35 PM PDT 24 May 16 12:33:06 PM PDT 24 33221084 ps
T205 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2488676118 May 16 12:31:27 PM PDT 24 May 16 12:32:47 PM PDT 24 46030180 ps
T1365 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2961066369 May 16 12:31:29 PM PDT 24 May 16 12:32:51 PM PDT 24 18420845 ps
T1366 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1127235191 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 30072111 ps
T1367 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3245845550 May 16 12:31:34 PM PDT 24 May 16 12:33:02 PM PDT 24 52068088 ps
T1368 /workspace/coverage/cover_reg_top/30.i2c_intr_test.4184656232 May 16 12:31:46 PM PDT 24 May 16 12:33:28 PM PDT 24 25651931 ps
T192 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4219122240 May 16 12:31:41 PM PDT 24 May 16 12:33:25 PM PDT 24 81480940 ps
T1369 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3264918923 May 16 12:31:26 PM PDT 24 May 16 12:32:49 PM PDT 24 154131853 ps
T1370 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2852836039 May 16 12:31:21 PM PDT 24 May 16 12:32:32 PM PDT 24 25283969 ps
T1371 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1598753171 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 58794494 ps
T1372 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1919633182 May 16 12:31:35 PM PDT 24 May 16 12:33:05 PM PDT 24 126691244 ps
T1373 /workspace/coverage/cover_reg_top/14.i2c_intr_test.525221499 May 16 12:31:39 PM PDT 24 May 16 12:33:33 PM PDT 24 42576516 ps
T1374 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1351187938 May 16 12:31:27 PM PDT 24 May 16 12:32:47 PM PDT 24 16519455 ps
T1375 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3225681856 May 16 12:31:21 PM PDT 24 May 16 12:32:31 PM PDT 24 40931994 ps
T1376 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1002710141 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 15600792 ps
T188 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.436083861 May 16 12:31:39 PM PDT 24 May 16 12:33:41 PM PDT 24 135716914 ps
T1377 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2787388503 May 16 12:31:36 PM PDT 24 May 16 12:33:06 PM PDT 24 38830615 ps
T187 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4021879266 May 16 12:31:29 PM PDT 24 May 16 12:32:51 PM PDT 24 273733618 ps
T1378 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2291708586 May 16 12:31:46 PM PDT 24 May 16 12:33:28 PM PDT 24 26637154 ps
T1379 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.4161080602 May 16 12:31:25 PM PDT 24 May 16 12:32:46 PM PDT 24 170949146 ps
T1380 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1678941569 May 16 12:31:44 PM PDT 24 May 16 12:33:44 PM PDT 24 401396120 ps
T1381 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2815147058 May 16 12:31:59 PM PDT 24 May 16 12:33:49 PM PDT 24 73223424 ps
T1382 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4087888881 May 16 12:31:27 PM PDT 24 May 16 12:32:49 PM PDT 24 194685541 ps
T1383 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2038327726 May 16 12:32:25 PM PDT 24 May 16 12:34:15 PM PDT 24 68265180 ps
T1384 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.187605250 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 50911219 ps
T206 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3396576972 May 16 12:31:50 PM PDT 24 May 16 12:33:38 PM PDT 24 19302373 ps
T1385 /workspace/coverage/cover_reg_top/36.i2c_intr_test.652917773 May 16 12:31:53 PM PDT 24 May 16 12:33:41 PM PDT 24 17264196 ps
T1386 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.972320333 May 16 12:31:28 PM PDT 24 May 16 12:32:49 PM PDT 24 38931143 ps
T1387 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3154630075 May 16 12:31:35 PM PDT 24 May 16 12:33:04 PM PDT 24 39979389 ps
T1388 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1228529614 May 16 12:31:10 PM PDT 24 May 16 12:31:50 PM PDT 24 126794035 ps
T1389 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2561462278 May 16 12:32:25 PM PDT 24 May 16 12:34:14 PM PDT 24 51746189 ps
T1390 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2649044774 May 16 12:31:48 PM PDT 24 May 16 12:33:43 PM PDT 24 42709140 ps
T1391 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2698260784 May 16 12:31:43 PM PDT 24 May 16 12:33:23 PM PDT 24 17826730 ps
T1392 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1223355265 May 16 12:31:49 PM PDT 24 May 16 12:33:48 PM PDT 24 47578506 ps
T1393 /workspace/coverage/cover_reg_top/8.i2c_intr_test.21521042 May 16 12:31:35 PM PDT 24 May 16 12:33:04 PM PDT 24 19438732 ps
T1394 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2672000709 May 16 12:31:41 PM PDT 24 May 16 12:33:28 PM PDT 24 40642789 ps
T190 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.273008468 May 16 12:31:23 PM PDT 24 May 16 12:32:35 PM PDT 24 78928010 ps
T207 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2935340681 May 16 12:31:38 PM PDT 24 May 16 12:33:10 PM PDT 24 52115070 ps
T1395 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2078053652 May 16 12:31:35 PM PDT 24 May 16 12:33:05 PM PDT 24 54516365 ps
T1396 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.841648880 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 37620682 ps
T1397 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3476268459 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 32457784 ps
T1398 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2980242669 May 16 12:31:48 PM PDT 24 May 16 12:33:48 PM PDT 24 50514866 ps
T197 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1003459087 May 16 12:31:32 PM PDT 24 May 16 12:32:59 PM PDT 24 1886774102 ps
T1399 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2504842344 May 16 12:31:33 PM PDT 24 May 16 12:33:01 PM PDT 24 78590401 ps
T208 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.620537538 May 16 12:31:40 PM PDT 24 May 16 12:33:24 PM PDT 24 88165218 ps
T1400 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3077586530 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 17043758 ps
T1401 /workspace/coverage/cover_reg_top/39.i2c_intr_test.2002089014 May 16 12:31:50 PM PDT 24 May 16 12:33:48 PM PDT 24 32416868 ps
T209 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.325063054 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 20678995 ps
T213 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.49219825 May 16 12:31:33 PM PDT 24 May 16 12:33:01 PM PDT 24 28848317 ps
T1402 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.221336520 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 96335303 ps
T1403 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2019871237 May 16 12:31:38 PM PDT 24 May 16 12:33:10 PM PDT 24 56533845 ps
T1404 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4181700419 May 16 12:31:32 PM PDT 24 May 16 12:32:58 PM PDT 24 29306434 ps
T1405 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1128840034 May 16 12:31:14 PM PDT 24 May 16 12:32:08 PM PDT 24 1277867764 ps
T1406 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3424514106 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 40053946 ps
T1407 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2688794453 May 16 12:31:41 PM PDT 24 May 16 12:33:28 PM PDT 24 31583363 ps
T1408 /workspace/coverage/cover_reg_top/28.i2c_intr_test.864583586 May 16 12:31:38 PM PDT 24 May 16 12:33:10 PM PDT 24 21396060 ps
T214 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1823786673 May 16 12:31:25 PM PDT 24 May 16 12:32:43 PM PDT 24 76894579 ps
T1409 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1103113739 May 16 12:31:40 PM PDT 24 May 16 12:33:24 PM PDT 24 23598399 ps
T194 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1604841947 May 16 12:31:39 PM PDT 24 May 16 12:33:40 PM PDT 24 102423052 ps
T1410 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3880821080 May 16 12:31:34 PM PDT 24 May 16 12:33:01 PM PDT 24 21547467 ps
T1411 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2958745893 May 16 12:31:38 PM PDT 24 May 16 12:33:11 PM PDT 24 89444767 ps
T1412 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4027460154 May 16 12:31:40 PM PDT 24 May 16 12:33:24 PM PDT 24 24828531 ps
T1413 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3319916470 May 16 12:31:48 PM PDT 24 May 16 12:33:43 PM PDT 24 40565160 ps
T1414 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1662879273 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 86741153 ps
T1415 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.912506008 May 16 12:31:42 PM PDT 24 May 16 12:33:29 PM PDT 24 29021900 ps
T1416 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3962679964 May 16 12:31:54 PM PDT 24 May 16 12:33:43 PM PDT 24 58971301 ps
T1417 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3839986986 May 16 12:31:40 PM PDT 24 May 16 12:33:24 PM PDT 24 91952910 ps
T1418 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1977954858 May 16 12:31:35 PM PDT 24 May 16 12:33:04 PM PDT 24 108704940 ps
T1419 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2904966715 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 40259170 ps
T1420 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1325040542 May 16 12:32:25 PM PDT 24 May 16 12:34:16 PM PDT 24 170219946 ps
T1421 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3693586883 May 16 12:31:43 PM PDT 24 May 16 12:33:22 PM PDT 24 79524384 ps
T196 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1155814255 May 16 12:31:38 PM PDT 24 May 16 12:33:11 PM PDT 24 53030331 ps
T191 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2114281283 May 16 12:31:39 PM PDT 24 May 16 12:33:35 PM PDT 24 161464747 ps
T1422 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2663322039 May 16 12:31:40 PM PDT 24 May 16 12:33:25 PM PDT 24 1165884192 ps
T1423 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3769540931 May 16 12:31:39 PM PDT 24 May 16 12:33:38 PM PDT 24 29549312 ps
T1424 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3198764273 May 16 12:31:25 PM PDT 24 May 16 12:32:43 PM PDT 24 69289900 ps
T1425 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.553546287 May 16 12:31:38 PM PDT 24 May 16 12:33:10 PM PDT 24 28522107 ps
T1426 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.758581158 May 16 12:31:46 PM PDT 24 May 16 12:33:29 PM PDT 24 23030793 ps
T189 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.823375377 May 16 12:31:35 PM PDT 24 May 16 12:33:06 PM PDT 24 752601927 ps
T1427 /workspace/coverage/cover_reg_top/17.i2c_intr_test.219515608 May 16 12:31:29 PM PDT 24 May 16 12:32:50 PM PDT 24 29553102 ps
T1428 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2985382876 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 47956616 ps
T1429 /workspace/coverage/cover_reg_top/35.i2c_intr_test.808008922 May 16 12:31:57 PM PDT 24 May 16 12:33:48 PM PDT 24 54098114 ps
T198 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.222826316 May 16 12:31:25 PM PDT 24 May 16 12:32:47 PM PDT 24 50970103 ps
T1430 /workspace/coverage/cover_reg_top/26.i2c_intr_test.233308263 May 16 12:31:54 PM PDT 24 May 16 12:33:43 PM PDT 24 39089482 ps
T1431 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.140937936 May 16 12:31:41 PM PDT 24 May 16 12:33:17 PM PDT 24 96981627 ps
T1432 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2185711491 May 16 12:31:45 PM PDT 24 May 16 12:33:27 PM PDT 24 172772772 ps
T1433 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2308921458 May 16 12:31:42 PM PDT 24 May 16 12:33:28 PM PDT 24 33147866 ps
T1434 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1547402180 May 16 12:31:43 PM PDT 24 May 16 12:33:29 PM PDT 24 108191735 ps
T1435 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2636274983 May 16 12:31:33 PM PDT 24 May 16 12:33:01 PM PDT 24 447508486 ps
T1436 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2343913728 May 16 12:31:36 PM PDT 24 May 16 12:33:06 PM PDT 24 79188560 ps
T1437 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3877441015 May 16 12:31:56 PM PDT 24 May 16 12:33:47 PM PDT 24 40277309 ps
T1438 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3757673302 May 16 12:31:17 PM PDT 24 May 16 12:32:15 PM PDT 24 838155650 ps
T215 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3165446289 May 16 12:31:39 PM PDT 24 May 16 12:33:33 PM PDT 24 19407935 ps
T1439 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4218623072 May 16 12:31:41 PM PDT 24 May 16 12:33:18 PM PDT 24 21455237 ps
T1440 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3660990309 May 16 12:31:21 PM PDT 24 May 16 12:32:29 PM PDT 24 16442199 ps
T1441 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1410820554 May 16 12:31:22 PM PDT 24 May 16 12:32:33 PM PDT 24 49094735 ps
T1442 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1827715315 May 16 12:31:35 PM PDT 24 May 16 12:33:05 PM PDT 24 58531851 ps
T1443 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2102121556 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 26236451 ps
T216 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3688084025 May 16 12:31:30 PM PDT 24 May 16 12:32:56 PM PDT 24 46242204 ps
T1444 /workspace/coverage/cover_reg_top/4.i2c_intr_test.579691478 May 16 12:31:33 PM PDT 24 May 16 12:33:01 PM PDT 24 45899959 ps
T1445 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3595991475 May 16 12:31:09 PM PDT 24 May 16 12:31:49 PM PDT 24 83045204 ps
T1446 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4067397373 May 16 12:31:41 PM PDT 24 May 16 12:33:19 PM PDT 24 133411810 ps
T217 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1737587153 May 16 12:31:40 PM PDT 24 May 16 12:33:24 PM PDT 24 20794859 ps
T1447 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2503870049 May 16 12:31:43 PM PDT 24 May 16 12:33:29 PM PDT 24 17212594 ps
T193 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.407071548 May 16 12:31:34 PM PDT 24 May 16 12:33:03 PM PDT 24 163816788 ps
T1448 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4117045594 May 16 12:31:37 PM PDT 24 May 16 12:33:10 PM PDT 24 36641242 ps
T1449 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1898351522 May 16 12:31:48 PM PDT 24 May 16 12:33:49 PM PDT 24 48329108 ps
T195 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1282806041 May 16 12:31:37 PM PDT 24 May 16 12:33:12 PM PDT 24 158702694 ps
T211 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2987671231 May 16 12:31:39 PM PDT 24 May 16 12:33:44 PM PDT 24 2501311365 ps
T1450 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2332401685 May 16 12:31:45 PM PDT 24 May 16 12:33:26 PM PDT 24 49094579 ps
T1451 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1550053277 May 16 12:31:30 PM PDT 24 May 16 12:32:54 PM PDT 24 60178576 ps
T212 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2789178585 May 16 12:31:19 PM PDT 24 May 16 12:32:20 PM PDT 24 26252082 ps

Test location /workspace/coverage/default/40.i2c_target_stretch.3999971893
Short name T6
Test name
Test status
Simulation time 31047245428 ps
CPU time 461.5 seconds
Started May 16 12:48:36 PM PDT 24
Finished May 16 12:56:40 PM PDT 24
Peak memory 1389712 kb
Host smart-b2714a63-6645-4d46-81c2-f2a43daa0d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999971893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3999971893
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2550126224
Short name T41
Test name
Test status
Simulation time 23874598415 ps
CPU time 97.29 seconds
Started May 16 12:46:24 PM PDT 24
Finished May 16 12:48:26 PM PDT 24
Peak memory 794640 kb
Host smart-e8a6a203-5471-4147-a3a2-7d803e3c5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550126224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2550126224
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3190573818
Short name T37
Test name
Test status
Simulation time 96172132894 ps
CPU time 1289.44 seconds
Started May 16 12:44:47 PM PDT 24
Finished May 16 01:06:39 PM PDT 24
Peak memory 1449372 kb
Host smart-f571378e-55d6-44c9-9caf-650157cc923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190573818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3190573818
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.307159830
Short name T15
Test name
Test status
Simulation time 12627575657 ps
CPU time 10.84 seconds
Started May 16 12:44:12 PM PDT 24
Finished May 16 12:44:31 PM PDT 24
Peak memory 213808 kb
Host smart-87b79c02-3c07-478a-8e1f-d65d15dbd503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307159830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.307159830
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2307102175
Short name T92
Test name
Test status
Simulation time 76879586 ps
CPU time 0.97 seconds
Started May 16 12:32:41 PM PDT 24
Finished May 16 12:34:22 PM PDT 24
Peak memory 203304 kb
Host smart-36657e56-24b6-41e6-8d0d-3b01468b565c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307102175 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2307102175
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3011574920
Short name T11
Test name
Test status
Simulation time 10086108047 ps
CPU time 67.33 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 439672 kb
Host smart-bdcc31f2-610f-41d7-b8ec-90faf66c938b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011574920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3011574920
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2846860961
Short name T173
Test name
Test status
Simulation time 145536997 ps
CPU time 0.82 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 222060 kb
Host smart-dff2c638-ec92-40b9-94d3-4f5d05d274b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846860961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2846860961
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2673630358
Short name T42
Test name
Test status
Simulation time 346365634 ps
CPU time 4.28 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:45:54 PM PDT 24
Peak memory 204920 kb
Host smart-24545a50-2dfc-4404-901e-6dc00cbdf788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673630358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2673630358
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.3467582894
Short name T128
Test name
Test status
Simulation time 73853970 ps
CPU time 0.71 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:13 PM PDT 24
Peak memory 204604 kb
Host smart-04f0ea05-60c3-4bb7-a508-14a847388d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467582894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3467582894
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3654265778
Short name T17
Test name
Test status
Simulation time 40373980864 ps
CPU time 104.21 seconds
Started May 16 12:45:14 PM PDT 24
Finished May 16 12:47:26 PM PDT 24
Peak memory 1521264 kb
Host smart-0ba7df4b-90b3-476d-a301-b685f800b422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654265778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3654265778
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3445230125
Short name T39
Test name
Test status
Simulation time 12687444617 ps
CPU time 922.19 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 01:01:00 PM PDT 24
Peak memory 2942864 kb
Host smart-1aa2dc46-f4d7-41c8-a35d-4a40af568059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445230125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3445230125
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2531813930
Short name T19
Test name
Test status
Simulation time 283094043 ps
CPU time 7.43 seconds
Started May 16 12:44:51 PM PDT 24
Finished May 16 12:45:24 PM PDT 24
Peak memory 204924 kb
Host smart-cecaf8e3-3ad5-43b5-97d8-7bf22cfe3e82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531813930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2531813930
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.781772158
Short name T202
Test name
Test status
Simulation time 16492033 ps
CPU time 0.68 seconds
Started May 16 12:31:32 PM PDT 24
Finished May 16 12:32:57 PM PDT 24
Peak memory 203548 kb
Host smart-8f838c58-66c2-4182-ba48-38c2edd9d7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781772158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.781772158
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2626510378
Short name T251
Test name
Test status
Simulation time 64927682448 ps
CPU time 785.91 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 01:00:05 PM PDT 24
Peak memory 792920 kb
Host smart-91d22f18-2f09-4f1c-9c92-ebdb7543ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626510378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2626510378
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3985556987
Short name T53
Test name
Test status
Simulation time 14504827093 ps
CPU time 1767.74 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 01:17:03 PM PDT 24
Peak memory 2364756 kb
Host smart-44c8baf4-51c1-44fa-8768-741fae2cdb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985556987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3985556987
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.3789208900
Short name T267
Test name
Test status
Simulation time 63235993164 ps
CPU time 192.48 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:49:29 PM PDT 24
Peak memory 1944372 kb
Host smart-903ffd80-c793-4af0-a46e-cd7f0ee0e56b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789208900 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.3789208900
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4219122240
Short name T192
Test name
Test status
Simulation time 81480940 ps
CPU time 2.19 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:25 PM PDT 24
Peak memory 203608 kb
Host smart-bf2a4370-c906-4024-9a02-4c8ffefc82f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219122240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4219122240
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2826822567
Short name T232
Test name
Test status
Simulation time 89992959 ps
CPU time 0.94 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:44:53 PM PDT 24
Peak memory 204684 kb
Host smart-aa88f8de-f3d4-4e92-a7fa-687d5ff32864
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826822567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2826822567
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3442750362
Short name T290
Test name
Test status
Simulation time 1059430889 ps
CPU time 5.19 seconds
Started May 16 12:44:26 PM PDT 24
Finished May 16 12:44:42 PM PDT 24
Peak memory 213168 kb
Host smart-b8681b01-1a6f-44a2-af6c-3ad2e63dabdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442750362 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3442750362
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4176005169
Short name T47
Test name
Test status
Simulation time 527301749 ps
CPU time 1.79 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:26 PM PDT 24
Peak memory 213236 kb
Host smart-6bec6725-a8ce-4827-b48d-117d16cc40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176005169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4176005169
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.417032249
Short name T186
Test name
Test status
Simulation time 143551298 ps
CPU time 2.36 seconds
Started May 16 12:31:44 PM PDT 24
Finished May 16 12:33:36 PM PDT 24
Peak memory 203732 kb
Host smart-a88b67d3-a982-4f7c-bf38-10470eaf90ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417032249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.417032249
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3449092111
Short name T83
Test name
Test status
Simulation time 8036536839 ps
CPU time 94.25 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:49:37 PM PDT 24
Peak memory 639448 kb
Host smart-70d937b7-4935-4726-82c7-6dc1c96670f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449092111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3449092111
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2029285454
Short name T869
Test name
Test status
Simulation time 1184728873 ps
CPU time 2.12 seconds
Started May 16 12:46:25 PM PDT 24
Finished May 16 12:46:52 PM PDT 24
Peak memory 205060 kb
Host smart-bf91f37f-1275-44c5-8d55-23666606ec96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029285454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2029285454
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_alert_test.4003930971
Short name T4
Test name
Test status
Simulation time 33291353 ps
CPU time 0.59 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 12:48:48 PM PDT 24
Peak memory 204612 kb
Host smart-2e8a9e34-6bc2-44e5-900d-52389c5be472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003930971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.4003930971
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1749665002
Short name T35
Test name
Test status
Simulation time 18866494716 ps
CPU time 18.2 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 294752 kb
Host smart-43c2082f-a666-4f60-997e-9e13365e872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749665002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1749665002
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3401991052
Short name T102
Test name
Test status
Simulation time 43914356937 ps
CPU time 407.51 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:55:07 PM PDT 24
Peak memory 2155188 kb
Host smart-9cecf8db-6a5b-4dc1-af98-d7e1c5542cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401991052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3401991052
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3765111934
Short name T80
Test name
Test status
Simulation time 7543925964 ps
CPU time 55.17 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:47:11 PM PDT 24
Peak memory 606948 kb
Host smart-472dd76e-6125-4e05-bdcb-cfb0f69f54d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765111934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3765111934
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.273008468
Short name T190
Test name
Test status
Simulation time 78928010 ps
CPU time 1.43 seconds
Started May 16 12:31:23 PM PDT 24
Finished May 16 12:32:35 PM PDT 24
Peak memory 203724 kb
Host smart-172df123-71c7-4487-be22-79ce68bfb00e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273008468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.273008468
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3335428150
Short name T120
Test name
Test status
Simulation time 122102949739 ps
CPU time 1439.55 seconds
Started May 16 12:45:06 PM PDT 24
Finished May 16 01:09:35 PM PDT 24
Peak memory 2979304 kb
Host smart-5084ae4d-b12d-4697-9f79-cd0084f833f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335428150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3335428150
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.421889816
Short name T228
Test name
Test status
Simulation time 24557406570 ps
CPU time 2193.99 seconds
Started May 16 12:46:07 PM PDT 24
Finished May 16 01:23:05 PM PDT 24
Peak memory 4655776 kb
Host smart-44257814-c9c6-4ef0-91c9-80580cd95e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421889816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.421889816
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.640670883
Short name T235
Test name
Test status
Simulation time 356440578 ps
CPU time 0.96 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:47:36 PM PDT 24
Peak memory 204844 kb
Host smart-4091bb56-8359-46d9-bfc4-68fdc375e333
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640670883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.640670883
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1912521906
Short name T258
Test name
Test status
Simulation time 473282245 ps
CPU time 7.26 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:49:58 PM PDT 24
Peak memory 204840 kb
Host smart-4d56c360-5b91-4c3e-8322-c24e01e18173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912521906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1912521906
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1323489540
Short name T3
Test name
Test status
Simulation time 28772836023 ps
CPU time 1480.17 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 01:09:55 PM PDT 24
Peak memory 3143884 kb
Host smart-1ae2e117-a86a-4eb1-95f2-2167c7820c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323489540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1323489540
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2418266800
Short name T154
Test name
Test status
Simulation time 10051723233 ps
CPU time 20.11 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:50:11 PM PDT 24
Peak memory 317480 kb
Host smart-6bb63fc4-f76a-410b-a1e0-32bde6c285cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418266800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2418266800
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2109932274
Short name T68
Test name
Test status
Simulation time 6860742074 ps
CPU time 100.55 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 471708 kb
Host smart-411e1750-6bcf-4582-9adc-205b44e3196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109932274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2109932274
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1282806041
Short name T195
Test name
Test status
Simulation time 158702694 ps
CPU time 2.6 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:12 PM PDT 24
Peak memory 203588 kb
Host smart-2b0134f6-9a82-485a-a69a-3b184d11c2de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282806041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1282806041
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3742982180
Short name T85
Test name
Test status
Simulation time 10081081588 ps
CPU time 87.86 seconds
Started May 16 12:45:34 PM PDT 24
Finished May 16 12:47:26 PM PDT 24
Peak memory 576388 kb
Host smart-43f3f1ba-f63e-461d-8a4c-7fd5fd6d038f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742982180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3742982180
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2338377080
Short name T269
Test name
Test status
Simulation time 41647597 ps
CPU time 0.69 seconds
Started May 16 12:31:18 PM PDT 24
Finished May 16 12:32:16 PM PDT 24
Peak memory 203616 kb
Host smart-201fd5b5-6da2-40f2-90fa-e0d6816b171d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338377080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2338377080
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1135707628
Short name T298
Test name
Test status
Simulation time 39711662163 ps
CPU time 46.14 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 419392 kb
Host smart-1e823ddc-2aa0-4069-ba35-59a33702b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135707628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1135707628
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1099322484
Short name T139
Test name
Test status
Simulation time 22388451536 ps
CPU time 395.58 seconds
Started May 16 12:46:24 PM PDT 24
Finished May 16 12:53:25 PM PDT 24
Peak memory 1461336 kb
Host smart-ab07681a-700b-4311-ad70-8c22172c3794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099322484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1099322484
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.293274537
Short name T1146
Test name
Test status
Simulation time 10134077751 ps
CPU time 76.35 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 468992 kb
Host smart-e0911f20-b305-468d-9c71-a73e57cb8d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293274537 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.293274537
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1826466163
Short name T253
Test name
Test status
Simulation time 1426946744 ps
CPU time 32.15 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 213200 kb
Host smart-ec9a1bfc-3487-486c-a0cd-d44680c5126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826466163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1826466163
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.536653799
Short name T103
Test name
Test status
Simulation time 43108033953 ps
CPU time 893.54 seconds
Started May 16 12:44:51 PM PDT 24
Finished May 16 01:00:10 PM PDT 24
Peak memory 3147132 kb
Host smart-25dc216e-a4f1-49ab-913a-051b31283eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536653799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.536653799
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1899534435
Short name T165
Test name
Test status
Simulation time 1096748322 ps
CPU time 2.97 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:12 PM PDT 24
Peak memory 205028 kb
Host smart-0c943215-c19e-4be8-9f4d-7ca339138b7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899534435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1899534435
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.999847561
Short name T49
Test name
Test status
Simulation time 315886610 ps
CPU time 2.62 seconds
Started May 16 12:45:21 PM PDT 24
Finished May 16 12:45:50 PM PDT 24
Peak memory 213156 kb
Host smart-d00d7c3a-2bb8-4d66-a4da-4805d0ff25cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999847561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.999847561
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3089647448
Short name T52
Test name
Test status
Simulation time 131251164596 ps
CPU time 1040.15 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 01:04:00 PM PDT 24
Peak memory 1881220 kb
Host smart-892ee07b-b181-448a-81e3-c8f4d90c051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089647448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3089647448
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.436083861
Short name T188
Test name
Test status
Simulation time 135716914 ps
CPU time 3.02 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:41 PM PDT 24
Peak memory 203588 kb
Host smart-7492c381-c507-41dc-81cb-0dfd86f66f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436083861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.436083861
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.4021879266
Short name T187
Test name
Test status
Simulation time 273733618 ps
CPU time 1.49 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:51 PM PDT 24
Peak memory 203704 kb
Host smart-a5ecdcaf-4284-411f-a30e-3b0a5529ddbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021879266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.4021879266
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1128840034
Short name T1405
Test name
Test status
Simulation time 1277867764 ps
CPU time 3.45 seconds
Started May 16 12:31:14 PM PDT 24
Finished May 16 12:32:08 PM PDT 24
Peak memory 203756 kb
Host smart-c535bd3e-da42-43bf-b1df-e0fe5b584e8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128840034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1128840034
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2852836039
Short name T1370
Test name
Test status
Simulation time 25283969 ps
CPU time 0.77 seconds
Started May 16 12:31:21 PM PDT 24
Finished May 16 12:32:32 PM PDT 24
Peak memory 203584 kb
Host smart-572d1b2c-7c36-445f-a383-131ea3e54bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852836039 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2852836039
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2789178585
Short name T212
Test name
Test status
Simulation time 26252082 ps
CPU time 0.74 seconds
Started May 16 12:31:19 PM PDT 24
Finished May 16 12:32:20 PM PDT 24
Peak memory 203516 kb
Host smart-4051aaa8-3ecf-4fc4-8a83-05d5fce2236e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789178585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2789178585
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3660990309
Short name T1440
Test name
Test status
Simulation time 16442199 ps
CPU time 0.6 seconds
Started May 16 12:31:21 PM PDT 24
Finished May 16 12:32:29 PM PDT 24
Peak memory 202888 kb
Host smart-3262a5ac-a803-449a-98cc-95328996527f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660990309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3660990309
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3198764273
Short name T1424
Test name
Test status
Simulation time 69289900 ps
CPU time 1.31 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:43 PM PDT 24
Peak memory 203668 kb
Host smart-22c7cacf-edde-44c9-8472-b31103370257
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198764273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3198764273
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1228529614
Short name T1388
Test name
Test status
Simulation time 126794035 ps
CPU time 2.35 seconds
Started May 16 12:31:10 PM PDT 24
Finished May 16 12:31:50 PM PDT 24
Peak memory 203724 kb
Host smart-973a4068-60fa-4249-a795-66263c8034f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228529614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1228529614
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3595991475
Short name T1445
Test name
Test status
Simulation time 83045204 ps
CPU time 1.37 seconds
Started May 16 12:31:09 PM PDT 24
Finished May 16 12:31:49 PM PDT 24
Peak memory 203480 kb
Host smart-68c4d7a1-d131-415a-8fd8-1a91751476e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595991475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3595991475
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2987671231
Short name T211
Test name
Test status
Simulation time 2501311365 ps
CPU time 6.47 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:44 PM PDT 24
Peak memory 203784 kb
Host smart-d6c5bfcd-6130-4f18-b64e-3a88ad1121e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987671231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2987671231
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.620537538
Short name T208
Test name
Test status
Simulation time 88165218 ps
CPU time 0.73 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:24 PM PDT 24
Peak memory 203568 kb
Host smart-fba3cfca-7378-47ea-9182-0fb446a49c3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620537538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.620537538
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2343913728
Short name T1436
Test name
Test status
Simulation time 79188560 ps
CPU time 0.84 seconds
Started May 16 12:31:36 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203328 kb
Host smart-c33f2e7e-1f58-471d-80ce-f87a1c9821c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343913728 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2343913728
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.248686056
Short name T236
Test name
Test status
Simulation time 29998093 ps
CPU time 0.77 seconds
Started May 16 12:31:24 PM PDT 24
Finished May 16 12:32:43 PM PDT 24
Peak memory 203580 kb
Host smart-dc40e7c2-9a38-4ef3-b406-7d11a10b3fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248686056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.248686056
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2299191222
Short name T125
Test name
Test status
Simulation time 51262486 ps
CPU time 0.7 seconds
Started May 16 12:32:18 PM PDT 24
Finished May 16 12:34:04 PM PDT 24
Peak memory 202772 kb
Host smart-2a11c281-95b5-498f-ab65-f9bc63bdcbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299191222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2299191222
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4117045594
Short name T1448
Test name
Test status
Simulation time 36641242 ps
CPU time 0.83 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203732 kb
Host smart-3b05f1d0-f365-43a8-b768-c285d90bac78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117045594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.4117045594
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3225681856
Short name T1375
Test name
Test status
Simulation time 40931994 ps
CPU time 1.88 seconds
Started May 16 12:31:21 PM PDT 24
Finished May 16 12:32:31 PM PDT 24
Peak memory 203704 kb
Host smart-ed6feaee-9e4f-4c90-9ee6-78454957ffa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225681856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3225681856
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1547402180
Short name T1434
Test name
Test status
Simulation time 108191735 ps
CPU time 0.94 seconds
Started May 16 12:31:43 PM PDT 24
Finished May 16 12:33:29 PM PDT 24
Peak memory 203580 kb
Host smart-3c651d3d-93e7-4e4d-89a9-d3d91f86b892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547402180 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1547402180
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.260306217
Short name T221
Test name
Test status
Simulation time 23401625 ps
CPU time 0.7 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203552 kb
Host smart-f9a87b9a-f6bc-4495-b36f-3dbdd2b0bc18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260306217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.260306217
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3282947035
Short name T1358
Test name
Test status
Simulation time 34483506 ps
CPU time 0.65 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 202976 kb
Host smart-9dfece7b-2a4a-4bfd-9119-b513c6baed8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282947035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3282947035
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.140937936
Short name T1431
Test name
Test status
Simulation time 96981627 ps
CPU time 1.13 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203704 kb
Host smart-76cd5f46-f618-4e30-a054-6b77ae2e98b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140937936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.140937936
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4191291258
Short name T98
Test name
Test status
Simulation time 108564215 ps
CPU time 1.25 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203692 kb
Host smart-91585333-ce66-4600-8591-4a25bed3a460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191291258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4191291258
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.553546287
Short name T1425
Test name
Test status
Simulation time 28522107 ps
CPU time 0.77 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203464 kb
Host smart-4f8b6844-5c19-46dc-9f07-139ca2018a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553546287 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.553546287
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2935340681
Short name T207
Test name
Test status
Simulation time 52115070 ps
CPU time 0.67 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203472 kb
Host smart-53fbbc06-fc09-4239-892f-bb3289650774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935340681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2935340681
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2698260784
Short name T1391
Test name
Test status
Simulation time 17826730 ps
CPU time 0.72 seconds
Started May 16 12:31:43 PM PDT 24
Finished May 16 12:33:23 PM PDT 24
Peak memory 203496 kb
Host smart-4b701fe6-a1d7-41e2-87b1-dc3f2d76b9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698260784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2698260784
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.758581158
Short name T1426
Test name
Test status
Simulation time 23030793 ps
CPU time 0.89 seconds
Started May 16 12:31:46 PM PDT 24
Finished May 16 12:33:29 PM PDT 24
Peak memory 203588 kb
Host smart-82571af3-53d1-4f4b-a512-4f33ce0bd0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758581158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.758581158
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.912506008
Short name T1415
Test name
Test status
Simulation time 29021900 ps
CPU time 1.24 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:29 PM PDT 24
Peak memory 203752 kb
Host smart-4bfab870-be69-4063-a2fb-09f4c87a7558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912506008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.912506008
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.841648880
Short name T1396
Test name
Test status
Simulation time 37620682 ps
CPU time 0.94 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203496 kb
Host smart-76f2e8ca-ed06-4889-8387-a178f0494654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841648880 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.841648880
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.294942829
Short name T219
Test name
Test status
Simulation time 82195257 ps
CPU time 0.77 seconds
Started May 16 12:31:44 PM PDT 24
Finished May 16 12:33:34 PM PDT 24
Peak memory 203624 kb
Host smart-43b7a9d5-2518-4fab-b062-000e1d6abee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294942829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.294942829
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3769540931
Short name T1423
Test name
Test status
Simulation time 29549312 ps
CPU time 0.65 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:38 PM PDT 24
Peak memory 203508 kb
Host smart-349f5b0b-6994-4ba3-b7a6-dc1bb6b0f1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769540931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3769540931
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3032402953
Short name T99
Test name
Test status
Simulation time 39430125 ps
CPU time 0.87 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:04 PM PDT 24
Peak memory 203524 kb
Host smart-c416a1a1-a74d-40b9-872b-24dc2acf3bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032402953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3032402953
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1678941569
Short name T1380
Test name
Test status
Simulation time 401396120 ps
CPU time 1.25 seconds
Started May 16 12:31:44 PM PDT 24
Finished May 16 12:33:44 PM PDT 24
Peak memory 203728 kb
Host smart-0c3ebf4d-ee93-40b2-badf-bc5115bf5cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678941569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1678941569
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.877583161
Short name T183
Test name
Test status
Simulation time 77744376 ps
CPU time 1.58 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:44 PM PDT 24
Peak memory 203736 kb
Host smart-6ed642a9-e843-4cdd-96da-e30f8a25fecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877583161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.877583161
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2102121556
Short name T1443
Test name
Test status
Simulation time 26236451 ps
CPU time 0.97 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203588 kb
Host smart-353137e7-11e2-471c-93a4-8de90272aa19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102121556 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2102121556
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3165446289
Short name T215
Test name
Test status
Simulation time 19407935 ps
CPU time 0.77 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:33 PM PDT 24
Peak memory 203512 kb
Host smart-33d89901-522f-49e4-9f76-c2f019a1b053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165446289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3165446289
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1867677075
Short name T1357
Test name
Test status
Simulation time 17022296 ps
CPU time 0.66 seconds
Started May 16 12:31:36 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203564 kb
Host smart-675fb0cf-a6c2-4616-97fb-1083624b4cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867677075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1867677075
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1662879273
Short name T1414
Test name
Test status
Simulation time 86741153 ps
CPU time 1.1 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203596 kb
Host smart-36482e83-74ad-4ca1-b043-6a7fcd6a0eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662879273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1662879273
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1604841947
Short name T194
Test name
Test status
Simulation time 102423052 ps
CPU time 2.15 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:40 PM PDT 24
Peak memory 203772 kb
Host smart-73bb93a1-15c2-4de1-b547-78f948937a36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604841947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1604841947
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3520881045
Short name T96
Test name
Test status
Simulation time 36482949 ps
CPU time 0.97 seconds
Started May 16 12:31:27 PM PDT 24
Finished May 16 12:32:47 PM PDT 24
Peak memory 203584 kb
Host smart-090196dd-b668-484f-ae1d-3c6f718b42da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520881045 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3520881045
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.772592813
Short name T222
Test name
Test status
Simulation time 130355908 ps
CPU time 0.67 seconds
Started May 16 12:31:45 PM PDT 24
Finished May 16 12:33:27 PM PDT 24
Peak memory 203380 kb
Host smart-ae13045e-a3d3-4789-948e-821e1a501f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772592813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.772592813
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.525221499
Short name T1373
Test name
Test status
Simulation time 42576516 ps
CPU time 0.63 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:33 PM PDT 24
Peak memory 203472 kb
Host smart-4279f26b-319f-48b7-8307-c6c96030181a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525221499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.525221499
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1039855906
Short name T220
Test name
Test status
Simulation time 99847855 ps
CPU time 1.16 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203656 kb
Host smart-9c303fb8-420a-4b95-8d85-b897a8783bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039855906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1039855906
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3264918923
Short name T1369
Test name
Test status
Simulation time 154131853 ps
CPU time 2.61 seconds
Started May 16 12:31:26 PM PDT 24
Finished May 16 12:32:49 PM PDT 24
Peak memory 203672 kb
Host smart-fb897589-5ec1-49b7-a9c9-3a1d6f083a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264918923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3264918923
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2958745893
Short name T1411
Test name
Test status
Simulation time 89444767 ps
CPU time 1.5 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:11 PM PDT 24
Peak memory 203740 kb
Host smart-01ff9f1e-5a84-4dd4-b865-2ef5828dc092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958745893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2958745893
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3693586883
Short name T1421
Test name
Test status
Simulation time 79524384 ps
CPU time 0.75 seconds
Started May 16 12:31:43 PM PDT 24
Finished May 16 12:33:22 PM PDT 24
Peak memory 203540 kb
Host smart-49b170ef-4e95-4452-a227-5042105abf79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693586883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3693586883
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2503870049
Short name T1447
Test name
Test status
Simulation time 17212594 ps
CPU time 0.63 seconds
Started May 16 12:31:43 PM PDT 24
Finished May 16 12:33:29 PM PDT 24
Peak memory 203412 kb
Host smart-4d83e119-0751-499c-903c-6c5bcc7398c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503870049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2503870049
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.4261830942
Short name T218
Test name
Test status
Simulation time 65403794 ps
CPU time 0.91 seconds
Started May 16 12:31:53 PM PDT 24
Finished May 16 12:33:41 PM PDT 24
Peak memory 203656 kb
Host smart-a94f6111-1b16-4eae-b56c-5ffc6f54ac76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261830942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.4261830942
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1898351522
Short name T1449
Test name
Test status
Simulation time 48329108 ps
CPU time 2.12 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:49 PM PDT 24
Peak memory 203592 kb
Host smart-b7f55ece-28da-46ad-bf11-29e091f6a846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898351522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1898351522
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.187605250
Short name T1384
Test name
Test status
Simulation time 50911219 ps
CPU time 1.3 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203692 kb
Host smart-e0021831-d0fa-4831-bddf-d02a3f1bf26a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187605250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.187605250
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2787388503
Short name T1377
Test name
Test status
Simulation time 38830615 ps
CPU time 0.94 seconds
Started May 16 12:31:36 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203724 kb
Host smart-bcaa2c20-5706-439b-819e-393828821ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787388503 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2787388503
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1737587153
Short name T217
Test name
Test status
Simulation time 20794859 ps
CPU time 0.76 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:24 PM PDT 24
Peak memory 203104 kb
Host smart-579576df-0adf-473f-b862-f2623dc826ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737587153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1737587153
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1002152188
Short name T1351
Test name
Test status
Simulation time 45527223 ps
CPU time 0.66 seconds
Started May 16 12:31:45 PM PDT 24
Finished May 16 12:33:27 PM PDT 24
Peak memory 203496 kb
Host smart-506f6860-fee0-4f92-8aa4-2c6fb77077c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002152188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1002152188
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4067397373
Short name T1446
Test name
Test status
Simulation time 133411810 ps
CPU time 1.16 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:19 PM PDT 24
Peak memory 203684 kb
Host smart-809af5a6-935d-4046-a21d-b22a169a2ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067397373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.4067397373
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.514784877
Short name T100
Test name
Test status
Simulation time 610400249 ps
CPU time 2.89 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:36 PM PDT 24
Peak memory 203592 kb
Host smart-ffa50b01-9775-453e-871f-218247ebc6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514784877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.514784877
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.823375377
Short name T189
Test name
Test status
Simulation time 752601927 ps
CPU time 2.51 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203752 kb
Host smart-cce65017-9e65-4bdb-b776-d39cc0ca8fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823375377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.823375377
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1598753171
Short name T1371
Test name
Test status
Simulation time 58794494 ps
CPU time 0.95 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203132 kb
Host smart-86e10529-ac04-46ed-8814-5d094dc8d0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598753171 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1598753171
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.49219825
Short name T213
Test name
Test status
Simulation time 28848317 ps
CPU time 0.78 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203444 kb
Host smart-d2b4e762-56a7-43f1-afb3-1bb84f583d13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49219825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.49219825
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.219515608
Short name T1427
Test name
Test status
Simulation time 29553102 ps
CPU time 0.63 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:50 PM PDT 24
Peak memory 203232 kb
Host smart-dabca084-60f8-4646-829b-f398547b9c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219515608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.219515608
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1919633182
Short name T1372
Test name
Test status
Simulation time 126691244 ps
CPU time 1.18 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:05 PM PDT 24
Peak memory 203512 kb
Host smart-f368f0f2-365c-4b44-a97b-610fedf3a14a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919633182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1919633182
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2185711491
Short name T1432
Test name
Test status
Simulation time 172772772 ps
CPU time 1.77 seconds
Started May 16 12:31:45 PM PDT 24
Finished May 16 12:33:27 PM PDT 24
Peak memory 203788 kb
Host smart-90dd8c3e-b4a1-45a6-a602-4f211ce6a256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185711491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2185711491
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.332066309
Short name T185
Test name
Test status
Simulation time 145139731 ps
CPU time 2.43 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:30 PM PDT 24
Peak memory 203748 kb
Host smart-e60a8755-257e-49c8-a137-7cf1d56814a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332066309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.332066309
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2672000709
Short name T1394
Test name
Test status
Simulation time 40642789 ps
CPU time 0.92 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203532 kb
Host smart-15b3661d-b874-4e1e-b233-fbe7bde90e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672000709 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2672000709
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3880821080
Short name T1410
Test name
Test status
Simulation time 21547467 ps
CPU time 0.78 seconds
Started May 16 12:31:34 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203552 kb
Host smart-06a94385-f7e3-457f-8ee8-29cdb20e6e2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880821080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3880821080
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3962679964
Short name T1416
Test name
Test status
Simulation time 58971301 ps
CPU time 0.65 seconds
Started May 16 12:31:54 PM PDT 24
Finished May 16 12:33:43 PM PDT 24
Peak memory 203556 kb
Host smart-8bada235-20c1-4bca-a197-13114a39e470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962679964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3962679964
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3139722057
Short name T101
Test name
Test status
Simulation time 256905281 ps
CPU time 1.17 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203600 kb
Host smart-44fd4696-6bda-4de2-8396-41187a9e65a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139722057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3139722057
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1604204415
Short name T93
Test name
Test status
Simulation time 109302254 ps
CPU time 1.33 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203556 kb
Host smart-9b7039ef-058d-470e-9c17-df2ab60f40cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604204415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1604204415
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1003459087
Short name T197
Test name
Test status
Simulation time 1886774102 ps
CPU time 2.72 seconds
Started May 16 12:31:32 PM PDT 24
Finished May 16 12:32:59 PM PDT 24
Peak memory 203752 kb
Host smart-cf8def7d-b297-435f-a8a4-d59fbc9eb35a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003459087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1003459087
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2815147058
Short name T1381
Test name
Test status
Simulation time 73223424 ps
CPU time 0.94 seconds
Started May 16 12:31:59 PM PDT 24
Finished May 16 12:33:49 PM PDT 24
Peak memory 203716 kb
Host smart-219b2d97-daf0-4d3b-b5a6-97bad388a485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815147058 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2815147058
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3396576972
Short name T206
Test name
Test status
Simulation time 19302373 ps
CPU time 0.71 seconds
Started May 16 12:31:50 PM PDT 24
Finished May 16 12:33:38 PM PDT 24
Peak memory 203444 kb
Host smart-d86b711e-aa6c-44e5-afa8-0671e69d4a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396576972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3396576972
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.391362867
Short name T1361
Test name
Test status
Simulation time 44434742 ps
CPU time 0.63 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203464 kb
Host smart-ec907913-7126-4aa3-b4bd-754e9539c4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391362867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.391362867
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.221336520
Short name T1402
Test name
Test status
Simulation time 96335303 ps
CPU time 1.08 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203748 kb
Host smart-78cca54a-5d27-47b7-aa9d-23fe897a38d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221336520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.221336520
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3704041701
Short name T118
Test name
Test status
Simulation time 154742301 ps
CPU time 1.01 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203604 kb
Host smart-3ecf55a4-037a-444a-9683-00891796b119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704041701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3704041701
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2663322039
Short name T1422
Test name
Test status
Simulation time 1165884192 ps
CPU time 2.23 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:25 PM PDT 24
Peak memory 203392 kb
Host smart-18ef83ef-82a6-4996-bfbc-c517da08f376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663322039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2663322039
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2530986434
Short name T148
Test name
Test status
Simulation time 1023563738 ps
CPU time 1.36 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203604 kb
Host smart-fc5d108b-25da-4277-b46d-11664c2d27c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530986434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2530986434
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1926338046
Short name T210
Test name
Test status
Simulation time 166326086 ps
CPU time 2.96 seconds
Started May 16 12:31:18 PM PDT 24
Finished May 16 12:32:18 PM PDT 24
Peak memory 203744 kb
Host smart-2c0194c3-899d-41b6-a021-451a21440e1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926338046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1926338046
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3444105770
Short name T1353
Test name
Test status
Simulation time 48187696 ps
CPU time 0.7 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:46 PM PDT 24
Peak memory 203568 kb
Host smart-4e8d3ee7-7ec8-43c8-9c38-21aaea603574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444105770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3444105770
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2688794453
Short name T1407
Test name
Test status
Simulation time 31583363 ps
CPU time 0.94 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203048 kb
Host smart-e8fb1e0a-7a73-4314-902e-cb9ba8348993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688794453 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2688794453
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3688084025
Short name T216
Test name
Test status
Simulation time 46242204 ps
CPU time 0.76 seconds
Started May 16 12:31:30 PM PDT 24
Finished May 16 12:32:56 PM PDT 24
Peak memory 203500 kb
Host smart-96a85712-89d5-47af-b921-d168f0c374a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688084025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3688084025
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1782088599
Short name T1363
Test name
Test status
Simulation time 25545513 ps
CPU time 0.63 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:00 PM PDT 24
Peak memory 203552 kb
Host smart-5478d230-8274-459d-86b8-ad29fa7dd8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782088599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1782088599
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1977954858
Short name T1418
Test name
Test status
Simulation time 108704940 ps
CPU time 0.92 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:04 PM PDT 24
Peak memory 203584 kb
Host smart-33c6b100-8e9d-4d68-ad19-4fae8c77eb1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977954858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1977954858
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3118110950
Short name T201
Test name
Test status
Simulation time 33221084 ps
CPU time 1.59 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203568 kb
Host smart-02fa7be8-14fe-40b6-9fa8-0dae892fc553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118110950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3118110950
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.222826316
Short name T198
Test name
Test status
Simulation time 50970103 ps
CPU time 1.51 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:47 PM PDT 24
Peak memory 203720 kb
Host smart-a6bec87c-504f-4be5-8eb5-8e34814b0ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222826316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.222826316
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3476268459
Short name T1397
Test name
Test status
Simulation time 32457784 ps
CPU time 0.63 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203544 kb
Host smart-80a75022-59ff-4ef8-bf34-fae549970e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476268459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3476268459
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4218623072
Short name T1439
Test name
Test status
Simulation time 21455237 ps
CPU time 0.65 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203408 kb
Host smart-98b0f182-7435-4c4c-b995-aca1df53a97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218623072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4218623072
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.618848516
Short name T1356
Test name
Test status
Simulation time 16211454 ps
CPU time 0.68 seconds
Started May 16 12:31:49 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203420 kb
Host smart-d992cde2-ccb1-4e6a-96fe-07dfdaa18e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618848516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.618848516
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2583834017
Short name T1352
Test name
Test status
Simulation time 38930915 ps
CPU time 0.62 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203568 kb
Host smart-daf59d1a-76c0-4c0b-8618-b0bbd8e2e4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583834017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2583834017
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.463667030
Short name T1355
Test name
Test status
Simulation time 35401367 ps
CPU time 0.63 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203552 kb
Host smart-62f1c0ec-4502-40fc-b043-4ef42446ac1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463667030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.463667030
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.937254049
Short name T1360
Test name
Test status
Simulation time 38717917 ps
CPU time 0.65 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:43 PM PDT 24
Peak memory 203668 kb
Host smart-71de2def-294c-4c61-8eef-98ba9b797fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937254049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.937254049
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.233308263
Short name T1430
Test name
Test status
Simulation time 39089482 ps
CPU time 0.67 seconds
Started May 16 12:31:54 PM PDT 24
Finished May 16 12:33:43 PM PDT 24
Peak memory 203416 kb
Host smart-83c1aefd-f8fe-4af1-9de9-db0a81072323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233308263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.233308263
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2308921458
Short name T1433
Test name
Test status
Simulation time 33147866 ps
CPU time 0.63 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203424 kb
Host smart-a79bb89f-cdd7-4f5d-beaf-f6c30e66e401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308921458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2308921458
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.864583586
Short name T1408
Test name
Test status
Simulation time 21396060 ps
CPU time 0.6 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 202792 kb
Host smart-3f4148e1-59b7-4474-b166-7c06c7197e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864583586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.864583586
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3077586530
Short name T1400
Test name
Test status
Simulation time 17043758 ps
CPU time 0.65 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203480 kb
Host smart-f82b93c8-e93a-4e67-90db-2b4f04d32d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077586530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3077586530
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2068883592
Short name T204
Test name
Test status
Simulation time 31284268 ps
CPU time 1.36 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203724 kb
Host smart-1f9d3c10-cbfb-481e-99e3-1eb65dd09a75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068883592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2068883592
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1823786673
Short name T214
Test name
Test status
Simulation time 76894579 ps
CPU time 0.73 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:43 PM PDT 24
Peak memory 203428 kb
Host smart-cb918e6a-d1f8-46f1-8ed5-63fa430e337b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823786673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1823786673
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.716731305
Short name T200
Test name
Test status
Simulation time 25120246 ps
CPU time 1.03 seconds
Started May 16 12:31:30 PM PDT 24
Finished May 16 12:32:55 PM PDT 24
Peak memory 203720 kb
Host smart-6cd05982-fd39-4b50-8d77-09458acd31f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716731305 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.716731305
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3172725940
Short name T203
Test name
Test status
Simulation time 52693424 ps
CPU time 0.76 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:12 PM PDT 24
Peak memory 203644 kb
Host smart-936a9ad4-1f6e-41e2-8343-7fee79db437a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172725940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3172725940
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2224683403
Short name T1359
Test name
Test status
Simulation time 114047958 ps
CPU time 0.65 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:53 PM PDT 24
Peak memory 203396 kb
Host smart-1c11cf7a-d15f-4014-83d6-00c47b66366f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224683403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2224683403
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1550053277
Short name T1451
Test name
Test status
Simulation time 60178576 ps
CPU time 0.85 seconds
Started May 16 12:31:30 PM PDT 24
Finished May 16 12:32:54 PM PDT 24
Peak memory 203552 kb
Host smart-c6ffb9ea-203c-4aff-937a-3678215cc078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550053277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1550053277
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3757673302
Short name T1438
Test name
Test status
Simulation time 838155650 ps
CPU time 1.34 seconds
Started May 16 12:31:17 PM PDT 24
Finished May 16 12:32:15 PM PDT 24
Peak memory 203688 kb
Host smart-b9c74d50-cd21-48e9-a7ef-b3d0edf56d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757673302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3757673302
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1155814255
Short name T196
Test name
Test status
Simulation time 53030331 ps
CPU time 1.51 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:11 PM PDT 24
Peak memory 203736 kb
Host smart-1f31744e-b7f3-4f97-b2c7-9a8cc591a9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155814255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1155814255
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.4184656232
Short name T1368
Test name
Test status
Simulation time 25651931 ps
CPU time 0.62 seconds
Started May 16 12:31:46 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203436 kb
Host smart-c21d7afc-e8d1-493f-baba-876ef68d06b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184656232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.4184656232
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3424514106
Short name T1406
Test name
Test status
Simulation time 40053946 ps
CPU time 0.72 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203460 kb
Host smart-37ce29d5-3b9f-44af-8930-0ed8b7c2edcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424514106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3424514106
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2980242669
Short name T1398
Test name
Test status
Simulation time 50514866 ps
CPU time 0.68 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203560 kb
Host smart-c8121930-92d8-4c17-a124-dd786daf76b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980242669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2980242669
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2332401685
Short name T1450
Test name
Test status
Simulation time 49094579 ps
CPU time 0.67 seconds
Started May 16 12:31:45 PM PDT 24
Finished May 16 12:33:26 PM PDT 24
Peak memory 203528 kb
Host smart-9097c1b4-278d-4a71-b21a-9a9dd89e9742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332401685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2332401685
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1002710141
Short name T1376
Test name
Test status
Simulation time 15600792 ps
CPU time 0.7 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203424 kb
Host smart-252b44b8-f812-4ad7-9b05-a1c876c23f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002710141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1002710141
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.808008922
Short name T1429
Test name
Test status
Simulation time 54098114 ps
CPU time 0.67 seconds
Started May 16 12:31:57 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203568 kb
Host smart-f4a4dbc1-c04c-40ca-9b12-a2d4ed64991b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808008922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.808008922
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.652917773
Short name T1385
Test name
Test status
Simulation time 17264196 ps
CPU time 0.63 seconds
Started May 16 12:31:53 PM PDT 24
Finished May 16 12:33:41 PM PDT 24
Peak memory 203408 kb
Host smart-d7b9f8cc-a0d2-4266-a3af-4ba97c40581b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652917773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.652917773
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1440001033
Short name T1362
Test name
Test status
Simulation time 20300758 ps
CPU time 0.65 seconds
Started May 16 12:31:45 PM PDT 24
Finished May 16 12:33:27 PM PDT 24
Peak memory 203572 kb
Host smart-d5a0eb3f-1ef3-4364-9a32-0e7c913927ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440001033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1440001033
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3877441015
Short name T1437
Test name
Test status
Simulation time 40277309 ps
CPU time 0.65 seconds
Started May 16 12:31:56 PM PDT 24
Finished May 16 12:33:47 PM PDT 24
Peak memory 203560 kb
Host smart-daa60db2-7fee-4cce-aead-fb7d203d5636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877441015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3877441015
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2002089014
Short name T1401
Test name
Test status
Simulation time 32416868 ps
CPU time 0.66 seconds
Started May 16 12:31:50 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203516 kb
Host smart-31704ced-f18a-47fb-aff0-175c50f0e12f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002089014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2002089014
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4087888881
Short name T1382
Test name
Test status
Simulation time 194685541 ps
CPU time 1.23 seconds
Started May 16 12:31:27 PM PDT 24
Finished May 16 12:32:49 PM PDT 24
Peak memory 203540 kb
Host smart-71fe5f28-5f1d-4b49-9b02-c6ad1bf6b68b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087888881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.4087888881
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3034407254
Short name T95
Test name
Test status
Simulation time 75750313 ps
CPU time 0.76 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:53 PM PDT 24
Peak memory 203408 kb
Host smart-cb8c4176-bc8f-4bb7-bd43-97038eac6f26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034407254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3034407254
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1989672377
Short name T145
Test name
Test status
Simulation time 30109217 ps
CPU time 0.87 seconds
Started May 16 12:31:34 PM PDT 24
Finished May 16 12:33:03 PM PDT 24
Peak memory 203560 kb
Host smart-20a9d98c-cb52-4c20-9594-c06318320f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989672377 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1989672377
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3126526796
Short name T94
Test name
Test status
Simulation time 34219594 ps
CPU time 0.71 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:09 PM PDT 24
Peak memory 203412 kb
Host smart-5eb99f60-4834-4b20-b271-53b8ee45cfed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126526796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3126526796
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.579691478
Short name T1444
Test name
Test status
Simulation time 45899959 ps
CPU time 0.66 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203604 kb
Host smart-9737098f-7436-4126-a0fd-d2fb67c1a5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579691478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.579691478
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1827715315
Short name T1442
Test name
Test status
Simulation time 58531851 ps
CPU time 0.87 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:05 PM PDT 24
Peak memory 203456 kb
Host smart-f7815c0b-bcdc-47fe-85c6-d110ece877b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827715315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1827715315
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3839986986
Short name T1417
Test name
Test status
Simulation time 91952910 ps
CPU time 1.57 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:24 PM PDT 24
Peak memory 203520 kb
Host smart-e2fd27f7-41de-44e8-97fb-20162d548af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839986986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3839986986
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4027460154
Short name T1412
Test name
Test status
Simulation time 24828531 ps
CPU time 0.64 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:24 PM PDT 24
Peak memory 203396 kb
Host smart-461999f3-24d8-4bb9-b947-e622e6da5b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027460154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4027460154
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2918627732
Short name T1350
Test name
Test status
Simulation time 29139829 ps
CPU time 0.63 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:32 PM PDT 24
Peak memory 203432 kb
Host smart-9d3d000d-b08a-4b1b-9d8c-f4523c29bfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918627732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2918627732
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2904966715
Short name T1419
Test name
Test status
Simulation time 40259170 ps
CPU time 0.63 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:18 PM PDT 24
Peak memory 203128 kb
Host smart-75c62169-c067-45f9-940e-ba14d53f12bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904966715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2904966715
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2985382876
Short name T1428
Test name
Test status
Simulation time 47956616 ps
CPU time 0.65 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203464 kb
Host smart-3f7e24f3-4939-4e00-be12-979412109bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985382876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2985382876
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1223355265
Short name T1392
Test name
Test status
Simulation time 47578506 ps
CPU time 0.62 seconds
Started May 16 12:31:49 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203556 kb
Host smart-0c37b6a2-1139-4bc0-9dd6-69dc619096c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223355265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1223355265
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1103113739
Short name T1409
Test name
Test status
Simulation time 23598399 ps
CPU time 0.63 seconds
Started May 16 12:31:40 PM PDT 24
Finished May 16 12:33:24 PM PDT 24
Peak memory 203088 kb
Host smart-2e5a2c26-223e-4ac6-a108-1604f940b1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103113739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1103113739
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1127235191
Short name T1366
Test name
Test status
Simulation time 30072111 ps
CPU time 0.69 seconds
Started May 16 12:31:41 PM PDT 24
Finished May 16 12:33:17 PM PDT 24
Peak memory 203540 kb
Host smart-8a642c2b-d8a5-440d-a544-9cfe164aa308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127235191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1127235191
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3319916470
Short name T1413
Test name
Test status
Simulation time 40565160 ps
CPU time 0.64 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:43 PM PDT 24
Peak memory 203564 kb
Host smart-cc69515c-7f93-4dee-b1d1-44aa10452523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319916470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3319916470
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3309509021
Short name T1349
Test name
Test status
Simulation time 18545153 ps
CPU time 0.68 seconds
Started May 16 12:31:49 PM PDT 24
Finished May 16 12:33:48 PM PDT 24
Peak memory 203564 kb
Host smart-6b15e7ea-acc7-428b-8e4c-30aae66b1dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309509021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3309509021
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2649044774
Short name T1390
Test name
Test status
Simulation time 42709140 ps
CPU time 0.64 seconds
Started May 16 12:31:48 PM PDT 24
Finished May 16 12:33:43 PM PDT 24
Peak memory 203564 kb
Host smart-21c0e426-db4d-4674-8719-14ac44950de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649044774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2649044774
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2038327726
Short name T1383
Test name
Test status
Simulation time 68265180 ps
CPU time 1.35 seconds
Started May 16 12:32:25 PM PDT 24
Finished May 16 12:34:15 PM PDT 24
Peak memory 203392 kb
Host smart-ff3a83af-d6b1-4606-9615-c41941148962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038327726 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2038327726
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1602542753
Short name T1364
Test name
Test status
Simulation time 23783794 ps
CPU time 0.76 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:54 PM PDT 24
Peak memory 203628 kb
Host smart-42837df1-66e7-475b-a73b-97bd4a9a92c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602542753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1602542753
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1697295044
Short name T1354
Test name
Test status
Simulation time 47055984 ps
CPU time 0.68 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:00 PM PDT 24
Peak memory 203492 kb
Host smart-4534adf0-62f4-4427-b60c-de3f48099dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697295044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1697295044
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3245845550
Short name T1367
Test name
Test status
Simulation time 52068088 ps
CPU time 1.4 seconds
Started May 16 12:31:34 PM PDT 24
Finished May 16 12:33:02 PM PDT 24
Peak memory 203560 kb
Host smart-cba739f1-f3cb-4eca-8c75-158798908717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245845550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3245845550
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.407071548
Short name T193
Test name
Test status
Simulation time 163816788 ps
CPU time 2.41 seconds
Started May 16 12:31:34 PM PDT 24
Finished May 16 12:33:03 PM PDT 24
Peak memory 203772 kb
Host smart-63a3fe0e-8cae-4677-8509-527e9447a47f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407071548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.407071548
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.972320333
Short name T1386
Test name
Test status
Simulation time 38931143 ps
CPU time 0.75 seconds
Started May 16 12:31:28 PM PDT 24
Finished May 16 12:32:49 PM PDT 24
Peak memory 203628 kb
Host smart-d277f7fa-7c1d-4eb1-9038-eed28c52ecd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972320333 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.972320333
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2961066369
Short name T1365
Test name
Test status
Simulation time 18420845 ps
CPU time 0.67 seconds
Started May 16 12:31:29 PM PDT 24
Finished May 16 12:32:51 PM PDT 24
Peak memory 203488 kb
Host smart-712895ff-63f7-4d8e-aec3-fe8092db5de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961066369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2961066369
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1351187938
Short name T1374
Test name
Test status
Simulation time 16519455 ps
CPU time 0.62 seconds
Started May 16 12:31:27 PM PDT 24
Finished May 16 12:32:47 PM PDT 24
Peak memory 203420 kb
Host smart-2c51f033-4400-449e-9555-e2a6d0475c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351187938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1351187938
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2019871237
Short name T1403
Test name
Test status
Simulation time 56533845 ps
CPU time 0.84 seconds
Started May 16 12:31:38 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203476 kb
Host smart-c724eb5f-f9fc-4366-a18a-642afb0f79de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019871237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2019871237
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3365018159
Short name T97
Test name
Test status
Simulation time 230899607 ps
CPU time 2.21 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:34 PM PDT 24
Peak memory 203596 kb
Host smart-1d0302d2-c268-4328-b853-40dbfccfb604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365018159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3365018159
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3108001233
Short name T147
Test name
Test status
Simulation time 93398361 ps
CPU time 1.41 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203652 kb
Host smart-eaa6e887-332d-4a5d-bf50-7696dcfa9db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108001233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3108001233
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4181700419
Short name T1404
Test name
Test status
Simulation time 29306434 ps
CPU time 0.82 seconds
Started May 16 12:31:32 PM PDT 24
Finished May 16 12:32:58 PM PDT 24
Peak memory 203596 kb
Host smart-0e643e85-0178-4a9b-b92a-8c3cd6fac47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181700419 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4181700419
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2488676118
Short name T205
Test name
Test status
Simulation time 46030180 ps
CPU time 0.78 seconds
Started May 16 12:31:27 PM PDT 24
Finished May 16 12:32:47 PM PDT 24
Peak memory 203400 kb
Host smart-56ea7700-0175-486a-b961-9a3b6eeaed3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488676118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2488676118
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2561462278
Short name T1389
Test name
Test status
Simulation time 51746189 ps
CPU time 0.63 seconds
Started May 16 12:32:25 PM PDT 24
Finished May 16 12:34:14 PM PDT 24
Peak memory 202480 kb
Host smart-fd38fdfc-75d7-43a0-952e-567e8fb1cca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561462278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2561462278
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2078053652
Short name T1395
Test name
Test status
Simulation time 54516365 ps
CPU time 1.22 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:05 PM PDT 24
Peak memory 203596 kb
Host smart-a7cd39e8-47b1-47c0-94c9-15cce3fe52e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078053652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2078053652
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1325040542
Short name T1420
Test name
Test status
Simulation time 170219946 ps
CPU time 2.91 seconds
Started May 16 12:32:25 PM PDT 24
Finished May 16 12:34:16 PM PDT 24
Peak memory 202376 kb
Host smart-a0ed6b60-96a6-4d16-a2e7-d97102d9d4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325040542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1325040542
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2291708586
Short name T1378
Test name
Test status
Simulation time 26637154 ps
CPU time 0.79 seconds
Started May 16 12:31:46 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203620 kb
Host smart-101bc321-4fc1-45e4-98cd-49b677da2b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291708586 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2291708586
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.21521042
Short name T1393
Test name
Test status
Simulation time 19438732 ps
CPU time 0.68 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:04 PM PDT 24
Peak memory 203572 kb
Host smart-809ef97e-a644-47c8-a7cf-c984d14b7d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.21521042
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3826731192
Short name T146
Test name
Test status
Simulation time 239296949 ps
CPU time 1.17 seconds
Started May 16 12:31:36 PM PDT 24
Finished May 16 12:33:06 PM PDT 24
Peak memory 203572 kb
Host smart-e7436422-7d04-4a6b-ba8d-1397bd46848b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826731192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3826731192
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.4161080602
Short name T1379
Test name
Test status
Simulation time 170949146 ps
CPU time 1.06 seconds
Started May 16 12:31:25 PM PDT 24
Finished May 16 12:32:46 PM PDT 24
Peak memory 203512 kb
Host smart-cb5cca77-2b02-43de-8d15-743de786d726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161080602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.4161080602
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2114281283
Short name T191
Test name
Test status
Simulation time 161464747 ps
CPU time 2.34 seconds
Started May 16 12:31:39 PM PDT 24
Finished May 16 12:33:35 PM PDT 24
Peak memory 203724 kb
Host smart-fe3e14b3-4f1e-4267-999f-094d977eb41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114281283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2114281283
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2504842344
Short name T1399
Test name
Test status
Simulation time 78590401 ps
CPU time 0.78 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203636 kb
Host smart-2a09d4ee-e5ac-4f99-84a2-469c2efcef3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504842344 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2504842344
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.325063054
Short name T209
Test name
Test status
Simulation time 20678995 ps
CPU time 0.68 seconds
Started May 16 12:31:42 PM PDT 24
Finished May 16 12:33:28 PM PDT 24
Peak memory 203624 kb
Host smart-8d169578-a082-4873-b10a-456e4840e01f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325063054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.325063054
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3154630075
Short name T1387
Test name
Test status
Simulation time 39979389 ps
CPU time 0.67 seconds
Started May 16 12:31:35 PM PDT 24
Finished May 16 12:33:04 PM PDT 24
Peak memory 203452 kb
Host smart-987d8cfe-9fec-4e94-b841-51ee8b730604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154630075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3154630075
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1410820554
Short name T1441
Test name
Test status
Simulation time 49094735 ps
CPU time 1.09 seconds
Started May 16 12:31:22 PM PDT 24
Finished May 16 12:32:33 PM PDT 24
Peak memory 203524 kb
Host smart-21083bd8-3151-4e75-a3ae-d5a59ac1cf7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410820554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1410820554
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2636274983
Short name T1435
Test name
Test status
Simulation time 447508486 ps
CPU time 1.49 seconds
Started May 16 12:31:33 PM PDT 24
Finished May 16 12:33:01 PM PDT 24
Peak memory 203732 kb
Host smart-ba69bb90-2780-49d2-86ad-288858f1cac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636274983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2636274983
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1737221307
Short name T184
Test name
Test status
Simulation time 92325143 ps
CPU time 1.42 seconds
Started May 16 12:31:37 PM PDT 24
Finished May 16 12:33:10 PM PDT 24
Peak memory 203720 kb
Host smart-bc124815-45eb-4c6f-b5ac-cfd7f8a6e0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737221307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1737221307
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3714755758
Short name T338
Test name
Test status
Simulation time 42659062 ps
CPU time 0.64 seconds
Started May 16 12:44:23 PM PDT 24
Finished May 16 12:44:35 PM PDT 24
Peak memory 204556 kb
Host smart-b10182fd-16cb-4401-88e3-e864952dd999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714755758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3714755758
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2028670214
Short name T1078
Test name
Test status
Simulation time 104117465 ps
CPU time 2.1 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:44:26 PM PDT 24
Peak memory 213280 kb
Host smart-56c9c041-6e2b-4d0c-93ef-6f705b6c8722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028670214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2028670214
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1236963500
Short name T1165
Test name
Test status
Simulation time 408622422 ps
CPU time 6.5 seconds
Started May 16 12:44:13 PM PDT 24
Finished May 16 12:44:29 PM PDT 24
Peak memory 266524 kb
Host smart-33154726-3339-4af9-ba1b-5873c2aa5716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236963500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1236963500
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3450539847
Short name T1196
Test name
Test status
Simulation time 2090441357 ps
CPU time 138.89 seconds
Started May 16 12:44:18 PM PDT 24
Finished May 16 12:46:48 PM PDT 24
Peak memory 665680 kb
Host smart-38954ee3-a49d-41f8-8fce-8f0546b8784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450539847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3450539847
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.965660757
Short name T999
Test name
Test status
Simulation time 44416959055 ps
CPU time 223.04 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:48:09 PM PDT 24
Peak memory 870552 kb
Host smart-9c9c8473-769b-4038-8ad8-7a60929e3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965660757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.965660757
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.917476343
Short name T1167
Test name
Test status
Simulation time 409753331 ps
CPU time 0.88 seconds
Started May 16 12:44:10 PM PDT 24
Finished May 16 12:44:19 PM PDT 24
Peak memory 204628 kb
Host smart-78fc9a74-9115-4231-b992-16539612d6c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917476343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.917476343
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1692044593
Short name T833
Test name
Test status
Simulation time 244632779 ps
CPU time 5.95 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:44:33 PM PDT 24
Peak memory 252916 kb
Host smart-32daf5a2-e403-4c41-aad0-68863b8dbcb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692044593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1692044593
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1667511720
Short name T502
Test name
Test status
Simulation time 59417265053 ps
CPU time 183.73 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 1564636 kb
Host smart-a54915c8-ae21-4df8-9286-964d2aa10dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667511720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1667511720
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2298911965
Short name T291
Test name
Test status
Simulation time 1647808979 ps
CPU time 6.6 seconds
Started May 16 12:44:23 PM PDT 24
Finished May 16 12:44:41 PM PDT 24
Peak memory 205032 kb
Host smart-3678444a-88ff-4384-911f-e57a1b7508b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298911965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2298911965
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.79294937
Short name T137
Test name
Test status
Simulation time 3045184746 ps
CPU time 28.4 seconds
Started May 16 12:44:23 PM PDT 24
Finished May 16 12:45:02 PM PDT 24
Peak memory 367016 kb
Host smart-c749669b-c9d3-4e19-8963-c05e31ebf3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79294937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.79294937
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3384075602
Short name T1229
Test name
Test status
Simulation time 319657704 ps
CPU time 0.66 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:44:26 PM PDT 24
Peak memory 204600 kb
Host smart-e0fda5a0-e182-4f34-81c5-98f7747ce94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384075602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3384075602
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1758758113
Short name T923
Test name
Test status
Simulation time 7465273409 ps
CPU time 107.05 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 222136 kb
Host smart-3cb5cd73-6e9a-4421-838c-099b3c7afccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758758113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1758758113
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3766249002
Short name T689
Test name
Test status
Simulation time 22710742233 ps
CPU time 27.44 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 368016 kb
Host smart-e6fb5b40-ba4c-4c3a-aa67-314d3be060b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766249002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3766249002
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1754368236
Short name T443
Test name
Test status
Simulation time 9388066367 ps
CPU time 854.28 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:58:41 PM PDT 24
Peak memory 1466332 kb
Host smart-da6d426a-1eaa-4df3-a6ce-673cf44b7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754368236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1754368236
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.4132142712
Short name T1035
Test name
Test status
Simulation time 1425077734 ps
CPU time 11.93 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 221216 kb
Host smart-97920dcd-2d64-40a0-b1c1-362c59c1a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132142712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.4132142712
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.942324397
Short name T176
Test name
Test status
Simulation time 148101936 ps
CPU time 0.86 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:44:34 PM PDT 24
Peak memory 222156 kb
Host smart-5917f39f-6c8d-4ee6-b0d5-9b586605b348
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942324397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.942324397
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.803769835
Short name T546
Test name
Test status
Simulation time 10726812162 ps
CPU time 7.11 seconds
Started May 16 12:44:18 PM PDT 24
Finished May 16 12:44:36 PM PDT 24
Peak memory 232196 kb
Host smart-2db65b51-c315-45e1-9960-3e755e8a578e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803769835 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_acq.803769835
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.146943288
Short name T627
Test name
Test status
Simulation time 10364467080 ps
CPU time 12.09 seconds
Started May 16 12:44:12 PM PDT 24
Finished May 16 12:44:33 PM PDT 24
Peak memory 272820 kb
Host smart-b1f712d3-a54a-47b1-8d3b-33eb485ca6f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146943288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.146943288
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3872109173
Short name T361
Test name
Test status
Simulation time 434519583 ps
CPU time 3.19 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:44:36 PM PDT 24
Peak memory 204948 kb
Host smart-37f30500-c945-49d6-8562-dba845ed9f19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872109173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3872109173
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2229511730
Short name T318
Test name
Test status
Simulation time 888669325 ps
CPU time 5.3 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:44:30 PM PDT 24
Peak memory 207520 kb
Host smart-c62a5f89-a9a8-4f2d-9b49-c37cf6739743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229511730 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2229511730
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1325531039
Short name T473
Test name
Test status
Simulation time 13276400834 ps
CPU time 15.44 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:44:42 PM PDT 24
Peak memory 424760 kb
Host smart-78b5d8a0-83e6-440b-94b4-a06194574c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325531039 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1325531039
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.167634701
Short name T756
Test name
Test status
Simulation time 2117074264 ps
CPU time 13.67 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 204912 kb
Host smart-c6995559-ef54-46f6-a37c-77252a44f8ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167634701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.167634701
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3519295240
Short name T282
Test name
Test status
Simulation time 2512125102 ps
CPU time 23.22 seconds
Started May 16 12:44:18 PM PDT 24
Finished May 16 12:44:53 PM PDT 24
Peak memory 204880 kb
Host smart-c6286293-c190-4f78-aa0d-a2e8bfb7ca4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519295240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3519295240
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1727040586
Short name T20
Test name
Test status
Simulation time 41876560559 ps
CPU time 63.11 seconds
Started May 16 12:44:16 PM PDT 24
Finished May 16 12:45:29 PM PDT 24
Peak memory 1039284 kb
Host smart-6409989e-03ee-45ab-9017-d0a07c017316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727040586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1727040586
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.56088434
Short name T796
Test name
Test status
Simulation time 42022035226 ps
CPU time 2375.5 seconds
Started May 16 12:44:15 PM PDT 24
Finished May 16 01:24:00 PM PDT 24
Peak memory 4258620 kb
Host smart-03346d88-8e14-4571-8ebe-4300eb613056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56088434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_stretch.56088434
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.701159153
Short name T912
Test name
Test status
Simulation time 1504485920 ps
CPU time 7.69 seconds
Started May 16 12:44:12 PM PDT 24
Finished May 16 12:44:28 PM PDT 24
Peak memory 213280 kb
Host smart-ef97cf41-f15c-4af3-956c-91f08323e971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701159153 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.701159153
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1284894410
Short name T828
Test name
Test status
Simulation time 17291540 ps
CPU time 0.6 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:44:34 PM PDT 24
Peak memory 204560 kb
Host smart-3fac58d2-5625-4f97-951e-4515c5df3985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284894410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1284894410
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3444394008
Short name T40
Test name
Test status
Simulation time 123668740 ps
CPU time 1.85 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:44:35 PM PDT 24
Peak memory 213284 kb
Host smart-afc61547-13e9-496d-9788-f3e0fc58193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444394008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3444394008
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2317298328
Short name T639
Test name
Test status
Simulation time 2383561363 ps
CPU time 32.08 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:45:06 PM PDT 24
Peak memory 336680 kb
Host smart-6e03d61c-2487-4c9c-9a63-0fa9aded41c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317298328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2317298328
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1970329317
Short name T1037
Test name
Test status
Simulation time 10538156314 ps
CPU time 157.58 seconds
Started May 16 12:44:25 PM PDT 24
Finished May 16 12:47:14 PM PDT 24
Peak memory 684956 kb
Host smart-206bd33c-baed-4353-8b5c-491b6a768375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970329317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1970329317
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.19515529
Short name T630
Test name
Test status
Simulation time 10568327570 ps
CPU time 96.74 seconds
Started May 16 12:44:23 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 839324 kb
Host smart-d2dc6061-89e5-445b-8e0c-968802c814a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19515529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.19515529
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1378660728
Short name T178
Test name
Test status
Simulation time 89842396 ps
CPU time 0.89 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:44:33 PM PDT 24
Peak memory 204728 kb
Host smart-f5e55ddb-0c4b-42f9-b00d-1dabc2ab0883
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378660728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1378660728
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1672374334
Short name T51
Test name
Test status
Simulation time 1062416472 ps
CPU time 4.73 seconds
Started May 16 12:44:20 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 239012 kb
Host smart-a0910598-5899-41b2-80ff-278cbe8111b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672374334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1672374334
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2341710567
Short name T839
Test name
Test status
Simulation time 31773788108 ps
CPU time 136.38 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:47:03 PM PDT 24
Peak memory 1230616 kb
Host smart-6d5f30b5-13ce-4d98-a765-51bf86c0ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341710567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2341710567
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2979061400
Short name T897
Test name
Test status
Simulation time 1006500094 ps
CPU time 8.15 seconds
Started May 16 12:44:24 PM PDT 24
Finished May 16 12:44:43 PM PDT 24
Peak memory 204976 kb
Host smart-90ad10c5-e223-428c-b17e-5c261721d80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979061400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2979061400
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.342638622
Short name T951
Test name
Test status
Simulation time 1018820644 ps
CPU time 44.6 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:45:31 PM PDT 24
Peak memory 302160 kb
Host smart-cd1986e6-466e-48fb-8c32-aefeb767c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342638622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.342638622
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1853011349
Short name T567
Test name
Test status
Simulation time 26028274 ps
CPU time 0.73 seconds
Started May 16 12:44:26 PM PDT 24
Finished May 16 12:44:38 PM PDT 24
Peak memory 204608 kb
Host smart-10ad2ccf-2279-4c3c-bd17-9dbbd68cf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853011349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1853011349
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.4012170208
Short name T404
Test name
Test status
Simulation time 26501226855 ps
CPU time 1060.84 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 01:02:15 PM PDT 24
Peak memory 214572 kb
Host smart-dac9a273-b783-4e55-8f15-702b5a7321f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012170208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.4012170208
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.118583239
Short name T58
Test name
Test status
Simulation time 5413753235 ps
CPU time 65.6 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:45:39 PM PDT 24
Peak memory 348328 kb
Host smart-40714a02-0088-4a80-a373-788b3e1cfacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118583239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.118583239
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1856666408
Short name T985
Test name
Test status
Simulation time 18202589593 ps
CPU time 1903.92 seconds
Started May 16 12:44:20 PM PDT 24
Finished May 16 01:16:16 PM PDT 24
Peak memory 1999004 kb
Host smart-e612369a-4da2-4578-9a42-dd5ef3a6decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856666408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1856666408
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.8015538
Short name T917
Test name
Test status
Simulation time 8184450083 ps
CPU time 9.69 seconds
Started May 16 12:44:20 PM PDT 24
Finished May 16 12:44:41 PM PDT 24
Peak memory 213240 kb
Host smart-5d1219ef-ddb9-4fe1-b60c-8d6b397f0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8015538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.8015538
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3029250872
Short name T272
Test name
Test status
Simulation time 797191764 ps
CPU time 3.88 seconds
Started May 16 12:44:25 PM PDT 24
Finished May 16 12:44:39 PM PDT 24
Peak memory 204692 kb
Host smart-ab073a3c-e308-4f34-aaf9-2c43a5f17604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029250872 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3029250872
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.4044666318
Short name T1290
Test name
Test status
Simulation time 10307527559 ps
CPU time 14.63 seconds
Started May 16 12:44:26 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 270528 kb
Host smart-80f45ddc-1f23-4b90-a15b-89a83ccf7c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044666318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.4044666318
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.520304430
Short name T116
Test name
Test status
Simulation time 10290239661 ps
CPU time 15.56 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:44:48 PM PDT 24
Peak memory 294620 kb
Host smart-c705021c-6e59-447b-b319-72612bc74eb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520304430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.520304430
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3005523003
Short name T16
Test name
Test status
Simulation time 1772784664 ps
CPU time 9.08 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:44:43 PM PDT 24
Peak memory 213664 kb
Host smart-84758731-4b8c-45ef-8429-dd59fbf7037d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005523003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3005523003
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.594288052
Short name T1019
Test name
Test status
Simulation time 1134236687 ps
CPU time 2.96 seconds
Started May 16 12:44:23 PM PDT 24
Finished May 16 12:44:37 PM PDT 24
Peak memory 205392 kb
Host smart-ddae5996-7558-406c-8b14-f28ad6d43e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594288052 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.594288052
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3357228398
Short name T836
Test name
Test status
Simulation time 428947171 ps
CPU time 2.93 seconds
Started May 16 12:44:27 PM PDT 24
Finished May 16 12:44:40 PM PDT 24
Peak memory 204972 kb
Host smart-06336584-d8d7-4b7d-b5d2-f7474a0e45c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357228398 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3357228398
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.735568862
Short name T903
Test name
Test status
Simulation time 5295417898 ps
CPU time 4.01 seconds
Started May 16 12:44:26 PM PDT 24
Finished May 16 12:44:41 PM PDT 24
Peak memory 205040 kb
Host smart-d91cbb3d-fc9b-4998-a3c3-1bbc0a5465c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735568862 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.735568862
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2443173605
Short name T597
Test name
Test status
Simulation time 1062771364 ps
CPU time 44.36 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 204988 kb
Host smart-a628932d-cf1b-47f9-8789-cf108f46f513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443173605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2443173605
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.420250013
Short name T574
Test name
Test status
Simulation time 1763345504 ps
CPU time 12.73 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:44:46 PM PDT 24
Peak memory 204980 kb
Host smart-3925409f-e246-43e4-b03e-c1ddb1f1a16d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420250013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.420250013
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.943744404
Short name T601
Test name
Test status
Simulation time 7310816840 ps
CPU time 13.19 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:44:46 PM PDT 24
Peak memory 204984 kb
Host smart-2ed91930-7644-4581-a9a3-5ea36f06cd56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943744404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.943744404
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1583053472
Short name T394
Test name
Test status
Simulation time 1218542896 ps
CPU time 7.2 seconds
Started May 16 12:44:21 PM PDT 24
Finished May 16 12:44:40 PM PDT 24
Peak memory 218056 kb
Host smart-0c3dd846-d019-4049-abe7-71d1be0b9fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583053472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1583053472
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3175070655
Short name T1277
Test name
Test status
Simulation time 18112447 ps
CPU time 0.63 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:45:36 PM PDT 24
Peak memory 204548 kb
Host smart-0ab7c620-5ee9-4deb-a1c9-4712e6d100dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175070655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3175070655
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2296049828
Short name T1015
Test name
Test status
Simulation time 348789715 ps
CPU time 1.32 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:45:37 PM PDT 24
Peak memory 213336 kb
Host smart-04422aca-61e2-4e99-b4ac-b0c3c87c8890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296049828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2296049828
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3997679813
Short name T741
Test name
Test status
Simulation time 899726471 ps
CPU time 8.15 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:45:42 PM PDT 24
Peak memory 292956 kb
Host smart-23a87c09-b46e-4f5c-9ff0-5e1fb14c449b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997679813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3997679813
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.4265556363
Short name T90
Test name
Test status
Simulation time 9201773057 ps
CPU time 64.36 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:46:41 PM PDT 24
Peak memory 555876 kb
Host smart-37276e22-f790-4722-abba-80e5742133c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265556363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.4265556363
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.256428553
Short name T744
Test name
Test status
Simulation time 2566582332 ps
CPU time 202.25 seconds
Started May 16 12:45:06 PM PDT 24
Finished May 16 12:48:57 PM PDT 24
Peak memory 824808 kb
Host smart-eb0a1c03-30db-4d05-bbbc-67f752cd22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256428553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.256428553
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3332235644
Short name T1346
Test name
Test status
Simulation time 805104932 ps
CPU time 0.81 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:45:42 PM PDT 24
Peak memory 204672 kb
Host smart-2736abae-2264-4f58-b819-18ad858e6118
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332235644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3332235644
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.185590639
Short name T397
Test name
Test status
Simulation time 446894138 ps
CPU time 2.62 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:45:40 PM PDT 24
Peak memory 204940 kb
Host smart-6277c972-57ba-4bf3-91b6-c1982ff122e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185590639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
185590639
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.852794703
Short name T1214
Test name
Test status
Simulation time 26767166777 ps
CPU time 373.21 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:51:45 PM PDT 24
Peak memory 1339144 kb
Host smart-5ede6ac4-7f87-4d7d-ba45-9423cb4877f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852794703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.852794703
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.743830631
Short name T238
Test name
Test status
Simulation time 529201728 ps
CPU time 6.43 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:45:43 PM PDT 24
Peak memory 204956 kb
Host smart-6daface7-7381-4c5a-bb49-95e7fd69e5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743830631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.743830631
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3397134902
Short name T1071
Test name
Test status
Simulation time 2524419477 ps
CPU time 23.01 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 269432 kb
Host smart-9539e774-e717-4869-90c4-52ab4ef09c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397134902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3397134902
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2095659149
Short name T131
Test name
Test status
Simulation time 44704799 ps
CPU time 0.65 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:45:34 PM PDT 24
Peak memory 204660 kb
Host smart-eda280ab-1a1e-4b7a-843f-97d793f9a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095659149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2095659149
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3334216006
Short name T1238
Test name
Test status
Simulation time 26251264714 ps
CPU time 838.62 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:59:40 PM PDT 24
Peak memory 2138948 kb
Host smart-da64e0cc-3d01-476f-861d-c8a7b1ea21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334216006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3334216006
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1959752287
Short name T667
Test name
Test status
Simulation time 1836909383 ps
CPU time 31.66 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 365500 kb
Host smart-447f03f9-fa64-465c-82c8-35ae08f34b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959752287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1959752287
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2628393897
Short name T302
Test name
Test status
Simulation time 2224805217 ps
CPU time 26.84 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 213320 kb
Host smart-117a0753-5d69-4dae-8954-90bad7f95ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628393897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2628393897
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.4239037900
Short name T948
Test name
Test status
Simulation time 924065064 ps
CPU time 4.86 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:45:36 PM PDT 24
Peak memory 213124 kb
Host smart-1cd398a9-2250-46d9-80ac-13ab6ea3a10d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239037900 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.4239037900
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.4029096635
Short name T1254
Test name
Test status
Simulation time 10391602407 ps
CPU time 14.34 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 264004 kb
Host smart-b38d8083-928c-4af9-89ce-180844ab55e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029096635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.4029096635
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.333159735
Short name T356
Test name
Test status
Simulation time 10152444737 ps
CPU time 31.14 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:46:06 PM PDT 24
Peak memory 347788 kb
Host smart-56ec2cf7-d082-4270-98c5-2d5e191393dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333159735 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.333159735
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3612036258
Short name T566
Test name
Test status
Simulation time 355867760 ps
CPU time 2.48 seconds
Started May 16 12:45:02 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 205060 kb
Host smart-36b0fc3b-374c-4ef9-844f-48118eae9e0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612036258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3612036258
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.4137975387
Short name T889
Test name
Test status
Simulation time 4060426094 ps
CPU time 5.49 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:45:37 PM PDT 24
Peak memory 211124 kb
Host smart-48d669ca-4dd7-4d86-94a5-4129629ae8c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137975387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.4137975387
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.907482757
Short name T411
Test name
Test status
Simulation time 11291631618 ps
CPU time 180.31 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 2735084 kb
Host smart-ba0f514b-9e9b-4629-9863-c44c3dfcebe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907482757 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.907482757
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.4118796278
Short name T561
Test name
Test status
Simulation time 4355771645 ps
CPU time 11.52 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:45:44 PM PDT 24
Peak memory 205048 kb
Host smart-902b3e07-8f63-47e7-9963-dfcf45c2115e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118796278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.4118796278
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2177238564
Short name T1115
Test name
Test status
Simulation time 8665123635 ps
CPU time 21.09 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:45:54 PM PDT 24
Peak memory 230360 kb
Host smart-3ba58f23-a08d-4f04-8ac8-90da126c1bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177238564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2177238564
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2384364504
Short name T408
Test name
Test status
Simulation time 65220257665 ps
CPU time 2307.96 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 01:24:10 PM PDT 24
Peak memory 11179732 kb
Host smart-da4d8495-fcc2-4497-a743-b1f86e94e6e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384364504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2384364504
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2686246615
Short name T867
Test name
Test status
Simulation time 27029782209 ps
CPU time 459.34 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:53:17 PM PDT 24
Peak memory 3101012 kb
Host smart-69baa90f-ea2f-49ef-bf49-d2f9ec170de9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686246615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2686246615
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3795510073
Short name T1186
Test name
Test status
Simulation time 1240809782 ps
CPU time 7.13 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:45:49 PM PDT 24
Peak memory 221148 kb
Host smart-e1c73f91-220f-49a6-a6c8-b1a39e6015d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795510073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3795510073
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3618697474
Short name T171
Test name
Test status
Simulation time 69319883 ps
CPU time 0.58 seconds
Started May 16 12:45:17 PM PDT 24
Finished May 16 12:45:46 PM PDT 24
Peak memory 204472 kb
Host smart-f774e1c4-869f-48f7-9dbe-27c16f0fe8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618697474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3618697474
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1693976342
Short name T784
Test name
Test status
Simulation time 152472237 ps
CPU time 3.29 seconds
Started May 16 12:45:10 PM PDT 24
Finished May 16 12:45:42 PM PDT 24
Peak memory 234084 kb
Host smart-5a9be109-4558-4f24-99ac-88c9f2c349a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693976342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1693976342
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2969934401
Short name T922
Test name
Test status
Simulation time 1420985618 ps
CPU time 18.71 seconds
Started May 16 12:45:06 PM PDT 24
Finished May 16 12:45:53 PM PDT 24
Peak memory 284496 kb
Host smart-cce8afb7-04f5-41dd-a17e-bf5ee1632747
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969934401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2969934401
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2541126025
Short name T684
Test name
Test status
Simulation time 4638795612 ps
CPU time 175.24 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:48:35 PM PDT 24
Peak memory 749948 kb
Host smart-3f0da486-9458-40e9-a257-e951188e5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541126025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2541126025
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.27853300
Short name T1130
Test name
Test status
Simulation time 6513821045 ps
CPU time 111.62 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:47:29 PM PDT 24
Peak memory 577452 kb
Host smart-cbf78413-fc16-4e37-b224-1acfcdac7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27853300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.27853300
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2583399109
Short name T59
Test name
Test status
Simulation time 168735318 ps
CPU time 1 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:45:34 PM PDT 24
Peak memory 204648 kb
Host smart-48b5a3f4-04ec-4172-bab1-bbd32229a7df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583399109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2583399109
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3291779603
Short name T904
Test name
Test status
Simulation time 505242553 ps
CPU time 7.58 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:45:40 PM PDT 24
Peak memory 204832 kb
Host smart-08cd2b50-483f-490b-a893-d2bab38fd699
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291779603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3291779603
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3118425671
Short name T1323
Test name
Test status
Simulation time 3967294189 ps
CPU time 113.66 seconds
Started May 16 12:45:06 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 1116180 kb
Host smart-f65597ee-2eed-47fd-b22f-0551ab6991a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118425671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3118425671
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2226283794
Short name T959
Test name
Test status
Simulation time 1583991931 ps
CPU time 4.74 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:45:39 PM PDT 24
Peak memory 204936 kb
Host smart-32c6267a-bfd4-4f73-914f-a07f86552f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226283794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2226283794
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.2617442692
Short name T343
Test name
Test status
Simulation time 10411011121 ps
CPU time 141.55 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 562736 kb
Host smart-059022a9-faf3-4c45-b392-efdf88fa62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617442692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2617442692
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3327291717
Short name T129
Test name
Test status
Simulation time 86656486 ps
CPU time 0.64 seconds
Started May 16 12:45:05 PM PDT 24
Finished May 16 12:45:34 PM PDT 24
Peak memory 204672 kb
Host smart-2811e251-0a91-4d9c-b46f-d9521a3deeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327291717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3327291717
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3807048772
Short name T223
Test name
Test status
Simulation time 6071597067 ps
CPU time 28.35 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:46:08 PM PDT 24
Peak memory 411596 kb
Host smart-9facb863-d10d-4f5d-a2ee-b6257fdba55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807048772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3807048772
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3543308987
Short name T1127
Test name
Test status
Simulation time 4802916014 ps
CPU time 50.46 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:46:32 PM PDT 24
Peak memory 245840 kb
Host smart-ef1e4f20-07c0-4d8d-b1e0-2efb23f4e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543308987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3543308987
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2348488729
Short name T683
Test name
Test status
Simulation time 805341181 ps
CPU time 15.32 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 218004 kb
Host smart-683d2e18-a19a-4b00-9418-b20a45b48bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348488729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2348488729
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1643551357
Short name T249
Test name
Test status
Simulation time 711791332 ps
CPU time 3.53 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:45:43 PM PDT 24
Peak memory 204988 kb
Host smart-263fd99f-d4ef-41f5-bd4c-eacc2cc3ad65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643551357 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1643551357
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.4011948294
Short name T1179
Test name
Test status
Simulation time 10151948107 ps
CPU time 13.46 seconds
Started May 16 12:45:17 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 253760 kb
Host smart-6ede4dbc-de6c-44d3-868a-455c44865eba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011948294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.4011948294
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3755438893
Short name T152
Test name
Test status
Simulation time 10233940151 ps
CPU time 15.14 seconds
Started May 16 12:45:08 PM PDT 24
Finished May 16 12:45:52 PM PDT 24
Peak memory 299736 kb
Host smart-9a148bf7-c75f-4bdd-8f52-6f68df9069c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755438893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3755438893
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1561742119
Short name T23
Test name
Test status
Simulation time 869013724 ps
CPU time 2.77 seconds
Started May 16 12:45:17 PM PDT 24
Finished May 16 12:45:48 PM PDT 24
Peak memory 204768 kb
Host smart-b4933ca5-8748-401d-a454-2ebc41451438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561742119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1561742119
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3386622311
Short name T268
Test name
Test status
Simulation time 2760413793 ps
CPU time 7.83 seconds
Started May 16 12:45:10 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 218784 kb
Host smart-5d48c8a6-5b78-4a7b-86e8-86cb2d656273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386622311 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3386622311
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.752055468
Short name T536
Test name
Test status
Simulation time 22142591513 ps
CPU time 8.52 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:45:50 PM PDT 24
Peak memory 345900 kb
Host smart-4ed224f2-5b62-4fc8-88e5-80eb3c61fa1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752055468 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.752055468
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2518170612
Short name T864
Test name
Test status
Simulation time 1563210577 ps
CPU time 30.15 seconds
Started May 16 12:45:16 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 204776 kb
Host smart-f7935a23-a077-4a08-88b8-ac4e68615323
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518170612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2518170612
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3639475634
Short name T895
Test name
Test status
Simulation time 3520779619 ps
CPU time 15.52 seconds
Started May 16 12:45:10 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 218032 kb
Host smart-4619384d-d8fe-49b3-8853-e15576eae22b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639475634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3639475634
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.706101576
Short name T292
Test name
Test status
Simulation time 38158053620 ps
CPU time 66.15 seconds
Started May 16 12:45:18 PM PDT 24
Finished May 16 12:46:52 PM PDT 24
Peak memory 1169368 kb
Host smart-7d742392-af4b-4c25-938f-77b02782607f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706101576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.706101576
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3976987102
Short name T485
Test name
Test status
Simulation time 16977501718 ps
CPU time 100.6 seconds
Started May 16 12:45:10 PM PDT 24
Finished May 16 12:47:20 PM PDT 24
Peak memory 997024 kb
Host smart-9392fb3f-b15d-48c0-914c-f10cef768eab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976987102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3976987102
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.214679883
Short name T783
Test name
Test status
Simulation time 4733368079 ps
CPU time 7.49 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 221384 kb
Host smart-53de767a-26ba-488f-84fc-5e0e18f510dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214679883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.214679883
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.664193357
Short name T1036
Test name
Test status
Simulation time 50951562 ps
CPU time 0.6 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 12:45:49 PM PDT 24
Peak memory 204516 kb
Host smart-6ae9c40c-1f9e-438c-8fca-01aa737b693c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664193357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.664193357
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3271077656
Short name T54
Test name
Test status
Simulation time 825484371 ps
CPU time 2.38 seconds
Started May 16 12:45:15 PM PDT 24
Finished May 16 12:45:45 PM PDT 24
Peak memory 229164 kb
Host smart-d069b9b0-bdb6-42f3-87b9-2d071302c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271077656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3271077656
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.154442734
Short name T732
Test name
Test status
Simulation time 1891864952 ps
CPU time 5.74 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 264640 kb
Host smart-df406ac8-8c4b-471a-9fc8-1ed86fb1fc8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154442734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.154442734
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.550666909
Short name T1026
Test name
Test status
Simulation time 4898253318 ps
CPU time 170.21 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:48:32 PM PDT 24
Peak memory 714588 kb
Host smart-b309833f-d144-4fdd-a22a-6ddc9af30801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550666909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.550666909
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.953152428
Short name T832
Test name
Test status
Simulation time 1980068426 ps
CPU time 68.1 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:46:49 PM PDT 24
Peak memory 695036 kb
Host smart-672e1a89-0faf-4617-8f09-c3a344e2be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953152428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.953152428
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3295570521
Short name T1226
Test name
Test status
Simulation time 122900404 ps
CPU time 0.92 seconds
Started May 16 12:45:28 PM PDT 24
Finished May 16 12:45:54 PM PDT 24
Peak memory 204256 kb
Host smart-98b5523f-2cc0-4486-bb16-a810593eb35c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295570521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3295570521
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.79371867
Short name T315
Test name
Test status
Simulation time 116427540 ps
CPU time 2.42 seconds
Started May 16 12:45:30 PM PDT 24
Finished May 16 12:45:57 PM PDT 24
Peak memory 204532 kb
Host smart-ad3d9008-b1e8-49d1-8961-b967cb7bb3da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79371867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.79371867
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3432219192
Short name T256
Test name
Test status
Simulation time 3072225681 ps
CPU time 215.81 seconds
Started May 16 12:45:14 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 966708 kb
Host smart-5b69b249-559c-4e5d-bf97-2b584aef5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432219192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3432219192
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_override.2305736836
Short name T1047
Test name
Test status
Simulation time 118312862 ps
CPU time 0.64 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:45:41 PM PDT 24
Peak memory 204676 kb
Host smart-a8da8be4-6ec5-422c-b0a3-779a5793818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305736836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2305736836
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2958674892
Short name T63
Test name
Test status
Simulation time 7430581308 ps
CPU time 318.62 seconds
Started May 16 12:45:28 PM PDT 24
Finished May 16 12:51:12 PM PDT 24
Peak memory 594396 kb
Host smart-e314edb5-dc86-41b4-b78e-807a471ed7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958674892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2958674892
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.358121983
Short name T608
Test name
Test status
Simulation time 12086698307 ps
CPU time 31.73 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 371720 kb
Host smart-53956d11-0019-434f-8197-5751418755fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358121983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.358121983
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.266839175
Short name T67
Test name
Test status
Simulation time 986559689 ps
CPU time 44.19 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 213076 kb
Host smart-6bd33333-aa3e-4756-8450-bd2cd86a8a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266839175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.266839175
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1641399778
Short name T323
Test name
Test status
Simulation time 1718720533 ps
CPU time 4.53 seconds
Started May 16 12:45:28 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 212696 kb
Host smart-1ee0e6c2-32a7-4fc9-9bcb-dace9508648d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641399778 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1641399778
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1463829837
Short name T155
Test name
Test status
Simulation time 10172792951 ps
CPU time 13.12 seconds
Started May 16 12:45:13 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 259700 kb
Host smart-0a1ca02e-8fd2-4201-9d44-08068317fdcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463829837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1463829837
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2600723100
Short name T457
Test name
Test status
Simulation time 10213008718 ps
CPU time 15.86 seconds
Started May 16 12:45:28 PM PDT 24
Finished May 16 12:46:10 PM PDT 24
Peak memory 302012 kb
Host smart-2533af8e-06d0-4e61-86d9-3a468dc5497e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600723100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2600723100
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3302218354
Short name T1140
Test name
Test status
Simulation time 1167803385 ps
CPU time 2.28 seconds
Started May 16 12:45:11 PM PDT 24
Finished May 16 12:45:42 PM PDT 24
Peak memory 205048 kb
Host smart-bafa1a43-65c3-42d5-89be-eca0d25bb505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302218354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3302218354
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2932345640
Short name T729
Test name
Test status
Simulation time 748146644 ps
CPU time 4.14 seconds
Started May 16 12:45:29 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 204456 kb
Host smart-4c945f6e-c892-4d36-8183-7b5110a73385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932345640 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2932345640
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1096904163
Short name T1319
Test name
Test status
Simulation time 3198545469 ps
CPU time 24.36 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:46:05 PM PDT 24
Peak memory 881196 kb
Host smart-42a4598d-5e7f-4216-ad5b-b3d9301d6658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096904163 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1096904163
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2758159797
Short name T359
Test name
Test status
Simulation time 7822949931 ps
CPU time 36.24 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:46:18 PM PDT 24
Peak memory 205008 kb
Host smart-955ed9ba-2549-4f1d-9697-8f6f9ad788fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758159797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2758159797
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1995000459
Short name T244
Test name
Test status
Simulation time 1688772161 ps
CPU time 29.06 seconds
Started May 16 12:45:28 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 222380 kb
Host smart-b8af9caa-6a6a-4c29-bbc8-14efa739a3f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995000459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1995000459
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3269377455
Short name T471
Test name
Test status
Simulation time 7619217254 ps
CPU time 259.62 seconds
Started May 16 12:45:12 PM PDT 24
Finished May 16 12:50:01 PM PDT 24
Peak memory 1942872 kb
Host smart-f0b96701-d5bf-4977-8d25-f9873045effc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269377455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3269377455
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3407219476
Short name T351
Test name
Test status
Simulation time 1754573000 ps
CPU time 8.28 seconds
Started May 16 12:45:27 PM PDT 24
Finished May 16 12:46:01 PM PDT 24
Peak memory 219656 kb
Host smart-83e8420c-5eff-4c3a-a113-57c4e2e94e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407219476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3407219476
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.887301751
Short name T382
Test name
Test status
Simulation time 18033847 ps
CPU time 0.64 seconds
Started May 16 12:45:35 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 204524 kb
Host smart-38f63031-a93f-4b9f-b615-2c53dca20db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887301751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.887301751
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.845839343
Short name T558
Test name
Test status
Simulation time 587463780 ps
CPU time 29.97 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:46:18 PM PDT 24
Peak memory 294964 kb
Host smart-9c94bf45-e8a4-41d2-a866-2126d0270185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845839343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.845839343
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.804327695
Short name T862
Test name
Test status
Simulation time 8962575089 ps
CPU time 64.46 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:46:54 PM PDT 24
Peak memory 673080 kb
Host smart-f8bfb2cb-4972-4abf-bd79-55fec336a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804327695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.804327695
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.669448080
Short name T919
Test name
Test status
Simulation time 1797773041 ps
CPU time 132.37 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 12:48:01 PM PDT 24
Peak memory 649148 kb
Host smart-ee2115df-9c89-4e0d-a540-3adc8e96eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669448080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.669448080
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2973070034
Short name T859
Test name
Test status
Simulation time 96184745 ps
CPU time 0.98 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:45:50 PM PDT 24
Peak memory 204680 kb
Host smart-8f2a79f1-496a-4f6b-b532-cbda17abcced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973070034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2973070034
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3576785725
Short name T526
Test name
Test status
Simulation time 1363631671 ps
CPU time 11.35 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 241728 kb
Host smart-cebddde7-8beb-4d2e-9668-e7808baa8502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576785725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3576785725
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1282247639
Short name T1147
Test name
Test status
Simulation time 10750238832 ps
CPU time 173.51 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 1519460 kb
Host smart-8cd11992-a84b-49e7-bd5d-da59ca94ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282247639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1282247639
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.261419431
Short name T281
Test name
Test status
Simulation time 3254726091 ps
CPU time 12.71 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:46:10 PM PDT 24
Peak memory 205120 kb
Host smart-ef7d48a4-bbf8-4218-b174-b0316078969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261419431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.261419431
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2656078636
Short name T1065
Test name
Test status
Simulation time 1172792846 ps
CPU time 22.02 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:46:19 PM PDT 24
Peak memory 289124 kb
Host smart-15fbcf2d-45f9-4b4e-9ae6-c6f0b821abd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656078636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2656078636
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1326839130
Short name T133
Test name
Test status
Simulation time 53091724 ps
CPU time 0.65 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:45:49 PM PDT 24
Peak memory 204604 kb
Host smart-79e39205-bc6d-4a69-b92f-b87f3c017236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326839130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1326839130
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3640448018
Short name T700
Test name
Test status
Simulation time 6574596322 ps
CPU time 66.42 seconds
Started May 16 12:45:25 PM PDT 24
Finished May 16 12:46:57 PM PDT 24
Peak memory 205020 kb
Host smart-e3133217-1d8b-4e72-901d-d2c40d400e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640448018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3640448018
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2127548262
Short name T507
Test name
Test status
Simulation time 1417905091 ps
CPU time 61.41 seconds
Started May 16 12:45:29 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 375372 kb
Host smart-557fec64-c60e-428a-8eac-f6d2a899ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127548262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2127548262
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1105111126
Short name T592
Test name
Test status
Simulation time 13621673475 ps
CPU time 926.19 seconds
Started May 16 12:45:25 PM PDT 24
Finished May 16 01:01:17 PM PDT 24
Peak memory 2532664 kb
Host smart-298b911d-ebac-440b-88f3-8a8908cd4785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105111126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1105111126
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.567595840
Short name T1100
Test name
Test status
Simulation time 1320950617 ps
CPU time 10.57 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 219936 kb
Host smart-5b2d30f8-e778-4871-a6f5-5b651e6b8fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567595840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.567595840
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1431938577
Short name T656
Test name
Test status
Simulation time 1071382704 ps
CPU time 5.35 seconds
Started May 16 12:45:25 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 213328 kb
Host smart-e28c1c89-0838-4652-84c6-7ff4cb832745
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431938577 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1431938577
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3533318848
Short name T381
Test name
Test status
Simulation time 10098397637 ps
CPU time 32.64 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 312840 kb
Host smart-a94f061f-f154-4872-9483-c35ed201eeba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533318848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3533318848
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3516664391
Short name T330
Test name
Test status
Simulation time 10080153534 ps
CPU time 66.77 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 447112 kb
Host smart-0776a64f-c9a0-4a50-a1be-2641209d846d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516664391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3516664391
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1390468808
Short name T1321
Test name
Test status
Simulation time 1670914062 ps
CPU time 2.58 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:45:51 PM PDT 24
Peak memory 204904 kb
Host smart-f3806467-2a83-467a-889e-7669055ef2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390468808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1390468808
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3852767898
Short name T958
Test name
Test status
Simulation time 1761125084 ps
CPU time 4.7 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 12:45:53 PM PDT 24
Peak memory 204928 kb
Host smart-d9d3d617-ac88-4f4e-8269-2b6ee67ee870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852767898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3852767898
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3947755010
Short name T613
Test name
Test status
Simulation time 14729094114 ps
CPU time 6 seconds
Started May 16 12:45:25 PM PDT 24
Finished May 16 12:45:57 PM PDT 24
Peak memory 295616 kb
Host smart-2badb408-6293-48f5-a9f2-1ae17aa73af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947755010 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3947755010
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.933578034
Short name T663
Test name
Test status
Simulation time 10684574366 ps
CPU time 9.3 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 205052 kb
Host smart-8f327b80-94ae-43d4-ba12-89df1315203e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933578034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.933578034
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.144856117
Short name T603
Test name
Test status
Simulation time 2157688720 ps
CPU time 9.3 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 207008 kb
Host smart-57856580-5fa4-4153-8e66-238382259b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144856117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.144856117
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.690485619
Short name T390
Test name
Test status
Simulation time 45188101539 ps
CPU time 844.88 seconds
Started May 16 12:45:22 PM PDT 24
Finished May 16 12:59:53 PM PDT 24
Peak memory 6286252 kb
Host smart-2a08de7d-1da1-4e84-ba74-4191943292ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690485619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.690485619
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.690339589
Short name T1300
Test name
Test status
Simulation time 16524905287 ps
CPU time 1089.05 seconds
Started May 16 12:45:23 PM PDT 24
Finished May 16 01:03:58 PM PDT 24
Peak memory 4005724 kb
Host smart-098551ca-786e-4261-9d4f-0fe3f7b9c4e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690339589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.690339589
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1924450421
Short name T759
Test name
Test status
Simulation time 1275624207 ps
CPU time 7.09 seconds
Started May 16 12:45:24 PM PDT 24
Finished May 16 12:45:57 PM PDT 24
Peak memory 204984 kb
Host smart-739ced75-5c15-40f8-afdd-62cad39e2643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924450421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1924450421
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.4213951142
Short name T549
Test name
Test status
Simulation time 15815777 ps
CPU time 0.61 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 204572 kb
Host smart-b7263615-025b-455d-98e6-ba5762341c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213951142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.4213951142
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3866318571
Short name T1096
Test name
Test status
Simulation time 49540575 ps
CPU time 1.23 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 213184 kb
Host smart-b7850011-93bd-4e1a-97d1-294db112344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866318571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3866318571
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1790451707
Short name T518
Test name
Test status
Simulation time 1129548520 ps
CPU time 14.54 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 262616 kb
Host smart-0c671025-25b5-4678-ba9f-79b750b1f963
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790451707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1790451707
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2826880063
Short name T579
Test name
Test status
Simulation time 7846699209 ps
CPU time 45.54 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:46:43 PM PDT 24
Peak memory 283852 kb
Host smart-0e006551-2870-49e8-b6a3-24f5392d804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826880063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2826880063
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.440377268
Short name T358
Test name
Test status
Simulation time 2358391360 ps
CPU time 69.08 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:47:06 PM PDT 24
Peak memory 753552 kb
Host smart-0810452f-a505-4df1-aa9d-b19f2f36dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440377268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.440377268
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1732597080
Short name T61
Test name
Test status
Simulation time 114188036 ps
CPU time 0.92 seconds
Started May 16 12:45:34 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 204780 kb
Host smart-17e94887-065c-4c0f-af0b-95cd9b9da2ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732597080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1732597080
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1957960589
Short name T1224
Test name
Test status
Simulation time 464445065 ps
CPU time 5.01 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:46:02 PM PDT 24
Peak memory 204912 kb
Host smart-db89c80f-b846-4ab2-a9da-bd31b1102323
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957960589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1957960589
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.741702853
Short name T1297
Test name
Test status
Simulation time 3127437889 ps
CPU time 219.7 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:49:36 PM PDT 24
Peak memory 967472 kb
Host smart-a1e0edc1-b2f5-4ac0-b8f3-b30378445efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741702853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.741702853
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.256592460
Short name T424
Test name
Test status
Simulation time 2212342717 ps
CPU time 20.26 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:20 PM PDT 24
Peak memory 205104 kb
Host smart-ad8a12c3-c821-49e2-ac4d-bf1efc01ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256592460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.256592460
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.252661107
Short name T1045
Test name
Test status
Simulation time 9149659092 ps
CPU time 60.67 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:46:58 PM PDT 24
Peak memory 320236 kb
Host smart-f1ead4a1-2a6a-4d1e-a68d-ed84be3d8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252661107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.252661107
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.2100210423
Short name T685
Test name
Test status
Simulation time 86283165 ps
CPU time 0.65 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 204680 kb
Host smart-f358e049-4c02-4d40-b629-9aae99406d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100210423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2100210423
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1999937205
Short name T528
Test name
Test status
Simulation time 6762208342 ps
CPU time 389.73 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:52:27 PM PDT 24
Peak memory 832308 kb
Host smart-24ca856e-b159-46e2-acb1-8a70ff6470f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999937205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1999937205
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.471551123
Short name T610
Test name
Test status
Simulation time 1461076241 ps
CPU time 74.42 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 375720 kb
Host smart-dc07c235-642e-4fbf-a835-d2e91260b410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471551123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.471551123
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3100500643
Short name T1124
Test name
Test status
Simulation time 2074188440 ps
CPU time 8.39 seconds
Started May 16 12:45:34 PM PDT 24
Finished May 16 12:46:07 PM PDT 24
Peak memory 213088 kb
Host smart-5b84cf64-e9a4-417e-a950-f46cb199262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100500643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3100500643
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.938027180
Short name T551
Test name
Test status
Simulation time 1936241914 ps
CPU time 2.93 seconds
Started May 16 12:45:38 PM PDT 24
Finished May 16 12:46:05 PM PDT 24
Peak memory 204908 kb
Host smart-38bb227e-2999-467b-aea7-3587953c195c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938027180 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.938027180
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2656372176
Short name T1203
Test name
Test status
Simulation time 10066914876 ps
CPU time 63.42 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:47:01 PM PDT 24
Peak memory 493276 kb
Host smart-dcb45797-0d29-4efb-885f-43b2f32efd7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656372176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2656372176
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.825470468
Short name T835
Test name
Test status
Simulation time 481848018 ps
CPU time 3.03 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:03 PM PDT 24
Peak memory 204968 kb
Host smart-21e22447-158c-492f-96e0-8a74c709927d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825470468 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.825470468
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.4096322963
Short name T475
Test name
Test status
Simulation time 2516348369 ps
CPU time 6.23 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:46:03 PM PDT 24
Peak memory 204980 kb
Host smart-f68dbda5-0b1f-4247-8ca7-89d2d3ec9a1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096322963 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.4096322963
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1489644078
Short name T790
Test name
Test status
Simulation time 19293652656 ps
CPU time 113.15 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 1599800 kb
Host smart-d14fde0e-44e9-4192-b8c3-822fb2c8c805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489644078 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1489644078
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.620577531
Short name T416
Test name
Test status
Simulation time 5631656974 ps
CPU time 41.08 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:46:38 PM PDT 24
Peak memory 205096 kb
Host smart-fb6b9442-adcb-400f-8441-f2353a97515c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620577531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.620577531
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3902969082
Short name T266
Test name
Test status
Simulation time 644819425 ps
CPU time 28.01 seconds
Started May 16 12:45:32 PM PDT 24
Finished May 16 12:46:25 PM PDT 24
Peak memory 204984 kb
Host smart-63f2558c-59c9-4603-b6ae-9f0baa86c1cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902969082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3902969082
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3910744069
Short name T474
Test name
Test status
Simulation time 45756009550 ps
CPU time 436.46 seconds
Started May 16 12:45:33 PM PDT 24
Finished May 16 12:53:14 PM PDT 24
Peak memory 4089460 kb
Host smart-56a3a30f-f85a-4078-9c83-fd9e1567f4a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910744069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3910744069
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1134481233
Short name T886
Test name
Test status
Simulation time 1480986449 ps
CPU time 6.89 seconds
Started May 16 12:45:34 PM PDT 24
Finished May 16 12:46:05 PM PDT 24
Peak memory 221204 kb
Host smart-4fa1fc6f-f1f0-4da1-ad5a-7d83b0f7a805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134481233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1134481233
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1434628754
Short name T540
Test name
Test status
Simulation time 52035473 ps
CPU time 0.62 seconds
Started May 16 12:45:43 PM PDT 24
Finished May 16 12:46:07 PM PDT 24
Peak memory 204628 kb
Host smart-eb38563a-7533-41d8-80e0-bd271a0aca04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434628754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1434628754
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3413151324
Short name T900
Test name
Test status
Simulation time 83873213 ps
CPU time 2.1 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 216972 kb
Host smart-90e15f20-a411-41db-a25d-44e4b5ec0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413151324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3413151324
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3125802494
Short name T921
Test name
Test status
Simulation time 658675973 ps
CPU time 6.05 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 272932 kb
Host smart-6b840420-80ca-4a59-937d-64fba0a77450
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125802494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3125802494
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1865464634
Short name T257
Test name
Test status
Simulation time 2150016182 ps
CPU time 79.36 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:47:26 PM PDT 24
Peak memory 740600 kb
Host smart-8297879a-f592-4e11-9017-58eabb664009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865464634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1865464634
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3751236992
Short name T50
Test name
Test status
Simulation time 5314411781 ps
CPU time 36.7 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 534056 kb
Host smart-6053c9b0-b9f3-4542-be2b-bd2ba56c2f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751236992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3751236992
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2360286258
Short name T535
Test name
Test status
Simulation time 287628899 ps
CPU time 0.87 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:01 PM PDT 24
Peak memory 204752 kb
Host smart-2b9c2820-c163-4451-bbd7-5aec1d38da05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360286258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2360286258
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1518588656
Short name T1174
Test name
Test status
Simulation time 637305499 ps
CPU time 8.87 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:18 PM PDT 24
Peak memory 204988 kb
Host smart-534e9c6e-eed1-492d-9f2f-089daef105b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518588656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1518588656
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2872980485
Short name T1314
Test name
Test status
Simulation time 16536579930 ps
CPU time 275.36 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:50:35 PM PDT 24
Peak memory 1111544 kb
Host smart-dd2a689d-2693-45a0-830b-7f26d871fdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872980485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2872980485
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2105927887
Short name T1002
Test name
Test status
Simulation time 512462218 ps
CPU time 7.3 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 204948 kb
Host smart-d36c0963-168e-4394-815f-ba9f91ee245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105927887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2105927887
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1981833776
Short name T240
Test name
Test status
Simulation time 21614300791 ps
CPU time 32.24 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:41 PM PDT 24
Peak memory 408992 kb
Host smart-7c9ed5b3-9aba-4802-957c-aba43a771b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981833776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1981833776
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1155381903
Short name T126
Test name
Test status
Simulation time 20261046 ps
CPU time 0.66 seconds
Started May 16 12:45:34 PM PDT 24
Finished May 16 12:45:59 PM PDT 24
Peak memory 204632 kb
Host smart-0592eeb9-df38-49d7-9382-00123ecb9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155381903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1155381903
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3726401324
Short name T5
Test name
Test status
Simulation time 19638981992 ps
CPU time 216.98 seconds
Started May 16 12:45:45 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 1111872 kb
Host smart-d84f3f57-b6cb-4eeb-bb94-704893ef0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726401324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3726401324
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3702443306
Short name T676
Test name
Test status
Simulation time 2990858787 ps
CPU time 31.61 seconds
Started May 16 12:45:36 PM PDT 24
Finished May 16 12:46:32 PM PDT 24
Peak memory 294464 kb
Host smart-345210d1-ae1a-4a47-b205-083673e07287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702443306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3702443306
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2141769366
Short name T121
Test name
Test status
Simulation time 12535778275 ps
CPU time 422.21 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:53:12 PM PDT 24
Peak memory 1981720 kb
Host smart-c1976f22-b69c-4740-ab65-53be2a2a03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141769366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2141769366
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.539619298
Short name T1088
Test name
Test status
Simulation time 1847184712 ps
CPU time 17.43 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:24 PM PDT 24
Peak memory 213172 kb
Host smart-67a6b19f-1fc2-41cc-8b5c-528bf2de6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539619298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.539619298
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1197563533
Short name T1306
Test name
Test status
Simulation time 16475043294 ps
CPU time 5.11 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:46:15 PM PDT 24
Peak memory 213768 kb
Host smart-613991ea-96c6-4612-9f17-7064f71fa6a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197563533 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1197563533
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2061753021
Short name T1042
Test name
Test status
Simulation time 10198852390 ps
CPU time 26.97 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:46:37 PM PDT 24
Peak memory 331428 kb
Host smart-5a8cb5d2-3ac2-4ae6-a927-f9716c9b4b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061753021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2061753021
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2116793167
Short name T1245
Test name
Test status
Simulation time 10098623961 ps
CPU time 74.3 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:47:24 PM PDT 24
Peak memory 550340 kb
Host smart-d0bfbf7e-c936-41e3-ad4a-c0e0da6d3872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116793167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2116793167
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.942987810
Short name T1051
Test name
Test status
Simulation time 1323068702 ps
CPU time 6.56 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:16 PM PDT 24
Peak memory 209492 kb
Host smart-24934292-62ef-4f73-b107-1ba1a9d5a2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942987810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.942987810
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2831553897
Short name T682
Test name
Test status
Simulation time 6067644198 ps
CPU time 3.91 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 205016 kb
Host smart-c71e17a4-1144-4495-8506-81d53225151d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831553897 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2831553897
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.4022661981
Short name T1286
Test name
Test status
Simulation time 4396704934 ps
CPU time 14.79 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 12:46:30 PM PDT 24
Peak memory 205016 kb
Host smart-a7dd53d2-e27c-4fe8-a351-63a4066a99ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022661981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.4022661981
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2259853419
Short name T462
Test name
Test status
Simulation time 5237808427 ps
CPU time 21.29 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:46:30 PM PDT 24
Peak memory 228716 kb
Host smart-63bc6efd-303d-462b-9d1c-c9dad38e7f82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259853419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2259853419
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1810972934
Short name T279
Test name
Test status
Simulation time 7655169967 ps
CPU time 14.97 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:21 PM PDT 24
Peak memory 204948 kb
Host smart-9ebb6175-7ab1-4fd0-b2ad-1e71281bf26c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810972934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1810972934
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3250469650
Short name T179
Test name
Test status
Simulation time 9014694540 ps
CPU time 385.65 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:52:33 PM PDT 24
Peak memory 2387192 kb
Host smart-9c796097-4ca2-4270-be52-c8a692eea61c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250469650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3250469650
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3274841059
Short name T334
Test name
Test status
Simulation time 6515122475 ps
CPU time 7.52 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 220024 kb
Host smart-9361992e-1749-4edf-b184-bf3b3b38f3b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274841059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3274841059
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2950950634
Short name T1082
Test name
Test status
Simulation time 58760777 ps
CPU time 0.59 seconds
Started May 16 12:45:51 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 204548 kb
Host smart-0c0150fa-080a-4c9c-99ec-f5204d11598f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950950634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2950950634
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3745197601
Short name T1211
Test name
Test status
Simulation time 812525657 ps
CPU time 3.37 seconds
Started May 16 12:45:51 PM PDT 24
Finished May 16 12:46:17 PM PDT 24
Peak memory 213164 kb
Host smart-7a28db49-1859-42f7-abb3-4bdc55909f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745197601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3745197601
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2691461819
Short name T1207
Test name
Test status
Simulation time 470375821 ps
CPU time 12.21 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:46:22 PM PDT 24
Peak memory 254060 kb
Host smart-cef12b87-b7ef-44b4-8e98-467bd05089bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691461819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2691461819
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3155589144
Short name T371
Test name
Test status
Simulation time 1864641369 ps
CPU time 63.09 seconds
Started May 16 12:45:46 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 650348 kb
Host smart-242a80e9-081e-4843-af1f-93170e515592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155589144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3155589144
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3616809630
Short name T324
Test name
Test status
Simulation time 4199133532 ps
CPU time 143.13 seconds
Started May 16 12:45:43 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 668484 kb
Host smart-71bbd66e-e0b9-4802-a39a-cef01bbfcc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616809630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3616809630
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2164656644
Short name T680
Test name
Test status
Simulation time 155788684 ps
CPU time 1.1 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:08 PM PDT 24
Peak memory 204904 kb
Host smart-d39a3fd9-f67d-4a2b-a0d6-aec0fd879da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164656644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2164656644
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.676314292
Short name T654
Test name
Test status
Simulation time 336712782 ps
CPU time 9.1 seconds
Started May 16 12:45:47 PM PDT 24
Finished May 16 12:46:19 PM PDT 24
Peak memory 232876 kb
Host smart-ccf0bcf6-9658-4dbd-b3ce-22021e3ca03e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676314292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
676314292
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2641384056
Short name T1079
Test name
Test status
Simulation time 22110888140 ps
CPU time 129.12 seconds
Started May 16 12:45:45 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 1398336 kb
Host smart-eab4ed1f-e958-43dc-a6c7-745ad2ee5650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641384056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2641384056
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2685257188
Short name T575
Test name
Test status
Simulation time 613134136 ps
CPU time 7.98 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 205032 kb
Host smart-fb964f5c-1081-4680-9ec2-421c6b1c5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685257188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2685257188
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2631331859
Short name T33
Test name
Test status
Simulation time 9426598246 ps
CPU time 41.08 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:46:58 PM PDT 24
Peak memory 412720 kb
Host smart-92815c99-1590-467f-a720-de028b65def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631331859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2631331859
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2224667417
Short name T1329
Test name
Test status
Simulation time 49334512 ps
CPU time 0.65 seconds
Started May 16 12:45:45 PM PDT 24
Finished May 16 12:46:08 PM PDT 24
Peak memory 204588 kb
Host smart-31d030b5-952a-4139-b438-a98b465896d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224667417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2224667417
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2516109412
Short name T1103
Test name
Test status
Simulation time 6821769840 ps
CPU time 20.17 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 205032 kb
Host smart-4fdebc6c-9b63-4c3d-a006-88084ef40b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516109412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2516109412
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3367442229
Short name T1006
Test name
Test status
Simulation time 4187765614 ps
CPU time 50.82 seconds
Started May 16 12:45:44 PM PDT 24
Finished May 16 12:46:57 PM PDT 24
Peak memory 289916 kb
Host smart-37655f6f-370b-406c-b53f-be521680eba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367442229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3367442229
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2391888176
Short name T788
Test name
Test status
Simulation time 40735108185 ps
CPU time 919.03 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 01:01:37 PM PDT 24
Peak memory 1734680 kb
Host smart-2f291b2b-4cec-42bf-977d-9a9fd0096720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391888176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2391888176
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.707195910
Short name T792
Test name
Test status
Simulation time 2012061176 ps
CPU time 8.01 seconds
Started May 16 12:45:43 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 213052 kb
Host smart-b8ae19d9-b65a-46cf-849e-956bc7e40bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707195910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.707195910
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1784389600
Short name T455
Test name
Test status
Simulation time 2323191387 ps
CPU time 3.56 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:46:21 PM PDT 24
Peak memory 205132 kb
Host smart-2e354b3a-d25c-436b-a7cc-27b761aeaa80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784389600 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1784389600
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1866947440
Short name T674
Test name
Test status
Simulation time 10062297941 ps
CPU time 28.38 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:46:46 PM PDT 24
Peak memory 335620 kb
Host smart-e25f2977-cd6c-442d-9694-880a0259cbde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866947440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1866947440
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3128823393
Short name T84
Test name
Test status
Simulation time 10264137208 ps
CPU time 37.18 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:46:53 PM PDT 24
Peak memory 400996 kb
Host smart-f2621225-c250-42dd-ad0f-3ffcca874cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128823393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3128823393
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.973934411
Short name T1265
Test name
Test status
Simulation time 1563721844 ps
CPU time 1.84 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:46:19 PM PDT 24
Peak memory 204904 kb
Host smart-cb26be36-99b7-4032-9b3f-23b1b1b5b436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973934411 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.973934411
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1354641199
Short name T686
Test name
Test status
Simulation time 2693701620 ps
CPU time 7.17 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 210112 kb
Host smart-9529a5a4-fe2e-4ae7-9fdc-83ddc4710bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354641199 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1354641199
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1999140119
Short name T1332
Test name
Test status
Simulation time 3885130164 ps
CPU time 8.62 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:46:24 PM PDT 24
Peak memory 205024 kb
Host smart-2acff2aa-7312-4775-9a7a-f1b90e8c7766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999140119 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1999140119
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3894503828
Short name T466
Test name
Test status
Simulation time 1340906589 ps
CPU time 56.62 seconds
Started May 16 12:45:51 PM PDT 24
Finished May 16 12:47:10 PM PDT 24
Peak memory 204940 kb
Host smart-9556ca3a-d2fe-40d7-bd49-9be98e3244c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894503828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3894503828
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.689235501
Short name T489
Test name
Test status
Simulation time 506818608 ps
CPU time 4.59 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 12:46:20 PM PDT 24
Peak memory 204780 kb
Host smart-b496e1c6-35b0-45bd-afcf-9df21ab0da7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689235501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.689235501
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.878637309
Short name T614
Test name
Test status
Simulation time 34565415195 ps
CPU time 58.71 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:47:17 PM PDT 24
Peak memory 1054884 kb
Host smart-001e821e-567a-4209-a4bb-3eb0c7d3a3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878637309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.878637309
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3674747769
Short name T346
Test name
Test status
Simulation time 22557615711 ps
CPU time 399.02 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:52:57 PM PDT 24
Peak memory 1349180 kb
Host smart-9508bb6f-bcc8-483f-9752-5d1a78ffc09a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674747769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3674747769
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.4206275726
Short name T628
Test name
Test status
Simulation time 1510288155 ps
CPU time 7.59 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:46:24 PM PDT 24
Peak memory 211760 kb
Host smart-ccd3b5fa-1fea-48b0-8313-2a510bdd3821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206275726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.4206275726
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4118914495
Short name T915
Test name
Test status
Simulation time 15800825 ps
CPU time 0.62 seconds
Started May 16 12:46:01 PM PDT 24
Finished May 16 12:46:24 PM PDT 24
Peak memory 204664 kb
Host smart-d6c17b2c-400d-491f-ad4e-fda40e380a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118914495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4118914495
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.381757050
Short name T793
Test name
Test status
Simulation time 335327418 ps
CPU time 1.85 seconds
Started May 16 12:45:55 PM PDT 24
Finished May 16 12:46:19 PM PDT 24
Peak memory 213148 kb
Host smart-9a033ccc-bcee-4687-bb08-aa7657e8d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381757050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.381757050
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1521353291
Short name T309
Test name
Test status
Simulation time 269975137 ps
CPU time 6.04 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:46:22 PM PDT 24
Peak memory 258856 kb
Host smart-ee1079d0-de41-482d-aac1-83822e1a0dbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521353291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1521353291
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2870629480
Short name T77
Test name
Test status
Simulation time 2711244517 ps
CPU time 42.9 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 540336 kb
Host smart-25ec1cf9-211d-4c7d-904a-4917a790c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870629480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2870629480
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.874184723
Short name T1268
Test name
Test status
Simulation time 235254847 ps
CPU time 1.05 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:46:16 PM PDT 24
Peak memory 204712 kb
Host smart-ca0c2ccd-2e72-4419-a086-72c1e2b61b37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874184723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.874184723
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3525395552
Short name T1257
Test name
Test status
Simulation time 203348227 ps
CPU time 5.41 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 242164 kb
Host smart-f05065e1-2846-4cce-b237-0e6c83d83fd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525395552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3525395552
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.748710890
Short name T108
Test name
Test status
Simulation time 12515475906 ps
CPU time 67.7 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 12:47:22 PM PDT 24
Peak memory 854096 kb
Host smart-63242ca9-6ebb-4503-a219-e31b7046ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748710890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.748710890
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3338559465
Short name T438
Test name
Test status
Simulation time 1614499928 ps
CPU time 5.23 seconds
Started May 16 12:46:02 PM PDT 24
Finished May 16 12:46:29 PM PDT 24
Peak memory 204896 kb
Host smart-bc24893e-4011-4fbf-9642-dd8cb5e3606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338559465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3338559465
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2530444490
Short name T297
Test name
Test status
Simulation time 2308405738 ps
CPU time 34.12 seconds
Started May 16 12:46:06 PM PDT 24
Finished May 16 12:47:02 PM PDT 24
Peak memory 376668 kb
Host smart-f487022c-5747-44ea-bfda-f67883f213cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530444490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2530444490
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.169753458
Short name T141
Test name
Test status
Simulation time 158789006 ps
CPU time 0.63 seconds
Started May 16 12:45:55 PM PDT 24
Finished May 16 12:46:18 PM PDT 24
Peak memory 204676 kb
Host smart-5cc1d24a-da3f-4c63-b081-889ff3a2af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169753458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.169753458
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1964571080
Short name T1183
Test name
Test status
Simulation time 12299369078 ps
CPU time 47.65 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:47:03 PM PDT 24
Peak memory 561876 kb
Host smart-3409e347-1559-48cb-98c8-0994209a3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964571080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1964571080
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3941715823
Short name T696
Test name
Test status
Simulation time 6675737206 ps
CPU time 31.9 seconds
Started May 16 12:45:56 PM PDT 24
Finished May 16 12:46:50 PM PDT 24
Peak memory 366572 kb
Host smart-52fe38eb-9fde-4b35-b871-60c1575148c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941715823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3941715823
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.4134083357
Short name T261
Test name
Test status
Simulation time 86648695047 ps
CPU time 641.71 seconds
Started May 16 12:45:53 PM PDT 24
Finished May 16 12:56:57 PM PDT 24
Peak memory 1795916 kb
Host smart-0fb1213c-ae96-4d29-84c7-292327dfaaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134083357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4134083357
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1570894906
Short name T580
Test name
Test status
Simulation time 2185154931 ps
CPU time 10.54 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 213260 kb
Host smart-b9548688-ace0-41e5-9cf0-892e8dfea747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570894906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1570894906
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3901098308
Short name T412
Test name
Test status
Simulation time 484510366 ps
CPU time 2.8 seconds
Started May 16 12:46:07 PM PDT 24
Finished May 16 12:46:32 PM PDT 24
Peak memory 204868 kb
Host smart-68c72acb-eb2c-4bea-9661-533b1b054cd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901098308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3901098308
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.952422476
Short name T754
Test name
Test status
Simulation time 10092790676 ps
CPU time 74.68 seconds
Started May 16 12:46:06 PM PDT 24
Finished May 16 12:47:43 PM PDT 24
Peak memory 492016 kb
Host smart-f0fb82b5-2c2d-4e84-bb8b-048aa5bbdd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952422476 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.952422476
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2148635138
Short name T1206
Test name
Test status
Simulation time 10032167080 ps
CPU time 75.06 seconds
Started May 16 12:46:10 PM PDT 24
Finished May 16 12:47:49 PM PDT 24
Peak memory 474600 kb
Host smart-e197c580-5077-41e4-9386-6b804f79522d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148635138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2148635138
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2789593473
Short name T22
Test name
Test status
Simulation time 450932384 ps
CPU time 2.72 seconds
Started May 16 12:46:01 PM PDT 24
Finished May 16 12:46:26 PM PDT 24
Peak memory 204928 kb
Host smart-e9818101-4bcf-421e-8a4a-091cce2d402c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789593473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2789593473
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3060569209
Short name T1119
Test name
Test status
Simulation time 4277836806 ps
CPU time 6.13 seconds
Started May 16 12:45:55 PM PDT 24
Finished May 16 12:46:24 PM PDT 24
Peak memory 216388 kb
Host smart-a8f701da-4fb6-4282-94d7-276bf606e469
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060569209 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3060569209
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3123596434
Short name T1089
Test name
Test status
Simulation time 2855898578 ps
CPU time 21.54 seconds
Started May 16 12:46:06 PM PDT 24
Finished May 16 12:46:50 PM PDT 24
Peak memory 822196 kb
Host smart-a7205371-2bf5-4bcd-bf4a-53479f0e0465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123596434 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3123596434
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3959213566
Short name T78
Test name
Test status
Simulation time 3147713819 ps
CPU time 11.19 seconds
Started May 16 12:45:54 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 205064 kb
Host smart-05724c03-89a7-4368-a3c8-a1545bd18da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959213566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3959213566
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3142311096
Short name T717
Test name
Test status
Simulation time 636253104 ps
CPU time 27.55 seconds
Started May 16 12:45:51 PM PDT 24
Finished May 16 12:46:40 PM PDT 24
Peak memory 205004 kb
Host smart-78221ac4-4a6c-4d56-bc3a-40fd0084953b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142311096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3142311096
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3443923039
Short name T314
Test name
Test status
Simulation time 36960171136 ps
CPU time 455.05 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 12:53:50 PM PDT 24
Peak memory 4301692 kb
Host smart-3b978254-adf9-4fe2-aa7d-eda65a46c32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443923039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3443923039
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2014290998
Short name T819
Test name
Test status
Simulation time 31772775019 ps
CPU time 1695.45 seconds
Started May 16 12:45:52 PM PDT 24
Finished May 16 01:14:31 PM PDT 24
Peak memory 6961496 kb
Host smart-252be493-5be0-4cc0-8527-6906a079cb78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014290998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2014290998
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.731773297
Short name T774
Test name
Test status
Simulation time 1277480492 ps
CPU time 6.82 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:46:32 PM PDT 24
Peak memory 213192 kb
Host smart-5ef8fba4-0b07-4b55-b5a1-bdcfdc875b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731773297 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.731773297
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3641184446
Short name T1061
Test name
Test status
Simulation time 37311115 ps
CPU time 0.62 seconds
Started May 16 12:46:07 PM PDT 24
Finished May 16 12:46:31 PM PDT 24
Peak memory 204500 kb
Host smart-9e575459-fcef-449b-9811-01e3e6738f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641184446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3641184446
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3559109641
Short name T48
Test name
Test status
Simulation time 1254262970 ps
CPU time 8.33 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 233888 kb
Host smart-05f7f17f-3223-471d-aea0-7d03d5ab9e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559109641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3559109641
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1379413269
Short name T1028
Test name
Test status
Simulation time 1487731052 ps
CPU time 4.26 seconds
Started May 16 12:46:01 PM PDT 24
Finished May 16 12:46:28 PM PDT 24
Peak memory 249660 kb
Host smart-fc9cfac6-d264-4dab-87c4-289ec0802d5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379413269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1379413269
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3514534310
Short name T1123
Test name
Test status
Simulation time 2894977725 ps
CPU time 107.93 seconds
Started May 16 12:46:09 PM PDT 24
Finished May 16 12:48:21 PM PDT 24
Peak memory 900288 kb
Host smart-f716e827-77f8-401a-be6a-56c5c288fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514534310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3514534310
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1653942490
Short name T767
Test name
Test status
Simulation time 2465317202 ps
CPU time 71.6 seconds
Started May 16 12:46:06 PM PDT 24
Finished May 16 12:47:40 PM PDT 24
Peak memory 723388 kb
Host smart-29fce8b3-3710-4c6b-a779-b2fe56d9540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653942490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1653942490
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3727471531
Short name T1344
Test name
Test status
Simulation time 426980903 ps
CPU time 1.02 seconds
Started May 16 12:46:07 PM PDT 24
Finished May 16 12:46:32 PM PDT 24
Peak memory 204800 kb
Host smart-eb5ac05f-eed4-40cc-a37e-b2552da0a8da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727471531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3727471531
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2812500651
Short name T1058
Test name
Test status
Simulation time 223848519 ps
CPU time 4.04 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:30 PM PDT 24
Peak memory 235216 kb
Host smart-0dbf3416-d6bd-45ca-98dd-97c9bff047a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812500651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2812500651
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2203018659
Short name T305
Test name
Test status
Simulation time 13098126662 ps
CPU time 196.81 seconds
Started May 16 12:46:02 PM PDT 24
Finished May 16 12:49:41 PM PDT 24
Peak memory 923036 kb
Host smart-6ed41a9c-9cc5-41fa-802e-17354da3e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203018659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2203018659
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4255631926
Short name T804
Test name
Test status
Simulation time 543361181 ps
CPU time 18.79 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:46:46 PM PDT 24
Peak memory 204988 kb
Host smart-bec14e5a-2e33-4f04-8cd2-4741f5120af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255631926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4255631926
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.4279827952
Short name T465
Test name
Test status
Simulation time 1464453493 ps
CPU time 20.58 seconds
Started May 16 12:46:10 PM PDT 24
Finished May 16 12:46:55 PM PDT 24
Peak memory 301348 kb
Host smart-378fad40-770c-42c9-b39d-619f60531b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279827952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.4279827952
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2167358065
Short name T477
Test name
Test status
Simulation time 128548325 ps
CPU time 0.65 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:26 PM PDT 24
Peak memory 204716 kb
Host smart-e0342286-0a6d-4b6b-b9e5-3b8d861f29ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167358065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2167358065
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3185943497
Short name T433
Test name
Test status
Simulation time 21394606757 ps
CPU time 31.6 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:46:59 PM PDT 24
Peak memory 236832 kb
Host smart-67b1cf18-0239-4239-8534-af90560ea7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185943497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3185943497
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.66456834
Short name T327
Test name
Test status
Simulation time 5952384132 ps
CPU time 84.75 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:47:52 PM PDT 24
Peak memory 370264 kb
Host smart-a3d523a4-a94f-4a7d-a1ea-a7b60eeb81a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66456834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.66456834
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.997339547
Short name T255
Test name
Test status
Simulation time 3971349773 ps
CPU time 21.91 seconds
Started May 16 12:46:02 PM PDT 24
Finished May 16 12:46:46 PM PDT 24
Peak memory 213272 kb
Host smart-4ac5d5e2-f7f0-4df6-805e-dd54b730d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997339547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.997339547
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3306765184
Short name T1302
Test name
Test status
Simulation time 2034793887 ps
CPU time 4.72 seconds
Started May 16 12:46:09 PM PDT 24
Finished May 16 12:46:37 PM PDT 24
Peak memory 220608 kb
Host smart-2e1d7078-fe7b-4dfa-b24e-e112259ef174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306765184 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3306765184
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2450540828
Short name T483
Test name
Test status
Simulation time 10191291141 ps
CPU time 31.98 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:46:58 PM PDT 24
Peak memory 356848 kb
Host smart-166b3856-432b-4be3-a556-a190dbe35838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450540828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2450540828
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3864296535
Short name T1143
Test name
Test status
Simulation time 10065055686 ps
CPU time 31.18 seconds
Started May 16 12:46:09 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 325888 kb
Host smart-1fc9294c-c3f0-4a05-8035-592c63869a7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864296535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3864296535
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.4062019092
Short name T441
Test name
Test status
Simulation time 736746650 ps
CPU time 2.36 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:29 PM PDT 24
Peak memory 204956 kb
Host smart-a28d917b-b3a0-4c72-aef4-f19d6ac190a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062019092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.4062019092
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1100656367
Short name T300
Test name
Test status
Simulation time 923434284 ps
CPU time 5.47 seconds
Started May 16 12:46:02 PM PDT 24
Finished May 16 12:46:29 PM PDT 24
Peak memory 215060 kb
Host smart-f6d44837-6d0b-4915-8f8f-eb8f590c1a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100656367 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1100656367
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2589681666
Short name T1144
Test name
Test status
Simulation time 21694488331 ps
CPU time 375.84 seconds
Started May 16 12:46:07 PM PDT 24
Finished May 16 12:52:45 PM PDT 24
Peak memory 3390140 kb
Host smart-39740319-db5e-49a5-af61-65c925983430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589681666 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2589681666
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.442800110
Short name T1275
Test name
Test status
Simulation time 3183166910 ps
CPU time 27.19 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:46:52 PM PDT 24
Peak memory 205076 kb
Host smart-6977e583-4638-41cc-ae06-9d714f5dd80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442800110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.442800110
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3054485034
Short name T409
Test name
Test status
Simulation time 5660284675 ps
CPU time 20.15 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:47 PM PDT 24
Peak memory 218664 kb
Host smart-f4859b07-4e5a-4567-bc24-241d81591b57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054485034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3054485034
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.2766097670
Short name T1189
Test name
Test status
Simulation time 35109156348 ps
CPU time 59.55 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:47:24 PM PDT 24
Peak memory 1021652 kb
Host smart-1ea03e4f-4841-4764-b142-81c0d87b490a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766097670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.2766097670
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4160837777
Short name T671
Test name
Test status
Simulation time 17136115611 ps
CPU time 105.69 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:48:10 PM PDT 24
Peak memory 1044260 kb
Host smart-f1672f64-888c-4dbe-a45c-a8cf572e6a6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160837777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4160837777
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4210465061
Short name T71
Test name
Test status
Simulation time 4890314068 ps
CPU time 6.7 seconds
Started May 16 12:46:10 PM PDT 24
Finished May 16 12:46:41 PM PDT 24
Peak memory 205140 kb
Host smart-5b57af2e-bc99-4720-acec-241f03ca5f50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210465061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4210465061
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2488163156
Short name T512
Test name
Test status
Simulation time 22485579 ps
CPU time 0.63 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:40 PM PDT 24
Peak memory 204620 kb
Host smart-730bae05-47ec-4757-b148-c2a77db11e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488163156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2488163156
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.599576345
Short name T647
Test name
Test status
Simulation time 152047959 ps
CPU time 4.35 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:44 PM PDT 24
Peak memory 213196 kb
Host smart-d3add8ec-67c6-4fbf-b36f-933986a344b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599576345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.599576345
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3005646772
Short name T293
Test name
Test status
Simulation time 410298466 ps
CPU time 9.06 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 287956 kb
Host smart-cbce7f25-695c-4909-aa8a-970f8e08af4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005646772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3005646772
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1060210211
Short name T140
Test name
Test status
Simulation time 6091737773 ps
CPU time 95.85 seconds
Started May 16 12:46:02 PM PDT 24
Finished May 16 12:48:00 PM PDT 24
Peak memory 711308 kb
Host smart-84938fb3-83a8-4c95-b666-5ec82f4a9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060210211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1060210211
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2309760316
Short name T419
Test name
Test status
Simulation time 2681709998 ps
CPU time 87.28 seconds
Started May 16 12:46:08 PM PDT 24
Finished May 16 12:47:59 PM PDT 24
Peak memory 492312 kb
Host smart-dce18ddd-71b2-4882-afed-a002dba578b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309760316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2309760316
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2950951708
Short name T413
Test name
Test status
Simulation time 595986333 ps
CPU time 1.18 seconds
Started May 16 12:46:03 PM PDT 24
Finished May 16 12:46:27 PM PDT 24
Peak memory 204832 kb
Host smart-888a7ad6-bb83-44ac-ab57-00f8e36b88a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950951708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2950951708
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2081330865
Short name T573
Test name
Test status
Simulation time 881757226 ps
CPU time 9.13 seconds
Started May 16 12:46:04 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 233124 kb
Host smart-ae6db111-4879-4758-81a8-1420e3dd413f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081330865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2081330865
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3395001534
Short name T372
Test name
Test status
Simulation time 4907215627 ps
CPU time 384.84 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:52:53 PM PDT 24
Peak memory 1320752 kb
Host smart-8d5e9b37-32d1-430d-9b01-5ed02e180299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395001534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3395001534
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2436405498
Short name T760
Test name
Test status
Simulation time 3083624103 ps
CPU time 7.8 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:48 PM PDT 24
Peak memory 205040 kb
Host smart-8ab971bb-8d76-4ad2-97e0-334d52b6307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436405498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2436405498
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1861430076
Short name T988
Test name
Test status
Simulation time 15574282869 ps
CPU time 37.82 seconds
Started May 16 12:46:12 PM PDT 24
Finished May 16 12:47:14 PM PDT 24
Peak memory 425628 kb
Host smart-28e39748-e8fd-4971-bf94-c2c785316dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861430076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1861430076
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.4265121809
Short name T380
Test name
Test status
Simulation time 28038885 ps
CPU time 0.65 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:46:28 PM PDT 24
Peak memory 204680 kb
Host smart-aee58a35-153a-4f83-860b-7111470e528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265121809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.4265121809
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4269798985
Short name T1030
Test name
Test status
Simulation time 26710850198 ps
CPU time 1706.65 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 01:14:55 PM PDT 24
Peak memory 4252104 kb
Host smart-0ee671f0-ea37-4204-bb19-95d2547a98dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269798985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4269798985
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3503736143
Short name T876
Test name
Test status
Simulation time 2640077207 ps
CPU time 59.58 seconds
Started May 16 12:46:05 PM PDT 24
Finished May 16 12:47:27 PM PDT 24
Peak memory 267532 kb
Host smart-21fb1263-e4cf-41f0-82ed-e2b5e08e93a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503736143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3503736143
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3863463961
Short name T45
Test name
Test status
Simulation time 49121870900 ps
CPU time 1610.68 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 01:13:30 PM PDT 24
Peak memory 3934492 kb
Host smart-dc256522-ba74-41d7-8165-700d42abff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863463961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3863463961
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1016231728
Short name T1086
Test name
Test status
Simulation time 7353253462 ps
CPU time 34.52 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 213292 kb
Host smart-c1f7b59a-842b-4179-ae3a-fc91883f525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016231728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1016231728
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2107532751
Short name T776
Test name
Test status
Simulation time 1979176208 ps
CPU time 2.78 seconds
Started May 16 12:46:12 PM PDT 24
Finished May 16 12:46:39 PM PDT 24
Peak memory 204888 kb
Host smart-d0097494-d09b-4875-840f-c18c56a019b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107532751 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2107532751
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1200549196
Short name T87
Test name
Test status
Simulation time 10262158276 ps
CPU time 12.57 seconds
Started May 16 12:46:12 PM PDT 24
Finished May 16 12:46:48 PM PDT 24
Peak memory 275184 kb
Host smart-eed37673-f371-41ff-aedf-6191a605dc36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200549196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1200549196
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.4156357704
Short name T1137
Test name
Test status
Simulation time 10157378520 ps
CPU time 14.17 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:54 PM PDT 24
Peak memory 264024 kb
Host smart-3614c117-fd74-4fc4-a1ca-3549427e706b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156357704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.4156357704
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.710116506
Short name T1017
Test name
Test status
Simulation time 1620320385 ps
CPU time 2.47 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:42 PM PDT 24
Peak memory 205000 kb
Host smart-4b0a5173-6e39-468f-b162-b54f657a5b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710116506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.710116506
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.861333039
Short name T9
Test name
Test status
Simulation time 1873084749 ps
CPU time 5.52 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:46 PM PDT 24
Peak memory 210452 kb
Host smart-8f49d46f-5649-4474-a509-aa23e0a48136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861333039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.861333039
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3590992787
Short name T553
Test name
Test status
Simulation time 5584282190 ps
CPU time 12.75 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:37 PM PDT 24
Peak memory 528844 kb
Host smart-bfb48c4a-b7bc-4f99-a469-7f34feff290c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590992787 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3590992787
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1894747720
Short name T487
Test name
Test status
Simulation time 1296026551 ps
CPU time 20.73 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:46:57 PM PDT 24
Peak memory 204940 kb
Host smart-bc6f4820-0ef8-4b3d-aade-05083382b00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894747720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1894747720
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1287832326
Short name T963
Test name
Test status
Simulation time 871570877 ps
CPU time 12.84 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:52 PM PDT 24
Peak memory 217484 kb
Host smart-58471146-4fe7-42f5-8d59-97cbd3600447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287832326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1287832326
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1921979813
Short name T583
Test name
Test status
Simulation time 22721000670 ps
CPU time 29.53 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 12:47:08 PM PDT 24
Peak memory 455104 kb
Host smart-983328e8-ac4b-438b-b43f-9184548cc3d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921979813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1921979813
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2661336416
Short name T385
Test name
Test status
Simulation time 24908147297 ps
CPU time 1969.48 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 01:19:28 PM PDT 24
Peak memory 6241428 kb
Host smart-d613e5d7-cfde-4206-aaa5-bd499758ece5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661336416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2661336416
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2952688927
Short name T1239
Test name
Test status
Simulation time 6012631367 ps
CPU time 7.68 seconds
Started May 16 12:46:18 PM PDT 24
Finished May 16 12:46:50 PM PDT 24
Peak memory 217356 kb
Host smart-4e31272e-9c58-410f-af1c-902c1640bb4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952688927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2952688927
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2843633098
Short name T811
Test name
Test status
Simulation time 44091818 ps
CPU time 0.59 seconds
Started May 16 12:44:32 PM PDT 24
Finished May 16 12:44:45 PM PDT 24
Peak memory 204636 kb
Host smart-52ca358e-25aa-422c-815d-251e5ecf4956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843633098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2843633098
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1886776007
Short name T405
Test name
Test status
Simulation time 403756824 ps
CPU time 6.09 seconds
Started May 16 12:44:24 PM PDT 24
Finished May 16 12:44:41 PM PDT 24
Peak memory 213228 kb
Host smart-f6ef6e0b-1d91-4139-b595-546eeaad7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886776007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1886776007
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1442202227
Short name T652
Test name
Test status
Simulation time 1331177120 ps
CPU time 6.34 seconds
Started May 16 12:44:28 PM PDT 24
Finished May 16 12:44:45 PM PDT 24
Peak memory 265664 kb
Host smart-1658fc66-bb4d-4040-bbc8-f6ab4d5bd10b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442202227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1442202227
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1828617983
Short name T82
Test name
Test status
Simulation time 1776309020 ps
CPU time 121.8 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:46:52 PM PDT 24
Peak memory 628472 kb
Host smart-2c0d1595-fd2e-444c-9891-b635ace96e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828617983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1828617983
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.858422654
Short name T841
Test name
Test status
Simulation time 5343428281 ps
CPU time 79.97 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:46:13 PM PDT 24
Peak memory 717808 kb
Host smart-1ce213b6-c4f9-47c4-8433-3f32837e4df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858422654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.858422654
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3820050226
Short name T706
Test name
Test status
Simulation time 623898011 ps
CPU time 1.07 seconds
Started May 16 12:44:35 PM PDT 24
Finished May 16 12:44:49 PM PDT 24
Peak memory 204812 kb
Host smart-6fc01b77-6388-4e0d-af4d-da24d0fab9e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820050226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3820050226
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1000839118
Short name T967
Test name
Test status
Simulation time 1331520197 ps
CPU time 13.08 seconds
Started May 16 12:44:24 PM PDT 24
Finished May 16 12:44:48 PM PDT 24
Peak memory 250212 kb
Host smart-4b3918e1-3c9f-4e46-97d5-9d55e3d8ac7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000839118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1000839118
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1679113024
Short name T771
Test name
Test status
Simulation time 19873348514 ps
CPU time 169.43 seconds
Started May 16 12:44:22 PM PDT 24
Finished May 16 12:47:23 PM PDT 24
Peak memory 1469864 kb
Host smart-c9f6c9e0-db43-4a2d-b033-ce01bba0ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679113024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1679113024
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1511326489
Short name T779
Test name
Test status
Simulation time 1085352508 ps
CPU time 23.03 seconds
Started May 16 12:44:32 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 205052 kb
Host smart-717b4d80-ab02-4ad9-9a4d-19ba707c344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511326489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1511326489
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1034616415
Short name T807
Test name
Test status
Simulation time 1923114299 ps
CPU time 44.9 seconds
Started May 16 12:44:32 PM PDT 24
Finished May 16 12:45:28 PM PDT 24
Peak memory 282224 kb
Host smart-89e136c9-5d05-4316-b91a-f464e99c1557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034616415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1034616415
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.4161921970
Short name T800
Test name
Test status
Simulation time 85573589 ps
CPU time 0.65 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:44:48 PM PDT 24
Peak memory 204660 kb
Host smart-9377f50f-83e2-45b6-9b3c-28c88fa12160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161921970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.4161921970
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.4163574110
Short name T1192
Test name
Test status
Simulation time 8482438734 ps
CPU time 17.86 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:45:11 PM PDT 24
Peak memory 379416 kb
Host smart-5d5a2e46-ee7d-42e8-8757-8c8538b2796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163574110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.4163574110
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2967035020
Short name T902
Test name
Test status
Simulation time 6452800592 ps
CPU time 24.77 seconds
Started May 16 12:44:24 PM PDT 24
Finished May 16 12:45:00 PM PDT 24
Peak memory 296292 kb
Host smart-66e36cfa-365c-4b67-b7e4-50441aa1e482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967035020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2967035020
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2733678323
Short name T778
Test name
Test status
Simulation time 1564593610 ps
CPU time 11.33 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:45:02 PM PDT 24
Peak memory 221260 kb
Host smart-de0565c6-0149-4914-ad41-d8ca4f11ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733678323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2733678323
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.4271570389
Short name T175
Test name
Test status
Simulation time 115156806 ps
CPU time 0.94 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:44:48 PM PDT 24
Peak memory 222172 kb
Host smart-607f70fc-ea50-415a-8686-fb8e936312cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271570389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.4271570389
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.103218475
Short name T453
Test name
Test status
Simulation time 3758007469 ps
CPU time 4.65 seconds
Started May 16 12:44:32 PM PDT 24
Finished May 16 12:44:49 PM PDT 24
Peak memory 213292 kb
Host smart-bb9b3050-43f2-4817-b019-0b5cada18bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103218475 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.103218475
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3683736496
Short name T157
Test name
Test status
Simulation time 10064384591 ps
CPU time 68.51 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 482224 kb
Host smart-28347f61-0bc9-4976-9322-e4018a457533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683736496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3683736496
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.51758615
Short name T972
Test name
Test status
Simulation time 10217459506 ps
CPU time 14.4 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 266820 kb
Host smart-7bdf6067-deff-4218-94f7-66f5d7cee152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51758615 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_fifo_reset_tx.51758615
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1924307817
Short name T1338
Test name
Test status
Simulation time 1735291099 ps
CPU time 2.96 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:44:54 PM PDT 24
Peak memory 205756 kb
Host smart-afb707e2-9424-474c-ac9e-01c5fdb625cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924307817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1924307817
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3202213364
Short name T557
Test name
Test status
Simulation time 714226574 ps
CPU time 4.3 seconds
Started May 16 12:44:28 PM PDT 24
Finished May 16 12:44:43 PM PDT 24
Peak memory 205044 kb
Host smart-9fd89097-a066-4a58-b083-ee8b6883b174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202213364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3202213364
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3201556235
Short name T533
Test name
Test status
Simulation time 13717887871 ps
CPU time 88.49 seconds
Started May 16 12:44:28 PM PDT 24
Finished May 16 12:46:07 PM PDT 24
Peak memory 1669576 kb
Host smart-5e1c0d38-4829-4d59-90e4-1d55bda32060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201556235 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3201556235
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1384023035
Short name T328
Test name
Test status
Simulation time 930902706 ps
CPU time 15.85 seconds
Started May 16 12:44:25 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 204856 kb
Host smart-764c4f2b-03d9-47e6-884c-a45722c798a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384023035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1384023035
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1313933292
Short name T7
Test name
Test status
Simulation time 2785027962 ps
CPU time 59.51 seconds
Started May 16 12:44:25 PM PDT 24
Finished May 16 12:45:35 PM PDT 24
Peak memory 208172 kb
Host smart-585abd4b-35d9-4d2f-9571-e328a681a494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313933292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1313933292
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1044713680
Short name T721
Test name
Test status
Simulation time 53415039359 ps
CPU time 81.53 seconds
Started May 16 12:44:35 PM PDT 24
Finished May 16 12:46:11 PM PDT 24
Peak memory 1197208 kb
Host smart-b31fa614-d190-4d2a-ae31-dec38d4850e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044713680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1044713680
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3763493375
Short name T1299
Test name
Test status
Simulation time 16451963283 ps
CPU time 225.76 seconds
Started May 16 12:44:24 PM PDT 24
Finished May 16 12:48:21 PM PDT 24
Peak memory 1883852 kb
Host smart-1a9b428f-6e86-439a-8f8d-478be72e4d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763493375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3763493375
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1329163256
Short name T1287
Test name
Test status
Simulation time 6748737654 ps
CPU time 7.89 seconds
Started May 16 12:44:28 PM PDT 24
Finished May 16 12:44:46 PM PDT 24
Peak memory 212144 kb
Host smart-24759ade-458e-4379-910b-ba3798d6a05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329163256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1329163256
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2938643065
Short name T1255
Test name
Test status
Simulation time 24931473 ps
CPU time 0.62 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:46:47 PM PDT 24
Peak memory 204516 kb
Host smart-7fec5e73-63f5-4c45-b486-64dc03dc4a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938643065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2938643065
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2286089317
Short name T398
Test name
Test status
Simulation time 276806244 ps
CPU time 1.61 seconds
Started May 16 12:46:18 PM PDT 24
Finished May 16 12:46:45 PM PDT 24
Peak memory 216292 kb
Host smart-f81ed294-cc5e-4048-aacc-0a5eb591359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286089317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2286089317
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3201955167
Short name T1235
Test name
Test status
Simulation time 976183799 ps
CPU time 4.91 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:45 PM PDT 24
Peak memory 254664 kb
Host smart-3725506b-c63a-476d-8d32-aba0da5fc6d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201955167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3201955167
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4254720263
Short name T64
Test name
Test status
Simulation time 2285731807 ps
CPU time 66.87 seconds
Started May 16 12:46:17 PM PDT 24
Finished May 16 12:47:49 PM PDT 24
Peak memory 650848 kb
Host smart-5cc98dca-e0cb-4251-a2b5-b7ef2a04639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254720263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4254720263
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2627628245
Short name T283
Test name
Test status
Simulation time 3574444875 ps
CPU time 78.36 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:47:56 PM PDT 24
Peak memory 805804 kb
Host smart-75e966aa-3748-48eb-8cb2-1967c632ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627628245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2627628245
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2613254266
Short name T866
Test name
Test status
Simulation time 106212706 ps
CPU time 1.01 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:46:38 PM PDT 24
Peak memory 204756 kb
Host smart-31930e74-7b39-4632-831e-e30fd8f6dbf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613254266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2613254266
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3809895657
Short name T1293
Test name
Test status
Simulation time 243472573 ps
CPU time 5.11 seconds
Started May 16 12:46:15 PM PDT 24
Finished May 16 12:46:45 PM PDT 24
Peak memory 204852 kb
Host smart-4bd3fde2-5cd5-4b41-8d76-0037e681abc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809895657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3809895657
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3786135939
Short name T1126
Test name
Test status
Simulation time 22000459212 ps
CPU time 388.75 seconds
Started May 16 12:46:11 PM PDT 24
Finished May 16 12:53:04 PM PDT 24
Peak memory 1356688 kb
Host smart-b19ff2a9-c599-4792-92c3-5fcfd799727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786135939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3786135939
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3159779595
Short name T529
Test name
Test status
Simulation time 1702662739 ps
CPU time 17.8 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:46:55 PM PDT 24
Peak memory 204972 kb
Host smart-6e4a85a5-ebc2-49d6-a6f4-d94ff798ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159779595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3159779595
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2697723164
Short name T981
Test name
Test status
Simulation time 1582533471 ps
CPU time 29.78 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:47:08 PM PDT 24
Peak memory 315492 kb
Host smart-343206df-ace0-4504-97dc-46f13da5afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697723164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2697723164
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.526144505
Short name T1122
Test name
Test status
Simulation time 28486860 ps
CPU time 0.65 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 12:46:40 PM PDT 24
Peak memory 204648 kb
Host smart-ae075af3-e8f2-4df5-b1d0-c8e011766038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526144505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.526144505
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2866185386
Short name T138
Test name
Test status
Simulation time 5237433245 ps
CPU time 58.2 seconds
Started May 16 12:46:12 PM PDT 24
Finished May 16 12:47:34 PM PDT 24
Peak memory 252412 kb
Host smart-c440a1f9-ab89-4644-94a9-8d5a6012e9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866185386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2866185386
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1531239224
Short name T1166
Test name
Test status
Simulation time 1621473498 ps
CPU time 78.85 seconds
Started May 16 12:46:17 PM PDT 24
Finished May 16 12:48:01 PM PDT 24
Peak memory 332968 kb
Host smart-5b5112f0-9558-47f1-831a-ab3de04daade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531239224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1531239224
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.4148696387
Short name T665
Test name
Test status
Simulation time 5851130181 ps
CPU time 21.28 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:46:58 PM PDT 24
Peak memory 221004 kb
Host smart-e4be05c6-0d1d-4079-a4e6-ac4694099c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148696387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.4148696387
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.4271912327
Short name T375
Test name
Test status
Simulation time 4120338539 ps
CPU time 4.87 seconds
Started May 16 12:46:17 PM PDT 24
Finished May 16 12:46:47 PM PDT 24
Peak memory 204528 kb
Host smart-3c27d5af-e195-49cc-b5f2-37e0041a658c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271912327 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.4271912327
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1798533668
Short name T755
Test name
Test status
Simulation time 10108834014 ps
CPU time 68.77 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 12:47:47 PM PDT 24
Peak memory 431968 kb
Host smart-292bc581-3b22-4c5c-b2e2-4caaf6ef2436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798533668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1798533668
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.686348501
Short name T265
Test name
Test status
Simulation time 10108064602 ps
CPU time 16.65 seconds
Started May 16 12:46:13 PM PDT 24
Finished May 16 12:46:54 PM PDT 24
Peak memory 305752 kb
Host smart-436a9a25-2ea4-4038-bdd2-3d4ad1bf2b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686348501 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.686348501
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1985440855
Short name T1219
Test name
Test status
Simulation time 402744213 ps
CPU time 2.56 seconds
Started May 16 12:46:19 PM PDT 24
Finished May 16 12:46:46 PM PDT 24
Peak memory 205060 kb
Host smart-693d6b05-cf78-44ec-ab7e-4abf48f1f8c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985440855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1985440855
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.863868182
Short name T1171
Test name
Test status
Simulation time 1579050346 ps
CPU time 7.56 seconds
Started May 16 12:46:18 PM PDT 24
Finished May 16 12:46:51 PM PDT 24
Peak memory 213100 kb
Host smart-aae6f39b-b88e-4fee-ac3b-7c6e010ff5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863868182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.863868182
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3748149194
Short name T1095
Test name
Test status
Simulation time 22047076587 ps
CPU time 155.04 seconds
Started May 16 12:46:18 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 2520280 kb
Host smart-c3ef7fec-0b6f-494c-803f-e74b3bb20c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748149194 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3748149194
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1667804476
Short name T715
Test name
Test status
Simulation time 2481490959 ps
CPU time 47.32 seconds
Started May 16 12:46:19 PM PDT 24
Finished May 16 12:47:31 PM PDT 24
Peak memory 205088 kb
Host smart-c5b2c72d-b287-4717-824c-900828eca13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667804476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1667804476
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3530351210
Short name T961
Test name
Test status
Simulation time 4996509972 ps
CPU time 42.6 seconds
Started May 16 12:46:14 PM PDT 24
Finished May 16 12:47:21 PM PDT 24
Peak memory 204900 kb
Host smart-8eed5bea-2abd-4eae-8404-96d7fb576fab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530351210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3530351210
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3246056217
Short name T882
Test name
Test status
Simulation time 35020204286 ps
CPU time 53.21 seconds
Started May 16 12:46:16 PM PDT 24
Finished May 16 12:47:35 PM PDT 24
Peak memory 981772 kb
Host smart-d7ecc9d4-ab38-44bc-983a-346b5cb7e246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246056217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3246056217
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3484845689
Short name T156
Test name
Test status
Simulation time 31270549346 ps
CPU time 227.96 seconds
Started May 16 12:46:16 PM PDT 24
Finished May 16 12:50:30 PM PDT 24
Peak memory 863388 kb
Host smart-3ef55802-043a-43d6-9d8c-d2c7d5a41ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484845689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3484845689
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1975318840
Short name T1156
Test name
Test status
Simulation time 5085992081 ps
CPU time 6.88 seconds
Started May 16 12:46:17 PM PDT 24
Finished May 16 12:46:49 PM PDT 24
Peak memory 212708 kb
Host smart-b666f2c4-fb12-46b9-994d-9378f98dbec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975318840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1975318840
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2524421507
Short name T1178
Test name
Test status
Simulation time 44261043 ps
CPU time 0.63 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:46:47 PM PDT 24
Peak memory 204540 kb
Host smart-51fc3458-1360-4f99-af14-d2026be223d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524421507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2524421507
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.633789491
Short name T747
Test name
Test status
Simulation time 583766448 ps
CPU time 4.78 seconds
Started May 16 12:46:26 PM PDT 24
Finished May 16 12:46:57 PM PDT 24
Peak memory 221380 kb
Host smart-a4bde7d9-517c-4f76-85e7-08006f896927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633789491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.633789491
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.489809422
Short name T937
Test name
Test status
Simulation time 507684784 ps
CPU time 17.78 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:47:06 PM PDT 24
Peak memory 263988 kb
Host smart-82fb7706-7131-4d23-94f5-2578f29a7744
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489809422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.489809422
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1753809109
Short name T939
Test name
Test status
Simulation time 1452911487 ps
CPU time 44.09 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:47:32 PM PDT 24
Peak memory 544740 kb
Host smart-d12e841b-4389-4934-8999-fea327912cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753809109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1753809109
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2382409012
Short name T1161
Test name
Test status
Simulation time 912404244 ps
CPU time 0.97 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 204764 kb
Host smart-0ed5bc02-0b78-4dac-925f-8a49b8122df9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382409012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2382409012
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3931845831
Short name T989
Test name
Test status
Simulation time 400417788 ps
CPU time 4.81 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:46:51 PM PDT 24
Peak memory 235540 kb
Host smart-f6a61e36-17cc-4f89-a2d3-ee371ec76d1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931845831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3931845831
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.60860543
Short name T736
Test name
Test status
Simulation time 1403434388 ps
CPU time 5.61 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 205012 kb
Host smart-8a47fcb3-e529-4f2a-8073-9bc80c1a5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60860543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.60860543
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2184011194
Short name T65
Test name
Test status
Simulation time 3665308547 ps
CPU time 36.42 seconds
Started May 16 12:46:29 PM PDT 24
Finished May 16 12:47:33 PM PDT 24
Peak memory 414444 kb
Host smart-366a81e6-1220-49f7-8428-3c6cd99374a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184011194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2184011194
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3722844889
Short name T392
Test name
Test status
Simulation time 28262850 ps
CPU time 0.66 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 204680 kb
Host smart-07896f75-f44c-471f-956d-98ba74cf648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722844889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3722844889
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1913314899
Short name T444
Test name
Test status
Simulation time 7276640879 ps
CPU time 32.73 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:47:19 PM PDT 24
Peak memory 214112 kb
Host smart-ef2cd0d9-fc19-4583-8fa3-d617fba2b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913314899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1913314899
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3811651777
Short name T490
Test name
Test status
Simulation time 1652556403 ps
CPU time 32.43 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:47:32 PM PDT 24
Peak memory 336944 kb
Host smart-be2665de-088a-4b2b-ae4a-e1bb206a52f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811651777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3811651777
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2210636682
Short name T376
Test name
Test status
Simulation time 669610958 ps
CPU time 11.95 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 220992 kb
Host smart-65d248f6-c374-45f5-b486-4da1885cab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210636682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2210636682
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2788522187
Short name T604
Test name
Test status
Simulation time 16125933112 ps
CPU time 5.39 seconds
Started May 16 12:46:26 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 205108 kb
Host smart-79eeaff1-606a-4e83-8e66-80fa227ac5a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788522187 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2788522187
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3326285845
Short name T942
Test name
Test status
Simulation time 10146636976 ps
CPU time 28.36 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 294312 kb
Host smart-8c090616-3a2b-4fe7-8740-4ec81ac09421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326285845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3326285845
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3105844427
Short name T86
Test name
Test status
Simulation time 10799167854 ps
CPU time 11.11 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:47:11 PM PDT 24
Peak memory 281704 kb
Host smart-aa7b169e-0176-422c-b457-297547b051d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105844427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3105844427
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3342295838
Short name T768
Test name
Test status
Simulation time 1246561284 ps
CPU time 6.82 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:47:05 PM PDT 24
Peak memory 213168 kb
Host smart-a4333959-5f9f-4585-9142-be596968deb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342295838 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3342295838
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.731393505
Short name T559
Test name
Test status
Simulation time 12424049157 ps
CPU time 236.57 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:50:43 PM PDT 24
Peak memory 3059552 kb
Host smart-9981317b-3924-4c29-8dae-dcab90622443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731393505 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.731393505
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.390656458
Short name T775
Test name
Test status
Simulation time 632321358 ps
CPU time 8.9 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:08 PM PDT 24
Peak memory 204944 kb
Host smart-40df1af6-8215-4ec0-9839-6a8cf97a81ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390656458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.390656458
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3134966163
Short name T492
Test name
Test status
Simulation time 1063437826 ps
CPU time 11.02 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:46:57 PM PDT 24
Peak memory 204912 kb
Host smart-d257c4f6-ddd3-44d3-9984-2e82748334cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134966163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3134966163
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3084704515
Short name T447
Test name
Test status
Simulation time 31673615296 ps
CPU time 274.14 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:51:22 PM PDT 24
Peak memory 3072568 kb
Host smart-9da05577-eb4f-4a2a-9699-ca7a5620b3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084704515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3084704515
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.4272718637
Short name T679
Test name
Test status
Simulation time 36007358342 ps
CPU time 380.58 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:53:08 PM PDT 24
Peak memory 2801684 kb
Host smart-55ddf19d-5ae2-4c66-9d69-315a7527f53b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272718637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.4272718637
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3977273578
Short name T1149
Test name
Test status
Simulation time 2718822339 ps
CPU time 7.66 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 221132 kb
Host smart-ca467ffd-907a-4696-9147-1b36ed006669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977273578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3977273578
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2335691352
Short name T1159
Test name
Test status
Simulation time 46372572 ps
CPU time 0.61 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 204596 kb
Host smart-fe53af4d-c690-4875-bfe1-5ef0f1300779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335691352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2335691352
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.775383967
Short name T73
Test name
Test status
Simulation time 613982520 ps
CPU time 3.7 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:46:50 PM PDT 24
Peak memory 221424 kb
Host smart-2ff91f24-7d62-49bd-98e3-efe4516ac84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775383967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.775383967
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3270424224
Short name T705
Test name
Test status
Simulation time 273951592 ps
CPU time 13.79 seconds
Started May 16 12:46:21 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 259156 kb
Host smart-3b81e195-31c9-485e-94ae-ac285d31a4d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270424224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3270424224
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1920362711
Short name T1014
Test name
Test status
Simulation time 2426944325 ps
CPU time 82.11 seconds
Started May 16 12:46:25 PM PDT 24
Finished May 16 12:48:11 PM PDT 24
Peak memory 803788 kb
Host smart-6b10587d-925a-4b16-aa3e-480471f0a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920362711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1920362711
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3793708917
Short name T388
Test name
Test status
Simulation time 2053349577 ps
CPU time 75.55 seconds
Started May 16 12:46:24 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 715596 kb
Host smart-8847331f-d745-4a89-be39-2d6f3d1bb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793708917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3793708917
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3932053498
Short name T934
Test name
Test status
Simulation time 127690597 ps
CPU time 0.98 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:46:49 PM PDT 24
Peak memory 204672 kb
Host smart-daad7ed6-5559-4a8f-94ee-6d3012722f33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932053498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3932053498
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3096229181
Short name T1336
Test name
Test status
Simulation time 692899864 ps
CPU time 10.36 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:47:10 PM PDT 24
Peak memory 239168 kb
Host smart-b2fefde6-1115-4fc1-a9fa-e16eb85c30c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096229181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3096229181
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2154103111
Short name T801
Test name
Test status
Simulation time 8996961493 ps
CPU time 147.27 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:49:15 PM PDT 24
Peak memory 1290788 kb
Host smart-3cb978dd-5731-4971-aba6-b23f03d64f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154103111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2154103111
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2769947530
Short name T655
Test name
Test status
Simulation time 327901546 ps
CPU time 5.45 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:47:03 PM PDT 24
Peak memory 204992 kb
Host smart-a0fc88c5-52e0-4cf3-94e9-903eff641163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769947530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2769947530
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.1269463695
Short name T459
Test name
Test status
Simulation time 1507904079 ps
CPU time 29.23 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:29 PM PDT 24
Peak memory 330196 kb
Host smart-cb54b468-f080-4083-8d5c-320e077385bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269463695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.1269463695
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2359204109
Short name T74
Test name
Test status
Simulation time 45083514 ps
CPU time 0.64 seconds
Started May 16 12:46:24 PM PDT 24
Finished May 16 12:46:49 PM PDT 24
Peak memory 204660 kb
Host smart-14ea32ac-3496-474f-8a47-217caac11337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359204109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2359204109
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.796775015
Short name T421
Test name
Test status
Simulation time 12073491335 ps
CPU time 350.41 seconds
Started May 16 12:46:22 PM PDT 24
Finished May 16 12:52:38 PM PDT 24
Peak memory 1563104 kb
Host smart-961052df-6865-4acc-9406-a3289f27ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796775015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.796775015
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2613996716
Short name T1025
Test name
Test status
Simulation time 1712471764 ps
CPU time 27.02 seconds
Started May 16 12:46:23 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 398624 kb
Host smart-0f131ce9-7724-4c21-847f-2d96afc2cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613996716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2613996716
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.468345103
Short name T1194
Test name
Test status
Simulation time 3861405209 ps
CPU time 43.47 seconds
Started May 16 12:46:24 PM PDT 24
Finished May 16 12:47:32 PM PDT 24
Peak memory 221512 kb
Host smart-e1639736-1aac-4dfa-82da-95d5cdd9b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468345103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.468345103
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3696120991
Short name T27
Test name
Test status
Simulation time 2213857785 ps
CPU time 2.72 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:01 PM PDT 24
Peak memory 205040 kb
Host smart-c4a999f3-041f-47c6-a3cc-39c0a9221807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696120991 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3696120991
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1038994975
Short name T410
Test name
Test status
Simulation time 10038022253 ps
CPU time 40.77 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:47:38 PM PDT 24
Peak memory 401888 kb
Host smart-bd050e99-9662-4a69-a2a5-91e1952244a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038994975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1038994975
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.4019917794
Short name T1129
Test name
Test status
Simulation time 10051676902 ps
CPU time 71.96 seconds
Started May 16 12:46:30 PM PDT 24
Finished May 16 12:48:09 PM PDT 24
Peak memory 605212 kb
Host smart-6c575d51-a2ab-4fdf-8061-8972345beaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019917794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.4019917794
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2656889112
Short name T1050
Test name
Test status
Simulation time 1452832682 ps
CPU time 2.35 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:01 PM PDT 24
Peak memory 205024 kb
Host smart-a460d23d-d941-4bff-a9fc-8d661ee12767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656889112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2656889112
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2578334086
Short name T481
Test name
Test status
Simulation time 1536801144 ps
CPU time 4 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:47:03 PM PDT 24
Peak memory 204884 kb
Host smart-015524c3-a963-4306-ad50-6f61897ff749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578334086 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2578334086
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2872744343
Short name T1285
Test name
Test status
Simulation time 17134467843 ps
CPU time 30.71 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 616868 kb
Host smart-e64a26a2-7263-4855-803a-a0950fa5e081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872744343 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2872744343
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3009850769
Short name T250
Test name
Test status
Simulation time 2144642589 ps
CPU time 14.47 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:14 PM PDT 24
Peak memory 204952 kb
Host smart-0fabdbb4-a419-47a1-b36e-b346b44064ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009850769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3009850769
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1091714865
Short name T530
Test name
Test status
Simulation time 291780238 ps
CPU time 4.54 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 205024 kb
Host smart-fbff861c-b2f0-49c7-9635-dc87d189056f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091714865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1091714865
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1652782950
Short name T501
Test name
Test status
Simulation time 26315152185 ps
CPU time 19.33 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:47:17 PM PDT 24
Peak memory 435428 kb
Host smart-e066fd7e-e45c-4c5d-b4ed-972779733115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652782950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1652782950
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3987437318
Short name T299
Test name
Test status
Simulation time 19461131202 ps
CPU time 389.69 seconds
Started May 16 12:46:34 PM PDT 24
Finished May 16 12:53:29 PM PDT 24
Peak memory 2405776 kb
Host smart-a3983ce1-e56b-4447-9cb8-8d8a4a0ca9da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987437318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3987437318
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2489859997
Short name T1327
Test name
Test status
Simulation time 2467263398 ps
CPU time 7.51 seconds
Started May 16 12:46:30 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 221288 kb
Host smart-e59d7900-b6ff-4c17-a103-347e3040083f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489859997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2489859997
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3090595140
Short name T702
Test name
Test status
Simulation time 19945090 ps
CPU time 0.6 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:11 PM PDT 24
Peak memory 204608 kb
Host smart-d7c6b5d4-ee01-41da-b638-14c222001b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090595140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3090595140
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2821171156
Short name T1307
Test name
Test status
Simulation time 141853674 ps
CPU time 1.66 seconds
Started May 16 12:46:38 PM PDT 24
Finished May 16 12:47:06 PM PDT 24
Peak memory 213180 kb
Host smart-7d33be37-22cd-497b-a903-eeb4d3ccdd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821171156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2821171156
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.487318299
Short name T593
Test name
Test status
Simulation time 837662291 ps
CPU time 16.03 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 257904 kb
Host smart-336a5d14-d064-4c43-8227-360f570638f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487318299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.487318299
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2568541863
Short name T1105
Test name
Test status
Simulation time 2382362119 ps
CPU time 88.1 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:48:25 PM PDT 24
Peak memory 779144 kb
Host smart-929a817c-081b-4e95-aeae-f91a1de2c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568541863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2568541863
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.122422462
Short name T748
Test name
Test status
Simulation time 8912962246 ps
CPU time 80.92 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 756728 kb
Host smart-b4ea05bf-610f-4ff8-a27e-420d5b502041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122422462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.122422462
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3317474115
Short name T1154
Test name
Test status
Simulation time 136426631 ps
CPU time 0.92 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:00 PM PDT 24
Peak memory 204680 kb
Host smart-372f00db-05f3-4e68-a9cc-5d703639522c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317474115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3317474115
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2441787025
Short name T1176
Test name
Test status
Simulation time 348681204 ps
CPU time 4.75 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:04 PM PDT 24
Peak memory 238840 kb
Host smart-cfa0de67-f70a-447c-9ef6-78bc6956ab9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441787025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2441787025
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.4159992411
Short name T762
Test name
Test status
Simulation time 3199498658 ps
CPU time 85.68 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:48:23 PM PDT 24
Peak memory 961388 kb
Host smart-45b2bde5-124d-439f-9d88-814ec650750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159992411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.4159992411
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.3435804342
Short name T237
Test name
Test status
Simulation time 681707431 ps
CPU time 29.38 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 204860 kb
Host smart-61ea1950-2040-4c4f-9a64-9fffcd8f4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435804342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3435804342
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.765799491
Short name T724
Test name
Test status
Simulation time 18476060 ps
CPU time 0.72 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:46:58 PM PDT 24
Peak memory 204600 kb
Host smart-36c8d9fa-0f9a-49ea-841f-934c5cd76594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765799491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.765799491
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2980489847
Short name T509
Test name
Test status
Simulation time 7299108308 ps
CPU time 37.99 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:47:35 PM PDT 24
Peak memory 523804 kb
Host smart-9f84c5e1-fc14-437b-9843-a6ea71bb0155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980489847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2980489847
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3002591776
Short name T56
Test name
Test status
Simulation time 5111037887 ps
CPU time 21.64 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:21 PM PDT 24
Peak memory 299892 kb
Host smart-990ae4bd-fcbd-4971-9232-21d8bbfe216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002591776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3002591776
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2597669720
Short name T1202
Test name
Test status
Simulation time 13541456565 ps
CPU time 490.05 seconds
Started May 16 12:46:30 PM PDT 24
Finished May 16 12:55:07 PM PDT 24
Peak memory 1241936 kb
Host smart-e0138aaf-8f43-4f6b-97ef-47e6518c20be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597669720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2597669720
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.390139942
Short name T1256
Test name
Test status
Simulation time 3808913716 ps
CPU time 40.98 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:47:40 PM PDT 24
Peak memory 213336 kb
Host smart-c71004b3-2f1b-48f6-8ddc-882d936d5a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390139942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.390139942
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.117699787
Short name T29
Test name
Test status
Simulation time 1431120179 ps
CPU time 4.03 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:13 PM PDT 24
Peak memory 213072 kb
Host smart-eb80a8f0-d2d7-40f0-8e27-250789dd260c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117699787 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.117699787
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1739184973
Short name T646
Test name
Test status
Simulation time 10173532021 ps
CPU time 27.9 seconds
Started May 16 12:46:38 PM PDT 24
Finished May 16 12:47:32 PM PDT 24
Peak memory 317476 kb
Host smart-6ec93ed5-1eac-4052-abd4-cdc757ddfbc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739184973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1739184973
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1032378615
Short name T1200
Test name
Test status
Simulation time 1631428649 ps
CPU time 2.73 seconds
Started May 16 12:46:47 PM PDT 24
Finished May 16 12:47:16 PM PDT 24
Peak memory 204908 kb
Host smart-5d48f2a4-6a9a-41fb-b50b-f8922446e40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032378615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1032378615
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1645426652
Short name T753
Test name
Test status
Simulation time 1005891086 ps
CPU time 6.08 seconds
Started May 16 12:46:35 PM PDT 24
Finished May 16 12:47:06 PM PDT 24
Peak memory 219512 kb
Host smart-c1a4b87f-e6a5-4d53-9624-d76e2b44b037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645426652 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1645426652
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3061133776
Short name T1007
Test name
Test status
Simulation time 10799427135 ps
CPU time 7.97 seconds
Started May 16 12:46:32 PM PDT 24
Finished May 16 12:47:07 PM PDT 24
Peak memory 254712 kb
Host smart-c64026d3-6987-48ea-8f80-19370b172f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061133776 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3061133776
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2605470151
Short name T649
Test name
Test status
Simulation time 5973555849 ps
CPU time 28.27 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 204980 kb
Host smart-28031077-298a-4052-a8e8-097a727ae9ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605470151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2605470151
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3796807471
Short name T1136
Test name
Test status
Simulation time 944923101 ps
CPU time 14.41 seconds
Started May 16 12:46:38 PM PDT 24
Finished May 16 12:47:19 PM PDT 24
Peak memory 216680 kb
Host smart-0ce999f6-56c1-49c9-8c5a-ada5f6e90ffb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796807471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3796807471
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2928241482
Short name T990
Test name
Test status
Simulation time 39972223707 ps
CPU time 623.3 seconds
Started May 16 12:46:31 PM PDT 24
Finished May 16 12:57:21 PM PDT 24
Peak memory 5038564 kb
Host smart-2cf7b0ac-483c-4fa3-b027-c18d6220bd99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928241482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2928241482
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1312899466
Short name T504
Test name
Test status
Simulation time 14929330961 ps
CPU time 7.29 seconds
Started May 16 12:46:33 PM PDT 24
Finished May 16 12:47:06 PM PDT 24
Peak memory 204944 kb
Host smart-7acc04cd-43dc-4510-a8db-008eb0cb9edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312899466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1312899466
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2814599290
Short name T422
Test name
Test status
Simulation time 36504151 ps
CPU time 0.61 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 204620 kb
Host smart-5f06b763-e211-4124-91e8-c2b4102c4fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814599290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2814599290
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.385954687
Short name T751
Test name
Test status
Simulation time 709455422 ps
CPU time 4.45 seconds
Started May 16 12:46:42 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 229452 kb
Host smart-ab26e8fe-2452-42df-9d01-e7d1ab9e12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385954687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.385954687
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.4140398380
Short name T1208
Test name
Test status
Simulation time 2047053287 ps
CPU time 65.14 seconds
Started May 16 12:46:47 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 714356 kb
Host smart-f442a67f-ef84-4205-928d-35ce9a1a6c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140398380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.4140398380
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2381621696
Short name T1150
Test name
Test status
Simulation time 10109335421 ps
CPU time 183.18 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:50:14 PM PDT 24
Peak memory 732196 kb
Host smart-5524a4f9-f196-4ecc-9783-a333b1e70e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381621696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2381621696
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3435859937
Short name T734
Test name
Test status
Simulation time 328191635 ps
CPU time 0.98 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:12 PM PDT 24
Peak memory 204976 kb
Host smart-eb33e87a-def9-4738-8d47-142fc89a7898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435859937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3435859937
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3666134536
Short name T499
Test name
Test status
Simulation time 730998794 ps
CPU time 4.7 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 233152 kb
Host smart-c8498694-ae9a-4996-97b7-d35e125c2f8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666134536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3666134536
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1438357273
Short name T1055
Test name
Test status
Simulation time 3410869270 ps
CPU time 78.85 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 1042168 kb
Host smart-1c3d19b7-59f9-4e10-8d20-dba80a07aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438357273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1438357273
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3665843271
Short name T436
Test name
Test status
Simulation time 2898851435 ps
CPU time 30.48 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:41 PM PDT 24
Peak memory 205124 kb
Host smart-3e285860-b36e-4ac9-af34-820f24ece7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665843271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3665843271
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.994777322
Short name T636
Test name
Test status
Simulation time 2813436777 ps
CPU time 21.48 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:34 PM PDT 24
Peak memory 289384 kb
Host smart-5ce5029d-9706-4e06-83fc-e3e856d0c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994777322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.994777322
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3632005091
Short name T1182
Test name
Test status
Simulation time 64145871 ps
CPU time 0.63 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:13 PM PDT 24
Peak memory 204592 kb
Host smart-76a6bdfc-136a-4088-bf08-6c60ad6158b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632005091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3632005091
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3790121291
Short name T1125
Test name
Test status
Simulation time 50041476942 ps
CPU time 255.43 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:51:26 PM PDT 24
Peak memory 205084 kb
Host smart-ed78fef5-08cf-4c7b-9b21-ef19aa9fed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790121291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3790121291
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.518032488
Short name T1195
Test name
Test status
Simulation time 3681051219 ps
CPU time 24.18 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:36 PM PDT 24
Peak memory 321136 kb
Host smart-8c24388a-8208-408d-9083-83066ab62737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518032488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.518032488
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.4285399402
Short name T871
Test name
Test status
Simulation time 713331834 ps
CPU time 10.44 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:22 PM PDT 24
Peak memory 218172 kb
Host smart-e9b5a371-2e55-4086-bef5-fc716896514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285399402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.4285399402
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2921643647
Short name T524
Test name
Test status
Simulation time 964264916 ps
CPU time 4.57 seconds
Started May 16 12:46:47 PM PDT 24
Finished May 16 12:47:18 PM PDT 24
Peak memory 213120 kb
Host smart-f3274d1a-88b3-45cb-8c24-3d543e11eccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921643647 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2921643647
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.719178274
Short name T637
Test name
Test status
Simulation time 10260792552 ps
CPU time 12.63 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 275960 kb
Host smart-413b1f41-f0ae-4e55-af02-d54bdfcc4eb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719178274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.719178274
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3506603204
Short name T1309
Test name
Test status
Simulation time 10424474894 ps
CPU time 6.69 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:17 PM PDT 24
Peak memory 256640 kb
Host smart-bc8465e0-1fc3-4ea7-aced-c0155eb75828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506603204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3506603204
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2630468183
Short name T1313
Test name
Test status
Simulation time 5025117696 ps
CPU time 2.2 seconds
Started May 16 12:46:51 PM PDT 24
Finished May 16 12:47:20 PM PDT 24
Peak memory 205140 kb
Host smart-51e06e8e-f73c-4ef3-8228-a3bde5a82b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630468183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2630468183
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1693572717
Short name T513
Test name
Test status
Simulation time 6370332405 ps
CPU time 8.47 seconds
Started May 16 12:46:47 PM PDT 24
Finished May 16 12:47:21 PM PDT 24
Peak memory 221180 kb
Host smart-dcae1b1a-8beb-4c8d-969f-209377a308cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693572717 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1693572717
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1081751271
Short name T1230
Test name
Test status
Simulation time 22223572914 ps
CPU time 55.35 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:48:07 PM PDT 24
Peak memory 1158756 kb
Host smart-4dbb14bb-7f48-4765-9e3c-d5c8d2690bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081751271 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1081751271
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.4135824391
Short name T1134
Test name
Test status
Simulation time 808728316 ps
CPU time 12.79 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:23 PM PDT 24
Peak memory 204956 kb
Host smart-8c34bfd9-08d9-4c8b-a348-856f20ac5285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135824391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.4135824391
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4116046579
Short name T785
Test name
Test status
Simulation time 1506495557 ps
CPU time 24.33 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:36 PM PDT 24
Peak memory 232456 kb
Host smart-ba6571dc-6ade-40a3-b907-73c168a656d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116046579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4116046579
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3320014210
Short name T1298
Test name
Test status
Simulation time 31970764762 ps
CPU time 40.44 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:52 PM PDT 24
Peak memory 797052 kb
Host smart-9b17cde3-a605-4733-b9ce-fd7cf62e5287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320014210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3320014210
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1948968933
Short name T620
Test name
Test status
Simulation time 35104917668 ps
CPU time 2746.4 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 01:32:58 PM PDT 24
Peak memory 7689852 kb
Host smart-f2ac4dcd-0b19-4252-9267-e90a80802b2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948968933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1948968933
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2608292564
Short name T1031
Test name
Test status
Simulation time 1169453184 ps
CPU time 6.45 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:16 PM PDT 24
Peak memory 213196 kb
Host smart-51416438-b261-4889-8774-9f688d7c3b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608292564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2608292564
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2794331977
Short name T606
Test name
Test status
Simulation time 22181380 ps
CPU time 0.62 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:47:24 PM PDT 24
Peak memory 204664 kb
Host smart-44d1de57-32e4-4894-911a-3660339d9c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794331977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2794331977
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.488151346
Short name T740
Test name
Test status
Simulation time 2311377051 ps
CPU time 4.96 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:17 PM PDT 24
Peak memory 248100 kb
Host smart-8ef558a8-d7aa-4d1e-9a88-32e9cb74133c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488151346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.488151346
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.257250588
Short name T588
Test name
Test status
Simulation time 4971948549 ps
CPU time 89.49 seconds
Started May 16 12:46:54 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 801560 kb
Host smart-be59ce5a-9591-434c-bd0e-324fa26849ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257250588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.257250588
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.842000516
Short name T1331
Test name
Test status
Simulation time 9069236484 ps
CPU time 54.18 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 660172 kb
Host smart-954957a9-4244-4bf3-91f1-96ef90d7f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842000516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.842000516
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2082616017
Short name T231
Test name
Test status
Simulation time 494267163 ps
CPU time 0.87 seconds
Started May 16 12:46:47 PM PDT 24
Finished May 16 12:47:14 PM PDT 24
Peak memory 204744 kb
Host smart-3ac55dfe-974f-4252-93ee-031b4928ace4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082616017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2082616017
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1680976457
Short name T227
Test name
Test status
Simulation time 267708772 ps
CPU time 2.73 seconds
Started May 16 12:46:46 PM PDT 24
Finished May 16 12:47:15 PM PDT 24
Peak memory 204856 kb
Host smart-b5a7b882-8a67-4a5a-935d-ef1ef1a077e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680976457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1680976457
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3748370897
Short name T170
Test name
Test status
Simulation time 5166969494 ps
CPU time 181.35 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:50:11 PM PDT 24
Peak memory 1517760 kb
Host smart-832b2c16-857a-4039-b92c-837c3a425229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748370897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3748370897
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1384170253
Short name T44
Test name
Test status
Simulation time 828449436 ps
CPU time 5.55 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:29 PM PDT 24
Peak memory 204988 kb
Host smart-5db1f613-996f-4d76-a3d8-ea999db02a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384170253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1384170253
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1887727055
Short name T506
Test name
Test status
Simulation time 2420011269 ps
CPU time 97.09 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:49:01 PM PDT 24
Peak memory 375380 kb
Host smart-8979e6ce-a59e-4014-a646-0c4d43a3f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887727055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1887727055
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1209588504
Short name T1280
Test name
Test status
Simulation time 98223647 ps
CPU time 0.66 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:11 PM PDT 24
Peak memory 204676 kb
Host smart-e7e3f91e-75ec-476d-a3c8-827a4165fb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209588504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1209588504
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3558829223
Short name T817
Test name
Test status
Simulation time 50171927018 ps
CPU time 1100.5 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 01:05:31 PM PDT 24
Peak memory 927364 kb
Host smart-ce7ad19f-e719-4df8-9048-506777a08abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558829223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3558829223
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1158307937
Short name T395
Test name
Test status
Simulation time 7418891616 ps
CPU time 32.55 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:44 PM PDT 24
Peak memory 326792 kb
Host smart-e722e70e-c927-4232-b2f2-e1297bbef313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158307937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1158307937
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2898968198
Short name T36
Test name
Test status
Simulation time 27032081037 ps
CPU time 1293.83 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 01:08:45 PM PDT 24
Peak memory 3231516 kb
Host smart-5eb7116f-6e5c-4747-9e8c-3657cc783381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898968198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2898968198
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.4291328513
Short name T320
Test name
Test status
Simulation time 2480908685 ps
CPU time 10.68 seconds
Started May 16 12:46:43 PM PDT 24
Finished May 16 12:47:19 PM PDT 24
Peak memory 218540 kb
Host smart-e47b7d97-4027-4fe1-82f0-be8c16be7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291328513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.4291328513
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3707863881
Short name T893
Test name
Test status
Simulation time 497657087 ps
CPU time 2.73 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:24 PM PDT 24
Peak memory 204964 kb
Host smart-da125351-b586-474e-90a4-2c0de1ffea47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707863881 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3707863881
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1997166033
Short name T1107
Test name
Test status
Simulation time 10088800575 ps
CPU time 67.84 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:48:31 PM PDT 24
Peak memory 476272 kb
Host smart-e6af7ccf-5706-4c43-b829-d3ae69e0fe7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997166033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1997166033
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3033779726
Short name T617
Test name
Test status
Simulation time 10066760220 ps
CPU time 31.66 seconds
Started May 16 12:47:00 PM PDT 24
Finished May 16 12:47:58 PM PDT 24
Peak memory 323720 kb
Host smart-517c6eb8-eee5-47c0-9d08-ac5061768bd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033779726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3033779726
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.63801299
Short name T482
Test name
Test status
Simulation time 1412872429 ps
CPU time 3.21 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:47:27 PM PDT 24
Peak memory 204972 kb
Host smart-1e6d4117-150c-485f-9ed6-584372037820
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63801299 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.i2c_target_hrst.63801299
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2854361939
Short name T883
Test name
Test status
Simulation time 943451739 ps
CPU time 5.44 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:17 PM PDT 24
Peak memory 213176 kb
Host smart-9ca54b2a-9ec0-4f24-9be7-347555aa4594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854361939 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2854361939
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1570592186
Short name T386
Test name
Test status
Simulation time 23050708537 ps
CPU time 34.71 seconds
Started May 16 12:46:52 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 821140 kb
Host smart-df2c3c67-21d6-4db7-84bf-3cad25e3906a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570592186 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1570592186
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3209327349
Short name T927
Test name
Test status
Simulation time 2662192555 ps
CPU time 10.97 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:47:21 PM PDT 24
Peak memory 204996 kb
Host smart-b9c52592-db59-4eca-81a5-f5b788d03e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209327349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3209327349
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3346057723
Short name T1295
Test name
Test status
Simulation time 785914545 ps
CPU time 12.88 seconds
Started May 16 12:46:46 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 210000 kb
Host smart-d3e3ddbe-06ce-4d95-af69-4f793b750a8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346057723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3346057723
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.924683545
Short name T1278
Test name
Test status
Simulation time 51134589823 ps
CPU time 159.5 seconds
Started May 16 12:46:44 PM PDT 24
Finished May 16 12:49:50 PM PDT 24
Peak memory 2046172 kb
Host smart-6aca199a-88e8-4340-bd4a-af251a5b9484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924683545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.924683545
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.4102895324
Short name T984
Test name
Test status
Simulation time 15653671924 ps
CPU time 731.74 seconds
Started May 16 12:46:51 PM PDT 24
Finished May 16 12:59:30 PM PDT 24
Peak memory 3764660 kb
Host smart-686e0693-d54b-4e96-8f8c-6cc16539bd03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102895324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.4102895324
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.4157479897
Short name T856
Test name
Test status
Simulation time 5331728846 ps
CPU time 6.58 seconds
Started May 16 12:46:45 PM PDT 24
Finished May 16 12:47:18 PM PDT 24
Peak memory 213148 kb
Host smart-d0d4a3f5-678a-4b96-8f82-49bd4c497da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157479897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.4157479897
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2591929195
Short name T861
Test name
Test status
Simulation time 60976898 ps
CPU time 0.65 seconds
Started May 16 12:47:08 PM PDT 24
Finished May 16 12:47:35 PM PDT 24
Peak memory 204620 kb
Host smart-ed14e743-878b-4fab-b090-c86e4ebb8205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591929195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2591929195
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.979953108
Short name T525
Test name
Test status
Simulation time 1113303761 ps
CPU time 13.48 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:37 PM PDT 24
Peak memory 240316 kb
Host smart-36739761-4741-417d-b556-584600aff2da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979953108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.979953108
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.513649207
Short name T562
Test name
Test status
Simulation time 8905787071 ps
CPU time 78.85 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 706052 kb
Host smart-d3cde018-3cde-41cb-a55d-150e19b6ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513649207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.513649207
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3390668537
Short name T1225
Test name
Test status
Simulation time 27835066034 ps
CPU time 77.22 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:48:41 PM PDT 24
Peak memory 727980 kb
Host smart-436e0096-311c-4581-8fed-66ca77d1117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390668537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3390668537
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.355132937
Short name T957
Test name
Test status
Simulation time 100395794 ps
CPU time 0.99 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 204600 kb
Host smart-73cf1fa3-ac65-4672-b964-8e97145815b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355132937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.355132937
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1746915020
Short name T1080
Test name
Test status
Simulation time 245163115 ps
CPU time 4.76 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 204964 kb
Host smart-98dbcc81-3d56-4b08-9100-ad24ca080c81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746915020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1746915020
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3308193324
Short name T1070
Test name
Test status
Simulation time 5524269054 ps
CPU time 152.75 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:49:56 PM PDT 24
Peak memory 1567624 kb
Host smart-568f987e-dcf6-4d78-b867-d6a835df7d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308193324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3308193324
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3557064262
Short name T662
Test name
Test status
Simulation time 483362178 ps
CPU time 18.26 seconds
Started May 16 12:46:55 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 204748 kb
Host smart-5f6f2c6b-f2b9-42f5-a70d-fa4a74f673f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557064262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3557064262
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2719303778
Short name T970
Test name
Test status
Simulation time 3476298453 ps
CPU time 36.43 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:59 PM PDT 24
Peak memory 418928 kb
Host smart-1221c8f8-7164-4981-a703-d6db49fb0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719303778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2719303778
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.729927012
Short name T731
Test name
Test status
Simulation time 26476889 ps
CPU time 0.67 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:22 PM PDT 24
Peak memory 204604 kb
Host smart-7b2457bc-18ec-44b2-92f3-b3598763948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729927012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.729927012
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.4272367566
Short name T572
Test name
Test status
Simulation time 6831639481 ps
CPU time 34.77 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:59 PM PDT 24
Peak memory 205120 kb
Host smart-e4b0c6da-ef91-4aa7-b96c-becfca9df4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272367566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.4272367566
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3776278065
Short name T445
Test name
Test status
Simulation time 9902454148 ps
CPU time 76.77 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 358664 kb
Host smart-5de600d4-a227-499b-8f78-d84c102b979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776278065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3776278065
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.4010938912
Short name T123
Test name
Test status
Simulation time 52906477879 ps
CPU time 322.58 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:52:46 PM PDT 24
Peak memory 1653380 kb
Host smart-64537476-1931-4268-8624-7a741db3de3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010938912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4010938912
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.445783507
Short name T880
Test name
Test status
Simulation time 517745121 ps
CPU time 8.44 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:32 PM PDT 24
Peak memory 212944 kb
Host smart-ed248f86-d288-4fa7-8389-ea92e9ee6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445783507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.445783507
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.58643040
Short name T920
Test name
Test status
Simulation time 1688641043 ps
CPU time 4.18 seconds
Started May 16 12:46:55 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 213008 kb
Host smart-e301d6c4-e43f-416f-8207-38d2ffe3dc74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58643040 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_bad_addr.58643040
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2849685665
Short name T975
Test name
Test status
Simulation time 10051360145 ps
CPU time 29.61 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:54 PM PDT 24
Peak memory 333648 kb
Host smart-b49d64ff-42d5-4590-94b2-965698bbe4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849685665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2849685665
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4137729154
Short name T1116
Test name
Test status
Simulation time 10252485076 ps
CPU time 10.22 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:47:34 PM PDT 24
Peak memory 255560 kb
Host smart-4af2f3ea-b04c-4920-8c8e-9337c214d32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137729154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4137729154
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3632412469
Short name T13
Test name
Test status
Simulation time 757142408 ps
CPU time 2.66 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:27 PM PDT 24
Peak memory 204276 kb
Host smart-10796f05-abda-44de-93bd-e7ce0753ef3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632412469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3632412469
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2112787756
Short name T852
Test name
Test status
Simulation time 3015086281 ps
CPU time 4.55 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:26 PM PDT 24
Peak memory 205888 kb
Host smart-89285e52-0ce8-475c-b54f-03d545472e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112787756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2112787756
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1271625943
Short name T360
Test name
Test status
Simulation time 9617940617 ps
CPU time 14.81 seconds
Started May 16 12:47:00 PM PDT 24
Finished May 16 12:47:41 PM PDT 24
Peak memory 353692 kb
Host smart-9c280d28-4140-4e76-a04f-4d2822d31752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271625943 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1271625943
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.286519171
Short name T399
Test name
Test status
Simulation time 1251014641 ps
CPU time 21.55 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:47:45 PM PDT 24
Peak memory 204852 kb
Host smart-9996a3be-2cd2-49f3-b20e-393a64337bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286519171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.286519171
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1598883360
Short name T962
Test name
Test status
Simulation time 1288612380 ps
CPU time 5.31 seconds
Started May 16 12:46:57 PM PDT 24
Finished May 16 12:47:29 PM PDT 24
Peak memory 204976 kb
Host smart-2eb90694-7d44-4ceb-bdbd-b95bec3fd3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598883360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1598883360
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.646561315
Short name T1120
Test name
Test status
Simulation time 11112005950 ps
CPU time 6.18 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:28 PM PDT 24
Peak memory 204992 kb
Host smart-4fcb81af-c012-4bee-900f-3988666697ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646561315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.646561315
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1151655483
Short name T30
Test name
Test status
Simulation time 24907832817 ps
CPU time 154.86 seconds
Started May 16 12:46:58 PM PDT 24
Finished May 16 12:49:59 PM PDT 24
Peak memory 1247776 kb
Host smart-58ea6770-499c-433d-b51f-5a847318b3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151655483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1151655483
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.847211771
Short name T611
Test name
Test status
Simulation time 2517686686 ps
CPU time 6.8 seconds
Started May 16 12:46:56 PM PDT 24
Finished May 16 12:47:29 PM PDT 24
Peak memory 213280 kb
Host smart-ec577b64-24b5-4de6-9427-339e834f1027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847211771 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.847211771
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.680132844
Short name T757
Test name
Test status
Simulation time 124127941 ps
CPU time 0.64 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:38 PM PDT 24
Peak memory 204524 kb
Host smart-10fd83a6-bc90-49c5-9113-5d5183c73bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680132844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.680132844
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2185133469
Short name T1318
Test name
Test status
Simulation time 227843861 ps
CPU time 3.68 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:47:42 PM PDT 24
Peak memory 219500 kb
Host smart-3b44a4dd-a15f-44ca-a791-a5140de05e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185133469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2185133469
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3567430788
Short name T1217
Test name
Test status
Simulation time 354617812 ps
CPU time 18.55 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:47:57 PM PDT 24
Peak memory 280048 kb
Host smart-f352d759-d156-4c43-8bf9-29bd2538e5c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567430788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3567430788
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.4276727981
Short name T926
Test name
Test status
Simulation time 8227053584 ps
CPU time 65.43 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 719012 kb
Host smart-621d6bc5-3a18-4433-9e4f-ea6411c26a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276727981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.4276727981
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3099142500
Short name T1000
Test name
Test status
Simulation time 11078079763 ps
CPU time 92.13 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:49:10 PM PDT 24
Peak memory 771600 kb
Host smart-2d766f4c-15ef-44b8-ad19-dacd03339870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099142500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3099142500
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.358522673
Short name T633
Test name
Test status
Simulation time 641029459 ps
CPU time 3.05 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:40 PM PDT 24
Peak memory 204904 kb
Host smart-f888e8f3-0cd9-4fc8-9486-ab04fcfad1b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358522673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
358522673
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2904196105
Short name T672
Test name
Test status
Simulation time 9469569986 ps
CPU time 349.36 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:53:24 PM PDT 24
Peak memory 1337384 kb
Host smart-008bbf50-e377-41c9-98e5-454bc2f49908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904196105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2904196105
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2707106957
Short name T678
Test name
Test status
Simulation time 739511507 ps
CPU time 3.66 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:40 PM PDT 24
Peak memory 205012 kb
Host smart-c7f4f942-261f-424c-a29c-1a386f4d3dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707106957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2707106957
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.1644711088
Short name T127
Test name
Test status
Simulation time 54372500 ps
CPU time 0.67 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:47:36 PM PDT 24
Peak memory 204708 kb
Host smart-23212c4b-dd57-4efd-b93d-f29fb90bd4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644711088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1644711088
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.236843006
Short name T317
Test name
Test status
Simulation time 2883788765 ps
CPU time 7.4 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:45 PM PDT 24
Peak memory 229556 kb
Host smart-b4257eb0-aa36-4365-901b-e878d8fb0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236843006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.236843006
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.902654075
Short name T750
Test name
Test status
Simulation time 1805553710 ps
CPU time 88.08 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 343540 kb
Host smart-3b42c209-35b5-4270-90cc-84fd7267d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902654075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.902654075
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3214315048
Short name T933
Test name
Test status
Simulation time 2773829473 ps
CPU time 13.44 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:51 PM PDT 24
Peak memory 220216 kb
Host smart-c1e324f2-258f-4b9d-afcd-d490e28c1a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214315048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3214315048
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1822039386
Short name T888
Test name
Test status
Simulation time 5093008597 ps
CPU time 4.03 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:41 PM PDT 24
Peak memory 213296 kb
Host smart-caaa8d9e-0725-4d36-9c47-92343b27ea28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822039386 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1822039386
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1276565630
Short name T598
Test name
Test status
Simulation time 10089769162 ps
CPU time 10.99 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:47:50 PM PDT 24
Peak memory 243592 kb
Host smart-16afe0b1-68f5-48f9-99ae-726a6a71d268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276565630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1276565630
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2854105355
Short name T425
Test name
Test status
Simulation time 10456761754 ps
CPU time 14.45 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:52 PM PDT 24
Peak memory 285464 kb
Host smart-0dfc0900-4181-44a3-8416-1ea58e01b88e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854105355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2854105355
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.4264775721
Short name T25
Test name
Test status
Simulation time 305801162 ps
CPU time 2.35 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:38 PM PDT 24
Peak memory 205060 kb
Host smart-39a90a89-7a1f-4118-80fb-beb499bbd860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264775721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.4264775721
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4124489771
Short name T1066
Test name
Test status
Simulation time 1292813283 ps
CPU time 6.42 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:47:46 PM PDT 24
Peak memory 209752 kb
Host smart-6e6ce7df-453f-4cab-98aa-91c7430ad016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124489771 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4124489771
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2913722742
Short name T468
Test name
Test status
Simulation time 7454744760 ps
CPU time 8.88 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:47:48 PM PDT 24
Peak memory 204704 kb
Host smart-07aa3588-4b48-4180-8026-3cdf14236aca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913722742 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2913722742
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1902911653
Short name T827
Test name
Test status
Simulation time 9420033131 ps
CPU time 42.02 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 205068 kb
Host smart-f55215e3-5583-4f8b-b66f-ee09b73cf5df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902911653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1902911653
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1490437867
Short name T270
Test name
Test status
Simulation time 380251470 ps
CPU time 15.21 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:51 PM PDT 24
Peak memory 204876 kb
Host smart-57190a9c-a84e-4e4f-b24e-32050aa11fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490437867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1490437867
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2883675427
Short name T1064
Test name
Test status
Simulation time 53734889220 ps
CPU time 154.54 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:50:14 PM PDT 24
Peak memory 1937952 kb
Host smart-98568370-a53b-432f-96ea-a17611671db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883675427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2883675427
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.4066829390
Short name T691
Test name
Test status
Simulation time 6626634337 ps
CPU time 124.48 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:49:41 PM PDT 24
Peak memory 1368512 kb
Host smart-869b769a-b52c-45f1-9139-e424f95045fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066829390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.4066829390
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1245475490
Short name T615
Test name
Test status
Simulation time 2495337924 ps
CPU time 7.37 seconds
Started May 16 12:47:08 PM PDT 24
Finished May 16 12:47:42 PM PDT 24
Peak memory 219416 kb
Host smart-c9b8786b-32b2-455e-926d-fd64a79c033a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245475490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1245475490
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1249415290
Short name T1128
Test name
Test status
Simulation time 19504286 ps
CPU time 0.62 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 204664 kb
Host smart-f18e715f-685b-4ff4-9304-25633abeddd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249415290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1249415290
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1952026877
Short name T576
Test name
Test status
Simulation time 343226478 ps
CPU time 2.74 seconds
Started May 16 12:47:08 PM PDT 24
Finished May 16 12:47:37 PM PDT 24
Peak memory 213284 kb
Host smart-a66b2d73-028c-47a4-b584-4df571e990b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952026877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1952026877
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.123636846
Short name T1010
Test name
Test status
Simulation time 397312185 ps
CPU time 19.69 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:47:55 PM PDT 24
Peak memory 272800 kb
Host smart-d7cc83c9-bb83-4ed7-8078-56e93d7c9d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123636846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.123636846
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.285262182
Short name T746
Test name
Test status
Simulation time 1932255195 ps
CPU time 66.07 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:48:41 PM PDT 24
Peak memory 664324 kb
Host smart-9c6f4852-34b2-432a-9ddb-cc659a210468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285262182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.285262182
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1358236776
Short name T822
Test name
Test status
Simulation time 5860915478 ps
CPU time 98.08 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:49:15 PM PDT 24
Peak memory 837756 kb
Host smart-045a6ea8-b2a3-4ded-a50c-b8d6e0ff419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358236776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1358236776
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.191794539
Short name T389
Test name
Test status
Simulation time 402950450 ps
CPU time 1 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:38 PM PDT 24
Peak memory 204984 kb
Host smart-28b4c124-f403-40c5-9647-69855557dbd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191794539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.191794539
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4091245758
Short name T719
Test name
Test status
Simulation time 409780363 ps
CPU time 3.43 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 204948 kb
Host smart-0f067452-d2d9-4de4-b9c7-9ea84e03ff4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091245758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4091245758
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2501721450
Short name T1005
Test name
Test status
Simulation time 3305810286 ps
CPU time 84.51 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:49:00 PM PDT 24
Peak memory 994516 kb
Host smart-34132271-87b5-43d8-a0d6-7a21677510f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501721450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2501721450
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.138576639
Short name T693
Test name
Test status
Simulation time 712478249 ps
CPU time 8.69 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:46 PM PDT 24
Peak memory 204976 kb
Host smart-2200a2c0-ae2c-4e32-8cbc-b7c0681d0071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138576639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.138576639
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2145369933
Short name T991
Test name
Test status
Simulation time 2182371621 ps
CPU time 33.78 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:48:13 PM PDT 24
Peak memory 383080 kb
Host smart-d57e54d8-3f06-42ee-b377-d85de0ba90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145369933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2145369933
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1640455826
Short name T76
Test name
Test status
Simulation time 153161346 ps
CPU time 0.74 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:37 PM PDT 24
Peak memory 204596 kb
Host smart-d8f69829-c3e4-4233-8b69-32b3f8226de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640455826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1640455826
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3805451136
Short name T977
Test name
Test status
Simulation time 7282325120 ps
CPU time 73.97 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:48:50 PM PDT 24
Peak memory 265296 kb
Host smart-64200294-0d2d-495a-bfe9-b16bb4edbe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805451136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3805451136
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.4037594350
Short name T799
Test name
Test status
Simulation time 6296761943 ps
CPU time 76.17 seconds
Started May 16 12:47:07 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 326924 kb
Host smart-25dbb321-69f4-45ae-a74a-82d4412fda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037594350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4037594350
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2020202558
Short name T119
Test name
Test status
Simulation time 8157955135 ps
CPU time 201.63 seconds
Started May 16 12:47:09 PM PDT 24
Finished May 16 12:50:56 PM PDT 24
Peak memory 1151848 kb
Host smart-c0713893-055f-401c-818b-d7a79b387eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020202558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2020202558
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3558766719
Short name T918
Test name
Test status
Simulation time 1158355441 ps
CPU time 10.87 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:48 PM PDT 24
Peak memory 215080 kb
Host smart-0626b285-e395-4aa2-a8b5-a5e6921ebbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558766719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3558766719
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3603924840
Short name T1322
Test name
Test status
Simulation time 2589944046 ps
CPU time 3.83 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:40 PM PDT 24
Peak memory 213236 kb
Host smart-4cedf57c-54d0-4f01-83c2-8c77f3bfa70a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603924840 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3603924840
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2884199926
Short name T532
Test name
Test status
Simulation time 11366468960 ps
CPU time 5.81 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:44 PM PDT 24
Peak memory 238072 kb
Host smart-8ec26a67-3b4b-4c5f-afb3-6f333187038a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884199926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2884199926
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.770245033
Short name T938
Test name
Test status
Simulation time 10206558158 ps
CPU time 35.42 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:48:15 PM PDT 24
Peak memory 413476 kb
Host smart-808ce533-aa9a-403d-8e0c-a15990721d1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770245033 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.770245033
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1677891689
Short name T301
Test name
Test status
Simulation time 1532579800 ps
CPU time 2.35 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:39 PM PDT 24
Peak memory 205024 kb
Host smart-b994f6df-b193-4bf8-a7da-ea23fa561789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677891689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1677891689
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3591929437
Short name T365
Test name
Test status
Simulation time 5093763717 ps
CPU time 7.78 seconds
Started May 16 12:47:11 PM PDT 24
Finished May 16 12:47:45 PM PDT 24
Peak memory 221340 kb
Host smart-52fedfcc-1369-45ef-86ef-e91eabcce059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591929437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3591929437
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2811477647
Short name T498
Test name
Test status
Simulation time 17430087096 ps
CPU time 48.32 seconds
Started May 16 12:47:13 PM PDT 24
Finished May 16 12:48:28 PM PDT 24
Peak memory 1102924 kb
Host smart-e35c4de7-7a80-4f38-8639-77e6546b62f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811477647 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2811477647
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1792575652
Short name T166
Test name
Test status
Simulation time 808986740 ps
CPU time 32.52 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:48:11 PM PDT 24
Peak memory 204984 kb
Host smart-f076b181-30f6-4db7-bf6d-23654e5643a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792575652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1792575652
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3319227282
Short name T391
Test name
Test status
Simulation time 1104641557 ps
CPU time 47.46 seconds
Started May 16 12:47:12 PM PDT 24
Finished May 16 12:48:26 PM PDT 24
Peak memory 205412 kb
Host smart-53e1e347-1c0c-4c3c-a7ed-754e6c1888ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319227282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3319227282
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2754926549
Short name T342
Test name
Test status
Simulation time 12772189426 ps
CPU time 13.82 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:50 PM PDT 24
Peak memory 204936 kb
Host smart-b1f1088f-5739-4e17-a4fb-7dc3a85c1777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754926549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2754926549
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3987274213
Short name T770
Test name
Test status
Simulation time 32871976582 ps
CPU time 2963.17 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 01:37:00 PM PDT 24
Peak memory 7912444 kb
Host smart-68f27f39-7ec9-4cf8-b19a-3d2acd5aefda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987274213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3987274213
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.123022815
Short name T952
Test name
Test status
Simulation time 5373734720 ps
CPU time 6.9 seconds
Started May 16 12:47:10 PM PDT 24
Finished May 16 12:47:43 PM PDT 24
Peak memory 220448 kb
Host smart-e1ca24b5-d52b-432e-bcdb-35175c62d82f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123022815 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.123022815
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3083759345
Short name T986
Test name
Test status
Simulation time 23943593 ps
CPU time 0.65 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:47:49 PM PDT 24
Peak memory 204616 kb
Host smart-36ab31b8-2e6a-4cfa-b771-e04a1df7a00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083759345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3083759345
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3577240920
Short name T352
Test name
Test status
Simulation time 215570155 ps
CPU time 1.68 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:47:51 PM PDT 24
Peak memory 213224 kb
Host smart-ea78a27a-8546-4fa1-88a7-852c19039086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577240920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3577240920
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.4001213671
Short name T554
Test name
Test status
Simulation time 1663583737 ps
CPU time 8.34 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:57 PM PDT 24
Peak memory 292680 kb
Host smart-9312584a-9223-425e-82e0-3315864dbb56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001213671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.4001213671
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.553230242
Short name T46
Test name
Test status
Simulation time 2349057352 ps
CPU time 180.56 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:50:51 PM PDT 24
Peak memory 766416 kb
Host smart-95bd1acc-0d74-4834-8866-e619301623a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553230242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.553230242
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.140636918
Short name T982
Test name
Test status
Simulation time 1739778012 ps
CPU time 49.79 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:48:37 PM PDT 24
Peak memory 584564 kb
Host smart-fdb68548-06e8-4555-8625-afb9c876a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140636918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.140636918
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1910274822
Short name T632
Test name
Test status
Simulation time 182303311 ps
CPU time 1.16 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:49 PM PDT 24
Peak memory 204872 kb
Host smart-475a65b8-9e44-4d81-afe8-1e1dc46faa79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910274822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1910274822
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.584922187
Short name T1184
Test name
Test status
Simulation time 177178243 ps
CPU time 4.43 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:52 PM PDT 24
Peak memory 236308 kb
Host smart-02ec1ccd-c65a-4c94-8c10-4e715032d4ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584922187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
584922187
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.292986529
Short name T1237
Test name
Test status
Simulation time 11578772266 ps
CPU time 71.35 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:49:01 PM PDT 24
Peak memory 868964 kb
Host smart-8e649803-58eb-4dce-a188-fd9fd0984c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292986529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.292986529
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.681038036
Short name T1074
Test name
Test status
Simulation time 971470504 ps
CPU time 7.22 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:56 PM PDT 24
Peak memory 205016 kb
Host smart-81f55a90-f21d-42f3-9dc7-a3abadad7a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681038036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.681038036
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.811720856
Short name T285
Test name
Test status
Simulation time 2068244591 ps
CPU time 47.75 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 301828 kb
Host smart-c02354b8-f184-4687-886c-c4dcd7fcde2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811720856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.811720856
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.2881211156
Short name T1264
Test name
Test status
Simulation time 29168780 ps
CPU time 0.68 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:49 PM PDT 24
Peak memory 204656 kb
Host smart-6308d006-4b1b-4c4a-a30a-f7f925f9efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881211156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2881211156
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1236645861
Short name T331
Test name
Test status
Simulation time 12836479013 ps
CPU time 97.21 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:49:28 PM PDT 24
Peak memory 910052 kb
Host smart-81561412-8541-4712-846a-2748837afc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236645861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1236645861
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2250152389
Short name T1170
Test name
Test status
Simulation time 6253933271 ps
CPU time 69.75 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:49:00 PM PDT 24
Peak memory 258832 kb
Host smart-83a503cc-65c0-4bdf-9dae-be222f5da4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250152389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2250152389
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2904662809
Short name T260
Test name
Test status
Simulation time 41361145633 ps
CPU time 1843.53 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 01:18:32 PM PDT 24
Peak memory 1985076 kb
Host smart-58e84ef5-c8a1-4887-a6b0-d4367b59c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904662809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2904662809
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1500748286
Short name T1098
Test name
Test status
Simulation time 2398651191 ps
CPU time 27.3 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:48:14 PM PDT 24
Peak memory 213340 kb
Host smart-1cda0731-c550-48fb-b60a-ced10df8d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500748286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1500748286
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1613780019
Short name T1112
Test name
Test status
Simulation time 940854589 ps
CPU time 3.99 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 204888 kb
Host smart-8af0607d-1916-49e2-a3f1-616eececd2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613780019 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1613780019
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1572279491
Short name T491
Test name
Test status
Simulation time 10238046686 ps
CPU time 13.37 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:48:02 PM PDT 24
Peak memory 262212 kb
Host smart-2875e30f-9439-48da-a9b2-f1e3bf2ef810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572279491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1572279491
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3528864200
Short name T932
Test name
Test status
Simulation time 10076779238 ps
CPU time 75.17 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:49:06 PM PDT 24
Peak memory 520936 kb
Host smart-1e2177b6-d03d-4075-a4c2-8f69d203eb27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528864200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3528864200
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3887713948
Short name T24
Test name
Test status
Simulation time 3942573735 ps
CPU time 2.5 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 205032 kb
Host smart-14dd84da-1ef3-4384-b8e8-b6562fbd1d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887713948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3887713948
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3135729250
Short name T1162
Test name
Test status
Simulation time 7517731544 ps
CPU time 6.7 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:47:57 PM PDT 24
Peak memory 211768 kb
Host smart-19c031ac-5c22-4a3d-90a0-929300ed969d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135729250 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3135729250
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.4030688359
Short name T596
Test name
Test status
Simulation time 5466656794 ps
CPU time 13.12 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:48:02 PM PDT 24
Peak memory 205004 kb
Host smart-a9b3f3e3-9882-4042-bd9d-ac9d67a4f5da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030688359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.4030688359
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.538921116
Short name T517
Test name
Test status
Simulation time 1186692469 ps
CPU time 44.83 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:48:32 PM PDT 24
Peak memory 204916 kb
Host smart-f1be2f90-d44f-4db5-b20c-719e2039ad1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538921116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.538921116
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1890195422
Short name T288
Test name
Test status
Simulation time 4196669361 ps
CPU time 17.03 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 220068 kb
Host smart-aa25426b-d302-4e5f-8a4d-862d1224a6d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890195422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1890195422
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.112160575
Short name T456
Test name
Test status
Simulation time 12168980289 ps
CPU time 12.02 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:48:02 PM PDT 24
Peak memory 205040 kb
Host smart-13f43327-393e-435f-856a-c280ab84a694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112160575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.112160575
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1571125815
Short name T653
Test name
Test status
Simulation time 15224024681 ps
CPU time 194.47 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:51:02 PM PDT 24
Peak memory 840584 kb
Host smart-a93840cf-6ef1-4b08-9d3a-d106df710ad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571125815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1571125815
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.753581292
Short name T718
Test name
Test status
Simulation time 7256156530 ps
CPU time 7.77 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:47:58 PM PDT 24
Peak memory 221280 kb
Host smart-d4d8cd77-7659-4d88-8063-a9f0dff5bc3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753581292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.753581292
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3795148366
Short name T712
Test name
Test status
Simulation time 38857566 ps
CPU time 0.61 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:44:54 PM PDT 24
Peak memory 204668 kb
Host smart-cb7ced85-d015-47f9-9734-c31a6083df0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795148366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3795148366
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1875511935
Short name T1205
Test name
Test status
Simulation time 210131372 ps
CPU time 2.95 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:44:59 PM PDT 24
Peak memory 213148 kb
Host smart-afb12ca0-83a4-403c-b299-f9e78cca46cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875511935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1875511935
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2432643955
Short name T1056
Test name
Test status
Simulation time 1759840156 ps
CPU time 24.02 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:45:19 PM PDT 24
Peak memory 307744 kb
Host smart-378d0ffe-f77e-49a2-a268-0358633db0a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432643955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2432643955
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1380894252
Short name T316
Test name
Test status
Simulation time 5843013709 ps
CPU time 102.76 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:46:41 PM PDT 24
Peak memory 794816 kb
Host smart-9dd23a38-d52a-4427-a325-c7ddbdaaf7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380894252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1380894252
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2880296155
Short name T144
Test name
Test status
Simulation time 3431864752 ps
CPU time 108.48 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:46:39 PM PDT 24
Peak memory 542500 kb
Host smart-10ca0ecf-6d92-451b-97d9-10b5b1a2efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880296155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2880296155
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2322920955
Short name T1260
Test name
Test status
Simulation time 538845489 ps
CPU time 1.02 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:44:54 PM PDT 24
Peak memory 204776 kb
Host smart-a05b8f08-f23c-4a4a-a916-a383aad913af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322920955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2322920955
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3807161343
Short name T640
Test name
Test status
Simulation time 775235161 ps
CPU time 11.86 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:45:03 PM PDT 24
Peak memory 244012 kb
Host smart-93eaf5f9-e358-4a10-a9b3-e3f1f66d99b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807161343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3807161343
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4234209714
Short name T18
Test name
Test status
Simulation time 13108691579 ps
CPU time 72.47 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 736424 kb
Host smart-62398be8-ba0e-4214-a471-31e7e0eb6903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234209714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4234209714
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3628316402
Short name T905
Test name
Test status
Simulation time 734054956 ps
CPU time 9.7 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:45:01 PM PDT 24
Peak memory 204960 kb
Host smart-6c325ef6-23af-42e5-8057-b5715089faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628316402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3628316402
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.784691339
Short name T1284
Test name
Test status
Simulation time 1504883054 ps
CPU time 68.41 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:45:54 PM PDT 24
Peak memory 327968 kb
Host smart-5088c321-bc1b-4722-9f05-efee99640e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784691339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.784691339
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3652414704
Short name T1220
Test name
Test status
Simulation time 34724022 ps
CPU time 0.66 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:44:47 PM PDT 24
Peak memory 204672 kb
Host smart-297f3219-5d87-4523-b442-d5f527ab64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652414704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3652414704
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.919258924
Short name T850
Test name
Test status
Simulation time 12110481909 ps
CPU time 31.46 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 455232 kb
Host smart-2d58bf5f-1627-4dfe-8851-7124b016b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919258924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.919258924
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1072941022
Short name T773
Test name
Test status
Simulation time 5638912874 ps
CPU time 65.13 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:45:53 PM PDT 24
Peak memory 310404 kb
Host smart-28997ebf-0f91-4a17-bacf-0205012c531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072941022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1072941022
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.1264713737
Short name T1328
Test name
Test status
Simulation time 39050242717 ps
CPU time 590.56 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:54:46 PM PDT 24
Peak memory 1829244 kb
Host smart-21cc03b8-6b8f-4344-a195-a4e148c2c28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264713737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.1264713737
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.374525256
Short name T941
Test name
Test status
Simulation time 1561919884 ps
CPU time 34.67 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:29 PM PDT 24
Peak memory 213112 kb
Host smart-b9bc8bda-7239-4a49-9344-d9e07fffd27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374525256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.374525256
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1680541293
Short name T177
Test name
Test status
Simulation time 83731910 ps
CPU time 0.93 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:44:58 PM PDT 24
Peak memory 223096 kb
Host smart-fdf41dc3-65a7-491f-8304-d0b3210983a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680541293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1680541293
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.494547922
Short name T960
Test name
Test status
Simulation time 1762044815 ps
CPU time 4.52 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:44:58 PM PDT 24
Peak memory 205024 kb
Host smart-e2d3231a-7a90-49d2-bfa9-adc1eabf2ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494547922 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.494547922
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1040357186
Short name T743
Test name
Test status
Simulation time 10171927363 ps
CPU time 36.93 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:45:27 PM PDT 24
Peak memory 362484 kb
Host smart-6ab8db28-0b39-4b55-8401-31d002bed0ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040357186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1040357186
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1914382368
Short name T363
Test name
Test status
Simulation time 10331884167 ps
CPU time 17.75 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:45:05 PM PDT 24
Peak memory 281228 kb
Host smart-cbe116d2-d5d6-4d7b-b445-a93f04bbfe44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914382368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1914382368
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1011219271
Short name T945
Test name
Test status
Simulation time 1612608203 ps
CPU time 2.39 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:44:49 PM PDT 24
Peak memory 204996 kb
Host smart-72545b1f-c071-49e4-851b-6329465202b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011219271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1011219271
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1175247288
Short name T589
Test name
Test status
Simulation time 3020624053 ps
CPU time 4.33 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:45:03 PM PDT 24
Peak memory 205724 kb
Host smart-2208b40b-a03d-44db-b51f-aae7e70f61d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175247288 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1175247288
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3596275639
Short name T1072
Test name
Test status
Simulation time 11448148051 ps
CPU time 23.46 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:45:13 PM PDT 24
Peak memory 771532 kb
Host smart-665ba92d-42cc-4663-bffd-98f8db010067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596275639 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3596275639
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.865227503
Short name T1169
Test name
Test status
Simulation time 2558087872 ps
CPU time 8.8 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:04 PM PDT 24
Peak memory 205104 kb
Host smart-06aece83-18ec-4f78-8a6b-3ed75c43025f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865227503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.865227503
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.363098035
Short name T450
Test name
Test status
Simulation time 2550750301 ps
CPU time 42.52 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:38 PM PDT 24
Peak memory 205832 kb
Host smart-bf7eda91-a74d-42aa-b189-4ac297156467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363098035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.363098035
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.945228978
Short name T1013
Test name
Test status
Simulation time 8341030554 ps
CPU time 9.25 seconds
Started May 16 12:44:34 PM PDT 24
Finished May 16 12:44:57 PM PDT 24
Peak memory 205012 kb
Host smart-8dec6e3e-800d-473d-b34c-e36a60668631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945228978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.945228978
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1520926908
Short name T1243
Test name
Test status
Simulation time 29166459541 ps
CPU time 53.34 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:48 PM PDT 24
Peak memory 629220 kb
Host smart-31922bf9-4a1f-4ae9-8b1d-d4eca20b4fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520926908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1520926908
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.178405817
Short name T643
Test name
Test status
Simulation time 5739157128 ps
CPU time 7.61 seconds
Started May 16 12:44:35 PM PDT 24
Finished May 16 12:44:56 PM PDT 24
Peak memory 205068 kb
Host smart-32917fb9-2fcc-4ad0-8da7-6068a46ab471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178405817 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.178405817
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3238729923
Short name T1118
Test name
Test status
Simulation time 53799231 ps
CPU time 0.61 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:00 PM PDT 24
Peak memory 204612 kb
Host smart-15504bfd-048d-4d4e-8e88-693070c8e6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238729923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3238729923
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1689521495
Short name T830
Test name
Test status
Simulation time 889986099 ps
CPU time 3.07 seconds
Started May 16 12:47:28 PM PDT 24
Finished May 16 12:47:55 PM PDT 24
Peak memory 226004 kb
Host smart-c0111cc9-262f-4434-9768-15b1ad76d10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689521495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1689521495
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1401813601
Short name T402
Test name
Test status
Simulation time 203778442 ps
CPU time 4.55 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:47:54 PM PDT 24
Peak memory 241356 kb
Host smart-ba4e1dd8-5d7b-4ce9-a23c-aa05c7adda99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401813601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1401813601
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3286493929
Short name T556
Test name
Test status
Simulation time 2216038591 ps
CPU time 63.96 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:48:54 PM PDT 24
Peak memory 522884 kb
Host smart-3f0bca49-cdf9-426e-8394-0f2d3417faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286493929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3286493929
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2452365293
Short name T354
Test name
Test status
Simulation time 2789232859 ps
CPU time 83.44 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:49:12 PM PDT 24
Peak memory 852744 kb
Host smart-cc4e821b-2e12-439a-b685-de70ad82bf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452365293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2452365293
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3281909279
Short name T234
Test name
Test status
Simulation time 696174111 ps
CPU time 1.05 seconds
Started May 16 12:47:24 PM PDT 24
Finished May 16 12:47:51 PM PDT 24
Peak memory 204936 kb
Host smart-18267b9b-ecc8-4591-bd02-9dfe8e682356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281909279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3281909279
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2620814150
Short name T1185
Test name
Test status
Simulation time 245403272 ps
CPU time 3.4 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:47:54 PM PDT 24
Peak memory 204928 kb
Host smart-5f7cd0aa-a546-4c74-8633-e6144dcfbc49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620814150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2620814150
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3213999008
Short name T1040
Test name
Test status
Simulation time 6660535406 ps
CPU time 77.24 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:49:05 PM PDT 24
Peak memory 1018092 kb
Host smart-9f6f2e3b-f3fa-484a-84e5-00e751720f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213999008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3213999008
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1321277876
Short name T275
Test name
Test status
Simulation time 268166898 ps
CPU time 3.69 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 204916 kb
Host smart-54c8e684-de47-4f6c-b35b-a2e94942b96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321277876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1321277876
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1846256051
Short name T1289
Test name
Test status
Simulation time 975218351 ps
CPU time 17.41 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:21 PM PDT 24
Peak memory 265128 kb
Host smart-e6a2a2b3-1655-4d52-aba1-9fc0c218de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846256051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1846256051
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.449283502
Short name T872
Test name
Test status
Simulation time 44567279 ps
CPU time 0.66 seconds
Started May 16 12:47:22 PM PDT 24
Finished May 16 12:47:48 PM PDT 24
Peak memory 204764 kb
Host smart-77d48704-678d-44b7-aa20-98896b6f2c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449283502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.449283502
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.322226848
Short name T810
Test name
Test status
Simulation time 11985444251 ps
CPU time 478.11 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:55:48 PM PDT 24
Peak memory 205084 kb
Host smart-5c54c08b-e6d9-4c90-b4d7-67a3d2b509b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322226848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.322226848
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1046311458
Short name T347
Test name
Test status
Simulation time 1207385768 ps
CPU time 57.38 seconds
Started May 16 12:47:23 PM PDT 24
Finished May 16 12:48:45 PM PDT 24
Peak memory 337172 kb
Host smart-86520efa-d1bb-4b55-80df-a9b64d6484c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046311458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1046311458
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.1872114432
Short name T885
Test name
Test status
Simulation time 7951839692 ps
CPU time 787.75 seconds
Started May 16 12:47:28 PM PDT 24
Finished May 16 01:01:00 PM PDT 24
Peak memory 1381508 kb
Host smart-8d1616c4-eb76-4df3-878e-d69356deaa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872114432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1872114432
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1307710576
Short name T1301
Test name
Test status
Simulation time 3793489377 ps
CPU time 40.2 seconds
Started May 16 12:47:27 PM PDT 24
Finished May 16 12:48:32 PM PDT 24
Peak memory 213252 kb
Host smart-11a54d49-baff-4b0b-bdb2-14058b6cd983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307710576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1307710576
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.4150900203
Short name T28
Test name
Test status
Simulation time 1030354376 ps
CPU time 4.95 seconds
Started May 16 12:47:41 PM PDT 24
Finished May 16 12:48:08 PM PDT 24
Peak memory 213132 kb
Host smart-1faf78d0-b9df-4dba-9af0-189a5ee3cd89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150900203 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.4150900203
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1025662891
Short name T357
Test name
Test status
Simulation time 10115265422 ps
CPU time 13.25 seconds
Started May 16 12:47:43 PM PDT 24
Finished May 16 12:48:19 PM PDT 24
Peak memory 259720 kb
Host smart-38e64be3-665e-4749-ae81-98e1fb56636d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025662891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1025662891
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2291463713
Short name T476
Test name
Test status
Simulation time 10101132691 ps
CPU time 85.59 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 485072 kb
Host smart-5ef99052-8b5a-4e82-a127-ed84c6413120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291463713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2291463713
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3845270063
Short name T548
Test name
Test status
Simulation time 558656462 ps
CPU time 3.03 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:03 PM PDT 24
Peak memory 204940 kb
Host smart-061b2d67-e435-43f6-9380-13bc4c13be23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845270063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3845270063
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.750445669
Short name T1348
Test name
Test status
Simulation time 592924376 ps
CPU time 3.93 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 204972 kb
Host smart-b1add5f5-496f-4625-8140-eb3e49b1fa48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750445669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.750445669
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.135530557
Short name T458
Test name
Test status
Simulation time 10189174397 ps
CPU time 22.45 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:22 PM PDT 24
Peak memory 547184 kb
Host smart-a4769030-3096-472f-b77f-719411c39430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135530557 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.135530557
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3132098023
Short name T377
Test name
Test status
Simulation time 874489234 ps
CPU time 33.96 seconds
Started May 16 12:47:26 PM PDT 24
Finished May 16 12:48:24 PM PDT 24
Peak memory 204924 kb
Host smart-5633fd23-e333-4c1b-9726-785935b0fc6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132098023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3132098023
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4279044771
Short name T560
Test name
Test status
Simulation time 1281160696 ps
CPU time 24.75 seconds
Started May 16 12:47:28 PM PDT 24
Finished May 16 12:48:17 PM PDT 24
Peak memory 220476 kb
Host smart-62712e3c-8a4d-4508-a0aa-fa9a9202d5f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279044771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4279044771
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3190354017
Short name T493
Test name
Test status
Simulation time 11269084943 ps
CPU time 11.54 seconds
Started May 16 12:47:25 PM PDT 24
Finished May 16 12:48:01 PM PDT 24
Peak memory 205044 kb
Host smart-3f4da5d0-b476-48f4-b4d2-9760fcced473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190354017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3190354017
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1515102289
Short name T353
Test name
Test status
Simulation time 5631357338 ps
CPU time 6.88 seconds
Started May 16 12:47:37 PM PDT 24
Finished May 16 12:48:07 PM PDT 24
Peak memory 212188 kb
Host smart-1f3f45f0-14f2-42a7-8ab8-f6a4bb59bf47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515102289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1515102289
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1965157867
Short name T1152
Test name
Test status
Simulation time 19946691 ps
CPU time 0.66 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:48:05 PM PDT 24
Peak memory 204620 kb
Host smart-ddf294a4-fda1-4fe5-9d55-54e1ba7a81f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965157867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1965157867
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2986965596
Short name T539
Test name
Test status
Simulation time 152924075 ps
CPU time 1.62 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 213248 kb
Host smart-8fe470f7-2b67-44d0-ba5f-ea47f98250b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986965596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2986965596
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3719591399
Short name T442
Test name
Test status
Simulation time 1298660816 ps
CPU time 16.37 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 268352 kb
Host smart-717effba-e882-4967-b05c-34565884561f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719591399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3719591399
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.382314850
Short name T1163
Test name
Test status
Simulation time 6713596183 ps
CPU time 82.61 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:49:23 PM PDT 24
Peak memory 374424 kb
Host smart-3c5712b1-808c-45a8-9e11-1fe0ac5ed071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382314850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.382314850
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1332143201
Short name T853
Test name
Test status
Simulation time 26828163332 ps
CPU time 160.12 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:50:40 PM PDT 24
Peak memory 677704 kb
Host smart-1623b5aa-9ada-4443-a586-023a8a675330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332143201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1332143201
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3001175987
Short name T996
Test name
Test status
Simulation time 118603519 ps
CPU time 0.95 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 204768 kb
Host smart-3e8ed1d4-a5e1-4bec-bca0-e0ffad103ef7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001175987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3001175987
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2657518356
Short name T1311
Test name
Test status
Simulation time 191429469 ps
CPU time 11.06 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:11 PM PDT 24
Peak memory 240824 kb
Host smart-87aaed21-8246-45e8-89b8-73b27262d598
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657518356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2657518356
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3478288392
Short name T542
Test name
Test status
Simulation time 3360923712 ps
CPU time 87.54 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:49:32 PM PDT 24
Peak memory 940300 kb
Host smart-679d1a20-2893-4c86-abdd-19f40964eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478288392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3478288392
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2074213519
Short name T1310
Test name
Test status
Simulation time 520646719 ps
CPU time 4.75 seconds
Started May 16 12:47:43 PM PDT 24
Finished May 16 12:48:11 PM PDT 24
Peak memory 204968 kb
Host smart-94af5085-0bec-4500-bd74-f692b5849e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074213519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2074213519
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3202023355
Short name T1221
Test name
Test status
Simulation time 7013698591 ps
CPU time 33.48 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 369360 kb
Host smart-c5f82ede-88ad-4cfc-91e7-4aea149ac2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202023355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3202023355
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2603722843
Short name T908
Test name
Test status
Simulation time 95621126 ps
CPU time 0.66 seconds
Started May 16 12:47:35 PM PDT 24
Finished May 16 12:47:58 PM PDT 24
Peak memory 204576 kb
Host smart-1172557e-74f6-47df-a5e5-9ce2c3e287e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603722843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2603722843
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2979021701
Short name T726
Test name
Test status
Simulation time 5057836875 ps
CPU time 280.86 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:52:42 PM PDT 24
Peak memory 623156 kb
Host smart-769bf8cd-34e3-4eaf-a025-b5c499f2d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979021701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2979021701
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.398394298
Short name T914
Test name
Test status
Simulation time 5439419402 ps
CPU time 27.71 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 372544 kb
Host smart-65d0bf84-50a5-4e89-a49b-46650289f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398394298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.398394298
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.4161701933
Short name T160
Test name
Test status
Simulation time 353146867 ps
CPU time 6.73 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:07 PM PDT 24
Peak memory 213076 kb
Host smart-33deb4ec-837f-4ae3-bce0-83d78cb48610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161701933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4161701933
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2798497553
Short name T1345
Test name
Test status
Simulation time 2513472868 ps
CPU time 3.38 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 204988 kb
Host smart-7f91a712-8bea-4600-a5cc-f2e623122c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798497553 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2798497553
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2899759842
Short name T312
Test name
Test status
Simulation time 10130902877 ps
CPU time 13.53 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:14 PM PDT 24
Peak memory 247868 kb
Host smart-ba83cc73-8729-4e98-84b8-bddced4677c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899759842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2899759842
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1289626320
Short name T697
Test name
Test status
Simulation time 10081849026 ps
CPU time 26.95 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 354060 kb
Host smart-5933624f-ee13-44fc-b4a7-4fdfb1556757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289626320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1289626320
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2761611753
Short name T14
Test name
Test status
Simulation time 655716353 ps
CPU time 2.44 seconds
Started May 16 12:47:41 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 204944 kb
Host smart-aeb105c9-c1b5-42f4-a65c-eeb99d6bcb7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761611753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2761611753
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1558281797
Short name T798
Test name
Test status
Simulation time 845240462 ps
CPU time 5.4 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:07 PM PDT 24
Peak memory 214640 kb
Host smart-630a5d7e-3089-4715-9a4e-787573f74c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558281797 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1558281797
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2431157711
Short name T758
Test name
Test status
Simulation time 16086072652 ps
CPU time 28.87 seconds
Started May 16 12:47:41 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 872560 kb
Host smart-1b227fc7-28a9-41b8-af6d-12db4a26fcf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431157711 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2431157711
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2175636156
Short name T1
Test name
Test status
Simulation time 2048854589 ps
CPU time 17.56 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 204988 kb
Host smart-f2e04ac0-f037-4a76-92fb-6c1616086468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175636156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2175636156
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2807758439
Short name T1190
Test name
Test status
Simulation time 401192994 ps
CPU time 6.31 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:06 PM PDT 24
Peak memory 205268 kb
Host smart-8d20f477-dbf3-4621-9449-37197935a2e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807758439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2807758439
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1892820262
Short name T337
Test name
Test status
Simulation time 57840198991 ps
CPU time 1872.84 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 01:19:15 PM PDT 24
Peak memory 9362604 kb
Host smart-12bdc1f7-c10a-44bd-9704-a42595ac4e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892820262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1892820262
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2496148429
Short name T1135
Test name
Test status
Simulation time 35727587618 ps
CPU time 3275.31 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 01:42:36 PM PDT 24
Peak memory 8888184 kb
Host smart-238d3c61-6443-46be-8241-bc6b75260d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496148429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2496148429
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3719408605
Short name T1023
Test name
Test status
Simulation time 5448497443 ps
CPU time 7.78 seconds
Started May 16 12:47:38 PM PDT 24
Finished May 16 12:48:08 PM PDT 24
Peak memory 221388 kb
Host smart-d7e8ecb8-9dbd-4c60-87ba-a1b98db60821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719408605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3719408605
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3844646307
Short name T172
Test name
Test status
Simulation time 51875269 ps
CPU time 0.62 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 204508 kb
Host smart-76938b61-cd29-44e0-ab25-4620f239e3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844646307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3844646307
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3625916084
Short name T795
Test name
Test status
Simulation time 819971126 ps
CPU time 1.73 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:05 PM PDT 24
Peak memory 213112 kb
Host smart-b4b7e967-d6be-4518-a745-2d3435567db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625916084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3625916084
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3938098258
Short name T420
Test name
Test status
Simulation time 352732485 ps
CPU time 7.63 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:11 PM PDT 24
Peak memory 279452 kb
Host smart-6b9c49eb-5f88-4f3f-af96-45e5fc81ee4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938098258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3938098258
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2299684069
Short name T821
Test name
Test status
Simulation time 4969870202 ps
CPU time 67.3 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:49:10 PM PDT 24
Peak memory 641180 kb
Host smart-c3ca0f1c-3796-4dfa-95e6-34c95660bf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299684069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2299684069
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2775000145
Short name T484
Test name
Test status
Simulation time 3414266546 ps
CPU time 121.03 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:50:04 PM PDT 24
Peak memory 620516 kb
Host smart-a5efd6f6-f0cc-487b-bfd2-2dbd37e4aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775000145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2775000145
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2750062713
Short name T925
Test name
Test status
Simulation time 150825299 ps
CPU time 1.17 seconds
Started May 16 12:47:40 PM PDT 24
Finished May 16 12:48:04 PM PDT 24
Peak memory 204972 kb
Host smart-16014fb9-6b40-468d-a19f-d066a419a452
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750062713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2750062713
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1571015769
Short name T332
Test name
Test status
Simulation time 998301478 ps
CPU time 6.29 seconds
Started May 16 12:47:41 PM PDT 24
Finished May 16 12:48:10 PM PDT 24
Peak memory 255316 kb
Host smart-7d608bb0-d5ea-4bf3-91e1-a0963b102739
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571015769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1571015769
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.427053707
Short name T1048
Test name
Test status
Simulation time 3325627065 ps
CPU time 230.47 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:51:55 PM PDT 24
Peak memory 1012916 kb
Host smart-98287e44-da42-4d8b-b092-d0cb761a033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427053707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.427053707
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.591911411
Short name T803
Test name
Test status
Simulation time 435944894 ps
CPU time 5.81 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:48:22 PM PDT 24
Peak memory 204940 kb
Host smart-313075a0-53c9-48b6-a537-ef4ae8bb20a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591911411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.591911411
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1802406577
Short name T373
Test name
Test status
Simulation time 7468801354 ps
CPU time 87.4 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 311980 kb
Host smart-0e34a18f-22dd-4d8d-bbf7-5caa91ff7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802406577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1802406577
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.674567604
Short name T787
Test name
Test status
Simulation time 32341085 ps
CPU time 0.7 seconds
Started May 16 12:47:44 PM PDT 24
Finished May 16 12:48:08 PM PDT 24
Peak memory 204652 kb
Host smart-6963fb0d-69e0-4f3e-a4ca-0485e8dabafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674567604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.674567604
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3837684379
Short name T393
Test name
Test status
Simulation time 7907826386 ps
CPU time 35.09 seconds
Started May 16 12:47:41 PM PDT 24
Finished May 16 12:48:39 PM PDT 24
Peak memory 296068 kb
Host smart-4d587687-ddd3-4cd2-80a2-4f893ef82238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837684379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3837684379
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.308684734
Short name T440
Test name
Test status
Simulation time 3394089297 ps
CPU time 74.24 seconds
Started May 16 12:47:42 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 294216 kb
Host smart-23b3163e-975e-4cf9-84fb-e4438a138825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308684734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.308684734
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1708180197
Short name T1272
Test name
Test status
Simulation time 399461850 ps
CPU time 6.48 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:07 PM PDT 24
Peak memory 213032 kb
Host smart-ed51a6fd-7b0e-465e-86aa-04eb0ae3970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708180197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1708180197
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.703452275
Short name T248
Test name
Test status
Simulation time 891012503 ps
CPU time 4.05 seconds
Started May 16 12:47:57 PM PDT 24
Finished May 16 12:48:26 PM PDT 24
Peak memory 204904 kb
Host smart-c6563923-ce7c-40ed-b405-f40503b6647a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703452275 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.703452275
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1488052389
Short name T728
Test name
Test status
Simulation time 10097262588 ps
CPU time 27.15 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:48:41 PM PDT 24
Peak memory 327636 kb
Host smart-c7259307-845e-403c-baf7-43b6c05abcd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488052389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1488052389
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1502748050
Short name T307
Test name
Test status
Simulation time 10141606645 ps
CPU time 76.78 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:49:37 PM PDT 24
Peak memory 572692 kb
Host smart-ea432556-8c2b-43b7-b46d-7f6ce3ddd5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502748050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1502748050
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3496228367
Short name T329
Test name
Test status
Simulation time 1685243125 ps
CPU time 2.41 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 205052 kb
Host smart-5abd8c09-f3f1-40c7-847c-2848015468c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496228367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3496228367
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.833234316
Short name T844
Test name
Test status
Simulation time 538697830 ps
CPU time 3.28 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:48:20 PM PDT 24
Peak memory 204996 kb
Host smart-e05cd786-2551-4ecc-be58-edbe4304d24a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833234316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.833234316
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1384322768
Short name T469
Test name
Test status
Simulation time 16512150211 ps
CPU time 35.24 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:48:50 PM PDT 24
Peak memory 627424 kb
Host smart-4baf67b2-e8dc-4409-a919-7510942d1e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384322768 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1384322768
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1648843512
Short name T843
Test name
Test status
Simulation time 5929168752 ps
CPU time 18.25 seconds
Started May 16 12:47:39 PM PDT 24
Finished May 16 12:48:19 PM PDT 24
Peak memory 205008 kb
Host smart-c72eaad1-1401-4245-a478-9a85992544dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648843512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1648843512
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2540853478
Short name T1246
Test name
Test status
Simulation time 2688399137 ps
CPU time 26.88 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 204996 kb
Host smart-b1fc1894-a492-4f3e-b737-95c5420ff629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540853478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2540853478
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1649736331
Short name T964
Test name
Test status
Simulation time 26836590638 ps
CPU time 20.14 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 458804 kb
Host smart-c03df5c4-9107-42dd-98f6-351f9d76fbbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649736331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1649736331
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.628828840
Short name T247
Test name
Test status
Simulation time 38635005204 ps
CPU time 908.45 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 01:03:22 PM PDT 24
Peak memory 3897224 kb
Host smart-d5e0f2d8-040f-417d-be56-9b649b5edd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628828840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.628828840
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3811894612
Short name T1145
Test name
Test status
Simulation time 6637933303 ps
CPU time 7.41 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:48:24 PM PDT 24
Peak memory 219348 kb
Host smart-831033a6-5609-43c4-a58a-e8f44b113168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811894612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3811894612
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.402595958
Short name T745
Test name
Test status
Simulation time 134190115 ps
CPU time 0.65 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 204628 kb
Host smart-856c406d-1324-4700-b8d6-0624e510c140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402595958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.402595958
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3812903899
Short name T1087
Test name
Test status
Simulation time 3519181398 ps
CPU time 8.42 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:48:36 PM PDT 24
Peak memory 265536 kb
Host smart-758ce59a-0053-41ef-ba5a-db7155d72849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812903899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3812903899
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.311237652
Short name T407
Test name
Test status
Simulation time 722411982 ps
CPU time 10.41 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:48:26 PM PDT 24
Peak memory 244496 kb
Host smart-42604889-5aa2-4e59-9ba4-0735f1ba2f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311237652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.311237652
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3415993655
Short name T112
Test name
Test status
Simulation time 2277525027 ps
CPU time 78.61 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:49:39 PM PDT 24
Peak memory 749752 kb
Host smart-67734f93-9592-4568-a079-bce4d7456c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415993655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3415993655
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.662484987
Short name T1177
Test name
Test status
Simulation time 3870054004 ps
CPU time 65.13 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 675696 kb
Host smart-f80c75da-86f3-4080-bd02-8f488a6f2015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662484987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.662484987
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.207423689
Short name T1193
Test name
Test status
Simulation time 81334812 ps
CPU time 1.08 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:48:18 PM PDT 24
Peak memory 204972 kb
Host smart-8c381d5e-99cf-4f3a-8116-6ae3975fdf72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207423689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.207423689
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3540816659
Short name T1292
Test name
Test status
Simulation time 996016134 ps
CPU time 6.03 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:48:20 PM PDT 24
Peak memory 255584 kb
Host smart-65f99075-87be-4906-8e95-1fa065752f4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540816659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3540816659
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2860821479
Short name T1317
Test name
Test status
Simulation time 4695359504 ps
CPU time 114.83 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:50:11 PM PDT 24
Peak memory 1301108 kb
Host smart-9b94f9b3-b2a5-4027-950a-cb652d5dc54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860821479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2860821479
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2743903733
Short name T626
Test name
Test status
Simulation time 1046184271 ps
CPU time 17.97 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 204980 kb
Host smart-9fec7751-7106-4f42-b27d-b02ac99c2d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743903733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2743903733
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.708979615
Short name T1104
Test name
Test status
Simulation time 3769131002 ps
CPU time 88.67 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 390400 kb
Host smart-3c0ffe53-8e4c-4238-b07f-c2686908095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708979615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.708979615
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2321625036
Short name T1204
Test name
Test status
Simulation time 16497483 ps
CPU time 0.64 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:48:14 PM PDT 24
Peak memory 204648 kb
Host smart-d34c8cd0-5dda-45ff-9037-ff44812fc277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321625036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2321625036
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1403382243
Short name T432
Test name
Test status
Simulation time 29938263376 ps
CPU time 696.88 seconds
Started May 16 12:47:50 PM PDT 24
Finished May 16 12:59:52 PM PDT 24
Peak memory 2270800 kb
Host smart-b9a259cf-45f5-4027-9896-048397567fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403382243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1403382243
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3509838893
Short name T708
Test name
Test status
Simulation time 1453193236 ps
CPU time 21.7 seconds
Started May 16 12:47:55 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 317856 kb
Host smart-3ccf4367-1854-4110-820a-70829614987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509838893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3509838893
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2990127102
Short name T110
Test name
Test status
Simulation time 87469656034 ps
CPU time 1233.5 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 01:08:50 PM PDT 24
Peak memory 3673528 kb
Host smart-53ed6307-f922-46fd-b3c7-0638625b8649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990127102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2990127102
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2485007442
Short name T1263
Test name
Test status
Simulation time 878961279 ps
CPU time 20.47 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 213164 kb
Host smart-154b41b6-765d-4611-b3fb-c5369cca03cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485007442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2485007442
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2411887505
Short name T335
Test name
Test status
Simulation time 912547776 ps
CPU time 4.73 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:48:22 PM PDT 24
Peak memory 213092 kb
Host smart-fbda53f5-9b7f-4f7f-97b3-d3ffe9a9c9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411887505 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2411887505
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2960157856
Short name T930
Test name
Test status
Simulation time 10103292135 ps
CPU time 64.64 seconds
Started May 16 12:47:55 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 414812 kb
Host smart-af00b3d1-d11d-4b17-b369-524ceea6c7a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960157856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2960157856
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.769100902
Short name T565
Test name
Test status
Simulation time 10181019285 ps
CPU time 32.11 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:49:00 PM PDT 24
Peak memory 351552 kb
Host smart-5fc3684d-b30d-41a1-bae5-144fb1966b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769100902 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.769100902
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3938446893
Short name T10
Test name
Test status
Simulation time 1964887170 ps
CPU time 2.81 seconds
Started May 16 12:47:57 PM PDT 24
Finished May 16 12:48:25 PM PDT 24
Peak memory 205040 kb
Host smart-72d5d3ee-9799-4b30-9eb5-6067b7f4e743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938446893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3938446893
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3095602955
Short name T523
Test name
Test status
Simulation time 623793347 ps
CPU time 3.89 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:48:32 PM PDT 24
Peak memory 204888 kb
Host smart-f9be2ee6-e15f-4c2f-ad13-1f37a05802c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095602955 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3095602955
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3765527052
Short name T587
Test name
Test status
Simulation time 15376933964 ps
CPU time 170.84 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:51:04 PM PDT 24
Peak memory 2244508 kb
Host smart-04e4d1c3-ba21-4a75-a4e8-6923dbdc7a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765527052 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3765527052
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1952415630
Short name T1231
Test name
Test status
Simulation time 1416380107 ps
CPU time 57.41 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 204860 kb
Host smart-8506db29-0e90-42c1-8333-405c5d884f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952415630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1952415630
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.778989084
Short name T304
Test name
Test status
Simulation time 999696865 ps
CPU time 40.4 seconds
Started May 16 12:47:57 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 204968 kb
Host smart-be885b43-9dcd-4b01-9199-35ef226bb3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778989084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.778989084
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1531164408
Short name T737
Test name
Test status
Simulation time 7215967940 ps
CPU time 8.49 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:48:37 PM PDT 24
Peak memory 205020 kb
Host smart-11fbece0-3a04-4201-8272-42d591e5866c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531164408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1531164408
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1569236486
Short name T1340
Test name
Test status
Simulation time 14108833198 ps
CPU time 143.24 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:50:37 PM PDT 24
Peak memory 1451816 kb
Host smart-0d719ac2-bbe9-4092-b3e3-27ff86dea571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569236486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1569236486
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2098656509
Short name T563
Test name
Test status
Simulation time 6528193595 ps
CPU time 7.48 seconds
Started May 16 12:47:49 PM PDT 24
Finished May 16 12:48:20 PM PDT 24
Peak memory 220104 kb
Host smart-1cb55d17-b222-4d6d-9fcf-34ce89fe6403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098656509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2098656509
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.380412870
Short name T688
Test name
Test status
Simulation time 38588789 ps
CPU time 0.66 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:48:28 PM PDT 24
Peak memory 204616 kb
Host smart-08fbad6d-217a-4054-9f08-79e901d57986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380412870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.380412870
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2834345019
Short name T464
Test name
Test status
Simulation time 267673698 ps
CPU time 2.25 seconds
Started May 16 12:47:53 PM PDT 24
Finished May 16 12:48:21 PM PDT 24
Peak memory 221084 kb
Host smart-3747cb07-6738-4fea-a87d-f02a497c8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834345019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2834345019
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3595298489
Short name T781
Test name
Test status
Simulation time 279135115 ps
CPU time 13.58 seconds
Started May 16 12:47:53 PM PDT 24
Finished May 16 12:48:31 PM PDT 24
Peak memory 257992 kb
Host smart-e7f89a61-72c9-418b-87a8-5776b529d632
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595298489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3595298489
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4074059652
Short name T150
Test name
Test status
Simulation time 11502685804 ps
CPU time 119.04 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:50:19 PM PDT 24
Peak memory 921320 kb
Host smart-60a04ab9-8e76-4585-be28-c9b7e0837f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074059652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4074059652
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3031286314
Short name T303
Test name
Test status
Simulation time 1377525302 ps
CPU time 34.54 seconds
Started May 16 12:47:55 PM PDT 24
Finished May 16 12:48:55 PM PDT 24
Peak memory 484088 kb
Host smart-d6e56356-ab67-45de-bcd7-4a95a362e260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031286314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3031286314
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1378361075
Short name T333
Test name
Test status
Simulation time 102590476 ps
CPU time 0.84 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:48:17 PM PDT 24
Peak memory 204744 kb
Host smart-f1f039b9-9a42-4f61-b231-d293721cbf04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378361075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1378361075
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.631374636
Short name T874
Test name
Test status
Simulation time 485809093 ps
CPU time 3.18 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:48:23 PM PDT 24
Peak memory 204964 kb
Host smart-3e10c076-d128-4db5-aad8-809d66846929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631374636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
631374636
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2139397392
Short name T577
Test name
Test status
Simulation time 2715256108 ps
CPU time 162.79 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 823656 kb
Host smart-48cfe07e-7dd6-4c83-9c0f-450fe5e7cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139397392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2139397392
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.415558775
Short name T1057
Test name
Test status
Simulation time 157340953 ps
CPU time 6.2 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:48:35 PM PDT 24
Peak memory 204988 kb
Host smart-95d4be90-557f-4a50-871a-8a6527864fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415558775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.415558775
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4208701163
Short name T241
Test name
Test status
Simulation time 6823159371 ps
CPU time 31.17 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:48:59 PM PDT 24
Peak memory 325404 kb
Host smart-2c0161d8-e1ca-4de6-a786-c60f3f6407ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208701163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4208701163
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.4256298549
Short name T1335
Test name
Test status
Simulation time 70042052 ps
CPU time 0.62 seconds
Started May 16 12:47:51 PM PDT 24
Finished May 16 12:48:16 PM PDT 24
Peak memory 204664 kb
Host smart-f9d72a81-50b5-402b-b0af-b623dee69d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256298549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.4256298549
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1798231175
Short name T1053
Test name
Test status
Simulation time 26096757656 ps
CPU time 1937.05 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 01:20:37 PM PDT 24
Peak memory 4026052 kb
Host smart-ce64180b-7c08-4ede-a94c-bcd5d7a4b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798231175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1798231175
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.744959318
Short name T278
Test name
Test status
Simulation time 2179888652 ps
CPU time 100.02 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:50:09 PM PDT 24
Peak memory 322244 kb
Host smart-f932bee5-1a8a-4bb7-ac5f-40281053e61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744959318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.744959318
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3850355554
Short name T780
Test name
Test status
Simulation time 1510843924 ps
CPU time 15.12 seconds
Started May 16 12:47:54 PM PDT 24
Finished May 16 12:48:34 PM PDT 24
Peak memory 216908 kb
Host smart-3eeb96c8-5093-4a2b-bb70-4c6a9e3e04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850355554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3850355554
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4727073
Short name T340
Test name
Test status
Simulation time 2047915223 ps
CPU time 5.54 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:48:34 PM PDT 24
Peak memory 213396 kb
Host smart-7099e230-3f7a-4a60-97b6-7cf90df697c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4727073 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4727073
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1608405196
Short name T448
Test name
Test status
Simulation time 10583367052 ps
CPU time 12.51 seconds
Started May 16 12:47:58 PM PDT 24
Finished May 16 12:48:36 PM PDT 24
Peak memory 253656 kb
Host smart-05983f5c-b19c-43d2-9d09-4a53e09d365e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608405196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1608405196
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1866633499
Short name T612
Test name
Test status
Simulation time 10134877957 ps
CPU time 12.95 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:48:41 PM PDT 24
Peak memory 252556 kb
Host smart-49618420-229c-4cdc-8cf4-4e9599504e3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866633499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1866633499
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3172584756
Short name T910
Test name
Test status
Simulation time 722852752 ps
CPU time 2.57 seconds
Started May 16 12:48:04 PM PDT 24
Finished May 16 12:48:34 PM PDT 24
Peak memory 204964 kb
Host smart-6e115b2f-1fa7-4e53-a8d6-be223d6432d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172584756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3172584756
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.265562634
Short name T1160
Test name
Test status
Simulation time 1792345991 ps
CPU time 5.24 seconds
Started May 16 12:47:59 PM PDT 24
Finished May 16 12:48:30 PM PDT 24
Peak memory 213148 kb
Host smart-ed480006-abc4-478f-95e8-405fd955c48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265562634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.265562634
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.908089570
Short name T659
Test name
Test status
Simulation time 21253108367 ps
CPU time 64.32 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:49:31 PM PDT 24
Peak memory 953028 kb
Host smart-7bd7b753-2002-4e40-9b08-838f52ca8dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908089570 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.908089570
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3702666289
Short name T947
Test name
Test status
Simulation time 729552235 ps
CPU time 10.94 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 204668 kb
Host smart-202e4b4c-e27a-4b08-b0fd-afbdeb78d4f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702666289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3702666289
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2818871797
Short name T992
Test name
Test status
Simulation time 1202597392 ps
CPU time 19.44 seconds
Started May 16 12:47:52 PM PDT 24
Finished May 16 12:48:36 PM PDT 24
Peak memory 214192 kb
Host smart-6fafbb4a-f3f0-4931-91ed-447b35ef7a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818871797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2818871797
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.173418840
Short name T582
Test name
Test status
Simulation time 9944254329 ps
CPU time 6.16 seconds
Started May 16 12:47:56 PM PDT 24
Finished May 16 12:48:28 PM PDT 24
Peak memory 204796 kb
Host smart-f673543b-9a14-4c24-ad2c-9bf78b4bee01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173418840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.173418840
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.859762915
Short name T973
Test name
Test status
Simulation time 31430968756 ps
CPU time 708.09 seconds
Started May 16 12:47:58 PM PDT 24
Finished May 16 01:00:11 PM PDT 24
Peak memory 1869440 kb
Host smart-463b7ad6-272a-4d9f-95d8-df1b7bedf905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859762915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.859762915
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.928135063
Short name T995
Test name
Test status
Simulation time 1223801854 ps
CPU time 6.62 seconds
Started May 16 12:48:03 PM PDT 24
Finished May 16 12:48:37 PM PDT 24
Peak memory 221176 kb
Host smart-ff0340c2-b4c7-4de0-a405-7f81a1b6d2cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928135063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.928135063
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2762601778
Short name T694
Test name
Test status
Simulation time 200561911 ps
CPU time 0.58 seconds
Started May 16 12:48:08 PM PDT 24
Finished May 16 12:48:35 PM PDT 24
Peak memory 204600 kb
Host smart-15f0ef9c-702c-470e-b583-72d94c3e311e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762601778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2762601778
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.429879970
Short name T875
Test name
Test status
Simulation time 707510583 ps
CPU time 2.2 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 220872 kb
Host smart-9554fe60-ca88-488a-b25d-302b52ea637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429879970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.429879970
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1187655403
Short name T840
Test name
Test status
Simulation time 1050663552 ps
CPU time 9.37 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:48:37 PM PDT 24
Peak memory 234896 kb
Host smart-a20a72f7-4a03-429f-a968-132f84fafafe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187655403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1187655403
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1884267707
Short name T855
Test name
Test status
Simulation time 7741560381 ps
CPU time 134.52 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:50:41 PM PDT 24
Peak memory 666428 kb
Host smart-f419b34c-6f58-401b-a838-c0a6c775f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884267707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1884267707
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1271274071
Short name T664
Test name
Test status
Simulation time 10178494686 ps
CPU time 50.36 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 586532 kb
Host smart-44d87fef-c0af-4c74-afa3-e5158840c485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271274071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1271274071
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4009504516
Short name T909
Test name
Test status
Simulation time 205517378 ps
CPU time 0.97 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 204676 kb
Host smart-7df7fc30-bfe4-4dd6-a42b-25181347f1a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009504516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4009504516
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2351268405
Short name T815
Test name
Test status
Simulation time 223116539 ps
CPU time 4.5 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:48:31 PM PDT 24
Peak memory 204848 kb
Host smart-30c22c8f-e10a-4003-ae88-c4aa94d26bb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351268405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2351268405
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1416748052
Short name T494
Test name
Test status
Simulation time 9805892297 ps
CPU time 152.25 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 727016 kb
Host smart-44ccabc5-b573-484f-88c5-b80e6c1ece0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416748052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1416748052
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1356825225
Short name T586
Test name
Test status
Simulation time 5105363522 ps
CPU time 22.6 seconds
Started May 16 12:48:06 PM PDT 24
Finished May 16 12:48:55 PM PDT 24
Peak memory 205112 kb
Host smart-ad314b7a-ca6a-41fa-b477-7c6f56c5177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356825225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1356825225
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3848112387
Short name T644
Test name
Test status
Simulation time 6194193512 ps
CPU time 47.93 seconds
Started May 16 12:48:06 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 489268 kb
Host smart-45267ef2-0c9e-4c57-89ea-b69a0c240ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848112387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3848112387
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2348123697
Short name T733
Test name
Test status
Simulation time 86455981 ps
CPU time 0.65 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:48:29 PM PDT 24
Peak memory 204592 kb
Host smart-9312813c-5d45-4de2-b890-a0a910bf6e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348123697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2348123697
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.4162108845
Short name T1333
Test name
Test status
Simulation time 2363914457 ps
CPU time 5.2 seconds
Started May 16 12:47:59 PM PDT 24
Finished May 16 12:48:30 PM PDT 24
Peak memory 205048 kb
Host smart-93bb580f-83f5-431e-bd08-cd6514a2431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162108845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4162108845
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2557296476
Short name T1291
Test name
Test status
Simulation time 1801916941 ps
CPU time 88.93 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:49:55 PM PDT 24
Peak memory 385480 kb
Host smart-46a385a5-1b79-451f-a92a-6f8a0807713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557296476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2557296476
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2740046066
Short name T931
Test name
Test status
Simulation time 15511592969 ps
CPU time 815.63 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 01:02:03 PM PDT 24
Peak memory 2363348 kb
Host smart-be8e6dc9-4348-4581-bfd6-2cbe62e5d4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740046066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2740046066
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.44343412
Short name T521
Test name
Test status
Simulation time 3892414067 ps
CPU time 34.1 seconds
Started May 16 12:48:00 PM PDT 24
Finished May 16 12:49:02 PM PDT 24
Peak memory 213300 kb
Host smart-754de3f7-1163-4cbb-a8df-9cec2c718254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44343412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.44343412
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3380045421
Short name T495
Test name
Test status
Simulation time 3115940260 ps
CPU time 3.75 seconds
Started May 16 12:48:04 PM PDT 24
Finished May 16 12:48:35 PM PDT 24
Peak memory 213300 kb
Host smart-6e416397-4463-4201-bb57-80948cd4f26c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380045421 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3380045421
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1326328908
Short name T704
Test name
Test status
Simulation time 10092295562 ps
CPU time 64.01 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:49:32 PM PDT 24
Peak memory 466048 kb
Host smart-2f4efabd-4014-4560-94c3-bd5a338000f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326328908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1326328908
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.4272604203
Short name T769
Test name
Test status
Simulation time 10163313763 ps
CPU time 72.41 seconds
Started May 16 12:48:05 PM PDT 24
Finished May 16 12:49:44 PM PDT 24
Peak memory 460252 kb
Host smart-0fb727b3-9e89-4230-be1a-a67be3596802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272604203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.4272604203
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1242058217
Short name T786
Test name
Test status
Simulation time 1771124374 ps
CPU time 2.43 seconds
Started May 16 12:47:59 PM PDT 24
Finished May 16 12:48:27 PM PDT 24
Peak memory 204916 kb
Host smart-c0908358-6490-4dd7-8f21-606cb50e6c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242058217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1242058217
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1489103477
Short name T8
Test name
Test status
Simulation time 2930166565 ps
CPU time 4.25 seconds
Started May 16 12:48:07 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 205252 kb
Host smart-ad0c383b-5362-4bbd-a84b-1d6c8cd05275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489103477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1489103477
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2792943943
Short name T431
Test name
Test status
Simulation time 8726280835 ps
CPU time 6.09 seconds
Started May 16 12:48:01 PM PDT 24
Finished May 16 12:48:34 PM PDT 24
Peak memory 343948 kb
Host smart-8b98a67c-5f77-47da-abd7-ae60f45b22bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792943943 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2792943943
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1998682459
Short name T1304
Test name
Test status
Simulation time 13735698715 ps
CPU time 11.53 seconds
Started May 16 12:48:04 PM PDT 24
Finished May 16 12:48:43 PM PDT 24
Peak memory 205016 kb
Host smart-1df5328f-5985-486f-a007-01e14f7e0c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998682459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1998682459
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.638510699
Short name T403
Test name
Test status
Simulation time 1266026108 ps
CPU time 52.98 seconds
Started May 16 12:48:02 PM PDT 24
Finished May 16 12:49:21 PM PDT 24
Peak memory 205960 kb
Host smart-88aecf7e-0607-4910-b6b5-7db207155d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638510699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.638510699
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.42703822
Short name T1164
Test name
Test status
Simulation time 28473833841 ps
CPU time 167.71 seconds
Started May 16 12:48:03 PM PDT 24
Finished May 16 12:51:18 PM PDT 24
Peak memory 2214508 kb
Host smart-cb4f3de1-d7d0-4daf-b184-9438f173af46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stress_wr.42703822
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1743940501
Short name T616
Test name
Test status
Simulation time 16254066662 ps
CPU time 230.89 seconds
Started May 16 12:48:08 PM PDT 24
Finished May 16 12:52:25 PM PDT 24
Peak memory 2005616 kb
Host smart-36e0f9cd-7919-427c-9b29-e82742665839
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743940501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1743940501
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2244369323
Short name T527
Test name
Test status
Simulation time 2766455523 ps
CPU time 7.44 seconds
Started May 16 12:48:04 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 205072 kb
Host smart-ba679c45-c72b-4e45-aceb-bcc20968f10f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244369323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2244369323
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3102773098
Short name T1180
Test name
Test status
Simulation time 17744137 ps
CPU time 0.62 seconds
Started May 16 12:48:14 PM PDT 24
Finished May 16 12:48:41 PM PDT 24
Peak memory 204492 kb
Host smart-751edd74-2d49-4c77-a26c-89bd7001b23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102773098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3102773098
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1933583418
Short name T1259
Test name
Test status
Simulation time 226538997 ps
CPU time 1.7 seconds
Started May 16 12:48:19 PM PDT 24
Finished May 16 12:48:47 PM PDT 24
Peak memory 216636 kb
Host smart-a579721e-e66d-44d6-b90a-80f0752de6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933583418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1933583418
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.357022181
Short name T720
Test name
Test status
Simulation time 2150713011 ps
CPU time 12.03 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 330212 kb
Host smart-295a86de-94f8-471b-8e6e-d9aebf54b113
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357022181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.357022181
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1526948324
Short name T595
Test name
Test status
Simulation time 2597361651 ps
CPU time 30.06 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 374336 kb
Host smart-574d0120-1289-478d-9913-ff948c124f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526948324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1526948324
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3610702291
Short name T631
Test name
Test status
Simulation time 5947182996 ps
CPU time 92.61 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 12:50:14 PM PDT 24
Peak memory 531836 kb
Host smart-0267d573-d3ff-4c9c-8803-06bed9ab2456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610702291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3610702291
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.694178870
Short name T1191
Test name
Test status
Simulation time 106902933 ps
CPU time 0.93 seconds
Started May 16 12:48:09 PM PDT 24
Finished May 16 12:48:37 PM PDT 24
Peak memory 204644 kb
Host smart-a53a4a57-1f38-4509-aeb0-22017902b12c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694178870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.694178870
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3237849777
Short name T692
Test name
Test status
Simulation time 126128673 ps
CPU time 7.11 seconds
Started May 16 12:48:16 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 224492 kb
Host smart-44881480-c61d-4c23-b6f5-c3a93f9d18a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237849777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3237849777
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.795869678
Short name T1283
Test name
Test status
Simulation time 5602436280 ps
CPU time 121.79 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:50:41 PM PDT 24
Peak memory 1209712 kb
Host smart-5aa82a63-826b-429e-b8a2-839969fa1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795869678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.795869678
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.428084243
Short name T239
Test name
Test status
Simulation time 1959136786 ps
CPU time 5.43 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:43 PM PDT 24
Peak memory 204976 kb
Host smart-fb67893a-5adf-417a-b901-72fb78718419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428084243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.428084243
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1909899535
Short name T1073
Test name
Test status
Simulation time 20867329761 ps
CPU time 55.76 seconds
Started May 16 12:48:16 PM PDT 24
Finished May 16 12:49:38 PM PDT 24
Peak memory 270080 kb
Host smart-b22782d7-70cc-4fd2-b32a-08e9c754f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909899535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1909899535
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1475713337
Short name T1249
Test name
Test status
Simulation time 43456457 ps
CPU time 0.61 seconds
Started May 16 12:48:05 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 204684 kb
Host smart-2edb29be-07b8-470d-a396-ff0111fcb0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475713337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1475713337
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1928044425
Short name T1085
Test name
Test status
Simulation time 578385287 ps
CPU time 22.6 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:00 PM PDT 24
Peak memory 229464 kb
Host smart-2481a12a-f090-4b5d-9f44-5ab0cd3eac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928044425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1928044425
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3602211965
Short name T496
Test name
Test status
Simulation time 5427634119 ps
CPU time 58.33 seconds
Started May 16 12:48:04 PM PDT 24
Finished May 16 12:49:29 PM PDT 24
Peak memory 295220 kb
Host smart-3c2c054e-4450-48c1-9829-298e31adc9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602211965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3602211965
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3859450903
Short name T104
Test name
Test status
Simulation time 67963344007 ps
CPU time 1088.68 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 01:06:46 PM PDT 24
Peak memory 3976432 kb
Host smart-2fabb6de-43cc-4797-ba24-9c6d40233bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859450903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3859450903
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3679522178
Short name T1094
Test name
Test status
Simulation time 709008336 ps
CPU time 31.14 seconds
Started May 16 12:48:14 PM PDT 24
Finished May 16 12:49:11 PM PDT 24
Peak memory 213092 kb
Host smart-0bd8aa43-ce2e-45b0-a163-a5305d8866d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679522178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3679522178
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.284581064
Short name T12
Test name
Test status
Simulation time 2571755494 ps
CPU time 3.35 seconds
Started May 16 12:48:09 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 205108 kb
Host smart-5576cf0b-09a0-4bfd-b9fa-6d5bfacfd815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284581064 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.284581064
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1497852687
Short name T568
Test name
Test status
Simulation time 10101020514 ps
CPU time 41.61 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 12:49:23 PM PDT 24
Peak memory 360888 kb
Host smart-5bc26afb-28dc-4e85-94c7-fe285a6aab57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497852687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1497852687
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.710346851
Short name T1046
Test name
Test status
Simulation time 10040847243 ps
CPU time 76.55 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 555856 kb
Host smart-f0069a38-47db-401e-b1fa-9240486e41f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710346851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.710346851
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.36069612
Short name T246
Test name
Test status
Simulation time 503339301 ps
CPU time 2.94 seconds
Started May 16 12:48:16 PM PDT 24
Finished May 16 12:48:46 PM PDT 24
Peak memory 205024 kb
Host smart-c51208fb-faa8-44bb-a3cd-7d84ffcfd70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069612 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.i2c_target_hrst.36069612
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2785970763
Short name T143
Test name
Test status
Simulation time 11100463152 ps
CPU time 6.77 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:48:44 PM PDT 24
Peak memory 221312 kb
Host smart-060bd4c3-7ce9-4491-b101-e410dffe7832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785970763 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2785970763
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3790169939
Short name T319
Test name
Test status
Simulation time 2308530040 ps
CPU time 2.37 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 205028 kb
Host smart-826cf65c-4197-4433-ac17-f42c6fcbf890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790169939 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3790169939
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2380456392
Short name T1276
Test name
Test status
Simulation time 704712332 ps
CPU time 10.53 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:48 PM PDT 24
Peak memory 204820 kb
Host smart-68b0472a-2a22-44b9-88df-7896a6a740e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380456392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2380456392
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1599379233
Short name T1018
Test name
Test status
Simulation time 5755689164 ps
CPU time 65.64 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:43 PM PDT 24
Peak memory 207700 kb
Host smart-58ded1f7-699a-476f-9b42-7a354336d919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599379233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1599379233
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1564257644
Short name T1033
Test name
Test status
Simulation time 11224660448 ps
CPU time 4.87 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:42 PM PDT 24
Peak memory 205004 kb
Host smart-2c83912f-f14f-491d-9dc1-66c5e4dcfe94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564257644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1564257644
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2172242297
Short name T1343
Test name
Test status
Simulation time 5691680960 ps
CPU time 117.51 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:50:35 PM PDT 24
Peak memory 1476960 kb
Host smart-13b20b4b-34e3-47d8-a1ee-5785d5647d35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172242297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2172242297
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3614066215
Short name T511
Test name
Test status
Simulation time 996432446 ps
CPU time 6.1 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 12:48:47 PM PDT 24
Peak memory 213152 kb
Host smart-2b1c3e90-7d08-40f3-9abb-0fe859b4646a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614066215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3614066215
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1858126675
Short name T429
Test name
Test status
Simulation time 23967130 ps
CPU time 0.62 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:47 PM PDT 24
Peak memory 204664 kb
Host smart-762d1b8b-6f1d-4aa1-8082-56d9020aec25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858126675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1858126675
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1156838976
Short name T722
Test name
Test status
Simulation time 60829798 ps
CPU time 1.32 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:48:39 PM PDT 24
Peak memory 205092 kb
Host smart-1820f8f6-7767-4684-9f88-6cf58216c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156838976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1156838976
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3289462455
Short name T295
Test name
Test status
Simulation time 597063162 ps
CPU time 7.99 seconds
Started May 16 12:48:19 PM PDT 24
Finished May 16 12:48:53 PM PDT 24
Peak memory 233552 kb
Host smart-c59c5733-723f-4b50-925a-773483a36f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289462455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3289462455
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3677955552
Short name T168
Test name
Test status
Simulation time 3415052688 ps
CPU time 48.64 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:49:28 PM PDT 24
Peak memory 620172 kb
Host smart-b82fe72f-5a16-48ec-89c4-68b7627a1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677955552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3677955552
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.263820929
Short name T594
Test name
Test status
Simulation time 3700475309 ps
CPU time 141.43 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:50:59 PM PDT 24
Peak memory 666636 kb
Host smart-2ebbf26e-2f13-4270-8f4e-4a3f1d83bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263820929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.263820929
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4090011197
Short name T229
Test name
Test status
Simulation time 513021156 ps
CPU time 1.05 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:48:40 PM PDT 24
Peak memory 204888 kb
Host smart-e0e0205b-7a8f-48d6-852b-330bf118d117
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090011197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4090011197
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3253859396
Short name T396
Test name
Test status
Simulation time 149474820 ps
CPU time 8.83 seconds
Started May 16 12:48:13 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 232120 kb
Host smart-27e4fe33-457d-46c4-a8e9-1042d65e488a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253859396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3253859396
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2624388982
Short name T1248
Test name
Test status
Simulation time 19046267626 ps
CPU time 104.51 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:50:23 PM PDT 24
Peak memory 1258880 kb
Host smart-773f972d-55fc-48fc-8236-a3205e2a4443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624388982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2624388982
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2864773207
Short name T242
Test name
Test status
Simulation time 214840070 ps
CPU time 8.55 seconds
Started May 16 12:48:24 PM PDT 24
Finished May 16 12:48:58 PM PDT 24
Peak memory 204940 kb
Host smart-fb7d7aa1-718e-4aa7-a34c-a2f28acd1f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864773207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2864773207
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1957250209
Short name T284
Test name
Test status
Simulation time 5457106414 ps
CPU time 19.34 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 300144 kb
Host smart-efd2b6f6-d56e-4bd1-b6b6-786d5f90c7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957250209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1957250209
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2150022749
Short name T1251
Test name
Test status
Simulation time 26998563 ps
CPU time 0.65 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:38 PM PDT 24
Peak memory 204676 kb
Host smart-906af779-3f91-460c-8e59-2369709a2fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150022749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2150022749
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1627462165
Short name T1337
Test name
Test status
Simulation time 5215634472 ps
CPU time 42.79 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 557628 kb
Host smart-f8fc37c3-a323-4277-997c-046f7c98d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627462165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1627462165
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2024582654
Short name T1209
Test name
Test status
Simulation time 3904676994 ps
CPU time 44.84 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 12:49:26 PM PDT 24
Peak memory 288152 kb
Host smart-7b75dfa0-9839-4919-8345-9048e419ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024582654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2024582654
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1206950958
Short name T263
Test name
Test status
Simulation time 69313104976 ps
CPU time 803.52 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 01:02:05 PM PDT 24
Peak memory 2579188 kb
Host smart-76e20cb9-bc16-4952-8395-cadffea18bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206950958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1206950958
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2986085275
Short name T1027
Test name
Test status
Simulation time 2960613863 ps
CPU time 34.82 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:13 PM PDT 24
Peak memory 213296 kb
Host smart-da0e2569-7a26-4114-b59f-236d07c3b688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986085275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2986085275
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3560146954
Short name T164
Test name
Test status
Simulation time 3311468728 ps
CPU time 3.94 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:48:51 PM PDT 24
Peak memory 204984 kb
Host smart-1d239339-096a-4b04-bffb-f9041395db44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560146954 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3560146954
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3086040699
Short name T838
Test name
Test status
Simulation time 10183679620 ps
CPU time 30.55 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:49:08 PM PDT 24
Peak memory 363904 kb
Host smart-92d5d91d-ea2c-460d-ae65-19ccbbe89cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086040699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3086040699
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1508917639
Short name T26
Test name
Test status
Simulation time 1606091782 ps
CPU time 2.43 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:48 PM PDT 24
Peak memory 204964 kb
Host smart-38b6d02b-53d8-43da-84a6-3c9fb601f86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508917639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1508917639
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1334076167
Short name T863
Test name
Test status
Simulation time 1183121570 ps
CPU time 6.34 seconds
Started May 16 12:48:15 PM PDT 24
Finished May 16 12:48:48 PM PDT 24
Peak memory 213140 kb
Host smart-17b44215-b981-45b1-8b61-25851c5870be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334076167 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1334076167
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.827158256
Short name T1099
Test name
Test status
Simulation time 17239071058 ps
CPU time 43.59 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 1043448 kb
Host smart-ac9d89c5-b45a-4086-ad57-f18fde92ab1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827158256 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.827158256
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2924307381
Short name T368
Test name
Test status
Simulation time 3953978717 ps
CPU time 15.79 seconds
Started May 16 12:48:14 PM PDT 24
Finished May 16 12:48:57 PM PDT 24
Peak memory 205044 kb
Host smart-bd22302b-aa66-46db-a04c-5e2d77c160b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924307381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2924307381
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3837449069
Short name T277
Test name
Test status
Simulation time 2543385495 ps
CPU time 50.47 seconds
Started May 16 12:48:10 PM PDT 24
Finished May 16 12:49:28 PM PDT 24
Peak memory 206332 kb
Host smart-2f776723-f831-4e1e-b322-9c4627bdb178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837449069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3837449069
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1215335102
Short name T378
Test name
Test status
Simulation time 16813640059 ps
CPU time 9.3 seconds
Started May 16 12:48:11 PM PDT 24
Finished May 16 12:48:47 PM PDT 24
Peak memory 205016 kb
Host smart-f4ae9906-1ae5-4616-9f9e-086cc5aef643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215335102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1215335102
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.814997442
Short name T609
Test name
Test status
Simulation time 7945126984 ps
CPU time 93.25 seconds
Started May 16 12:48:14 PM PDT 24
Finished May 16 12:50:14 PM PDT 24
Peak memory 566200 kb
Host smart-3ae559f2-68e6-4424-9889-fcc09df0c0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814997442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.814997442
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1999002255
Short name T434
Test name
Test status
Simulation time 1258154408 ps
CPU time 7.17 seconds
Started May 16 12:48:12 PM PDT 24
Finished May 16 12:48:45 PM PDT 24
Peak memory 213088 kb
Host smart-e887b3c6-c23e-48bc-8985-4e72e1204af6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999002255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1999002255
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3318718736
Short name T182
Test name
Test status
Simulation time 1177631560 ps
CPU time 3.75 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:48:52 PM PDT 24
Peak memory 213200 kb
Host smart-efb61506-d6dc-466f-8500-c21b4b1a171b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318718736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3318718736
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2860938150
Short name T287
Test name
Test status
Simulation time 333342834 ps
CPU time 16.95 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:49:04 PM PDT 24
Peak memory 273064 kb
Host smart-8fa52b3c-d64f-48e1-9f8d-68a0e4d1a933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860938150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2860938150
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.758138240
Short name T1215
Test name
Test status
Simulation time 4103700035 ps
CPU time 73.44 seconds
Started May 16 12:48:24 PM PDT 24
Finished May 16 12:50:03 PM PDT 24
Peak memory 650548 kb
Host smart-9d114594-673d-4ba9-a4c7-26a618f1c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758138240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.758138240
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1756901193
Short name T1339
Test name
Test status
Simulation time 2680144014 ps
CPU time 81.92 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:50:09 PM PDT 24
Peak memory 454844 kb
Host smart-f3dcbc9d-e748-4b55-bd7f-10768d35d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756901193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1756901193
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1288426537
Short name T1326
Test name
Test status
Simulation time 359973460 ps
CPU time 1.08 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 204840 kb
Host smart-2e2ad7e8-9494-4f1a-8e47-28dfc8070e82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288426537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1288426537
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3540916848
Short name T1029
Test name
Test status
Simulation time 1834825093 ps
CPU time 6.22 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:48:54 PM PDT 24
Peak memory 254892 kb
Host smart-28e359a1-e943-4ca1-8056-4e13d2225774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540916848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3540916848
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2990203929
Short name T400
Test name
Test status
Simulation time 13781422297 ps
CPU time 199.85 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:52:06 PM PDT 24
Peak memory 926560 kb
Host smart-0fe221b2-0900-44ec-9886-5089b9f6d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990203929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2990203929
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4149235540
Short name T713
Test name
Test status
Simulation time 1265093244 ps
CPU time 9.45 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:48:58 PM PDT 24
Peak memory 204944 kb
Host smart-76b5bff1-d5df-480a-9671-38fe135bb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149235540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4149235540
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.1177048944
Short name T367
Test name
Test status
Simulation time 51088456 ps
CPU time 0.73 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:48:49 PM PDT 24
Peak memory 204588 kb
Host smart-d9d947c7-68f0-45b8-8812-fe78821278bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177048944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1177048944
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1877508917
Short name T1324
Test name
Test status
Simulation time 6063708092 ps
CPU time 25.4 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:49:12 PM PDT 24
Peak memory 282668 kb
Host smart-6938ec45-e367-407f-8dd7-2c2408631b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877508917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1877508917
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.3257804652
Short name T322
Test name
Test status
Simulation time 32708986879 ps
CPU time 2651.81 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 01:33:00 PM PDT 24
Peak memory 4875660 kb
Host smart-7bc8422b-e98e-40ab-a93f-36131a49ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257804652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3257804652
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1184747592
Short name T808
Test name
Test status
Simulation time 2766604730 ps
CPU time 3.7 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:50 PM PDT 24
Peak memory 213072 kb
Host smart-954597fc-2121-4dd7-abf5-656f8850fd6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184747592 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1184747592
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.755832877
Short name T858
Test name
Test status
Simulation time 10064298710 ps
CPU time 67.77 seconds
Started May 16 12:48:24 PM PDT 24
Finished May 16 12:49:57 PM PDT 24
Peak memory 538996 kb
Host smart-10d70986-774f-4f1a-9c10-840d0b747db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755832877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.755832877
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.4169140334
Short name T350
Test name
Test status
Simulation time 10128803883 ps
CPU time 70.11 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 12:49:57 PM PDT 24
Peak memory 561896 kb
Host smart-0a2560f8-d391-4e53-9bf1-ff7a158cc1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169140334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.4169140334
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.4076316341
Short name T497
Test name
Test status
Simulation time 454158797 ps
CPU time 2.65 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:48:50 PM PDT 24
Peak memory 205012 kb
Host smart-7a02f6e0-0650-4f2a-bf75-40b16557c2a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076316341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.4076316341
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3200846292
Short name T446
Test name
Test status
Simulation time 732492565 ps
CPU time 4.7 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:48:53 PM PDT 24
Peak memory 204784 kb
Host smart-90d06a75-29ec-4220-a146-4e9e23846628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200846292 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3200846292
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1518156881
Short name T916
Test name
Test status
Simulation time 4607936548 ps
CPU time 48.46 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:49:35 PM PDT 24
Peak memory 1264084 kb
Host smart-d8f5d642-ff94-4b19-9d71-7fbe89b89457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518156881 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1518156881
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3355183222
Short name T730
Test name
Test status
Simulation time 11376088126 ps
CPU time 55.1 seconds
Started May 16 12:48:24 PM PDT 24
Finished May 16 12:49:44 PM PDT 24
Peak memory 204988 kb
Host smart-a15a6402-d3fe-4b9c-81a9-639097fa7f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355183222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3355183222
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1805139887
Short name T590
Test name
Test status
Simulation time 1650036458 ps
CPU time 22.45 seconds
Started May 16 12:48:19 PM PDT 24
Finished May 16 12:49:08 PM PDT 24
Peak memory 228320 kb
Host smart-1e5a30a1-b83f-4e5f-a900-b21e84b67fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805139887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1805139887
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.387642395
Short name T162
Test name
Test status
Simulation time 49915252122 ps
CPU time 1364.47 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 01:11:32 PM PDT 24
Peak memory 7663584 kb
Host smart-fed9e415-4ad9-462d-b4ee-05285c8029bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387642395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.387642395
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1185450575
Short name T831
Test name
Test status
Simulation time 27715673553 ps
CPU time 154.44 seconds
Started May 16 12:48:19 PM PDT 24
Finished May 16 12:51:20 PM PDT 24
Peak memory 1455012 kb
Host smart-ccc42e01-16a7-4f35-9d0b-a6f5d810ee49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185450575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1185450575
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2003742998
Short name T1181
Test name
Test status
Simulation time 1210954968 ps
CPU time 6.77 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:53 PM PDT 24
Peak memory 220292 kb
Host smart-9bf58a9d-07ac-4b9b-a72f-48fac64c613e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003742998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2003742998
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.161494316
Short name T994
Test name
Test status
Simulation time 16005805 ps
CPU time 0.68 seconds
Started May 16 12:48:33 PM PDT 24
Finished May 16 12:48:56 PM PDT 24
Peak memory 204492 kb
Host smart-e72bad66-dc1c-4f4c-90e3-711f3a7bf738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161494316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.161494316
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3551979037
Short name T865
Test name
Test status
Simulation time 412926059 ps
CPU time 1.75 seconds
Started May 16 12:48:28 PM PDT 24
Finished May 16 12:48:55 PM PDT 24
Peak memory 213280 kb
Host smart-b5d53a0c-302c-4561-bcee-00952fc93894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551979037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3551979037
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2316047585
Short name T1213
Test name
Test status
Simulation time 885510733 ps
CPU time 13.26 seconds
Started May 16 12:48:24 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 255720 kb
Host smart-9196a6d2-2165-4cde-9b75-f7fd423ff4f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316047585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2316047585
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.4197000551
Short name T88
Test name
Test status
Simulation time 2224360485 ps
CPU time 61.3 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:49:50 PM PDT 24
Peak memory 605856 kb
Host smart-56ed22d4-3b7c-4ab6-83c7-81777a3eb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197000551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.4197000551
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.4049271930
Short name T541
Test name
Test status
Simulation time 10411010107 ps
CPU time 94.63 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:50:23 PM PDT 24
Peak memory 826320 kb
Host smart-3d68257a-329d-4d53-9354-fea673f15961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049271930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.4049271930
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3961187215
Short name T294
Test name
Test status
Simulation time 102564930 ps
CPU time 0.97 seconds
Started May 16 12:48:28 PM PDT 24
Finished May 16 12:48:54 PM PDT 24
Peak memory 204752 kb
Host smart-9752272e-6674-4221-a0bc-0bad26386bc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961187215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3961187215
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.4108884628
Short name T1142
Test name
Test status
Simulation time 170172037 ps
CPU time 4.19 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:52 PM PDT 24
Peak memory 232624 kb
Host smart-7993bafd-52e9-4f45-9793-1ba0b6cfc609
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108884628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.4108884628
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3703178596
Short name T860
Test name
Test status
Simulation time 17461176988 ps
CPU time 304.48 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 1183352 kb
Host smart-ee3d1ee2-7ccb-4aff-a6e7-1cf230dd8618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703178596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3703178596
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1186144524
Short name T296
Test name
Test status
Simulation time 504361307 ps
CPU time 4.1 seconds
Started May 16 12:48:34 PM PDT 24
Finished May 16 12:49:01 PM PDT 24
Peak memory 204916 kb
Host smart-2d70d7fe-7e54-4850-bb9b-02fefd718c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186144524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1186144524
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3049065527
Short name T69
Test name
Test status
Simulation time 5624052353 ps
CPU time 21.01 seconds
Started May 16 12:48:33 PM PDT 24
Finished May 16 12:49:17 PM PDT 24
Peak memory 287184 kb
Host smart-82bb4dc6-0276-4789-bcb7-63575d7eaf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049065527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3049065527
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1765627504
Short name T1092
Test name
Test status
Simulation time 86355443 ps
CPU time 0.66 seconds
Started May 16 12:48:20 PM PDT 24
Finished May 16 12:48:47 PM PDT 24
Peak memory 204676 kb
Host smart-9816e98e-8a7c-4e9a-a5a1-4533af36908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765627504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1765627504
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1764870992
Short name T515
Test name
Test status
Simulation time 13258610937 ps
CPU time 372.44 seconds
Started May 16 12:48:22 PM PDT 24
Finished May 16 12:55:00 PM PDT 24
Peak memory 736548 kb
Host smart-06720891-f499-49d5-a3ae-1a568007bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764870992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1764870992
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1429608794
Short name T276
Test name
Test status
Simulation time 1743862176 ps
CPU time 23.58 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 12:49:11 PM PDT 24
Peak memory 323196 kb
Host smart-fb1d72ec-eacf-4728-9faa-3f0e3659b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429608794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1429608794
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.4043757440
Short name T55
Test name
Test status
Simulation time 105486762337 ps
CPU time 1165.57 seconds
Started May 16 12:48:28 PM PDT 24
Finished May 16 01:08:19 PM PDT 24
Peak memory 2251852 kb
Host smart-241b10af-1536-45e5-bd37-1e27698f3923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043757440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.4043757440
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.363613280
Short name T854
Test name
Test status
Simulation time 4287654376 ps
CPU time 18.04 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:49:06 PM PDT 24
Peak memory 221480 kb
Host smart-d50ab1c7-7898-4180-a8a4-2181c72ef007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363613280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.363613280
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1898230368
Short name T384
Test name
Test status
Simulation time 562003188 ps
CPU time 2.84 seconds
Started May 16 12:48:30 PM PDT 24
Finished May 16 12:48:58 PM PDT 24
Peak memory 204928 kb
Host smart-b8ba90e6-876e-4d2f-862b-7cb223fabd91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898230368 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1898230368
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2695577742
Short name T161
Test name
Test status
Simulation time 10112760458 ps
CPU time 29.23 seconds
Started May 16 12:48:32 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 332536 kb
Host smart-84fc4a73-7217-4be1-9c17-3fa5e1c7e28c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695577742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2695577742
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.4125067979
Short name T570
Test name
Test status
Simulation time 10119443495 ps
CPU time 71.37 seconds
Started May 16 12:48:33 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 488568 kb
Host smart-cbca679c-1748-4b2a-a7b5-b8e68166ed16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125067979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.4125067979
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2979005098
Short name T585
Test name
Test status
Simulation time 394851939 ps
CPU time 2.26 seconds
Started May 16 12:48:33 PM PDT 24
Finished May 16 12:48:58 PM PDT 24
Peak memory 204964 kb
Host smart-31b7aaf8-1cea-4229-92d6-8a76ec92c5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979005098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2979005098
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.740753272
Short name T547
Test name
Test status
Simulation time 3369250228 ps
CPU time 4.59 seconds
Started May 16 12:48:34 PM PDT 24
Finished May 16 12:49:01 PM PDT 24
Peak memory 208616 kb
Host smart-641cb290-b98b-4419-9b9a-f3474d5596f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740753272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.740753272
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1769805361
Short name T846
Test name
Test status
Simulation time 6091758974 ps
CPU time 22.08 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:17 PM PDT 24
Peak memory 838232 kb
Host smart-bf0f9ddb-f9cb-4235-9fa2-e510c4a0c4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769805361 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1769805361
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2100165263
Short name T1274
Test name
Test status
Simulation time 1694352033 ps
CPU time 6.06 seconds
Started May 16 12:48:23 PM PDT 24
Finished May 16 12:48:54 PM PDT 24
Peak memory 204796 kb
Host smart-b81f1b10-c6fa-4190-a1e4-75b16b9a2d7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100165263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2100165263
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2586855789
Short name T791
Test name
Test status
Simulation time 5126273141 ps
CPU time 56.03 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 206508 kb
Host smart-c71f67b6-66dc-40ad-8fa7-43011c93aec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586855789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2586855789
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.229492386
Short name T313
Test name
Test status
Simulation time 16720094267 ps
CPU time 16.44 seconds
Started May 16 12:48:21 PM PDT 24
Finished May 16 12:49:04 PM PDT 24
Peak memory 205016 kb
Host smart-c19c0ad3-e084-458f-a00d-9bcc0a6a122e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229492386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.229492386
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3381321355
Short name T642
Test name
Test status
Simulation time 6423585962 ps
CPU time 26.46 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:21 PM PDT 24
Peak memory 549396 kb
Host smart-b8898578-67c9-4a3b-9b71-b6a1bf582a37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381321355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3381321355
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.236281286
Short name T698
Test name
Test status
Simulation time 1761058256 ps
CPU time 7.73 seconds
Started May 16 12:48:32 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 213176 kb
Host smart-f6da6358-86f1-4168-9f58-56c993e4c0a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236281286 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.236281286
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.4131226657
Short name T911
Test name
Test status
Simulation time 23039696 ps
CPU time 0.66 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 204452 kb
Host smart-0bc263c8-5044-4fa4-bfbb-af123fa23659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131226657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.4131226657
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2111142410
Short name T564
Test name
Test status
Simulation time 798534737 ps
CPU time 5.47 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:44:52 PM PDT 24
Peak memory 236240 kb
Host smart-d51d00e3-b03f-441c-bf1b-db2972c9b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111142410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2111142410
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2460482082
Short name T1199
Test name
Test status
Simulation time 299004021 ps
CPU time 5.16 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:00 PM PDT 24
Peak memory 263492 kb
Host smart-fd42f93a-7e36-40ac-a0d4-2caa312dd501
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460482082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2460482082
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1595807092
Short name T1008
Test name
Test status
Simulation time 2431368758 ps
CPU time 80.97 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:46:14 PM PDT 24
Peak memory 683568 kb
Host smart-9cef724d-9c32-42c5-904e-ee26fd349e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595807092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1595807092
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3905448584
Short name T907
Test name
Test status
Simulation time 3019854515 ps
CPU time 42.51 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:45:38 PM PDT 24
Peak memory 581052 kb
Host smart-627fcd32-614a-45d7-a84e-7ffb4567e5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905448584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3905448584
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3639134658
Short name T1216
Test name
Test status
Simulation time 151632183 ps
CPU time 3.37 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:44:59 PM PDT 24
Peak memory 204936 kb
Host smart-9e9ec79e-3416-49df-96f9-50d17f4156e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639134658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3639134658
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3978046092
Short name T107
Test name
Test status
Simulation time 3931702194 ps
CPU time 89.65 seconds
Started May 16 12:44:35 PM PDT 24
Finished May 16 12:46:19 PM PDT 24
Peak memory 1021592 kb
Host smart-0542a5c1-f645-454f-bcc6-e05846ead3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978046092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3978046092
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1322915924
Short name T1069
Test name
Test status
Simulation time 460897414 ps
CPU time 7.14 seconds
Started May 16 12:44:42 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 204888 kb
Host smart-3f53cddc-a33f-4d7b-b9c7-d0fbe74578b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322915924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1322915924
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3472009565
Short name T1081
Test name
Test status
Simulation time 13449123554 ps
CPU time 44.19 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:38 PM PDT 24
Peak memory 494864 kb
Host smart-cb3f97a2-5df0-43f9-9954-1282285d79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472009565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3472009565
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3508265872
Short name T658
Test name
Test status
Simulation time 17294730 ps
CPU time 0.66 seconds
Started May 16 12:44:36 PM PDT 24
Finished May 16 12:44:51 PM PDT 24
Peak memory 204604 kb
Host smart-bc4d75b3-97d8-4193-9f25-7cc56d5f3cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508265872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3508265872
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1513550202
Short name T621
Test name
Test status
Simulation time 5393145692 ps
CPU time 38.77 seconds
Started May 16 12:44:39 PM PDT 24
Finished May 16 12:45:34 PM PDT 24
Peak memory 555252 kb
Host smart-da843238-073e-46ea-801f-916173d3b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513550202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1513550202
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2583591311
Short name T979
Test name
Test status
Simulation time 4630868233 ps
CPU time 86.62 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:46:13 PM PDT 24
Peak memory 359628 kb
Host smart-b59bbca9-14ff-4444-9b06-d5375fa700c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583591311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2583591311
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2986493860
Short name T892
Test name
Test status
Simulation time 43673006528 ps
CPU time 1871.32 seconds
Started May 16 12:44:41 PM PDT 24
Finished May 16 01:16:11 PM PDT 24
Peak memory 4838052 kb
Host smart-d9798e7b-b12e-4385-8e7f-d27f01b5781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986493860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2986493860
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2189143683
Short name T752
Test name
Test status
Simulation time 3285817404 ps
CPU time 27.44 seconds
Started May 16 12:44:33 PM PDT 24
Finished May 16 12:45:13 PM PDT 24
Peak memory 213204 kb
Host smart-44d55591-46fb-40ef-aa06-93dbc7faf42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189143683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2189143683
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.890136887
Short name T174
Test name
Test status
Simulation time 245437298 ps
CPU time 0.93 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:44:55 PM PDT 24
Peak memory 223184 kb
Host smart-e75fe846-e570-4dcf-ad84-09274a4ce24b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890136887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.890136887
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1169232476
Short name T993
Test name
Test status
Simulation time 1153754720 ps
CPU time 5.33 seconds
Started May 16 12:44:42 PM PDT 24
Finished May 16 12:45:06 PM PDT 24
Peak memory 215264 kb
Host smart-0ad6c090-3143-4b10-a17e-ec20bfd1bfd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169232476 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1169232476
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.46389993
Short name T1172
Test name
Test status
Simulation time 10221848839 ps
CPU time 15.85 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:45:14 PM PDT 24
Peak memory 258396 kb
Host smart-d47b2ee1-d069-407b-9860-66c9506d2248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46389993 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_acq.46389993
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3054255426
Short name T978
Test name
Test status
Simulation time 10241020424 ps
CPU time 10.52 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:45:09 PM PDT 24
Peak memory 262100 kb
Host smart-6d53e5ba-959a-4deb-a03d-8f54bf7a084a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054255426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3054255426
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1858562828
Short name T968
Test name
Test status
Simulation time 598760218 ps
CPU time 2.89 seconds
Started May 16 12:44:42 PM PDT 24
Finished May 16 12:45:04 PM PDT 24
Peak memory 204872 kb
Host smart-cbb85826-91c3-4362-8df9-9defecfbb5e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858562828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1858562828
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2669550967
Short name T271
Test name
Test status
Simulation time 1484417336 ps
CPU time 7.51 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:45:06 PM PDT 24
Peak memory 204956 kb
Host smart-4f3cae8a-8890-4064-afda-e0c3396d2347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669550967 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2669550967
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1533503171
Short name T552
Test name
Test status
Simulation time 13388143225 ps
CPU time 12.14 seconds
Started May 16 12:44:40 PM PDT 24
Finished May 16 12:45:11 PM PDT 24
Peak memory 340460 kb
Host smart-cc1747de-95aa-4675-9dbd-0c04c180ca2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533503171 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1533503171
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.491122249
Short name T349
Test name
Test status
Simulation time 4096257120 ps
CPU time 13.1 seconds
Started May 16 12:44:38 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 205024 kb
Host smart-6f9847b1-04de-4be5-900c-3977a9daffd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491122249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.491122249
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3957312830
Short name T878
Test name
Test status
Simulation time 3577919554 ps
CPU time 24.71 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 235436 kb
Host smart-8fa1f0c4-0187-4696-9e75-ed6daee2bd8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957312830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3957312830
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2219660368
Short name T965
Test name
Test status
Simulation time 9920730230 ps
CPU time 19.74 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:45:12 PM PDT 24
Peak memory 205008 kb
Host smart-10665e07-6300-4e4e-99f1-83c2469a78aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219660368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2219660368
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.1018324929
Short name T761
Test name
Test status
Simulation time 4560534248 ps
CPU time 15.98 seconds
Started May 16 12:44:35 PM PDT 24
Finished May 16 12:45:04 PM PDT 24
Peak memory 375456 kb
Host smart-6e7ede4d-4c3d-4a1a-8c01-36487cd76ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018324929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.1018324929
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1318070029
Short name T452
Test name
Test status
Simulation time 5053374991 ps
CPU time 7.33 seconds
Started May 16 12:44:37 PM PDT 24
Finished May 16 12:45:00 PM PDT 24
Peak memory 220324 kb
Host smart-c9b51270-1feb-48fd-845e-fc85be7faad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318070029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1318070029
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.517499543
Short name T1270
Test name
Test status
Simulation time 46482538 ps
CPU time 0.59 seconds
Started May 16 12:48:41 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 204584 kb
Host smart-297d709e-dd63-4262-abc0-55e7769f2872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517499543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.517499543
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3897522566
Short name T1004
Test name
Test status
Simulation time 288964637 ps
CPU time 2.15 seconds
Started May 16 12:48:34 PM PDT 24
Finished May 16 12:48:58 PM PDT 24
Peak memory 213248 kb
Host smart-03017572-a0c2-4d39-a84e-09ce60bc0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897522566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3897522566
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1275813910
Short name T1113
Test name
Test status
Simulation time 2374051396 ps
CPU time 9.28 seconds
Started May 16 12:48:30 PM PDT 24
Finished May 16 12:49:03 PM PDT 24
Peak memory 314048 kb
Host smart-3e90964b-2a7e-4ebf-8404-cecc230555d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275813910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1275813910
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.256015272
Short name T117
Test name
Test status
Simulation time 2520398755 ps
CPU time 189.62 seconds
Started May 16 12:48:34 PM PDT 24
Finished May 16 12:52:06 PM PDT 24
Peak memory 811600 kb
Host smart-00d7772f-6146-47e3-8b55-f33fcf274a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256015272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.256015272
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.963549603
Short name T1242
Test name
Test status
Simulation time 1851748219 ps
CPU time 54.58 seconds
Started May 16 12:48:30 PM PDT 24
Finished May 16 12:49:49 PM PDT 24
Peak memory 665556 kb
Host smart-9d0dc1c0-9a3a-431c-b176-bd36d5a51763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963549603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.963549603
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3100977517
Short name T825
Test name
Test status
Simulation time 199721834 ps
CPU time 0.97 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:48:56 PM PDT 24
Peak memory 204836 kb
Host smart-f044c778-0fb5-4d35-b93c-cea278d9cdeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100977517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3100977517
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2357280075
Short name T1131
Test name
Test status
Simulation time 237762753 ps
CPU time 13.64 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:09 PM PDT 24
Peak memory 252816 kb
Host smart-ab19101a-d7d3-45e9-a320-1558a64a6c58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357280075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2357280075
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1606548921
Short name T109
Test name
Test status
Simulation time 7252407112 ps
CPU time 98.21 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:50:33 PM PDT 24
Peak memory 1105636 kb
Host smart-d8f10692-01fb-4cb0-a111-39359fd951fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606548921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1606548921
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.746764566
Short name T873
Test name
Test status
Simulation time 295135141 ps
CPU time 3.47 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 204904 kb
Host smart-a1c622fd-08a8-4f00-8e05-7c0d1e4e380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746764566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.746764566
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2265201405
Short name T1244
Test name
Test status
Simulation time 7359085787 ps
CPU time 36.46 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:40 PM PDT 24
Peak memory 366096 kb
Host smart-9649de0e-f909-49dd-897b-e403f230edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265201405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2265201405
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1973600971
Short name T1234
Test name
Test status
Simulation time 31077750 ps
CPU time 0.71 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:48:56 PM PDT 24
Peak memory 204604 kb
Host smart-1fe86142-4ef2-4d01-bf39-0c79a8325541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973600971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1973600971
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1146125112
Short name T881
Test name
Test status
Simulation time 1317018746 ps
CPU time 59.17 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 294544 kb
Host smart-5cc22683-11be-47a5-97ef-49b0b6020be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146125112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1146125112
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1011898197
Short name T122
Test name
Test status
Simulation time 10064374745 ps
CPU time 369.79 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:55:05 PM PDT 24
Peak memory 2274784 kb
Host smart-b5f4f826-80cc-4388-936c-67c502b6a0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011898197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1011898197
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3359886517
Short name T1034
Test name
Test status
Simulation time 2871079219 ps
CPU time 11.92 seconds
Started May 16 12:48:35 PM PDT 24
Finished May 16 12:49:09 PM PDT 24
Peak memory 229212 kb
Host smart-42a638dd-076c-45c5-966d-6833483738d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359886517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3359886517
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3503376647
Short name T857
Test name
Test status
Simulation time 4491624513 ps
CPU time 5.27 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:08 PM PDT 24
Peak memory 213316 kb
Host smart-854d2eba-ddd6-4cb4-89cb-af21bc5018a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503376647 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3503376647
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.187879226
Short name T153
Test name
Test status
Simulation time 10050099700 ps
CPU time 81.79 seconds
Started May 16 12:48:36 PM PDT 24
Finished May 16 12:50:20 PM PDT 24
Peak memory 439528 kb
Host smart-3904bbdb-81f7-4208-9db1-78ba4360e158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187879226 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.187879226
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1665077150
Short name T114
Test name
Test status
Simulation time 10113583027 ps
CPU time 13.76 seconds
Started May 16 12:48:41 PM PDT 24
Finished May 16 12:49:16 PM PDT 24
Peak memory 263940 kb
Host smart-cf1a1256-87e1-4890-a54c-0e20ee931b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665077150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1665077150
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.601478657
Short name T286
Test name
Test status
Simulation time 986010620 ps
CPU time 3.11 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 204968 kb
Host smart-e2a08176-5086-4c6b-81bc-55b98febfd6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601478657 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.601478657
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.224756710
Short name T629
Test name
Test status
Simulation time 18008642148 ps
CPU time 6.92 seconds
Started May 16 12:48:36 PM PDT 24
Finished May 16 12:49:05 PM PDT 24
Peak memory 213308 kb
Host smart-4361afe9-48c0-48cf-a459-8f75d3203c04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224756710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.224756710
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.873887288
Short name T142
Test name
Test status
Simulation time 19427130275 ps
CPU time 388.19 seconds
Started May 16 12:48:34 PM PDT 24
Finished May 16 12:55:25 PM PDT 24
Peak memory 4474852 kb
Host smart-7a4289cd-9569-4d98-8c0d-e78414560988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873887288 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.873887288
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1443722258
Short name T550
Test name
Test status
Simulation time 709446738 ps
CPU time 9.84 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:05 PM PDT 24
Peak memory 204836 kb
Host smart-2e608610-3a06-4d2e-af55-155209eb294d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443722258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1443722258
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1354674063
Short name T1052
Test name
Test status
Simulation time 313982656 ps
CPU time 13.73 seconds
Started May 16 12:48:33 PM PDT 24
Finished May 16 12:49:10 PM PDT 24
Peak memory 204936 kb
Host smart-c6172bd2-934b-44bb-85b6-4a1f18033c3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354674063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1354674063
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2659383393
Short name T417
Test name
Test status
Simulation time 47043582939 ps
CPU time 961.04 seconds
Started May 16 12:48:36 PM PDT 24
Finished May 16 01:04:59 PM PDT 24
Peak memory 6725576 kb
Host smart-62deaa61-9414-4648-b2fa-042d27c9a695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659383393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2659383393
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2206777404
Short name T1138
Test name
Test status
Simulation time 1739962330 ps
CPU time 7.1 seconds
Started May 16 12:48:31 PM PDT 24
Finished May 16 12:49:02 PM PDT 24
Peak memory 210612 kb
Host smart-c9834cd0-5e6a-4bea-979e-b5bf76a0de63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206777404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2206777404
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.93703348
Short name T1001
Test name
Test status
Simulation time 49367099 ps
CPU time 0.6 seconds
Started May 16 12:48:58 PM PDT 24
Finished May 16 12:49:16 PM PDT 24
Peak memory 204500 kb
Host smart-05f7f58b-312e-4a25-8030-27f1637c434e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93703348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.93703348
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.480097236
Short name T321
Test name
Test status
Simulation time 176889507 ps
CPU time 2.57 seconds
Started May 16 12:48:45 PM PDT 24
Finished May 16 12:49:09 PM PDT 24
Peak memory 220644 kb
Host smart-87b14487-0694-44b0-8644-9058573e3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480097236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.480097236
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3831666337
Short name T1258
Test name
Test status
Simulation time 1657301268 ps
CPU time 8.22 seconds
Started May 16 12:48:44 PM PDT 24
Finished May 16 12:49:13 PM PDT 24
Peak memory 295812 kb
Host smart-39730ad4-9831-446c-9657-42f98740a418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831666337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3831666337
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3327066359
Short name T169
Test name
Test status
Simulation time 1568234472 ps
CPU time 103.17 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:50:47 PM PDT 24
Peak memory 528176 kb
Host smart-3a2af363-d328-4218-832a-53faf5381ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327066359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3327066359
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1746456441
Short name T877
Test name
Test status
Simulation time 3861649944 ps
CPU time 54.55 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:49:59 PM PDT 24
Peak memory 512904 kb
Host smart-2f1e6321-ee45-4ebc-8273-05ba2ab2ae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746456441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1746456441
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3254286657
Short name T848
Test name
Test status
Simulation time 185967417 ps
CPU time 1.17 seconds
Started May 16 12:48:44 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 204840 kb
Host smart-8d1de6f5-9a52-40c1-913e-f0ae1876c36b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254286657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3254286657
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.15564380
Short name T341
Test name
Test status
Simulation time 211395241 ps
CPU time 4.23 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:08 PM PDT 24
Peak memory 204928 kb
Host smart-428f569f-f573-4e4c-aea1-274384c430aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15564380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.15564380
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.376003143
Short name T254
Test name
Test status
Simulation time 9893388932 ps
CPU time 387.58 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:55:32 PM PDT 24
Peak memory 1403272 kb
Host smart-b05aa8f6-ceb7-4634-af56-e2b3453ec365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376003143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.376003143
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1886638689
Short name T537
Test name
Test status
Simulation time 814011189 ps
CPU time 35.19 seconds
Started May 16 12:48:52 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 204952 kb
Host smart-380c611f-8d40-40ec-b298-240fd38641bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886638689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1886638689
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3513485723
Short name T1210
Test name
Test status
Simulation time 1734082748 ps
CPU time 79.19 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:50:31 PM PDT 24
Peak memory 350648 kb
Host smart-b8e9c17f-9234-4551-b57d-d74ab6d2974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513485723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3513485723
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3698652161
Short name T901
Test name
Test status
Simulation time 142588160 ps
CPU time 0.63 seconds
Started May 16 12:48:47 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 204576 kb
Host smart-7823f39b-7721-4983-bc3b-7cae5bda1985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698652161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3698652161
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2362853803
Short name T401
Test name
Test status
Simulation time 6242067239 ps
CPU time 33.78 seconds
Started May 16 12:48:48 PM PDT 24
Finished May 16 12:49:41 PM PDT 24
Peak memory 213204 kb
Host smart-1a44ae33-bb28-4474-be1b-157ef2567973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362853803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2362853803
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2155174965
Short name T677
Test name
Test status
Simulation time 2334369245 ps
CPU time 41.84 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 440240 kb
Host smart-1f5d112f-5669-47b0-b020-6be92d0323a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155174965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2155174965
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3079450632
Short name T124
Test name
Test status
Simulation time 21441873621 ps
CPU time 505.56 seconds
Started May 16 12:48:41 PM PDT 24
Finished May 16 12:57:28 PM PDT 24
Peak memory 1330156 kb
Host smart-0b68f883-89aa-4b7d-9231-beea9ff5fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079450632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3079450632
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1111737436
Short name T820
Test name
Test status
Simulation time 817561572 ps
CPU time 15.48 seconds
Started May 16 12:48:41 PM PDT 24
Finished May 16 12:49:17 PM PDT 24
Peak memory 216672 kb
Host smart-a69162c6-7158-4421-b8d8-3f0b0a0bc4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111737436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1111737436
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.718782344
Short name T668
Test name
Test status
Simulation time 5721606932 ps
CPU time 4.12 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:49:16 PM PDT 24
Peak memory 213252 kb
Host smart-beae28db-6a43-4c3b-b457-f476525733c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718782344 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.718782344
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.317946096
Short name T1110
Test name
Test status
Simulation time 10112813065 ps
CPU time 65.9 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:50:10 PM PDT 24
Peak memory 504480 kb
Host smart-cf27ed6c-73d1-498d-87a5-e9c1c2656ec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317946096 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.317946096
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1620224536
Short name T308
Test name
Test status
Simulation time 11591462946 ps
CPU time 4.27 seconds
Started May 16 12:48:44 PM PDT 24
Finished May 16 12:49:10 PM PDT 24
Peak memory 229888 kb
Host smart-7062a8f5-f845-44e9-930c-328390185795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620224536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1620224536
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2082194766
Short name T673
Test name
Test status
Simulation time 954448292 ps
CPU time 2.56 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 205060 kb
Host smart-d56a27b1-c906-4993-83af-c63119c565d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082194766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2082194766
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1814010187
Short name T1003
Test name
Test status
Simulation time 1747707619 ps
CPU time 4.63 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:07 PM PDT 24
Peak memory 204916 kb
Host smart-6cc6219c-954e-463d-9e6c-65181dce52d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814010187 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1814010187
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.649140781
Short name T623
Test name
Test status
Simulation time 3094377682 ps
CPU time 7.1 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:11 PM PDT 24
Peak memory 204996 kb
Host smart-69edf5b3-de91-41b1-941a-4152cf694bd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649140781 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.649140781
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2243165403
Short name T1271
Test name
Test status
Simulation time 4700016112 ps
CPU time 13.53 seconds
Started May 16 12:48:42 PM PDT 24
Finished May 16 12:49:16 PM PDT 24
Peak memory 205060 kb
Host smart-8dcd45a7-c0bc-4301-a1d9-21c95bf3ea06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243165403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2243165403
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2066178883
Short name T470
Test name
Test status
Simulation time 2721421615 ps
CPU time 12.77 seconds
Started May 16 12:48:41 PM PDT 24
Finished May 16 12:49:15 PM PDT 24
Peak memory 209248 kb
Host smart-24d821ae-4f69-4c26-a270-736dfa8b9380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066178883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2066178883
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3489114822
Short name T1032
Test name
Test status
Simulation time 21962082636 ps
CPU time 52.75 seconds
Started May 16 12:48:46 PM PDT 24
Finished May 16 12:49:59 PM PDT 24
Peak memory 528192 kb
Host smart-d9e4c721-98d6-420f-9190-0523985a25f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489114822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3489114822
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2937424954
Short name T1075
Test name
Test status
Simulation time 13375578050 ps
CPU time 1958.29 seconds
Started May 16 12:48:45 PM PDT 24
Finished May 16 01:21:45 PM PDT 24
Peak memory 3057380 kb
Host smart-f85b1fae-5f26-45fa-b072-cc7f8bca73bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937424954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2937424954
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3767267715
Short name T505
Test name
Test status
Simulation time 1225954129 ps
CPU time 6.85 seconds
Started May 16 12:48:43 PM PDT 24
Finished May 16 12:49:11 PM PDT 24
Peak memory 221276 kb
Host smart-d3cf96b9-0675-4737-81cc-96856565a35d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767267715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3767267715
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1590780960
Short name T1151
Test name
Test status
Simulation time 49440255 ps
CPU time 0.6 seconds
Started May 16 12:48:52 PM PDT 24
Finished May 16 12:49:11 PM PDT 24
Peak memory 204548 kb
Host smart-7b1fa455-defd-4fb8-9c3e-ee5ed73fb8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590780960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1590780960
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1488145035
Short name T710
Test name
Test status
Simulation time 71247599 ps
CPU time 1.55 seconds
Started May 16 12:48:56 PM PDT 24
Finished May 16 12:49:15 PM PDT 24
Peak memory 213172 kb
Host smart-0365ade2-cbc4-4af9-9449-26012e41e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488145035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1488145035
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2971808705
Short name T1330
Test name
Test status
Simulation time 5982883410 ps
CPU time 26.03 seconds
Started May 16 12:48:53 PM PDT 24
Finished May 16 12:49:37 PM PDT 24
Peak memory 314508 kb
Host smart-daeb6e67-4523-461c-89b6-9af96d3bebd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971808705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2971808705
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3506579629
Short name T1044
Test name
Test status
Simulation time 25369828848 ps
CPU time 231.12 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:53:03 PM PDT 24
Peak memory 899988 kb
Host smart-164d8747-0864-4f61-bd24-6b429de65166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506579629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3506579629
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2195978764
Short name T806
Test name
Test status
Simulation time 1535241285 ps
CPU time 107.88 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:50:59 PM PDT 24
Peak memory 583792 kb
Host smart-6518eed8-b8f1-4d1e-a569-35b5e76cec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195978764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2195978764
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.33401082
Short name T233
Test name
Test status
Simulation time 762538316 ps
CPU time 1.16 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:49:13 PM PDT 24
Peak memory 204848 kb
Host smart-b14f95dd-6f51-4a70-bfc0-4fa96ba08e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt
.33401082
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.103550589
Short name T969
Test name
Test status
Simulation time 301770676 ps
CPU time 8.4 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 204924 kb
Host smart-ea18cd81-8ef5-4c56-a90a-b05482e978e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103550589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
103550589
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1294549096
Short name T105
Test name
Test status
Simulation time 7214382926 ps
CPU time 107.45 seconds
Started May 16 12:48:53 PM PDT 24
Finished May 16 12:50:59 PM PDT 24
Peak memory 1244840 kb
Host smart-5f7cb496-3858-4935-9646-4bf670dc0fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294549096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1294549096
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1792075477
Short name T423
Test name
Test status
Simulation time 466186712 ps
CPU time 18.31 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:33 PM PDT 24
Peak memory 205028 kb
Host smart-a2009808-0c99-4f4d-8654-40969e50bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792075477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1792075477
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2646048427
Short name T344
Test name
Test status
Simulation time 4266964086 ps
CPU time 39.93 seconds
Started May 16 12:48:56 PM PDT 24
Finished May 16 12:49:53 PM PDT 24
Peak memory 374072 kb
Host smart-b489f3e9-1d65-4950-a3c8-c794feb4d5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646048427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2646048427
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1705296311
Short name T75
Test name
Test status
Simulation time 192562746 ps
CPU time 0.68 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:15 PM PDT 24
Peak memory 204712 kb
Host smart-7e2da063-7bfa-4e54-999c-55b9caa34eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705296311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1705296311
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1419361995
Short name T764
Test name
Test status
Simulation time 584745337 ps
CPU time 7.68 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 237568 kb
Host smart-76672ef5-2cf2-4c2f-83bf-0b81588edefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419361995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1419361995
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3465176127
Short name T581
Test name
Test status
Simulation time 2046226756 ps
CPU time 37.31 seconds
Started May 16 12:48:56 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 447988 kb
Host smart-bf5d5d8f-5d2f-48d3-ad28-a5fe5d8ba2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465176127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3465176127
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2981209866
Short name T826
Test name
Test status
Simulation time 2687019351 ps
CPU time 12.16 seconds
Started May 16 12:48:56 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 216088 kb
Host smart-97ce41ba-60ea-42e5-a5a6-56011fdeb816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981209866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2981209866
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.697089720
Short name T789
Test name
Test status
Simulation time 2329019205 ps
CPU time 3.33 seconds
Started May 16 12:48:58 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 205084 kb
Host smart-1ea9e528-6933-4312-bfb8-4a5fbd12b3a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697089720 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.697089720
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2038059640
Short name T414
Test name
Test status
Simulation time 10091231679 ps
CPU time 33.49 seconds
Started May 16 12:48:56 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 322868 kb
Host smart-146f23a8-4e5e-4cd2-ba9c-b5e698cb416a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038059640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2038059640
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3182857906
Short name T89
Test name
Test status
Simulation time 10127714508 ps
CPU time 35.66 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:50 PM PDT 24
Peak memory 340816 kb
Host smart-12ce6411-48fc-4d60-9e8a-c93ee076452f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182857906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3182857906
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.714256687
Short name T794
Test name
Test status
Simulation time 1530912573 ps
CPU time 2.53 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:17 PM PDT 24
Peak memory 205036 kb
Host smart-ff640661-f9e0-431b-a53e-8387a0a835f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714256687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.714256687
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2392903204
Short name T1294
Test name
Test status
Simulation time 1561710722 ps
CPU time 7.54 seconds
Started May 16 12:48:52 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 219572 kb
Host smart-c834a796-7d8e-4a8b-9ad5-b085ab945cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392903204 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2392903204
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.918865232
Short name T555
Test name
Test status
Simulation time 24149272534 ps
CPU time 546.41 seconds
Started May 16 12:48:52 PM PDT 24
Finished May 16 12:58:17 PM PDT 24
Peak memory 5482420 kb
Host smart-7dfff3ad-91e1-47ac-a69f-3980c859c0c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918865232 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.918865232
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3703625633
Short name T765
Test name
Test status
Simulation time 3705369854 ps
CPU time 30.63 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 204988 kb
Host smart-363861fd-d061-4f3b-af14-b72719b9a3ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703625633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3703625633
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.650387674
Short name T181
Test name
Test status
Simulation time 394202219 ps
CPU time 6.04 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 204848 kb
Host smart-01cddcb8-64e6-440e-bad0-ed9104087bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650387674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.650387674
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.1645672378
Short name T1296
Test name
Test status
Simulation time 55997832096 ps
CPU time 517.14 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:57:52 PM PDT 24
Peak memory 4508188 kb
Host smart-5dcfb77a-0eac-4279-a81d-92241a367674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645672378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.1645672378
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1604951228
Short name T929
Test name
Test status
Simulation time 28213382655 ps
CPU time 2019.18 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 01:22:52 PM PDT 24
Peak memory 5987288 kb
Host smart-37006885-8421-44e7-a3c1-e06d1f705961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604951228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1604951228
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1296549188
Short name T158
Test name
Test status
Simulation time 5891762452 ps
CPU time 7.63 seconds
Started May 16 12:48:52 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 221228 kb
Host smart-56dca614-51c8-4e19-9cf6-b51e3ce81971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296549188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1296549188
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.4267703173
Short name T946
Test name
Test status
Simulation time 18792250 ps
CPU time 0.66 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 204588 kb
Host smart-1b325fe4-2f85-4151-94da-215af4f01438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267703173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.4267703173
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3961986087
Short name T818
Test name
Test status
Simulation time 87592250 ps
CPU time 1.72 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:20 PM PDT 24
Peak memory 213124 kb
Host smart-0e7fdc2c-8061-49b1-b9ca-024edf6e1966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961986087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3961986087
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.4024301901
Short name T1114
Test name
Test status
Simulation time 352917959 ps
CPU time 6.6 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:19 PM PDT 24
Peak memory 283028 kb
Host smart-6fbec9b5-09a8-40fc-9762-45b5531f4266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024301901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.4024301901
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1509073935
Short name T1097
Test name
Test status
Simulation time 2903903320 ps
CPU time 36.58 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 334412 kb
Host smart-1450db10-edc0-4b20-972d-d54c10a37851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509073935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1509073935
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.136413141
Short name T578
Test name
Test status
Simulation time 1768157225 ps
CPU time 131.39 seconds
Started May 16 12:48:57 PM PDT 24
Finished May 16 12:51:26 PM PDT 24
Peak memory 598760 kb
Host smart-671e43c2-82c6-4311-a5be-a24d5a256ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136413141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.136413141
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3712002375
Short name T230
Test name
Test status
Simulation time 226682176 ps
CPU time 0.95 seconds
Started May 16 12:48:58 PM PDT 24
Finished May 16 12:49:16 PM PDT 24
Peak memory 204744 kb
Host smart-4c5f10d8-0eb5-41e4-afe1-6ffc66a203df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712002375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3712002375
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.100024241
Short name T823
Test name
Test status
Simulation time 137592391 ps
CPU time 8.18 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:21 PM PDT 24
Peak memory 229492 kb
Host smart-16d61cee-540f-478e-baec-f045cad241a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100024241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
100024241
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2149244322
Short name T870
Test name
Test status
Simulation time 2906199044 ps
CPU time 168.98 seconds
Started May 16 12:48:54 PM PDT 24
Finished May 16 12:52:01 PM PDT 24
Peak memory 859804 kb
Host smart-3c82b0b7-4bae-4a0f-ba74-55dab37ce8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149244322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2149244322
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.230099791
Short name T1090
Test name
Test status
Simulation time 656859318 ps
CPU time 22.16 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 204984 kb
Host smart-8ea49c76-06c3-4e1e-8676-e94559dced58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230099791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.230099791
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3319440308
Short name T842
Test name
Test status
Simulation time 4332049467 ps
CPU time 31.13 seconds
Started May 16 12:49:05 PM PDT 24
Finished May 16 12:49:52 PM PDT 24
Peak memory 297192 kb
Host smart-5f1da2a9-bd9f-4d12-bb0a-82ef9da9b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319440308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3319440308
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3745776026
Short name T607
Test name
Test status
Simulation time 5503892201 ps
CPU time 79.36 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:50:32 PM PDT 24
Peak memory 531504 kb
Host smart-9cd25f1c-f8aa-476f-95f3-f6014f410898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745776026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3745776026
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1928603223
Short name T57
Test name
Test status
Simulation time 1555880059 ps
CPU time 28.25 seconds
Started May 16 12:48:58 PM PDT 24
Finished May 16 12:49:44 PM PDT 24
Peak memory 332984 kb
Host smart-d236a5ea-8bd6-4b14-93af-7117edc961fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928603223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1928603223
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.721614738
Short name T262
Test name
Test status
Simulation time 44888300955 ps
CPU time 1083.54 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 01:07:24 PM PDT 24
Peak memory 1748348 kb
Host smart-5326219b-7be4-4c5a-9878-79d504169a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721614738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.721614738
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3535006817
Short name T763
Test name
Test status
Simulation time 560951968 ps
CPU time 23.47 seconds
Started May 16 12:48:55 PM PDT 24
Finished May 16 12:49:36 PM PDT 24
Peak memory 213100 kb
Host smart-18032612-72ee-4507-8fdc-0fada0705301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535006817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3535006817
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1765006127
Short name T812
Test name
Test status
Simulation time 3196226583 ps
CPU time 3.88 seconds
Started May 16 12:49:01 PM PDT 24
Finished May 16 12:49:22 PM PDT 24
Peak memory 205144 kb
Host smart-f6001c0b-15ef-477a-bd06-eb85d5bb477e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765006127 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1765006127
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2377029508
Short name T435
Test name
Test status
Simulation time 10144859085 ps
CPU time 84.47 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 12:50:44 PM PDT 24
Peak memory 498236 kb
Host smart-106632ea-6fd5-45fe-a300-4409cecc08fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377029508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2377029508
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3591975689
Short name T650
Test name
Test status
Simulation time 10152505470 ps
CPU time 70.83 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:50:31 PM PDT 24
Peak memory 459380 kb
Host smart-5ad7c697-d766-466c-8169-013d8ad9f027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591975689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3591975689
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.600095815
Short name T802
Test name
Test status
Simulation time 1896211976 ps
CPU time 2.62 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:23 PM PDT 24
Peak memory 204996 kb
Host smart-04bd0db5-120e-46d4-bb54-a618f2560b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600095815 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.600095815
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.197106711
Short name T1325
Test name
Test status
Simulation time 1533352319 ps
CPU time 8.12 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:27 PM PDT 24
Peak memory 221272 kb
Host smart-a6e0b96f-12b2-47a0-9995-3e4bff020686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197106711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.197106711
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3864471186
Short name T500
Test name
Test status
Simulation time 5748595531 ps
CPU time 4.35 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:49:32 PM PDT 24
Peak memory 205104 kb
Host smart-c40f4b46-0116-4373-82d6-9226d040b44a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864471186 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3864471186
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3762541482
Short name T1093
Test name
Test status
Simulation time 2544658475 ps
CPU time 22.12 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 205164 kb
Host smart-d33bff0d-7a4c-4983-8234-dfc8baaa1c36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762541482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3762541482
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1635776190
Short name T163
Test name
Test status
Simulation time 13569463462 ps
CPU time 40.31 seconds
Started May 16 12:49:01 PM PDT 24
Finished May 16 12:49:58 PM PDT 24
Peak memory 206280 kb
Host smart-fa37d998-f064-4d10-83eb-7cc2b031f884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635776190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1635776190
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.971894465
Short name T845
Test name
Test status
Simulation time 37527106163 ps
CPU time 178.68 seconds
Started May 16 12:49:01 PM PDT 24
Finished May 16 12:52:16 PM PDT 24
Peak memory 2285328 kb
Host smart-0c218a3c-e4d9-4a3f-888b-998a8c63bd15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971894465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.971894465
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2987915225
Short name T1320
Test name
Test status
Simulation time 15364247183 ps
CPU time 1277.73 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 01:10:39 PM PDT 24
Peak memory 2763792 kb
Host smart-9deec289-68bc-48c3-8757-36f389f33494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987915225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2987915225
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1337340132
Short name T894
Test name
Test status
Simulation time 2253317149 ps
CPU time 6.3 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 12:49:26 PM PDT 24
Peak memory 219244 kb
Host smart-01ae453a-3142-4c40-a947-6de94a97532b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337340132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1337340132
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2625438736
Short name T289
Test name
Test status
Simulation time 18160483 ps
CPU time 0.64 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:49:31 PM PDT 24
Peak memory 204600 kb
Host smart-01b6b259-58a0-4f81-8bab-fea8665906e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625438736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2625438736
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2810040542
Short name T538
Test name
Test status
Simulation time 102873113 ps
CPU time 1.32 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:49:22 PM PDT 24
Peak memory 213112 kb
Host smart-7916020c-7431-46b5-8cb3-2d9caf0e3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810040542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2810040542
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3512273708
Short name T648
Test name
Test status
Simulation time 432370208 ps
CPU time 23.47 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 298304 kb
Host smart-4f83f16a-6eef-4597-8e52-b2e844b9dc43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512273708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3512273708
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3321934999
Short name T79
Test name
Test status
Simulation time 2430606171 ps
CPU time 93.7 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 12:50:54 PM PDT 24
Peak memory 548024 kb
Host smart-440a4077-dc1a-4278-9b1a-bd50e63b2aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321934999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3321934999
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3994243536
Short name T703
Test name
Test status
Simulation time 2092002722 ps
CPU time 74.06 seconds
Started May 16 12:49:05 PM PDT 24
Finished May 16 12:50:35 PM PDT 24
Peak memory 704528 kb
Host smart-7694b787-ff51-4efa-8990-8adb80ad6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994243536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3994243536
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1066145102
Short name T1041
Test name
Test status
Simulation time 171405415 ps
CPU time 0.97 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:49:22 PM PDT 24
Peak memory 204772 kb
Host smart-d29d76eb-12b1-4d71-b369-df17539576a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066145102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1066145102
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1203218698
Short name T534
Test name
Test status
Simulation time 198087782 ps
CPU time 4.78 seconds
Started May 16 12:49:03 PM PDT 24
Finished May 16 12:49:25 PM PDT 24
Peak memory 238980 kb
Host smart-cfea60df-800a-4371-ab06-672ce312060a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203218698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1203218698
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1380679994
Short name T451
Test name
Test status
Simulation time 13521538235 ps
CPU time 207.37 seconds
Started May 16 12:49:05 PM PDT 24
Finished May 16 12:52:49 PM PDT 24
Peak memory 912772 kb
Host smart-ba371528-8f3b-4230-990a-e52296be0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380679994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1380679994
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3371216565
Short name T43
Test name
Test status
Simulation time 594551661 ps
CPU time 6.93 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:49:37 PM PDT 24
Peak memory 204800 kb
Host smart-cf620ea5-5e7e-48db-9aaf-a3e0e1e0a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371216565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3371216565
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.610217199
Short name T34
Test name
Test status
Simulation time 7464610342 ps
CPU time 34.76 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:50:04 PM PDT 24
Peak memory 350452 kb
Host smart-89af9d31-bfd0-4df3-aef3-91dd8573cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610217199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.610217199
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.28929462
Short name T132
Test name
Test status
Simulation time 33740131 ps
CPU time 0.63 seconds
Started May 16 12:49:01 PM PDT 24
Finished May 16 12:49:18 PM PDT 24
Peak memory 204680 kb
Host smart-d4c4067e-ae26-4ff1-acbd-9f4a6b7882b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28929462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.28929462
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.308816848
Short name T115
Test name
Test status
Simulation time 1106189215 ps
CPU time 4.99 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:49:26 PM PDT 24
Peak memory 221860 kb
Host smart-f1c0aac1-9aff-443f-8190-cd0db47ab7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308816848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.308816848
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2239224587
Short name T1106
Test name
Test status
Simulation time 1458509415 ps
CPU time 65.95 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:50:26 PM PDT 24
Peak memory 295224 kb
Host smart-e504f9d2-14d1-429a-bd60-2e81a16c6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239224587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2239224587
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4023248826
Short name T605
Test name
Test status
Simulation time 7647088486 ps
CPU time 239.96 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:53:28 PM PDT 24
Peak memory 1562504 kb
Host smart-80115a27-b6c1-4a40-8d65-232f89089dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023248826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4023248826
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.966267209
Short name T1173
Test name
Test status
Simulation time 1619369390 ps
CPU time 7.42 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:49:35 PM PDT 24
Peak memory 221356 kb
Host smart-483c227d-0681-4d81-9dcf-4d4c8d362456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966267209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.966267209
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1482826312
Short name T1240
Test name
Test status
Simulation time 798124733 ps
CPU time 4.4 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:49:33 PM PDT 24
Peak memory 213188 kb
Host smart-bb16ce15-4d62-47b1-bd1a-a1fce9632c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482826312 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1482826312
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.57031008
Short name T983
Test name
Test status
Simulation time 10257793667 ps
CPU time 26.96 seconds
Started May 16 12:49:08 PM PDT 24
Finished May 16 12:49:51 PM PDT 24
Peak memory 301116 kb
Host smart-62eadee7-aff6-4470-9d3d-4fbbe510f94c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57031008 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_acq.57031008
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2545279451
Short name T516
Test name
Test status
Simulation time 10070370978 ps
CPU time 72.97 seconds
Started May 16 12:49:15 PM PDT 24
Finished May 16 12:50:44 PM PDT 24
Peak memory 455404 kb
Host smart-431d7228-97c8-4211-b19e-21e4be613313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545279451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2545279451
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1917855135
Short name T1232
Test name
Test status
Simulation time 419048157 ps
CPU time 2.55 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:49:31 PM PDT 24
Peak memory 205028 kb
Host smart-81254fc1-3930-401f-b8b1-f32ffe486547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917855135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1917855135
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1019631180
Short name T998
Test name
Test status
Simulation time 3926537397 ps
CPU time 4.84 seconds
Started May 16 12:49:08 PM PDT 24
Finished May 16 12:49:29 PM PDT 24
Peak memory 208804 kb
Host smart-ec5531a8-3efe-43d3-adf9-049cf13fa333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019631180 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1019631180
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3642518559
Short name T428
Test name
Test status
Simulation time 14082252603 ps
CPU time 50.96 seconds
Started May 16 12:49:07 PM PDT 24
Finished May 16 12:50:14 PM PDT 24
Peak memory 961488 kb
Host smart-4be47916-8ba8-4253-b113-da6deed1635f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642518559 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3642518559
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2853588926
Short name T1316
Test name
Test status
Simulation time 1337415301 ps
CPU time 19.93 seconds
Started May 16 12:49:05 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 204920 kb
Host smart-fc572ad3-7afb-499a-9eb3-729bb6ad9f0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853588926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2853588926
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3664524383
Short name T1261
Test name
Test status
Simulation time 291536443 ps
CPU time 12.18 seconds
Started May 16 12:49:05 PM PDT 24
Finished May 16 12:49:34 PM PDT 24
Peak memory 204944 kb
Host smart-6351f2b8-3ef3-4a8c-bbae-c7c9db1f7582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664524383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3664524383
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3409846920
Short name T635
Test name
Test status
Simulation time 10041735762 ps
CPU time 20.65 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 12:49:41 PM PDT 24
Peak memory 205096 kb
Host smart-cd59bdc4-5dc6-4f1b-98b3-c97f51796fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409846920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3409846920
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2808195496
Short name T467
Test name
Test status
Simulation time 21598552343 ps
CPU time 1171.89 seconds
Started May 16 12:49:04 PM PDT 24
Finished May 16 01:08:53 PM PDT 24
Peak memory 4375236 kb
Host smart-191dae35-4de2-4b1c-81b3-d201c883167c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808195496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2808195496
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2182295704
Short name T1133
Test name
Test status
Simulation time 4332989170 ps
CPU time 7.2 seconds
Started May 16 12:49:02 PM PDT 24
Finished May 16 12:49:27 PM PDT 24
Peak memory 221168 kb
Host smart-02780386-a2c1-4c89-8716-1ca1935ba0e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182295704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2182295704
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.640672601
Short name T824
Test name
Test status
Simulation time 74886287 ps
CPU time 0.67 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:40 PM PDT 24
Peak memory 204620 kb
Host smart-f5827740-1e31-4090-8dbe-e28cf63e55ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640672601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.640672601
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2029516493
Short name T675
Test name
Test status
Simulation time 1011694713 ps
CPU time 2.39 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:49:33 PM PDT 24
Peak memory 213156 kb
Host smart-6951a5e6-959c-4ef9-aa5e-23bc228fb4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029516493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2029516493
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.662948385
Short name T1155
Test name
Test status
Simulation time 840341055 ps
CPU time 10.59 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:49:40 PM PDT 24
Peak memory 243276 kb
Host smart-ae425259-9ff6-4dcd-a2b3-d4292f0dbf0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662948385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.662948385
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3259039
Short name T661
Test name
Test status
Simulation time 1578222657 ps
CPU time 78.58 seconds
Started May 16 12:49:15 PM PDT 24
Finished May 16 12:50:50 PM PDT 24
Peak memory 213140 kb
Host smart-02557b31-8fd3-4cda-95a7-8bfd2617fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3259039
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2465661968
Short name T383
Test name
Test status
Simulation time 1457963296 ps
CPU time 36.46 seconds
Started May 16 12:49:16 PM PDT 24
Finished May 16 12:50:09 PM PDT 24
Peak memory 518500 kb
Host smart-b935dde6-542a-48a1-848d-8b2427a78d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465661968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2465661968
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2609060712
Short name T1091
Test name
Test status
Simulation time 206920003 ps
CPU time 1.19 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:49:30 PM PDT 24
Peak memory 204928 kb
Host smart-1b335e95-8fd8-43ac-9615-5dc98e090cf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609060712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2609060712
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2683681315
Short name T1303
Test name
Test status
Simulation time 252679077 ps
CPU time 3.2 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:49:33 PM PDT 24
Peak memory 204736 kb
Host smart-54fbe5a4-7c69-4527-bb0c-0571aff460a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683681315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2683681315
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.428257269
Short name T913
Test name
Test status
Simulation time 21416554230 ps
CPU time 173.29 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:52:22 PM PDT 24
Peak memory 1512280 kb
Host smart-7723f5f2-e496-49d1-8097-77ec11455a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428257269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.428257269
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2709933439
Short name T936
Test name
Test status
Simulation time 3576552462 ps
CPU time 4.69 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 205008 kb
Host smart-ce6b3179-37a4-4dee-92ed-fbe60e088252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709933439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2709933439
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.305254743
Short name T437
Test name
Test status
Simulation time 14808204413 ps
CPU time 76.78 seconds
Started May 16 12:49:27 PM PDT 24
Finished May 16 12:51:02 PM PDT 24
Peak memory 292092 kb
Host smart-0156be8a-9ef9-43b1-b64e-85220647fb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305254743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.305254743
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.47491447
Short name T522
Test name
Test status
Simulation time 27910677 ps
CPU time 0.68 seconds
Started May 16 12:49:15 PM PDT 24
Finished May 16 12:49:31 PM PDT 24
Peak memory 204580 kb
Host smart-0ad92477-471a-4733-8c43-6f13ff84cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47491447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.47491447
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2258795008
Short name T159
Test name
Test status
Simulation time 12950377713 ps
CPU time 236.18 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:53:25 PM PDT 24
Peak memory 642396 kb
Host smart-20b0ff42-b25d-4fda-a45a-9c2cf0f9d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258795008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2258795008
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3314126987
Short name T714
Test name
Test status
Simulation time 1395097701 ps
CPU time 69.58 seconds
Started May 16 12:49:16 PM PDT 24
Finished May 16 12:50:42 PM PDT 24
Peak memory 327800 kb
Host smart-eef6e3df-9814-4744-a946-bbab5bdf1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314126987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3314126987
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3312780111
Short name T1188
Test name
Test status
Simulation time 660640767 ps
CPU time 30.31 seconds
Started May 16 12:49:16 PM PDT 24
Finished May 16 12:50:03 PM PDT 24
Peak memory 213152 kb
Host smart-0d253b19-92a0-4887-9b7b-6939f274888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312780111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3312780111
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3890483558
Short name T387
Test name
Test status
Simulation time 737469360 ps
CPU time 3.63 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 204968 kb
Host smart-aed1441d-85e7-4a48-b3d8-cb5ebfb46023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890483558 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3890483558
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1633247330
Short name T306
Test name
Test status
Simulation time 10034193569 ps
CPU time 29.54 seconds
Started May 16 12:49:16 PM PDT 24
Finished May 16 12:50:02 PM PDT 24
Peak memory 326364 kb
Host smart-ce21af48-8a64-4cd6-b65b-6235f5e39d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633247330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1633247330
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2513998782
Short name T369
Test name
Test status
Simulation time 10394666057 ps
CPU time 20.96 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:50:06 PM PDT 24
Peak memory 320740 kb
Host smart-8ad7b1d4-0eb2-437d-a809-b6dc3dcd3f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513998782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2513998782
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1034685542
Short name T2
Test name
Test status
Simulation time 1440415179 ps
CPU time 2.47 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:43 PM PDT 24
Peak memory 204944 kb
Host smart-119c9447-3f9b-449e-8855-70b4fd0025a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034685542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1034685542
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1918832493
Short name T32
Test name
Test status
Simulation time 6521650528 ps
CPU time 4.98 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:49:35 PM PDT 24
Peak memory 210056 kb
Host smart-4b94b228-215f-4791-bac1-9ecaa041b424
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918832493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1918832493
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1799044203
Short name T738
Test name
Test status
Simulation time 15899687476 ps
CPU time 187.22 seconds
Started May 16 12:49:14 PM PDT 24
Finished May 16 12:52:37 PM PDT 24
Peak memory 2305544 kb
Host smart-8a54198f-f182-4c78-8a6e-f53e3c8dc9a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799044203 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1799044203
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.9381107
Short name T460
Test name
Test status
Simulation time 2418076471 ps
CPU time 8.39 seconds
Started May 16 12:49:17 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 205092 kb
Host smart-ff967704-9f84-463a-ae41-0a465fa05fe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9381107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_targe
t_smoke.9381107
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3605050814
Short name T1305
Test name
Test status
Simulation time 829670174 ps
CPU time 16.33 seconds
Started May 16 12:49:13 PM PDT 24
Finished May 16 12:49:45 PM PDT 24
Peak memory 212444 kb
Host smart-6c2cb241-9702-4ff8-ae6a-46b56d6eb183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605050814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3605050814
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.880320704
Short name T739
Test name
Test status
Simulation time 61226711829 ps
CPU time 267.01 seconds
Started May 16 12:49:16 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 2673124 kb
Host smart-243ef78c-ceef-40c4-935c-ff68bb688f36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880320704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.880320704
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2773600299
Short name T735
Test name
Test status
Simulation time 6198171995 ps
CPU time 283.19 seconds
Started May 16 12:49:15 PM PDT 24
Finished May 16 12:54:14 PM PDT 24
Peak memory 1170188 kb
Host smart-17c2d3a6-929e-4046-89c7-8b2941889781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773600299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2773600299
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1158227500
Short name T72
Test name
Test status
Simulation time 1423881414 ps
CPU time 7.73 seconds
Started May 16 12:49:12 PM PDT 24
Finished May 16 12:49:36 PM PDT 24
Peak memory 211220 kb
Host smart-a89e392e-7326-4ac4-a388-13ed69df6f76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158227500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1158227500
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.710479491
Short name T1020
Test name
Test status
Simulation time 67470308 ps
CPU time 0.62 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 204552 kb
Host smart-6e187215-c43d-42ae-8ecf-e9653a2418a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710479491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.710479491
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3525545030
Short name T1068
Test name
Test status
Simulation time 885109596 ps
CPU time 3.21 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:46 PM PDT 24
Peak memory 229392 kb
Host smart-33521a8e-224b-4c43-982c-353f0752fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525545030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3525545030
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.118177500
Short name T1282
Test name
Test status
Simulation time 997875267 ps
CPU time 8.58 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:48 PM PDT 24
Peak memory 282456 kb
Host smart-36f93fb1-5bd7-4850-b4b3-567cf50271dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118177500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.118177500
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3631946409
Short name T1012
Test name
Test status
Simulation time 4711372077 ps
CPU time 166.3 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:52:40 PM PDT 24
Peak memory 680320 kb
Host smart-f1902017-79c5-410a-a140-4e18bfe2c634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631946409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3631946409
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.487535730
Short name T766
Test name
Test status
Simulation time 3870387729 ps
CPU time 60.43 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:50:41 PM PDT 24
Peak memory 685068 kb
Host smart-1d3b2d3c-e38b-4a6d-8df0-be131c1809a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487535730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.487535730
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.727700660
Short name T928
Test name
Test status
Simulation time 658930892 ps
CPU time 0.92 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:44 PM PDT 24
Peak memory 204616 kb
Host smart-6abfbe42-3c25-4f1a-a073-3dc1a35fd0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727700660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.727700660
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1704050737
Short name T379
Test name
Test status
Simulation time 179524017 ps
CPU time 3.9 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:44 PM PDT 24
Peak memory 204980 kb
Host smart-3d5f0337-b1df-40eb-afa9-97c89d7b7fa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704050737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1704050737
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2483463509
Short name T851
Test name
Test status
Simulation time 11356011224 ps
CPU time 68.01 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:50:48 PM PDT 24
Peak memory 757688 kb
Host smart-e885ffc6-4d88-462a-b3c4-2fe96c2ef2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483463509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2483463509
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2953678190
Short name T935
Test name
Test status
Simulation time 859881800 ps
CPU time 15.78 seconds
Started May 16 12:49:26 PM PDT 24
Finished May 16 12:50:00 PM PDT 24
Peak memory 204880 kb
Host smart-013d4063-1693-4f89-b622-bca518fd9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953678190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2953678190
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3185904004
Short name T1157
Test name
Test status
Simulation time 4263091410 ps
CPU time 103.89 seconds
Started May 16 12:49:26 PM PDT 24
Finished May 16 12:51:28 PM PDT 24
Peak memory 405748 kb
Host smart-a417b8c8-ccf4-417f-afcd-fc12edd39e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185904004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3185904004
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3661276191
Short name T1062
Test name
Test status
Simulation time 26540585 ps
CPU time 0.73 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:43 PM PDT 24
Peak memory 204576 kb
Host smart-ea9aff44-7462-4655-8f9c-92eb2f443507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661276191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3661276191
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2529981382
Short name T1223
Test name
Test status
Simulation time 24656377523 ps
CPU time 344.68 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:55:25 PM PDT 24
Peak memory 215376 kb
Host smart-02426399-b702-438b-9ad1-e042e337b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529981382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2529981382
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3182450268
Short name T310
Test name
Test status
Simulation time 1393305963 ps
CPU time 26.76 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 309448 kb
Host smart-cea9e920-3a49-4b5a-b3c3-2853f1714dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182450268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3182450268
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.900127146
Short name T259
Test name
Test status
Simulation time 53647489065 ps
CPU time 1473.52 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 01:14:19 PM PDT 24
Peak memory 1959204 kb
Host smart-99bd8230-5d8c-4ad1-b7fc-590566125d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900127146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.900127146
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1440929653
Short name T699
Test name
Test status
Simulation time 801366028 ps
CPU time 13.61 seconds
Started May 16 12:49:29 PM PDT 24
Finished May 16 12:50:00 PM PDT 24
Peak memory 221260 kb
Host smart-892d91bc-3bfa-4306-8ed3-16110516624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440929653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1440929653
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3454794737
Short name T723
Test name
Test status
Simulation time 2218885514 ps
CPU time 3.02 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:49:49 PM PDT 24
Peak memory 205028 kb
Host smart-484c92ca-e0ad-4813-801b-071b0c0c8aa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454794737 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3454794737
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2269933817
Short name T1269
Test name
Test status
Simulation time 10314986796 ps
CPU time 34.33 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:50:15 PM PDT 24
Peak memory 322208 kb
Host smart-d33f80d0-165b-4a52-83ac-bd8be49d268a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269933817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2269933817
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2561474805
Short name T987
Test name
Test status
Simulation time 10133057147 ps
CPU time 27.87 seconds
Started May 16 12:49:23 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 322672 kb
Host smart-5ae2f237-5dac-4fe0-9897-b52c8f586951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561474805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2561474805
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.871704638
Short name T829
Test name
Test status
Simulation time 321623319 ps
CPU time 2.23 seconds
Started May 16 12:49:27 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 204924 kb
Host smart-5f8be543-0695-4091-92fc-273dab782e67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871704638 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.871704638
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.233868338
Short name T486
Test name
Test status
Simulation time 692306099 ps
CPU time 3.78 seconds
Started May 16 12:49:26 PM PDT 24
Finished May 16 12:49:48 PM PDT 24
Peak memory 204876 kb
Host smart-28c9f090-efe2-4411-a134-da148cf2d7ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233868338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.233868338
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4020062823
Short name T136
Test name
Test status
Simulation time 18056968039 ps
CPU time 251.39 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:53:57 PM PDT 24
Peak memory 2831260 kb
Host smart-eb0b4e60-7adc-40a6-bd77-a1f8fe77c2cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020062823 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4020062823
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.508662875
Short name T1054
Test name
Test status
Simulation time 2021294082 ps
CPU time 6.31 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 204948 kb
Host smart-9f956028-1192-40c5-9762-8f32aa7af7fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508662875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.508662875
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.3649898183
Short name T1148
Test name
Test status
Simulation time 93899709859 ps
CPU time 24.84 seconds
Started May 16 12:49:29 PM PDT 24
Finished May 16 12:50:11 PM PDT 24
Peak memory 221400 kb
Host smart-dab2794b-2c76-497a-821f-9dea977fd723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649898183 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.3649898183
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.4228510307
Short name T418
Test name
Test status
Simulation time 473756899 ps
CPU time 7.88 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:49:50 PM PDT 24
Peak memory 207932 kb
Host smart-7ce5a14d-d9ea-46b8-b5c8-43aec8d6c310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228510307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.4228510307
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.308260715
Short name T1222
Test name
Test status
Simulation time 47043374363 ps
CPU time 282.05 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:54:28 PM PDT 24
Peak memory 2788616 kb
Host smart-48df3033-fb5d-4512-b757-34c7f6adba02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308260715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.308260715
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3080278327
Short name T1262
Test name
Test status
Simulation time 18905005750 ps
CPU time 939.12 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 01:05:20 PM PDT 24
Peak memory 4447992 kb
Host smart-a9d41863-5e39-40a6-8263-6c864f355138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080278327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3080278327
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2813302484
Short name T727
Test name
Test status
Simulation time 1180470310 ps
CPU time 6.32 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 213184 kb
Host smart-701042c2-4430-401a-970a-8907ef8da24e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813302484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2813302484
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1705571719
Short name T943
Test name
Test status
Simulation time 14540820 ps
CPU time 0.58 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 204612 kb
Host smart-d870220c-29ac-46a4-81cd-8b83d0bf41fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705571719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1705571719
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2997896271
Short name T797
Test name
Test status
Simulation time 111950555 ps
CPU time 1.27 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:42 PM PDT 24
Peak memory 213260 kb
Host smart-f85473f4-16b9-413c-bcb9-b2bde8d4d39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997896271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2997896271
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2815632432
Short name T1247
Test name
Test status
Simulation time 578736836 ps
CPU time 4.25 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:49:57 PM PDT 24
Peak memory 252680 kb
Host smart-03c35905-10df-4d12-8607-65d415bef792
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815632432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2815632432
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2214043968
Short name T1342
Test name
Test status
Simulation time 2484563802 ps
CPU time 93.4 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:51:27 PM PDT 24
Peak memory 824688 kb
Host smart-af91a579-03ed-4b00-9e90-ff2d189c6270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214043968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2214043968
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2780647101
Short name T906
Test name
Test status
Simulation time 4873126847 ps
CPU time 73.96 seconds
Started May 16 12:49:27 PM PDT 24
Finished May 16 12:50:59 PM PDT 24
Peak memory 596352 kb
Host smart-65db88df-7bd6-4b1c-b908-1dc127b24bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780647101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2780647101
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.685907582
Short name T950
Test name
Test status
Simulation time 106535711 ps
CPU time 0.9 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 204668 kb
Host smart-39a75192-7b72-47f5-b287-6324c8267b81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685907582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fm
t.685907582
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1685798124
Short name T725
Test name
Test status
Simulation time 103796120 ps
CPU time 2.89 seconds
Started May 16 12:49:26 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 216576 kb
Host smart-5f5e2ec4-35ab-4b36-8125-da4a5f9169ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685798124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1685798124
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.4070913050
Short name T111
Test name
Test status
Simulation time 14285014399 ps
CPU time 86.78 seconds
Started May 16 12:49:25 PM PDT 24
Finished May 16 12:51:09 PM PDT 24
Peak memory 1135404 kb
Host smart-406a4bd8-a15b-4097-9e71-969ce646a768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070913050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.4070913050
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.1668217414
Short name T366
Test name
Test status
Simulation time 2568826157 ps
CPU time 37.9 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:50:30 PM PDT 24
Peak memory 366576 kb
Host smart-3dd5925e-13aa-4b3d-abd5-d745774768c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668217414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.1668217414
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3583725286
Short name T1043
Test name
Test status
Simulation time 45534979 ps
CPU time 0.62 seconds
Started May 16 12:49:24 PM PDT 24
Finished May 16 12:49:41 PM PDT 24
Peak memory 204604 kb
Host smart-e9d39d86-0e95-48c4-83ef-f7133c382968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583725286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3583725286
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1956253054
Short name T62
Test name
Test status
Simulation time 6714903994 ps
CPU time 562.95 seconds
Started May 16 12:49:29 PM PDT 24
Finished May 16 12:59:09 PM PDT 24
Peak memory 1524996 kb
Host smart-f1b1b66c-1b48-4971-b88b-ea0ac88a5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956253054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1956253054
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2051147817
Short name T651
Test name
Test status
Simulation time 1859662774 ps
CPU time 30.21 seconds
Started May 16 12:49:27 PM PDT 24
Finished May 16 12:50:15 PM PDT 24
Peak memory 290836 kb
Host smart-60107ffd-6d6b-47b9-9200-1bb238f2ef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051147817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2051147817
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3605833347
Short name T199
Test name
Test status
Simulation time 34981771515 ps
CPU time 617.2 seconds
Started May 16 12:49:26 PM PDT 24
Finished May 16 01:00:01 PM PDT 24
Peak memory 993808 kb
Host smart-5ccf65a2-695e-47ed-8e47-2df71b70124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605833347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3605833347
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1015459082
Short name T887
Test name
Test status
Simulation time 3583330059 ps
CPU time 7.63 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:50:01 PM PDT 24
Peak memory 214252 kb
Host smart-cb9188e1-0a29-4fc4-a1a4-9d49d75aa859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015459082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1015459082
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.606038953
Short name T311
Test name
Test status
Simulation time 708870219 ps
CPU time 3.76 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:49:55 PM PDT 24
Peak memory 204968 kb
Host smart-4c34026b-0834-49a9-a778-21405c79ea88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606038953 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.606038953
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2922558109
Short name T519
Test name
Test status
Simulation time 10151471211 ps
CPU time 38.91 seconds
Started May 16 12:49:32 PM PDT 24
Finished May 16 12:50:28 PM PDT 24
Peak memory 362288 kb
Host smart-6fe26c5a-ade6-4c9c-befc-36fa38f36eb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922558109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2922558109
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3077202350
Short name T711
Test name
Test status
Simulation time 10803716195 ps
CPU time 6.16 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:49:59 PM PDT 24
Peak memory 242160 kb
Host smart-73e3f6e9-391b-4e7a-9f19-ba23a6f84868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077202350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3077202350
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3153706851
Short name T1347
Test name
Test status
Simulation time 1679857507 ps
CPU time 2.45 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:49:53 PM PDT 24
Peak memory 204976 kb
Host smart-686496e6-91ed-415e-990f-9d028ef615a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153706851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3153706851
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.4212572747
Short name T670
Test name
Test status
Simulation time 6523149590 ps
CPU time 5.59 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:49:58 PM PDT 24
Peak memory 215396 kb
Host smart-2d02e8c1-732c-449f-9b82-f699563dc4e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212572747 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.4212572747
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.824400183
Short name T898
Test name
Test status
Simulation time 11268686187 ps
CPU time 62.09 seconds
Started May 16 12:49:39 PM PDT 24
Finished May 16 12:50:57 PM PDT 24
Peak memory 1347680 kb
Host smart-72980602-53b2-47f6-8317-0e6cbac07c17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824400183 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.824400183
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.4100573641
Short name T348
Test name
Test status
Simulation time 2628254822 ps
CPU time 9.92 seconds
Started May 16 12:49:28 PM PDT 24
Finished May 16 12:49:56 PM PDT 24
Peak memory 204944 kb
Host smart-57ca4d50-4f36-4fde-8b64-6211a4ba4eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100573641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.4100573641
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2205306768
Short name T660
Test name
Test status
Simulation time 3000321874 ps
CPU time 26.29 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:50:20 PM PDT 24
Peak memory 217984 kb
Host smart-98d5467c-09ba-4358-9861-3ce5a4300338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205306768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2205306768
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2751190945
Short name T701
Test name
Test status
Simulation time 35418525805 ps
CPU time 53.3 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:50:46 PM PDT 24
Peak memory 1031268 kb
Host smart-5f8a9134-634c-4783-ae22-1e287333ec82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751190945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2751190945
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2920664115
Short name T1308
Test name
Test status
Simulation time 14925382523 ps
CPU time 270.02 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:54:25 PM PDT 24
Peak memory 1833748 kb
Host smart-dd4e0d11-a207-4b3a-8392-64b7ce05043f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920664115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2920664115
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.346673498
Short name T1266
Test name
Test status
Simulation time 1579250904 ps
CPU time 8.06 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:50:02 PM PDT 24
Peak memory 213196 kb
Host smart-57efccd0-bc1e-4ec1-a1ee-ad5883e19c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346673498 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.346673498
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.843201276
Short name T669
Test name
Test status
Simulation time 26047952 ps
CPU time 0.61 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:49:56 PM PDT 24
Peak memory 204540 kb
Host smart-6256df12-9f44-42d1-be2d-c6167fc40841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843201276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.843201276
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2603192210
Short name T618
Test name
Test status
Simulation time 190843394 ps
CPU time 2.61 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 213312 kb
Host smart-8c046a19-1448-4adf-840a-43b90509eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603192210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2603192210
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.397435137
Short name T91
Test name
Test status
Simulation time 877006076 ps
CPU time 7.29 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:49:58 PM PDT 24
Peak memory 227988 kb
Host smart-c792479f-0b5e-4a3d-bffe-145961bf0d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397435137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.397435137
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.382524953
Short name T772
Test name
Test status
Simulation time 5891985857 ps
CPU time 187.99 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:53:00 PM PDT 24
Peak memory 761528 kb
Host smart-bd938cd1-f1c4-4f14-9d43-a4c991824df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382524953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.382524953
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.842965218
Short name T520
Test name
Test status
Simulation time 3201316144 ps
CPU time 112.92 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:51:45 PM PDT 24
Peak memory 601680 kb
Host smart-cfea8ae9-a7ce-4970-bb64-d0abbfd4c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842965218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.842965218
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.362566822
Short name T1111
Test name
Test status
Simulation time 198241547 ps
CPU time 0.91 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:49:52 PM PDT 24
Peak memory 204760 kb
Host smart-d76303b9-0e5a-4d0e-a319-189dd9936191
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362566822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.362566822
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3111444332
Short name T1132
Test name
Test status
Simulation time 1847848827 ps
CPU time 4.14 seconds
Started May 16 12:49:32 PM PDT 24
Finished May 16 12:49:53 PM PDT 24
Peak memory 204952 kb
Host smart-d1127053-73ca-44b1-9dd5-341ad76471b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111444332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3111444332
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1800984634
Short name T816
Test name
Test status
Simulation time 13386046196 ps
CPU time 87.25 seconds
Started May 16 12:49:34 PM PDT 24
Finished May 16 12:51:18 PM PDT 24
Peak memory 1075312 kb
Host smart-0cad5bc0-429c-45d2-ba23-5fe3381c692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800984634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1800984634
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3183125069
Short name T1158
Test name
Test status
Simulation time 1601656456 ps
CPU time 10.02 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:50:05 PM PDT 24
Peak memory 204508 kb
Host smart-a6b48a5d-102c-4889-9548-95c1b8b53c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183125069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3183125069
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.875351125
Short name T463
Test name
Test status
Simulation time 8110263248 ps
CPU time 104.58 seconds
Started May 16 12:49:41 PM PDT 24
Finished May 16 12:51:41 PM PDT 24
Peak memory 476092 kb
Host smart-76c8be27-6a4e-4121-9933-df039c1526ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875351125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.875351125
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1276485498
Short name T134
Test name
Test status
Simulation time 22105596 ps
CPU time 0.64 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:49:54 PM PDT 24
Peak memory 204440 kb
Host smart-5c8c42b7-7a81-4055-890e-4435a9e6c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276485498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1276485498
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1557058348
Short name T1077
Test name
Test status
Simulation time 499782998 ps
CPU time 7.14 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:49:58 PM PDT 24
Peak memory 270660 kb
Host smart-302cb840-16b5-4bdf-8cd6-6084a3b3a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557058348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1557058348
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3431829596
Short name T1108
Test name
Test status
Simulation time 3121136968 ps
CPU time 26.85 seconds
Started May 16 12:49:33 PM PDT 24
Finished May 16 12:50:16 PM PDT 24
Peak memory 364272 kb
Host smart-a92b1da1-e627-4d4f-acc2-d57b3f4298fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431829596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3431829596
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.462797767
Short name T81
Test name
Test status
Simulation time 26596074696 ps
CPU time 799.28 seconds
Started May 16 12:49:33 PM PDT 24
Finished May 16 01:03:09 PM PDT 24
Peak memory 1760676 kb
Host smart-06e3aef9-86d3-45a7-966a-52466d5eacfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462797767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.462797767
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3406950930
Short name T940
Test name
Test status
Simulation time 766853742 ps
CPU time 14.48 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:50:08 PM PDT 24
Peak memory 214844 kb
Host smart-d5ea4d1d-96d2-42eb-9975-ee9dadf30500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406950930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3406950930
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2698791245
Short name T944
Test name
Test status
Simulation time 3233737763 ps
CPU time 3.84 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:49:59 PM PDT 24
Peak memory 205044 kb
Host smart-8afedd01-f32d-4349-bf9d-188ea1f6882f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698791245 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2698791245
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1332377121
Short name T1228
Test name
Test status
Simulation time 10064855859 ps
CPU time 15.67 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:50:09 PM PDT 24
Peak memory 279968 kb
Host smart-7bcc20bc-a6ea-4f31-8990-422a3acf0b8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332377121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1332377121
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1114871137
Short name T896
Test name
Test status
Simulation time 1406999011 ps
CPU time 2.48 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:49:57 PM PDT 24
Peak memory 204956 kb
Host smart-502c4ff5-2a1c-40c9-85e4-825b6c2da19d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114871137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1114871137
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3958862022
Short name T531
Test name
Test status
Simulation time 5266694645 ps
CPU time 6.15 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:50:01 PM PDT 24
Peak memory 217016 kb
Host smart-866b9142-00fc-4a46-9a92-e519a37908b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958862022 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3958862022
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2755335176
Short name T1009
Test name
Test status
Simulation time 4682694222 ps
CPU time 3.66 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:49:57 PM PDT 24
Peak memory 204944 kb
Host smart-bab9459b-549f-4a5d-a43f-e61a447a938c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755335176 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2755335176
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2737324422
Short name T782
Test name
Test status
Simulation time 922815485 ps
CPU time 35.63 seconds
Started May 16 12:49:36 PM PDT 24
Finished May 16 12:50:28 PM PDT 24
Peak memory 204844 kb
Host smart-1b2d7216-2d7c-43ec-9738-1f42680a4f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737324422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2737324422
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.4245469010
Short name T355
Test name
Test status
Simulation time 1359795214 ps
CPU time 24.94 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:50:17 PM PDT 24
Peak memory 223876 kb
Host smart-fb912ad8-8eed-483e-a80c-df3ad6b239cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245469010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.4245469010
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3507461881
Short name T1288
Test name
Test status
Simulation time 31387429546 ps
CPU time 93.4 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:51:27 PM PDT 24
Peak memory 1562396 kb
Host smart-fc496b41-21d3-4172-9c3d-c1ffdc71b7b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507461881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3507461881
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.988081077
Short name T325
Test name
Test status
Simulation time 4059127589 ps
CPU time 27.26 seconds
Started May 16 12:49:33 PM PDT 24
Finished May 16 12:50:17 PM PDT 24
Peak memory 294644 kb
Host smart-9a35bc93-c2a7-429a-89d7-c98ed2278152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988081077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.988081077
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3687171416
Short name T571
Test name
Test status
Simulation time 1220516258 ps
CPU time 6.68 seconds
Started May 16 12:49:37 PM PDT 24
Finished May 16 12:50:00 PM PDT 24
Peak memory 204792 kb
Host smart-51c6dec8-4cb8-4e50-9ae3-948a77536dea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687171416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3687171416
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.555809255
Short name T868
Test name
Test status
Simulation time 43850761 ps
CPU time 0.64 seconds
Started May 16 12:49:45 PM PDT 24
Finished May 16 12:50:00 PM PDT 24
Peak memory 204696 kb
Host smart-4f4e0cc9-b859-42a1-a993-8ca96050bc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555809255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.555809255
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3788194756
Short name T813
Test name
Test status
Simulation time 435204947 ps
CPU time 1.78 seconds
Started May 16 12:49:48 PM PDT 24
Finished May 16 12:50:03 PM PDT 24
Peak memory 213284 kb
Host smart-1fda35b3-77f4-443e-93c8-b69bb54cdc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788194756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3788194756
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3472022296
Short name T180
Test name
Test status
Simulation time 480724914 ps
CPU time 5.59 seconds
Started May 16 12:49:43 PM PDT 24
Finished May 16 12:50:03 PM PDT 24
Peak memory 251800 kb
Host smart-48c39b19-f3a6-4a27-847c-9f807ae78528
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472022296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3472022296
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2064859890
Short name T997
Test name
Test status
Simulation time 3137271681 ps
CPU time 52.45 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 12:50:51 PM PDT 24
Peak memory 544020 kb
Host smart-1bbaaa19-49e8-4481-9495-a1eaa2f07ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064859890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2064859890
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1377405554
Short name T480
Test name
Test status
Simulation time 1411976315 ps
CPU time 94.56 seconds
Started May 16 12:49:45 PM PDT 24
Finished May 16 12:51:34 PM PDT 24
Peak memory 538220 kb
Host smart-74916f84-9039-466c-86a8-dac922262682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377405554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1377405554
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2003332137
Short name T60
Test name
Test status
Simulation time 69992614 ps
CPU time 0.84 seconds
Started May 16 12:49:54 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 204744 kb
Host smart-fd864db6-a7eb-4ef6-9af9-e09438c67fd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003332137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2003332137
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.443698132
Short name T226
Test name
Test status
Simulation time 172871181 ps
CPU time 9.85 seconds
Started May 16 12:49:43 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 234396 kb
Host smart-c3b1e832-1cc4-413d-970e-c0dd2fa5811c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443698132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
443698132
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.42553884
Short name T1121
Test name
Test status
Simulation time 12883466370 ps
CPU time 56.17 seconds
Started May 16 12:49:35 PM PDT 24
Finished May 16 12:50:48 PM PDT 24
Peak memory 814252 kb
Host smart-a129d34e-a92a-4931-9c3b-da48bc1acbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42553884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.42553884
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3477097814
Short name T1253
Test name
Test status
Simulation time 620566183 ps
CPU time 4.13 seconds
Started May 16 12:49:49 PM PDT 24
Finished May 16 12:50:07 PM PDT 24
Peak memory 204892 kb
Host smart-1c9c578f-3d12-43ef-ae49-45f1709873e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477097814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3477097814
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1743083351
Short name T1212
Test name
Test status
Simulation time 1783971019 ps
CPU time 28.24 seconds
Started May 16 12:49:46 PM PDT 24
Finished May 16 12:50:28 PM PDT 24
Peak memory 348032 kb
Host smart-17ed387a-1895-4715-b2dc-d7ce88327f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743083351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1743083351
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.711200187
Short name T130
Test name
Test status
Simulation time 29560942 ps
CPU time 0.63 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:49:56 PM PDT 24
Peak memory 204600 kb
Host smart-bfc85507-9b96-4b9d-9b45-e5fd2cce5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711200187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.711200187
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1651469697
Short name T814
Test name
Test status
Simulation time 938952215 ps
CPU time 14.24 seconds
Started May 16 12:49:47 PM PDT 24
Finished May 16 12:50:15 PM PDT 24
Peak memory 204852 kb
Host smart-dcde3620-bfa5-4fd1-a648-f8ef223ccad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651469697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1651469697
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1799471436
Short name T1063
Test name
Test status
Simulation time 1702510755 ps
CPU time 22.38 seconds
Started May 16 12:49:38 PM PDT 24
Finished May 16 12:50:17 PM PDT 24
Peak memory 287276 kb
Host smart-1d4f3625-520a-442e-9677-33211bf3356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799471436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1799471436
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.3563932019
Short name T149
Test name
Test status
Simulation time 13111545478 ps
CPU time 484.78 seconds
Started May 16 12:49:47 PM PDT 24
Finished May 16 12:58:06 PM PDT 24
Peak memory 890036 kb
Host smart-64fd3414-c1e1-4e21-ba7e-5f78660cb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563932019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.3563932019
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.1998384871
Short name T834
Test name
Test status
Simulation time 1371286592 ps
CPU time 10.84 seconds
Started May 16 12:49:48 PM PDT 24
Finished May 16 12:50:12 PM PDT 24
Peak memory 221352 kb
Host smart-3f14987d-b1cb-4c3c-adb5-26534075680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998384871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1998384871
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3442533577
Short name T1241
Test name
Test status
Simulation time 522133442 ps
CPU time 3.22 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 12:50:02 PM PDT 24
Peak memory 204952 kb
Host smart-9a19c3f4-d041-4cb8-859f-7a5c1fdeb5ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442533577 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3442533577
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1079984372
Short name T1218
Test name
Test status
Simulation time 10195467172 ps
CPU time 14.17 seconds
Started May 16 12:49:47 PM PDT 24
Finished May 16 12:50:15 PM PDT 24
Peak memory 265788 kb
Host smart-cbd4b28f-82aa-42d0-8e38-624ab4cf1cfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079984372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1079984372
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.4276248900
Short name T31
Test name
Test status
Simulation time 10109028770 ps
CPU time 61.44 seconds
Started May 16 12:49:49 PM PDT 24
Finished May 16 12:51:04 PM PDT 24
Peak memory 511716 kb
Host smart-182ef1aa-8e9a-4a33-af69-48cac2b96a8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276248900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.4276248900
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2867906502
Short name T1250
Test name
Test status
Simulation time 1074610410 ps
CPU time 1.85 seconds
Started May 16 12:49:48 PM PDT 24
Finished May 16 12:50:03 PM PDT 24
Peak memory 205080 kb
Host smart-560436fb-5230-48b6-953a-1c504dede0e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867906502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2867906502
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3896388224
Short name T273
Test name
Test status
Simulation time 2755635104 ps
CPU time 7.47 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 12:50:06 PM PDT 24
Peak memory 217032 kb
Host smart-2a807d08-11a7-42fe-92f7-1e4f9b851772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896388224 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3896388224
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1322786088
Short name T1341
Test name
Test status
Simulation time 12763677509 ps
CPU time 227.16 seconds
Started May 16 12:49:43 PM PDT 24
Finished May 16 12:53:45 PM PDT 24
Peak memory 3211856 kb
Host smart-11acffff-3025-4429-ab9e-ef5571d1e8d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322786088 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1322786088
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2182340097
Short name T955
Test name
Test status
Simulation time 1158193403 ps
CPU time 43.9 seconds
Started May 16 12:49:46 PM PDT 24
Finished May 16 12:50:44 PM PDT 24
Peak memory 204956 kb
Host smart-5633f5ad-8cee-4fb7-b5d2-b9294c03eefe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182340097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2182340097
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2665496765
Short name T625
Test name
Test status
Simulation time 613357391 ps
CPU time 9.04 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 12:50:08 PM PDT 24
Peak memory 208200 kb
Host smart-02f2d82b-f09b-4a8e-a029-2cd5db40f846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665496765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2665496765
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2011189538
Short name T370
Test name
Test status
Simulation time 30338216461 ps
CPU time 34.35 seconds
Started May 16 12:49:48 PM PDT 24
Finished May 16 12:50:36 PM PDT 24
Peak memory 719544 kb
Host smart-8e93846c-5a36-4340-bec4-70acd1f77ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011189538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2011189538
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.677179543
Short name T1315
Test name
Test status
Simulation time 13191042752 ps
CPU time 1613.14 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 01:16:53 PM PDT 24
Peak memory 3267516 kb
Host smart-fd7ed81e-cd20-428a-816b-64334804b206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677179543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.677179543
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.789910361
Short name T1141
Test name
Test status
Simulation time 1290034494 ps
CPU time 7.33 seconds
Started May 16 12:49:44 PM PDT 24
Finished May 16 12:50:06 PM PDT 24
Peak memory 213088 kb
Host smart-25a0adad-22aa-409e-ade5-88595fca49bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789910361 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.789910361
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3069133078
Short name T890
Test name
Test status
Simulation time 41547599 ps
CPU time 0.62 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:16 PM PDT 24
Peak memory 204596 kb
Host smart-574e8375-dbb0-442d-a743-a895d3607c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069133078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3069133078
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2568433003
Short name T38
Test name
Test status
Simulation time 667330280 ps
CPU time 4.78 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 229412 kb
Host smart-f76573c5-3eed-44cb-9d6d-8c9fc2e1acc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568433003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2568433003
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.600445069
Short name T709
Test name
Test status
Simulation time 682903682 ps
CPU time 3.04 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 234636 kb
Host smart-21c8873e-9a0f-4e38-97a0-96fb9d2e0acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600445069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.600445069
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2150137735
Short name T326
Test name
Test status
Simulation time 6936757126 ps
CPU time 164.29 seconds
Started May 16 12:44:48 PM PDT 24
Finished May 16 12:47:55 PM PDT 24
Peak memory 745612 kb
Host smart-1f53725e-2bee-4fa1-b7a3-7a3f22a386ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150137735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2150137735
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1163459928
Short name T1252
Test name
Test status
Simulation time 5791985854 ps
CPU time 110.12 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:46:56 PM PDT 24
Peak memory 574196 kb
Host smart-8ad6df76-2403-42a2-8cb9-cad7031119fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163459928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1163459928
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3366736558
Short name T449
Test name
Test status
Simulation time 345384342 ps
CPU time 0.85 seconds
Started May 16 12:44:48 PM PDT 24
Finished May 16 12:45:12 PM PDT 24
Peak memory 204752 kb
Host smart-a9dbe2e3-8798-47c9-af39-d60091dd65d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366736558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3366736558
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1236609007
Short name T657
Test name
Test status
Simulation time 494874997 ps
CPU time 7.26 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:11 PM PDT 24
Peak memory 224012 kb
Host smart-99c54e89-a224-4212-ac46-41b1135fa802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236609007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1236609007
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1100966211
Short name T641
Test name
Test status
Simulation time 2703951369 ps
CPU time 181.85 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:48:15 PM PDT 24
Peak memory 863864 kb
Host smart-c619a798-3575-449f-be49-d829e3d2396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100966211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1100966211
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2227353139
Short name T1312
Test name
Test status
Simulation time 257817117 ps
CPU time 4.32 seconds
Started May 16 12:44:48 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 204988 kb
Host smart-39d662be-71bf-40d2-8583-752703338a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227353139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2227353139
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2040960282
Short name T569
Test name
Test status
Simulation time 2901766484 ps
CPU time 36.84 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:51 PM PDT 24
Peak memory 398924 kb
Host smart-443bd738-050f-4da1-984c-6c12faa8421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040960282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2040960282
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1817518944
Short name T510
Test name
Test status
Simulation time 27186586 ps
CPU time 0.66 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:05 PM PDT 24
Peak memory 204680 kb
Host smart-c903172f-1041-4cd1-89d6-70d59891f79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817518944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1817518944
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3680246791
Short name T478
Test name
Test status
Simulation time 1184816588 ps
CPU time 48.7 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 255188 kb
Host smart-6a0631b3-e095-4c30-afcf-2b988d7ec804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680246791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3680246791
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3332578996
Short name T687
Test name
Test status
Simulation time 1263384502 ps
CPU time 59.53 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:46:08 PM PDT 24
Peak memory 302156 kb
Host smart-bc1bd6b7-1a33-4797-993a-34c7e12215d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332578996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3332578996
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.696146757
Short name T1279
Test name
Test status
Simulation time 621168329 ps
CPU time 27.96 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 213152 kb
Host smart-ef4c4e44-a8ce-4794-aeb4-b15dbb0b532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696146757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.696146757
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3811296499
Short name T426
Test name
Test status
Simulation time 1596115298 ps
CPU time 2.36 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:07 PM PDT 24
Peak memory 204880 kb
Host smart-fe317160-0c65-4f0b-a928-31eabb93bec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811296499 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3811296499
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3124456085
Short name T707
Test name
Test status
Simulation time 10179083946 ps
CPU time 66.47 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:46:21 PM PDT 24
Peak memory 503800 kb
Host smart-72eb1fd7-fc36-4243-9381-1bea3181271a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124456085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3124456085
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.322020724
Short name T690
Test name
Test status
Simulation time 10433485786 ps
CPU time 6.19 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:14 PM PDT 24
Peak memory 231936 kb
Host smart-e9032494-e013-4300-80ee-20ee34a4e473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322020724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.322020724
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2158891699
Short name T1083
Test name
Test status
Simulation time 1955520172 ps
CPU time 2.87 seconds
Started May 16 12:44:47 PM PDT 24
Finished May 16 12:45:12 PM PDT 24
Peak memory 205032 kb
Host smart-c9fe6483-8d8d-4438-97e9-a7dbe1e6bb9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158891699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2158891699
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.599194973
Short name T974
Test name
Test status
Simulation time 1675441716 ps
CPU time 4.39 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:19 PM PDT 24
Peak memory 205052 kb
Host smart-d885cdfd-0d83-4df9-8ef7-3683f6d66c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599194973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.599194973
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2915269588
Short name T847
Test name
Test status
Simulation time 3553924274 ps
CPU time 5.79 seconds
Started May 16 12:44:45 PM PDT 24
Finished May 16 12:45:13 PM PDT 24
Peak memory 205196 kb
Host smart-f524a0eb-eb2e-4880-936a-9f924a6e0ac0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915269588 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2915269588
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2547904605
Short name T406
Test name
Test status
Simulation time 2339731948 ps
CPU time 15.77 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:21 PM PDT 24
Peak memory 205024 kb
Host smart-22202386-b9f0-4ed1-8697-77693a425dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547904605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2547904605
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2146490296
Short name T1175
Test name
Test status
Simulation time 952604160 ps
CPU time 14.31 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:22 PM PDT 24
Peak memory 214764 kb
Host smart-f0f9ade7-7efb-4b40-853d-6a0cdaa953b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146490296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2146490296
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2358922874
Short name T245
Test name
Test status
Simulation time 42873012965 ps
CPU time 793.52 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:58:22 PM PDT 24
Peak memory 5983736 kb
Host smart-f489ae33-d32d-49a7-862c-81176fc10113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358922874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2358922874
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2074034090
Short name T243
Test name
Test status
Simulation time 8872178959 ps
CPU time 674.37 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:56:19 PM PDT 24
Peak memory 1839968 kb
Host smart-4dee6b5f-110c-4e54-9043-7bd9ff61af95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074034090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2074034090
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3534827111
Short name T1060
Test name
Test status
Simulation time 1153474728 ps
CPU time 6.87 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:12 PM PDT 24
Peak memory 213112 kb
Host smart-69e19c77-63d7-4453-8e4e-e2ceb1a853d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534827111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3534827111
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2711127295
Short name T634
Test name
Test status
Simulation time 17134308 ps
CPU time 0.6 seconds
Started May 16 12:44:52 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 204632 kb
Host smart-c812e09b-21cb-4b9f-a356-fec1f10df339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711127295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2711127295
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2158517824
Short name T345
Test name
Test status
Simulation time 537050501 ps
CPU time 1.9 seconds
Started May 16 12:44:44 PM PDT 24
Finished May 16 12:45:07 PM PDT 24
Peak memory 213252 kb
Host smart-4083ed55-987d-4cf3-b60c-05ac4191bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158517824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2158517824
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1725022346
Short name T1039
Test name
Test status
Simulation time 620824651 ps
CPU time 8.47 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 233928 kb
Host smart-c7e3e99c-a58f-4cda-91ef-e60050dc3789
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725022346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1725022346
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.260423200
Short name T966
Test name
Test status
Simulation time 1773432996 ps
CPU time 51.99 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:46:00 PM PDT 24
Peak memory 601936 kb
Host smart-65c8d261-fbf6-4c07-a29c-edd5779810fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260423200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.260423200
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3369405399
Short name T544
Test name
Test status
Simulation time 2558025895 ps
CPU time 204.42 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:48:33 PM PDT 24
Peak memory 800936 kb
Host smart-b352a42c-6651-490f-8252-bacd0bfee11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369405399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3369405399
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2184512106
Short name T1198
Test name
Test status
Simulation time 163206859 ps
CPU time 1.18 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:15 PM PDT 24
Peak memory 204948 kb
Host smart-ca4bc66e-6c03-4b28-8ae3-43c651f19d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184512106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2184512106
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2489053303
Short name T924
Test name
Test status
Simulation time 500480244 ps
CPU time 5.72 seconds
Started May 16 12:44:45 PM PDT 24
Finished May 16 12:45:11 PM PDT 24
Peak memory 251416 kb
Host smart-af67f879-1cfc-451c-a7e5-56f8f0d2e3a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489053303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2489053303
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.628196309
Short name T1067
Test name
Test status
Simulation time 2710769515 ps
CPU time 81.66 seconds
Started May 16 12:44:45 PM PDT 24
Finished May 16 12:46:28 PM PDT 24
Peak memory 876292 kb
Host smart-7613948f-f984-42a3-8566-4d71a2e5f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628196309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.628196309
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2914762277
Short name T514
Test name
Test status
Simulation time 633027417 ps
CPU time 4.09 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:19 PM PDT 24
Peak memory 204976 kb
Host smart-ce94bd65-ebdb-45e1-913a-5cb577103da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914762277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2914762277
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3393589947
Short name T66
Test name
Test status
Simulation time 8279605919 ps
CPU time 38.17 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 368096 kb
Host smart-8c983bab-6841-4521-bd00-0002e2f60135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393589947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3393589947
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1152682225
Short name T599
Test name
Test status
Simulation time 41672999 ps
CPU time 0.65 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:08 PM PDT 24
Peak memory 204548 kb
Host smart-f8c101dc-7fe6-414f-a594-4de125b62ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152682225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1152682225
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.966383771
Short name T225
Test name
Test status
Simulation time 3545833401 ps
CPU time 34.38 seconds
Started May 16 12:44:46 PM PDT 24
Finished May 16 12:45:42 PM PDT 24
Peak memory 465704 kb
Host smart-a91d7f23-87d1-4a85-a223-e61d39c3a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966383771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.966383771
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1749902392
Short name T1197
Test name
Test status
Simulation time 10686920827 ps
CPU time 104.79 seconds
Started May 16 12:44:51 PM PDT 24
Finished May 16 12:47:01 PM PDT 24
Peak memory 424084 kb
Host smart-fa89f5be-4ad5-442c-aef7-a942313a59c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749902392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1749902392
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3378515913
Short name T151
Test name
Test status
Simulation time 11293278185 ps
CPU time 1497.43 seconds
Started May 16 12:44:47 PM PDT 24
Finished May 16 01:10:08 PM PDT 24
Peak memory 2777560 kb
Host smart-addaab52-12fb-4826-a2be-db8f197c5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378515913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3378515913
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.4026175246
Short name T837
Test name
Test status
Simulation time 1011696128 ps
CPU time 15.02 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:29 PM PDT 24
Peak memory 220160 kb
Host smart-c281f799-033a-41ff-9b24-4c5e628402c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026175246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.4026175246
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4083355395
Short name T884
Test name
Test status
Simulation time 6007263298 ps
CPU time 3.51 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:45:22 PM PDT 24
Peak memory 205064 kb
Host smart-569e2c60-533a-4273-b8b3-3c169fca57af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083355395 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4083355395
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3924869
Short name T805
Test name
Test status
Simulation time 10153741972 ps
CPU time 71.95 seconds
Started May 16 12:44:48 PM PDT 24
Finished May 16 12:46:23 PM PDT 24
Peak memory 441236 kb
Host smart-c25e0e6c-880d-4ef0-984e-21e7e990d4d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924869 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_fifo_reset_acq.3924869
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.4184411730
Short name T622
Test name
Test status
Simulation time 10463690480 ps
CPU time 14.03 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:28 PM PDT 24
Peak memory 276352 kb
Host smart-74edcf1c-f53f-4fd5-8395-ab3cc6e0a652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184411730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.4184411730
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1057303677
Short name T1102
Test name
Test status
Simulation time 573506262 ps
CPU time 3.19 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:16 PM PDT 24
Peak memory 204864 kb
Host smart-bcac3778-468f-4771-a86e-614f03e31ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057303677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1057303677
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2376649790
Short name T1016
Test name
Test status
Simulation time 4348222920 ps
CPU time 5.82 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 213332 kb
Host smart-04b41235-f67e-4472-99e3-9141d2e86ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376649790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2376649790
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2104149963
Short name T1021
Test name
Test status
Simulation time 9778901874 ps
CPU time 129.95 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:47:25 PM PDT 24
Peak memory 2447768 kb
Host smart-ec3b0faa-5c64-4776-85e7-bd1be84fce05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104149963 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2104149963
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3430235543
Short name T167
Test name
Test status
Simulation time 890840042 ps
CPU time 15.5 seconds
Started May 16 12:44:45 PM PDT 24
Finished May 16 12:45:21 PM PDT 24
Peak memory 204992 kb
Host smart-7f8dc86f-e857-4de9-9fed-59000d1149d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430235543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3430235543
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4138246770
Short name T1024
Test name
Test status
Simulation time 4608492909 ps
CPU time 48.74 seconds
Started May 16 12:44:45 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 208024 kb
Host smart-3a06250f-7c3c-4b22-95bd-b414bc602ff3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138246770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4138246770
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3615391865
Short name T976
Test name
Test status
Simulation time 20740058747 ps
CPU time 11.27 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:26 PM PDT 24
Peak memory 205084 kb
Host smart-b0e661c2-ffdd-4531-92fa-1680c0599ee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615391865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3615391865
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.918754420
Short name T362
Test name
Test status
Simulation time 1316746859 ps
CPU time 7.25 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:45:25 PM PDT 24
Peak memory 218092 kb
Host smart-0a758860-5d97-4df5-90ff-bcb1900d4c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918754420 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.918754420
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1806409979
Short name T1281
Test name
Test status
Simulation time 22224126 ps
CPU time 0.62 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:21 PM PDT 24
Peak memory 204628 kb
Host smart-2791c10a-0879-4e50-adea-ba77d7f327ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806409979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1806409979
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2790680063
Short name T695
Test name
Test status
Simulation time 726800823 ps
CPU time 1.2 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:45:19 PM PDT 24
Peak memory 213244 kb
Host smart-11e6ceae-7bf0-47cd-b604-cdd3658ee693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790680063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2790680063
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.519875804
Short name T742
Test name
Test status
Simulation time 263302170 ps
CPU time 5.47 seconds
Started May 16 12:44:48 PM PDT 24
Finished May 16 12:45:17 PM PDT 24
Peak memory 249964 kb
Host smart-b37b7053-8628-4ebd-8aca-4328149fee4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519875804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.519875804
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2860835234
Short name T1101
Test name
Test status
Simulation time 13037219956 ps
CPU time 219.74 seconds
Started May 16 12:44:51 PM PDT 24
Finished May 16 12:48:56 PM PDT 24
Peak memory 886532 kb
Host smart-1332f609-11af-49ff-9b7a-7100b91781b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860835234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2860835234
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.869342666
Short name T971
Test name
Test status
Simulation time 9893477740 ps
CPU time 39.84 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:53 PM PDT 24
Peak memory 575624 kb
Host smart-8cdbf08a-5594-4128-b3fe-f50888477807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869342666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.869342666
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.4260160583
Short name T427
Test name
Test status
Simulation time 257577636 ps
CPU time 0.97 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:23 PM PDT 24
Peak memory 204864 kb
Host smart-3c307686-0568-44ac-a00f-934bec2a1e83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260160583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.4260160583
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3555638310
Short name T602
Test name
Test status
Simulation time 2741188571 ps
CPU time 75.83 seconds
Started May 16 12:44:54 PM PDT 24
Finished May 16 12:46:36 PM PDT 24
Peak memory 886148 kb
Host smart-8c84b6bf-b6f1-4137-b22a-020eb56f6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555638310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3555638310
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1310353623
Short name T1201
Test name
Test status
Simulation time 1378971679 ps
CPU time 16.07 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:45:39 PM PDT 24
Peak memory 204884 kb
Host smart-c424b068-f0fd-4a41-b4d3-0a93d5dff8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310353623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1310353623
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3156296366
Short name T949
Test name
Test status
Simulation time 1162467123 ps
CPU time 19.4 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:43 PM PDT 24
Peak memory 333516 kb
Host smart-40ce0b52-9458-482e-bac4-fda1271bbfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156296366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3156296366
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1515835621
Short name T716
Test name
Test status
Simulation time 31639628 ps
CPU time 0.68 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:45:19 PM PDT 24
Peak memory 204692 kb
Host smart-d6c4e63a-8d42-41f2-b7ef-954e7bbfba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515835621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1515835621
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2657289896
Short name T430
Test name
Test status
Simulation time 28183896705 ps
CPU time 69.12 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:46:28 PM PDT 24
Peak memory 205140 kb
Host smart-c63a4c6e-b029-41d5-abee-c786319c4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657289896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2657289896
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3888783581
Short name T264
Test name
Test status
Simulation time 3101597238 ps
CPU time 27.74 seconds
Started May 16 12:44:49 PM PDT 24
Finished May 16 12:45:41 PM PDT 24
Peak memory 328232 kb
Host smart-26e7b76e-de52-4b9c-a461-92700b688c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888783581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3888783581
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2187640999
Short name T1168
Test name
Test status
Simulation time 820818706 ps
CPU time 14.47 seconds
Started May 16 12:44:54 PM PDT 24
Finished May 16 12:45:35 PM PDT 24
Peak memory 229424 kb
Host smart-ab37f89a-7c2a-4748-be4f-c0765ace4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187640999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2187640999
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1864324100
Short name T953
Test name
Test status
Simulation time 4079274667 ps
CPU time 4.33 seconds
Started May 16 12:44:54 PM PDT 24
Finished May 16 12:45:24 PM PDT 24
Peak memory 205156 kb
Host smart-e09698d3-995d-425f-b48b-fbf0546e298e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864324100 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1864324100
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2044479879
Short name T1153
Test name
Test status
Simulation time 10169836606 ps
CPU time 13.73 seconds
Started May 16 12:44:53 PM PDT 24
Finished May 16 12:45:32 PM PDT 24
Peak memory 256172 kb
Host smart-470cbebe-f372-4a28-9568-d9aa0464e712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044479879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2044479879
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1353480243
Short name T1049
Test name
Test status
Simulation time 10152654263 ps
CPU time 10.67 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:32 PM PDT 24
Peak memory 257300 kb
Host smart-5b52bc2f-7267-46be-a574-e4ac4710120c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353480243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1353480243
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.418483767
Short name T1139
Test name
Test status
Simulation time 936511610 ps
CPU time 2.81 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:27 PM PDT 24
Peak memory 205060 kb
Host smart-4ba61380-3439-4102-a4fa-d7e23bdd28cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418483767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.418483767
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1938919742
Short name T274
Test name
Test status
Simulation time 525741668 ps
CPU time 3.08 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:45:18 PM PDT 24
Peak memory 204832 kb
Host smart-9cd9c7ed-7280-48bd-81b2-a622c196aa40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938919742 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1938919742
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2313111948
Short name T336
Test name
Test status
Simulation time 13437373952 ps
CPU time 112.09 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:47:07 PM PDT 24
Peak memory 1683048 kb
Host smart-3ced7da2-9cec-473b-a12e-ed1e97212877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313111948 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2313111948
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3625448851
Short name T666
Test name
Test status
Simulation time 3407640310 ps
CPU time 12.32 seconds
Started May 16 12:44:47 PM PDT 24
Finished May 16 12:45:21 PM PDT 24
Peak memory 205004 kb
Host smart-2cc0ee79-91ef-493f-896e-5ae4a5a6a3dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625448851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3625448851
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.839324742
Short name T749
Test name
Test status
Simulation time 3063094575 ps
CPU time 70.26 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:46:25 PM PDT 24
Peak memory 208052 kb
Host smart-4eb617ef-7a6b-46b5-ad9d-f56fb9b17468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839324742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.839324742
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.312948496
Short name T1117
Test name
Test status
Simulation time 16391978777 ps
CPU time 32.25 seconds
Started May 16 12:44:51 PM PDT 24
Finished May 16 12:45:48 PM PDT 24
Peak memory 205012 kb
Host smart-7780d06e-a32d-4366-be3a-7016eb3e1f15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312948496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.312948496
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2175410269
Short name T472
Test name
Test status
Simulation time 12564561119 ps
CPU time 561.16 seconds
Started May 16 12:44:50 PM PDT 24
Finished May 16 12:54:36 PM PDT 24
Peak memory 3132420 kb
Host smart-bc0c1856-c335-47ce-bfa1-c9f41b80e2ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175410269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2175410269
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1393971981
Short name T619
Test name
Test status
Simulation time 1191440003 ps
CPU time 7.19 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:31 PM PDT 24
Peak memory 221084 kb
Host smart-37e187a9-2f95-4b23-b0ee-a469d87dc9af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393971981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1393971981
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.218534370
Short name T1273
Test name
Test status
Simulation time 108390673 ps
CPU time 0.61 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:45:37 PM PDT 24
Peak memory 204640 kb
Host smart-212dca47-264c-4d8b-b911-f7d9dbb2d20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218534370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.218534370
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1310070489
Short name T461
Test name
Test status
Simulation time 1223917787 ps
CPU time 5 seconds
Started May 16 12:45:00 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 242040 kb
Host smart-6feaf917-0b43-496e-aa3e-944b6abe6043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310070489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1310070489
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1293517492
Short name T280
Test name
Test status
Simulation time 1391075935 ps
CPU time 19.61 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:45:51 PM PDT 24
Peak memory 282900 kb
Host smart-e085bcee-8788-4f28-94ea-46b522251abc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293517492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1293517492
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2385975883
Short name T584
Test name
Test status
Simulation time 3950027787 ps
CPU time 140.75 seconds
Started May 16 12:45:04 PM PDT 24
Finished May 16 12:47:53 PM PDT 24
Peak memory 685216 kb
Host smart-bdd841c8-0624-4d5a-8fda-d659aa3a9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385975883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2385975883
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.4093281143
Short name T364
Test name
Test status
Simulation time 7087104941 ps
CPU time 130.87 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:47:34 PM PDT 24
Peak memory 610984 kb
Host smart-53d5a08a-6163-4a0c-88a3-3da558d53f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093281143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4093281143
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3124579481
Short name T1076
Test name
Test status
Simulation time 201453120 ps
CPU time 1.07 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 204872 kb
Host smart-4e9bf5b6-dfe6-4c48-9410-4adf5ec63447
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124579481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3124579481
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3899167628
Short name T113
Test name
Test status
Simulation time 221035631 ps
CPU time 11.36 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:32 PM PDT 24
Peak memory 204936 kb
Host smart-2b30da28-abe9-4568-9b07-7d719a68d10b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899167628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3899167628
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.976993363
Short name T106
Test name
Test status
Simulation time 2957597386 ps
CPU time 69.06 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:46:35 PM PDT 24
Peak memory 932964 kb
Host smart-1b6e2509-c6f4-477c-9961-b12b093c448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976993363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.976993363
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2376529787
Short name T1187
Test name
Test status
Simulation time 269417502 ps
CPU time 10.76 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:36 PM PDT 24
Peak memory 205016 kb
Host smart-53dea005-f6d2-4a4c-b19b-951a715ea175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376529787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2376529787
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.4253287249
Short name T980
Test name
Test status
Simulation time 1484177533 ps
CPU time 71.88 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:46:35 PM PDT 24
Peak memory 330804 kb
Host smart-be25ffba-e9ce-41b0-8302-55aa4e94f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253287249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.4253287249
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.4074588994
Short name T1022
Test name
Test status
Simulation time 51501370 ps
CPU time 0.64 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:45:27 PM PDT 24
Peak memory 204668 kb
Host smart-2e9a1d3a-e8da-4df6-aa65-359d2f9a7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074588994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4074588994
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1167155444
Short name T439
Test name
Test status
Simulation time 1291964374 ps
CPU time 58.85 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:46:22 PM PDT 24
Peak memory 289716 kb
Host smart-332f4829-6b22-406d-9aea-f80cbcee31f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167155444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1167155444
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3240923365
Short name T1267
Test name
Test status
Simulation time 27712229094 ps
CPU time 258.04 seconds
Started May 16 12:45:01 PM PDT 24
Finished May 16 12:49:47 PM PDT 24
Peak memory 1014592 kb
Host smart-afe118d3-691d-4ffc-9adc-f785a884cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240923365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3240923365
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.4104467420
Short name T645
Test name
Test status
Simulation time 2509029651 ps
CPU time 28.61 seconds
Started May 16 12:45:01 PM PDT 24
Finished May 16 12:45:58 PM PDT 24
Peak memory 213164 kb
Host smart-f3337d2e-827d-4853-b5aa-d35934ad6890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104467420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.4104467420
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2506805732
Short name T1038
Test name
Test status
Simulation time 1018285825 ps
CPU time 4.36 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:28 PM PDT 24
Peak memory 213160 kb
Host smart-39bfbe14-f9d3-4fdf-9f76-c2f88336fb38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506805732 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2506805732
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2583952195
Short name T339
Test name
Test status
Simulation time 10102702934 ps
CPU time 24.16 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 313888 kb
Host smart-eca4bcfc-9c50-479b-850c-9cab574e745d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583952195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2583952195
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.721439528
Short name T479
Test name
Test status
Simulation time 10139926451 ps
CPU time 29.94 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:46:01 PM PDT 24
Peak memory 333100 kb
Host smart-0ef4530d-e388-400e-857e-7d27de4a54a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721439528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.721439528
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.143954696
Short name T809
Test name
Test status
Simulation time 967048289 ps
CPU time 2.83 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:27 PM PDT 24
Peak memory 204980 kb
Host smart-a702b430-7691-4f8a-9dd4-00dfdeab85a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143954696 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.143954696
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2691073893
Short name T415
Test name
Test status
Simulation time 1822704359 ps
CPU time 4.6 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:45:40 PM PDT 24
Peak memory 204968 kb
Host smart-6ccdfcd5-86a2-4804-a14a-f18290e527b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691073893 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2691073893
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1512645446
Short name T543
Test name
Test status
Simulation time 5751456276 ps
CPU time 21.55 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:46 PM PDT 24
Peak memory 791264 kb
Host smart-1cf2a9ce-c728-4589-ad82-b895cb8b4235
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512645446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1512645446
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1642091669
Short name T777
Test name
Test status
Simulation time 3298503452 ps
CPU time 23.48 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:47 PM PDT 24
Peak memory 204976 kb
Host smart-a919d8d7-1a20-4d35-8d11-669bf673f762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642091669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1642091669
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3027994468
Short name T508
Test name
Test status
Simulation time 1591611947 ps
CPU time 32.34 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:54 PM PDT 24
Peak memory 205004 kb
Host smart-a5954eeb-d086-4973-82b3-5cded0bb432f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027994468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3027994468
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1832067959
Short name T879
Test name
Test status
Simulation time 48664442828 ps
CPU time 377.25 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:51:53 PM PDT 24
Peak memory 3622024 kb
Host smart-77f14216-202b-41cf-a040-e207525e3495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832067959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1832067959
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3955139217
Short name T600
Test name
Test status
Simulation time 18261472087 ps
CPU time 318.86 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:50:43 PM PDT 24
Peak memory 2223508 kb
Host smart-364e6190-6eae-42b3-8712-d34e10dbf748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955139217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3955139217
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3868194892
Short name T70
Test name
Test status
Simulation time 6796668620 ps
CPU time 7.49 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:31 PM PDT 24
Peak memory 214056 kb
Host smart-3d43f1bb-ca38-4b22-866a-462d624a5092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868194892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3868194892
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1424913916
Short name T1233
Test name
Test status
Simulation time 184143214 ps
CPU time 0.59 seconds
Started May 16 12:45:01 PM PDT 24
Finished May 16 12:45:29 PM PDT 24
Peak memory 204560 kb
Host smart-45654249-e75b-4241-a8c5-5fa6a4a5c71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424913916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1424913916
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1817104356
Short name T956
Test name
Test status
Simulation time 475772046 ps
CPU time 1.93 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:45:25 PM PDT 24
Peak memory 213560 kb
Host smart-d2d49e69-13aa-43b9-ac77-153071656e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817104356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1817104356
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.94723729
Short name T488
Test name
Test status
Simulation time 1057638792 ps
CPU time 13.29 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:45:39 PM PDT 24
Peak memory 258276 kb
Host smart-8ba3d6cf-0905-46e8-88b1-ddd086fe2a11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94723729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.94723729
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3179386162
Short name T1334
Test name
Test status
Simulation time 17526526201 ps
CPU time 63.74 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:46:30 PM PDT 24
Peak memory 643296 kb
Host smart-e57dc486-b389-479f-bf1c-6bf64e0de1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179386162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3179386162
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3174575412
Short name T545
Test name
Test status
Simulation time 12750696587 ps
CPU time 76.26 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:46:53 PM PDT 24
Peak memory 702680 kb
Host smart-ce093c9a-39f1-4289-a227-905e16cb59a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174575412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3174575412
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2185243766
Short name T503
Test name
Test status
Simulation time 412187636 ps
CPU time 0.98 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:26 PM PDT 24
Peak memory 204724 kb
Host smart-265d2985-7ff0-40ff-a0e5-f309a28b037d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185243766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2185243766
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2887236644
Short name T624
Test name
Test status
Simulation time 674672690 ps
CPU time 9.38 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 234116 kb
Host smart-edc70f98-8ae8-4729-b026-302b38f81d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887236644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2887236644
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2555371706
Short name T638
Test name
Test status
Simulation time 4366924425 ps
CPU time 305.09 seconds
Started May 16 12:45:00 PM PDT 24
Finished May 16 12:50:32 PM PDT 24
Peak memory 1195348 kb
Host smart-30cb1a84-7392-4381-b9bc-874b5a47a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555371706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2555371706
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.581221655
Short name T1011
Test name
Test status
Simulation time 498155090 ps
CPU time 20.29 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:45:46 PM PDT 24
Peak memory 204836 kb
Host smart-f1145050-336e-4294-bf9e-33a826a9aa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581221655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.581221655
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.701927498
Short name T135
Test name
Test status
Simulation time 51601850 ps
CPU time 0.67 seconds
Started May 16 12:45:07 PM PDT 24
Finished May 16 12:45:37 PM PDT 24
Peak memory 204712 kb
Host smart-a611bd3c-2e11-43b2-94db-f0ffdca609a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701927498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.701927498
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3367736906
Short name T224
Test name
Test status
Simulation time 25546662707 ps
CPU time 260.53 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:49:52 PM PDT 24
Peak memory 205068 kb
Host smart-35423697-eb08-44b2-b378-59eb54f0e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367736906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3367736906
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2344276691
Short name T1109
Test name
Test status
Simulation time 1121444724 ps
CPU time 54.85 seconds
Started May 16 12:45:03 PM PDT 24
Finished May 16 12:46:26 PM PDT 24
Peak memory 333668 kb
Host smart-0e9cae0f-e944-44f1-85f3-5e0fa7664adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344276691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2344276691
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2567761542
Short name T252
Test name
Test status
Simulation time 15429100126 ps
CPU time 215.73 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:49:02 PM PDT 24
Peak memory 886396 kb
Host smart-e8508792-fd37-4c96-bbf0-f8ddb0a8facb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567761542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2567761542
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2168391652
Short name T681
Test name
Test status
Simulation time 1461481016 ps
CPU time 6.13 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:45:33 PM PDT 24
Peak memory 221120 kb
Host smart-c8530d6a-a6bc-42e7-9d56-30948f7192ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168391652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2168391652
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.3815822491
Short name T1084
Test name
Test status
Simulation time 719941891 ps
CPU time 3.62 seconds
Started May 16 12:44:59 PM PDT 24
Finished May 16 12:45:30 PM PDT 24
Peak memory 213104 kb
Host smart-12b3d110-a0ec-49a2-ace2-51ece538ef71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815822491 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3815822491
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3842479707
Short name T454
Test name
Test status
Simulation time 10071297278 ps
CPU time 27.56 seconds
Started May 16 12:45:01 PM PDT 24
Finished May 16 12:45:56 PM PDT 24
Peak memory 343356 kb
Host smart-32f4239c-af2c-4d4a-b7b1-de3800f9e18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842479707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3842479707
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.26992329
Short name T1059
Test name
Test status
Simulation time 10066202081 ps
CPU time 76.16 seconds
Started May 16 12:45:00 PM PDT 24
Finished May 16 12:46:43 PM PDT 24
Peak memory 501896 kb
Host smart-e484e3a9-03b6-4487-9d6c-30b517cfbaf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26992329 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_fifo_reset_tx.26992329
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1813045901
Short name T954
Test name
Test status
Simulation time 2236368662 ps
CPU time 3.13 seconds
Started May 16 12:44:58 PM PDT 24
Finished May 16 12:45:28 PM PDT 24
Peak memory 205068 kb
Host smart-075c5f6b-d257-4263-a73b-267c6b31f120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813045901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1813045901
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.961978966
Short name T891
Test name
Test status
Simulation time 1141915856 ps
CPU time 6.56 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:31 PM PDT 24
Peak memory 213040 kb
Host smart-fbed801b-d1df-449c-b9b1-a05372b38cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961978966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.961978966
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1035508704
Short name T374
Test name
Test status
Simulation time 26027094207 ps
CPU time 550.86 seconds
Started May 16 12:44:56 PM PDT 24
Finished May 16 12:54:34 PM PDT 24
Peak memory 6127664 kb
Host smart-26819eb2-e371-4ae8-a799-99e86f607ec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035508704 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1035508704
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3564026351
Short name T1236
Test name
Test status
Simulation time 2452817806 ps
CPU time 51.13 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:46:13 PM PDT 24
Peak memory 205100 kb
Host smart-2890f1ae-5c5e-4c73-963f-c8d14cf3daf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564026351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3564026351
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.4025480183
Short name T899
Test name
Test status
Simulation time 40426934854 ps
CPU time 26.54 seconds
Started May 16 12:45:00 PM PDT 24
Finished May 16 12:45:55 PM PDT 24
Peak memory 216196 kb
Host smart-0b7a9f99-9de4-4fce-b184-778a73ec4951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025480183 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.4025480183
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1254337271
Short name T849
Test name
Test status
Simulation time 845078870 ps
CPU time 15.96 seconds
Started May 16 12:44:57 PM PDT 24
Finished May 16 12:45:40 PM PDT 24
Peak memory 214056 kb
Host smart-097e12c6-95fc-4023-bdc9-c87a314a95f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254337271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1254337271
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.4005121985
Short name T21
Test name
Test status
Simulation time 63858511476 ps
CPU time 2513.3 seconds
Started May 16 12:44:54 PM PDT 24
Finished May 16 01:27:14 PM PDT 24
Peak memory 10782708 kb
Host smart-de6a2446-7661-4fd1-9f1a-bd3aab868695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005121985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.4005121985
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1261969251
Short name T1227
Test name
Test status
Simulation time 36838294372 ps
CPU time 270.7 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:49:53 PM PDT 24
Peak memory 2015900 kb
Host smart-2618266f-96f5-446e-b71d-f26c16bb82d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261969251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1261969251
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1458106945
Short name T591
Test name
Test status
Simulation time 2689223328 ps
CPU time 7.3 seconds
Started May 16 12:44:55 PM PDT 24
Finished May 16 12:45:30 PM PDT 24
Peak memory 221272 kb
Host smart-436e87d3-e85c-4123-bfc5-5a319fd8f950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458106945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1458106945
Directory /workspace/9.i2c_target_timeout/latest
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