Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	9	51	85.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	9	51	85.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	906740	1			T1	3		T2	43		T3	3
all_values[1]	906740	1			T1	3		T2	43		T3	3
all_values[2]	906740	1			T1	3		T2	43		T3	3
all_values[3]	906740	1			T1	3		T2	43		T3	3
all_values[4]	906740	1			T1	3		T2	43		T3	3
all_values[5]	906740	1			T1	3		T2	43		T3	3
all_values[6]	906740	1			T1	3		T2	43		T3	3
all_values[7]	906740	1			T1	3		T2	43		T3	3
all_values[8]	906740	1			T1	3		T2	43		T3	3
all_values[9]	906740	1			T1	3		T2	43		T3	3
all_values[10]	906740	1			T1	3		T2	43		T3	3
all_values[11]	906740	1			T1	3		T2	43		T3	3
all_values[12]	906740	1			T1	3		T2	43		T3	3
all_values[13]	906740	1			T1	3		T2	43		T3	3
all_values[14]	906740	1			T1	3		T2	43		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11138986

1

T1

38

T2

561

T3

40

auto[1]

2462114

1

T1

7

T2

84

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11654811

1

T1

45

T2

645

T3

45

auto[1]

1946289

1

T37

121

T45

512570

T48

257

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	9	51	85.00	9

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83244	1			T2	2		T3	1		T4	2
all_values[0]	auto[0]	auto[1]	8731	1			T45	812		T48	8		T57	6
all_values[0]	auto[1]	auto[0]	689791	1			T1	3		T2	41		T3	2
all_values[0]	auto[1]	auto[1]	124974	1			T37	7		T45	33360		T48	11
all_values[1]	auto[0]	auto[0]	786678	1			T1	3		T2	43		T3	3
all_values[1]	auto[0]	auto[1]	119154	1			T37	6		T45	34164		T57	1800
all_values[1]	auto[1]	auto[0]	655	1			T49	16		T55	57		T35	3
all_values[1]	auto[1]	auto[1]	253	1			T37	3		T45	8		T57	6
all_values[2]	auto[0]	auto[0]	786714	1			T1	3		T2	43		T3	3
all_values[2]	auto[0]	auto[1]	119816	1			T37	6		T45	34168		T48	16
all_values[2]	auto[1]	auto[1]	210	1			T37	2		T45	4		T48	2
all_values[3]	auto[0]	auto[0]	771581	1			T1	3		T2	43		T3	3
all_values[3]	auto[0]	auto[1]	134913	1			T37	6		T45	34167		T48	17
all_values[3]	auto[1]	auto[1]	246	1			T37	3		T45	1		T48	2
all_values[4]	auto[0]	auto[0]	771837	1			T1	3		T2	43		T3	3
all_values[4]	auto[0]	auto[1]	134675	1			T37	5		T45	34169		T48	17
all_values[4]	auto[1]	auto[0]	13	1			T235	1		T47	2		T236	1
all_values[4]	auto[1]	auto[1]	215	1			T37	1		T45	3		T48	2
all_values[5]	auto[0]	auto[0]	787001	1			T1	3		T2	43		T3	3
all_values[5]	auto[0]	auto[1]	119509	1			T37	2		T45	34169		T48	15
all_values[5]	auto[1]	auto[1]	230	1			T37	2		T45	3		T48	2
all_values[6]	auto[0]	auto[0]	772485	1			T1	3		T2	43		T3	3
all_values[6]	auto[0]	auto[1]	134034	1			T37	6		T45	34167		T48	15
all_values[6]	auto[1]	auto[1]	221	1			T37	3		T45	5		T48	3
all_values[7]	auto[0]	auto[0]	744932	1			T1	3		T2	43		T3	3
all_values[7]	auto[0]	auto[1]	131138	1			T37	6		T45	33822		T48	15
all_values[7]	auto[1]	auto[0]	26978	1			T5	80		T54	1		T49	234
all_values[7]	auto[1]	auto[1]	3692	1			T37	1		T45	348		T48	3
all_values[8]	auto[0]	auto[0]	771555	1			T1	3		T2	43		T3	3
all_values[8]	auto[0]	auto[1]	134963	1			T37	3		T45	34165		T48	17
all_values[8]	auto[1]	auto[1]	222	1			T37	6		T45	5		T48	2
all_values[9]	auto[0]	auto[0]	174473	1			T1	2		T2	41		T3	2
all_values[9]	auto[0]	auto[1]	22253	1			T37	4		T45	2323		T48	16
all_values[9]	auto[1]	auto[0]	597369	1			T1	1		T2	2		T3	1
all_values[9]	auto[1]	auto[1]	112645	1			T37	5		T45	31849		T48	2
all_values[10]	auto[0]	auto[0]	772100	1			T1	3		T2	43		T3	3
all_values[10]	auto[0]	auto[1]	134414	1			T37	5		T45	34168		T48	16
all_values[10]	auto[1]	auto[1]	226	1			T37	4		T45	3		T48	3
all_values[11]	auto[0]	auto[0]	2735	1			T2	2		T3	1		T4	2
all_values[11]	auto[0]	auto[1]	566	1			T45	28		T48	8		T57	6
all_values[11]	auto[1]	auto[0]	768844	1			T1	3		T2	41		T3	2
all_values[11]	auto[1]	auto[1]	134595	1			T37	9		T45	34144		T48	11
all_values[12]	auto[0]	auto[0]	802664	1			T1	3		T2	43		T3	3
all_values[12]	auto[0]	auto[1]	103848	1			T37	5		T45	34169		T48	17
all_values[12]	auto[1]	auto[1]	228	1			T37	4		T45	2		T48	2
all_values[13]	auto[0]	auto[0]	771582	1			T1	3		T2	43		T3	3
all_values[13]	auto[0]	auto[1]	134910	1			T37	3		T45	34168		T48	17
all_values[13]	auto[1]	auto[1]	248	1			T37	5		T45	4		T48	1
all_values[14]	auto[0]	auto[0]	771580	1			T1	3		T2	43		T3	3
all_values[14]	auto[0]	auto[1]	134901	1			T37	6		T45	34168		T48	15
all_values[14]	auto[1]	auto[1]	259	1			T37	3		T45	4		T48	2