Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	906740	1			T1	3		T2	43		T3	3
all_pins[1]	906740	1			T1	3		T2	43		T3	3
all_pins[2]	906740	1			T1	3		T2	43		T3	3
all_pins[3]	906740	1			T1	3		T2	43		T3	3
all_pins[4]	906740	1			T1	3		T2	43		T3	3
all_pins[5]	906740	1			T1	3		T2	43		T3	3
all_pins[6]	906740	1			T1	3		T2	43		T3	3
all_pins[7]	906740	1			T1	3		T2	43		T3	3
all_pins[8]	906740	1			T1	3		T2	43		T3	3
all_pins[9]	906740	1			T1	3		T2	43		T3	3
all_pins[10]	906740	1			T1	3		T2	43		T3	3
all_pins[11]	906740	1			T1	3		T2	43		T3	3
all_pins[12]	906740	1			T1	3		T2	43		T3	3
all_pins[13]	906740	1			T1	3		T2	43		T3	3
all_pins[14]	906740	1			T1	3		T2	43		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11144216	1			T1	38		T2	643		T3	40
values[0x1]	2456884	1			T1	7		T2	2		T3	5
transitions[0x0=>0x1]	2455604	1			T1	7		T2	2		T3	5
transitions[0x1=>0x0]	2454582	1			T1	6		T2	2		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95241	1			T2	43		T3	1		T4	2
all_pins[0]	values[0x1]	811499	1			T1	3		T3	2		T5	332
all_pins[0]	transitions[0x0=>0x1]	810627	1			T1	3		T3	2		T5	332
all_pins[0]	transitions[0x1=>0x0]	74	1			T45	1		T57	2		T104	2
all_pins[1]	values[0x0]	905794	1			T1	3		T2	43		T3	3
all_pins[1]	values[0x1]	946	1			T49	22		T37	1		T55	72
all_pins[1]	transitions[0x0=>0x1]	912	1			T49	22		T37	1		T55	72
all_pins[1]	transitions[0x1=>0x0]	77	1			T37	1		T45	2		T48	1
all_pins[2]	values[0x0]	906629	1			T1	3		T2	43		T3	3
all_pins[2]	values[0x1]	111	1			T37	1		T45	2		T48	1
all_pins[2]	transitions[0x0=>0x1]	92	1			T37	1		T45	2		T234	2
all_pins[2]	transitions[0x1=>0x0]	103	1			T37	3		T48	1		T57	5
all_pins[3]	values[0x0]	906618	1			T1	3		T2	43		T3	3
all_pins[3]	values[0x1]	122	1			T37	3		T48	2		T57	5
all_pins[3]	transitions[0x0=>0x1]	93	1			T37	3		T48	2		T57	4
all_pins[3]	transitions[0x1=>0x0]	107	1			T37	1		T45	1		T235	1
all_pins[4]	values[0x0]	906604	1			T1	3		T2	43		T3	3
all_pins[4]	values[0x1]	136	1			T37	1		T45	1		T235	1
all_pins[4]	transitions[0x0=>0x1]	109	1			T37	1		T235	1		T57	1
all_pins[4]	transitions[0x1=>0x0]	88	1			T57	3		T234	1		T123	2
all_pins[5]	values[0x0]	906625	1			T1	3		T2	43		T3	3
all_pins[5]	values[0x1]	115	1			T45	1		T57	4		T234	2
all_pins[5]	transitions[0x0=>0x1]	93	1			T45	1		T234	1		T53	1
all_pins[5]	transitions[0x1=>0x0]	96	1			T45	4		T48	2		T57	2
all_pins[6]	values[0x0]	906622	1			T1	3		T2	43		T3	3
all_pins[6]	values[0x1]	118	1			T45	4		T48	2		T57	6
all_pins[6]	transitions[0x0=>0x1]	88	1			T45	3		T48	2		T57	4
all_pins[6]	transitions[0x1=>0x0]	33411	1			T5	85		T54	1		T49	292
all_pins[7]	values[0x0]	873299	1			T1	3		T2	43		T3	3
all_pins[7]	values[0x1]	33441	1			T5	85		T54	1		T49	292
all_pins[7]	transitions[0x0=>0x1]	33421	1			T5	85		T54	1		T49	292
all_pins[7]	transitions[0x1=>0x0]	78	1			T37	2		T45	3		T57	2
all_pins[8]	values[0x0]	906642	1			T1	3		T2	43		T3	3
all_pins[8]	values[0x1]	98	1			T37	2		T45	3		T48	1
all_pins[8]	transitions[0x0=>0x1]	68	1			T37	2		T45	1		T48	1
all_pins[8]	transitions[0x1=>0x0]	709902	1			T1	1		T2	2		T3	1
all_pins[9]	values[0x0]	196808	1			T1	2		T2	41		T3	2
all_pins[9]	values[0x1]	709932	1			T1	1		T2	2		T3	1
all_pins[9]	transitions[0x0=>0x1]	709904	1			T1	1		T2	2		T3	1
all_pins[9]	transitions[0x1=>0x0]	94	1			T45	1		T48	1		T57	2
all_pins[10]	values[0x0]	906618	1			T1	3		T2	43		T3	3
all_pins[10]	values[0x1]	122	1			T45	2		T48	1		T57	4
all_pins[10]	transitions[0x0=>0x1]	87	1			T45	2		T48	1		T57	1
all_pins[10]	transitions[0x1=>0x0]	899833	1			T1	3		T3	2		T5	332
all_pins[11]	values[0x0]	6872	1			T2	43		T3	1		T4	2
all_pins[11]	values[0x1]	899868	1			T1	3		T3	2		T5	332
all_pins[11]	transitions[0x0=>0x1]	899836	1			T1	3		T3	2		T5	332
all_pins[11]	transitions[0x1=>0x0]	80	1			T45	1		T104	1		T226	2
all_pins[12]	values[0x0]	906628	1			T1	3		T2	43		T3	3
all_pins[12]	values[0x1]	112	1			T45	1		T48	1		T57	2
all_pins[12]	transitions[0x0=>0x1]	83	1			T45	1		T234	2		T226	1
all_pins[12]	transitions[0x1=>0x0]	97	1			T37	2		T45	2		T57	2
all_pins[13]	values[0x0]	906614	1			T1	3		T2	43		T3	3
all_pins[13]	values[0x1]	126	1			T37	2		T45	2		T48	1
all_pins[13]	transitions[0x0=>0x1]	95	1			T37	2		T45	2		T48	1
all_pins[13]	transitions[0x1=>0x0]	107	1			T45	2		T48	2		T57	2
all_pins[14]	values[0x0]	906602	1			T1	3		T2	43		T3	3
all_pins[14]	values[0x1]	138	1			T45	2		T48	2		T57	5
all_pins[14]	transitions[0x0=>0x1]	96	1			T45	2		T48	2		T57	2
all_pins[14]	transitions[0x1=>0x0]	810435	1			T1	2		T3	1		T5	331