Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	510	1			T37	7		T45	7		T48	4
all_values[1]	510	1			T37	7		T45	7		T48	4
all_values[2]	510	1			T37	7		T45	7		T48	4
all_values[3]	510	1			T37	7		T45	7		T48	4
all_values[4]	510	1			T37	7		T45	7		T48	4
all_values[5]	510	1			T37	7		T45	7		T48	4
all_values[6]	510	1			T37	7		T45	7		T48	4
all_values[7]	510	1			T37	7		T45	7		T48	4
all_values[8]	510	1			T37	7		T45	7		T48	4
all_values[9]	510	1			T37	7		T45	7		T48	4
all_values[10]	510	1			T37	7		T45	7		T48	4
all_values[11]	510	1			T37	7		T45	7		T48	4
all_values[12]	510	1			T37	7		T45	7		T48	4
all_values[13]	510	1			T37	7		T45	7		T48	4
all_values[14]	510	1			T37	7		T45	7		T48	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3949

1

T37

64

T45

56

T48

37

auto[1]

3701

1

T37

41

T45

49

T48

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T37

14

T45

10

T48

13

auto[1]

6464

1

T37

91

T45

95

T48

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4448

1

T37

57

T45

58

T48

35

auto[1]

3202

1

T37

48

T45

47

T48

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T37	2		T123	2		T264	2
all_values[0]	auto[0]	auto[0]	auto[1]	106	1			T37	1		T45	2		T48	2
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T53	2		T123	1		T264	3
all_values[0]	auto[0]	auto[1]	auto[1]	108	1			T37	1		T45	2		T57	1
all_values[0]	auto[1]	auto[0]	auto[1]	116	1			T37	1		T45	2		T48	2
all_values[0]	auto[1]	auto[1]	auto[1]	103	1			T37	2		T45	1		T57	4
all_values[1]	auto[0]	auto[0]	auto[0]	55	1			T48	1		T234	2		T264	1
all_values[1]	auto[0]	auto[0]	auto[1]	99	1			T37	2		T45	3		T57	1
all_values[1]	auto[0]	auto[1]	auto[0]	50	1			T48	3		T234	2		T104	2
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T37	2		T45	1		T57	5
all_values[1]	auto[1]	auto[0]	auto[1]	112	1			T37	2		T45	3		T57	1
all_values[1]	auto[1]	auto[1]	auto[1]	92	1			T37	1		T57	4		T104	1
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T37	1		T57	1		T265	2
all_values[2]	auto[0]	auto[0]	auto[1]	106	1			T37	2		T57	1		T234	3
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T48	1		T57	1		T265	2
all_values[2]	auto[0]	auto[1]	auto[1]	134	1			T37	2		T45	3		T48	1
all_values[2]	auto[1]	auto[0]	auto[1]	113	1			T37	1		T45	1		T48	1
all_values[2]	auto[1]	auto[1]	auto[1]	97	1			T37	1		T45	3		T48	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T45	2		T266	1		T124	3
all_values[3]	auto[0]	auto[0]	auto[1]	101	1			T57	2		T234	2		T104	2
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T45	2		T53	1		T265	1
all_values[3]	auto[0]	auto[1]	auto[1]	117	1			T37	3		T45	2		T48	2
all_values[3]	auto[1]	auto[0]	auto[1]	112	1			T37	1		T45	1		T48	1
all_values[3]	auto[1]	auto[1]	auto[1]	108	1			T37	3		T48	1		T57	3
all_values[4]	auto[0]	auto[0]	auto[0]	48	1			T37	2		T264	1		T267	2
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T45	2		T48	1		T57	3
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T37	1		T234	1		T125	1
all_values[4]	auto[0]	auto[1]	auto[1]	115	1			T37	3		T45	2		T48	1
all_values[4]	auto[1]	auto[0]	auto[1]	102	1			T37	1		T45	2		T48	2
all_values[4]	auto[1]	auto[1]	auto[1]	113	1			T45	1		T57	3		T234	3
all_values[5]	auto[0]	auto[0]	auto[0]	52	1			T37	4		T48	2		T265	2
all_values[5]	auto[0]	auto[0]	auto[1]	115	1			T37	1		T45	1		T48	1
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T37	1		T265	2		T111	1
all_values[5]	auto[0]	auto[1]	auto[1]	109	1			T45	2		T57	2		T234	1
all_values[5]	auto[1]	auto[0]	auto[1]	110	1			T37	1		T45	4		T234	1
all_values[5]	auto[1]	auto[1]	auto[1]	86	1			T48	1		T57	5		T234	3
all_values[6]	auto[0]	auto[0]	auto[0]	54	1			T48	1		T226	1		T53	1
all_values[6]	auto[0]	auto[0]	auto[1]	98	1			T37	5		T45	1		T48	1
all_values[6]	auto[0]	auto[1]	auto[0]	36	1			T226	2		T53	1		T265	1
all_values[6]	auto[0]	auto[1]	auto[1]	115	1			T45	2		T48	1		T57	3
all_values[6]	auto[1]	auto[0]	auto[1]	105	1			T37	1		T45	1		T48	1
all_values[6]	auto[1]	auto[1]	auto[1]	102	1			T37	1		T45	3		T57	7
all_values[7]	auto[0]	auto[0]	auto[0]	33	1			T37	1		T45	1		T48	1
all_values[7]	auto[0]	auto[0]	auto[1]	114	1			T37	2		T45	2		T57	3
all_values[7]	auto[0]	auto[1]	auto[0]	29	1			T37	1		T45	1		T234	1
all_values[7]	auto[0]	auto[1]	auto[1]	117	1			T37	1		T45	2		T48	2
all_values[7]	auto[1]	auto[0]	auto[1]	117	1			T37	2		T48	1		T57	3
all_values[7]	auto[1]	auto[1]	auto[1]	100	1			T45	1		T57	3		T234	2
all_values[8]	auto[0]	auto[0]	auto[0]	37	1			T45	1		T57	1		T234	1
all_values[8]	auto[0]	auto[0]	auto[1]	104	1			T37	1		T45	1		T48	1
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T45	1		T57	1		T234	1
all_values[8]	auto[0]	auto[1]	auto[1]	129	1			T37	1		T45	1		T48	2
all_values[8]	auto[1]	auto[0]	auto[1]	115	1			T37	2		T45	1		T48	1
all_values[8]	auto[1]	auto[1]	auto[1]	96	1			T37	3		T45	2		T57	3
all_values[9]	auto[0]	auto[0]	auto[0]	45	1			T48	1		T234	1		T104	1
all_values[9]	auto[0]	auto[0]	auto[1]	104	1			T37	1		T45	2		T48	1
all_values[9]	auto[0]	auto[1]	auto[0]	33	1			T234	1		T53	1		T112	1
all_values[9]	auto[0]	auto[1]	auto[1]	113	1			T37	2		T45	1		T57	4
all_values[9]	auto[1]	auto[0]	auto[1]	119	1			T37	2		T45	3		T48	2
all_values[9]	auto[1]	auto[1]	auto[1]	96	1			T37	2		T45	1		T57	4
all_values[10]	auto[0]	auto[0]	auto[0]	50	1			T45	1		T226	2		T111	1
all_values[10]	auto[0]	auto[0]	auto[1]	96	1			T37	3		T45	1		T57	2
all_values[10]	auto[0]	auto[1]	auto[0]	21	1			T53	1		T111	1		T124	1
all_values[10]	auto[0]	auto[1]	auto[1]	117	1			T45	2		T48	1		T57	1
all_values[10]	auto[1]	auto[0]	auto[1]	101	1			T37	4		T45	1		T48	3
all_values[10]	auto[1]	auto[1]	auto[1]	125	1			T45	2		T57	6		T234	5
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T123	1		T264	1		T266	1
all_values[11]	auto[0]	auto[0]	auto[1]	114	1			T37	2		T45	3		T48	1
all_values[11]	auto[0]	auto[1]	auto[0]	43	1			T226	2		T53	3		T265	1
all_values[11]	auto[0]	auto[1]	auto[1]	102	1			T37	1		T57	3		T234	2
all_values[11]	auto[1]	auto[0]	auto[1]	110	1			T37	2		T45	4		T48	2
all_values[11]	auto[1]	auto[1]	auto[1]	96	1			T37	2		T48	1		T57	4
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T45	1		T57	2		T104	2
all_values[12]	auto[0]	auto[0]	auto[1]	104	1			T37	1		T48	1		T57	2
all_values[12]	auto[0]	auto[1]	auto[0]	24	1			T57	2		T53	1		T268	2
all_values[12]	auto[0]	auto[1]	auto[1]	110	1			T37	2		T45	4		T48	1
all_values[12]	auto[1]	auto[0]	auto[1]	131	1			T37	4		T45	1		T48	2
all_values[12]	auto[1]	auto[1]	auto[1]	97	1			T45	1		T57	2		T234	1
all_values[13]	auto[0]	auto[0]	auto[0]	54	1			T57	3		T123	2		T269	1
all_values[13]	auto[0]	auto[0]	auto[1]	104	1			T37	1		T45	1		T48	1
all_values[13]	auto[0]	auto[1]	auto[0]	36	1			T37	1		T48	1		T57	1
all_values[13]	auto[0]	auto[1]	auto[1]	106	1			T45	2		T57	4		T234	4
all_values[13]	auto[1]	auto[0]	auto[1]	112	1			T37	3		T45	2		T57	1
all_values[13]	auto[1]	auto[1]	auto[1]	98	1			T37	2		T45	2		T48	2
all_values[14]	auto[0]	auto[0]	auto[0]	52	1			T48	2		T104	1		T111	4
all_values[14]	auto[0]	auto[0]	auto[1]	92	1			T37	1		T45	2		T57	1
all_values[14]	auto[0]	auto[1]	auto[0]	35	1			T104	2		T53	1		T265	1
all_values[14]	auto[0]	auto[1]	auto[1]	113	1			T37	2		T45	1		T48	1
all_values[14]	auto[1]	auto[0]	auto[1]	123	1			T37	4		T45	3		T48	1
all_values[14]	auto[1]	auto[1]	auto[1]	95	1			T45	1		T57	3		T104	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal