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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.79 96.50 89.66 97.67 69.05 93.48 98.44 90.74


Total test records in report: 1459
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T1301 /workspace/coverage/default/43.i2c_host_override.1959937526 May 19 01:59:39 PM PDT 24 May 19 01:59:41 PM PDT 24 42565925 ps
T1302 /workspace/coverage/default/23.i2c_target_stress_rd.622499658 May 19 01:58:03 PM PDT 24 May 19 01:58:21 PM PDT 24 3529118576 ps
T1303 /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2755133698 May 19 01:57:53 PM PDT 24 May 19 01:59:00 PM PDT 24 10060826600 ps
T1304 /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3750694109 May 19 01:58:52 PM PDT 24 May 19 02:00:04 PM PDT 24 10044089290 ps
T1305 /workspace/coverage/default/3.i2c_target_smoke.2134770097 May 19 01:56:40 PM PDT 24 May 19 01:57:19 PM PDT 24 2994947376 ps
T1306 /workspace/coverage/default/29.i2c_host_fifo_watermark.1972679650 May 19 01:58:30 PM PDT 24 May 19 02:02:08 PM PDT 24 3213352645 ps
T1307 /workspace/coverage/default/16.i2c_target_intr_stress_wr.3768184460 May 19 01:57:38 PM PDT 24 May 19 01:59:18 PM PDT 24 7795607882 ps
T1308 /workspace/coverage/default/18.i2c_host_smoke.3561094064 May 19 01:57:40 PM PDT 24 May 19 01:58:16 PM PDT 24 16227893312 ps
T1309 /workspace/coverage/default/20.i2c_host_perf.3363236857 May 19 01:57:42 PM PDT 24 May 19 01:58:19 PM PDT 24 3094967586 ps
T1310 /workspace/coverage/default/44.i2c_host_stretch_timeout.2141396524 May 19 01:59:50 PM PDT 24 May 19 02:00:27 PM PDT 24 1488043136 ps
T1311 /workspace/coverage/default/43.i2c_host_stretch_timeout.2978566800 May 19 01:59:42 PM PDT 24 May 19 02:00:07 PM PDT 24 616519567 ps
T1312 /workspace/coverage/default/5.i2c_host_fifo_full.4245170879 May 19 01:56:41 PM PDT 24 May 19 01:57:51 PM PDT 24 3509426587 ps
T1313 /workspace/coverage/default/0.i2c_target_fifo_reset_acq.4196219759 May 19 01:56:19 PM PDT 24 May 19 01:56:26 PM PDT 24 10507665808 ps
T1314 /workspace/coverage/default/3.i2c_target_stress_rd.1797170216 May 19 01:56:51 PM PDT 24 May 19 01:57:04 PM PDT 24 401459867 ps
T1315 /workspace/coverage/default/43.i2c_target_intr_stress_wr.4177025980 May 19 01:59:55 PM PDT 24 May 19 02:00:04 PM PDT 24 4763561892 ps
T1316 /workspace/coverage/default/3.i2c_target_bad_addr.2764039055 May 19 01:56:39 PM PDT 24 May 19 01:56:48 PM PDT 24 735102385 ps
T1317 /workspace/coverage/default/43.i2c_target_timeout.2829497940 May 19 01:59:54 PM PDT 24 May 19 02:00:04 PM PDT 24 2363471458 ps
T1318 /workspace/coverage/default/31.i2c_target_timeout.4144325729 May 19 01:58:48 PM PDT 24 May 19 01:58:56 PM PDT 24 1243637117 ps
T128 /workspace/coverage/default/34.i2c_host_stress_all.2931683907 May 19 01:58:58 PM PDT 24 May 19 02:06:14 PM PDT 24 17820790774 ps
T1319 /workspace/coverage/default/36.i2c_host_stress_all.2222506894 May 19 01:59:08 PM PDT 24 May 19 02:27:08 PM PDT 24 46979797107 ps
T1320 /workspace/coverage/default/17.i2c_target_stress_rd.1794988808 May 19 01:57:40 PM PDT 24 May 19 01:57:47 PM PDT 24 231674574 ps
T1321 /workspace/coverage/default/11.i2c_host_fifo_overflow.2600374044 May 19 01:57:11 PM PDT 24 May 19 01:58:48 PM PDT 24 5427207214 ps
T1322 /workspace/coverage/default/16.i2c_host_fifo_overflow.214006403 May 19 01:57:37 PM PDT 24 May 19 01:59:01 PM PDT 24 35955057680 ps
T1323 /workspace/coverage/default/38.i2c_host_fifo_full.2998726674 May 19 01:59:21 PM PDT 24 May 19 02:00:26 PM PDT 24 8618510524 ps
T1324 /workspace/coverage/default/11.i2c_host_fifo_full.141413277 May 19 01:57:10 PM PDT 24 May 19 01:58:53 PM PDT 24 2980722189 ps
T1325 /workspace/coverage/default/26.i2c_target_smoke.1967082715 May 19 01:58:18 PM PDT 24 May 19 01:59:03 PM PDT 24 1317354312 ps
T1326 /workspace/coverage/default/30.i2c_host_fifo_watermark.1125290709 May 19 01:58:37 PM PDT 24 May 19 02:06:24 PM PDT 24 13552034498 ps
T1327 /workspace/coverage/default/15.i2c_host_fifo_full.1589934618 May 19 01:57:29 PM PDT 24 May 19 01:59:52 PM PDT 24 2268079238 ps
T1328 /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.586891630 May 19 01:57:31 PM PDT 24 May 19 01:57:37 PM PDT 24 314253981 ps
T1329 /workspace/coverage/default/10.i2c_host_stretch_timeout.1564592492 May 19 01:57:10 PM PDT 24 May 19 01:57:41 PM PDT 24 629549615 ps
T1330 /workspace/coverage/default/38.i2c_host_error_intr.1852953817 May 19 01:59:16 PM PDT 24 May 19 01:59:19 PM PDT 24 116037008 ps
T1331 /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2822394158 May 19 01:57:58 PM PDT 24 May 19 01:58:09 PM PDT 24 1157296882 ps
T1332 /workspace/coverage/default/40.i2c_host_fifo_watermark.1039403694 May 19 01:59:26 PM PDT 24 May 19 02:05:52 PM PDT 24 36510180605 ps
T1333 /workspace/coverage/default/27.i2c_host_fifo_watermark.2045666496 May 19 01:58:51 PM PDT 24 May 19 02:00:08 PM PDT 24 4522065057 ps
T1334 /workspace/coverage/default/49.i2c_host_fifo_reset_rx.439074555 May 19 02:00:17 PM PDT 24 May 19 02:00:29 PM PDT 24 748824382 ps
T1335 /workspace/coverage/default/1.i2c_host_fifo_watermark.2980055256 May 19 01:56:30 PM PDT 24 May 19 01:58:20 PM PDT 24 16121781851 ps
T1336 /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.717600169 May 19 01:59:47 PM PDT 24 May 19 01:59:50 PM PDT 24 108427694 ps
T1337 /workspace/coverage/default/10.i2c_host_fifo_overflow.3062548820 May 19 01:57:02 PM PDT 24 May 19 01:58:15 PM PDT 24 3981067488 ps
T1338 /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1761139787 May 19 01:58:10 PM PDT 24 May 19 01:58:41 PM PDT 24 10175023024 ps
T1339 /workspace/coverage/default/28.i2c_host_perf.1191322572 May 19 01:58:38 PM PDT 24 May 19 02:02:48 PM PDT 24 7047118272 ps
T1340 /workspace/coverage/default/48.i2c_host_fifo_watermark.753224199 May 19 02:00:12 PM PDT 24 May 19 02:02:55 PM PDT 24 11345201153 ps
T1341 /workspace/coverage/default/27.i2c_alert_test.2034049704 May 19 01:58:46 PM PDT 24 May 19 01:58:48 PM PDT 24 15241586 ps
T1342 /workspace/coverage/default/33.i2c_target_bad_addr.3234874183 May 19 01:59:07 PM PDT 24 May 19 01:59:15 PM PDT 24 818126911 ps
T1343 /workspace/coverage/default/29.i2c_target_smoke.2952795165 May 19 01:58:41 PM PDT 24 May 19 01:59:18 PM PDT 24 3986650373 ps
T1344 /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2050910267 May 19 01:56:35 PM PDT 24 May 19 01:56:42 PM PDT 24 3935489443 ps
T1345 /workspace/coverage/default/14.i2c_host_error_intr.704243647 May 19 01:57:28 PM PDT 24 May 19 01:57:31 PM PDT 24 114543202 ps
T1346 /workspace/coverage/default/11.i2c_host_fifo_watermark.3206935836 May 19 01:57:07 PM PDT 24 May 19 01:58:05 PM PDT 24 2877137926 ps
T1347 /workspace/coverage/default/17.i2c_target_intr_stress_wr.1343805830 May 19 01:57:38 PM PDT 24 May 19 02:02:55 PM PDT 24 16848820039 ps
T147 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2356857076 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 16241815 ps
T148 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1683249493 May 19 01:52:45 PM PDT 24 May 19 01:52:47 PM PDT 24 58264029 ps
T94 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3298184003 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 68300485 ps
T213 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1616398408 May 19 01:52:18 PM PDT 24 May 19 01:52:24 PM PDT 24 45608356 ps
T1348 /workspace/coverage/cover_reg_top/13.i2c_intr_test.723673551 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 14935953 ps
T175 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3420116278 May 19 01:52:00 PM PDT 24 May 19 01:52:04 PM PDT 24 78474057 ps
T176 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4108635456 May 19 01:52:12 PM PDT 24 May 19 01:52:20 PM PDT 24 277473699 ps
T1349 /workspace/coverage/cover_reg_top/36.i2c_intr_test.321629840 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 17930667 ps
T177 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.257744083 May 19 01:52:05 PM PDT 24 May 19 01:52:10 PM PDT 24 280085697 ps
T214 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2888266138 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 30441687 ps
T223 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1267025375 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 722724341 ps
T1350 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.516087333 May 19 01:52:10 PM PDT 24 May 19 01:52:21 PM PDT 24 1749201505 ps
T224 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1820369767 May 19 01:52:08 PM PDT 24 May 19 01:52:12 PM PDT 24 19508081 ps
T95 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.890751698 May 19 01:52:04 PM PDT 24 May 19 01:52:09 PM PDT 24 127379209 ps
T96 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4252766807 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 71035920 ps
T97 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3095852349 May 19 01:52:29 PM PDT 24 May 19 01:52:31 PM PDT 24 53939416 ps
T192 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4089629730 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 48522698 ps
T1351 /workspace/coverage/cover_reg_top/8.i2c_intr_test.962504122 May 19 01:52:15 PM PDT 24 May 19 01:52:21 PM PDT 24 16691584 ps
T1352 /workspace/coverage/cover_reg_top/25.i2c_intr_test.577739004 May 19 01:52:39 PM PDT 24 May 19 01:52:40 PM PDT 24 22758272 ps
T1353 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3920302242 May 19 01:52:11 PM PDT 24 May 19 01:52:20 PM PDT 24 144348318 ps
T98 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2042202678 May 19 01:52:34 PM PDT 24 May 19 01:52:35 PM PDT 24 128386832 ps
T195 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3787724887 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 20525603 ps
T99 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1994246926 May 19 01:52:15 PM PDT 24 May 19 01:52:23 PM PDT 24 147199305 ps
T196 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.49172025 May 19 01:52:18 PM PDT 24 May 19 01:52:25 PM PDT 24 48023896 ps
T1354 /workspace/coverage/cover_reg_top/6.i2c_intr_test.4100904638 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 28412565 ps
T197 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1318887480 May 19 01:52:22 PM PDT 24 May 19 01:52:29 PM PDT 24 273620171 ps
T225 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2404024013 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 50905947 ps
T215 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3860596057 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 135709960 ps
T1355 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.21188361 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 120276175 ps
T216 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3826713353 May 19 01:52:12 PM PDT 24 May 19 01:52:33 PM PDT 24 6862451908 ps
T1356 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4183471934 May 19 01:52:15 PM PDT 24 May 19 01:52:23 PM PDT 24 455944030 ps
T1357 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1037567629 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 43609028 ps
T100 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1894387221 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 106162261 ps
T1358 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.9677825 May 19 01:52:12 PM PDT 24 May 19 01:52:18 PM PDT 24 185171123 ps
T198 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1547233988 May 19 01:52:22 PM PDT 24 May 19 01:52:25 PM PDT 24 66634957 ps
T1359 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2105311338 May 19 01:51:59 PM PDT 24 May 19 01:52:02 PM PDT 24 127681552 ps
T217 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2725199818 May 19 01:52:03 PM PDT 24 May 19 01:52:07 PM PDT 24 199883567 ps
T207 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.389011725 May 19 01:52:06 PM PDT 24 May 19 01:52:11 PM PDT 24 71347992 ps
T212 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1370958593 May 19 01:52:15 PM PDT 24 May 19 01:52:25 PM PDT 24 25416652 ps
T193 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4242526253 May 19 01:52:14 PM PDT 24 May 19 01:52:23 PM PDT 24 488818835 ps
T194 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1326590532 May 19 01:52:14 PM PDT 24 May 19 01:52:23 PM PDT 24 406413639 ps
T1360 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3392796318 May 19 01:52:13 PM PDT 24 May 19 01:52:19 PM PDT 24 34553811 ps
T101 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1441318968 May 19 01:52:31 PM PDT 24 May 19 01:52:32 PM PDT 24 86673180 ps
T1361 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2539681584 May 19 01:52:25 PM PDT 24 May 19 01:52:26 PM PDT 24 44884368 ps
T204 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.797014285 May 19 01:52:10 PM PDT 24 May 19 01:52:16 PM PDT 24 192974726 ps
T1362 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3919582212 May 19 01:52:21 PM PDT 24 May 19 01:52:25 PM PDT 24 239593755 ps
T1363 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.442088315 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 58419974 ps
T1364 /workspace/coverage/cover_reg_top/30.i2c_intr_test.4031351681 May 19 01:52:32 PM PDT 24 May 19 01:52:33 PM PDT 24 38392349 ps
T1365 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3246672252 May 19 01:52:19 PM PDT 24 May 19 01:52:24 PM PDT 24 20226861 ps
T1366 /workspace/coverage/cover_reg_top/18.i2c_intr_test.259325799 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 39724875 ps
T1367 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4150231997 May 19 01:52:08 PM PDT 24 May 19 01:52:12 PM PDT 24 52180807 ps
T102 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2453480240 May 19 01:52:10 PM PDT 24 May 19 01:52:17 PM PDT 24 612444966 ps
T103 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1793283278 May 19 01:52:24 PM PDT 24 May 19 01:52:26 PM PDT 24 29825081 ps
T1368 /workspace/coverage/cover_reg_top/33.i2c_intr_test.179941028 May 19 01:52:39 PM PDT 24 May 19 01:52:40 PM PDT 24 27521544 ps
T218 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3376889763 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 125155010 ps
T121 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4012007287 May 19 01:52:26 PM PDT 24 May 19 01:52:29 PM PDT 24 157784845 ps
T222 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2947042298 May 19 01:52:34 PM PDT 24 May 19 01:52:36 PM PDT 24 21468813 ps
T1369 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2585667125 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 129063205 ps
T1370 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3500599413 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 114368462 ps
T199 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1669957161 May 19 01:52:08 PM PDT 24 May 19 01:52:13 PM PDT 24 102926077 ps
T1371 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1137469992 May 19 01:52:07 PM PDT 24 May 19 01:52:11 PM PDT 24 18947230 ps
T1372 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1979924258 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 57511385 ps
T1373 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3629886927 May 19 01:52:05 PM PDT 24 May 19 01:52:09 PM PDT 24 115302174 ps
T1374 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.725034174 May 19 01:52:14 PM PDT 24 May 19 01:52:23 PM PDT 24 227070804 ps
T1375 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1627575691 May 19 01:52:43 PM PDT 24 May 19 01:52:45 PM PDT 24 17699857 ps
T1376 /workspace/coverage/cover_reg_top/44.i2c_intr_test.353007306 May 19 01:52:12 PM PDT 24 May 19 01:52:18 PM PDT 24 58456143 ps
T1377 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.156799881 May 19 01:52:29 PM PDT 24 May 19 01:52:31 PM PDT 24 46241501 ps
T1378 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1544427492 May 19 01:52:35 PM PDT 24 May 19 01:52:37 PM PDT 24 26067517 ps
T1379 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1838310749 May 19 01:52:08 PM PDT 24 May 19 01:52:12 PM PDT 24 72690677 ps
T1380 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2560487398 May 19 01:52:02 PM PDT 24 May 19 01:52:06 PM PDT 24 117515735 ps
T1381 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2606506577 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 38661993 ps
T1382 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1334295931 May 19 01:52:24 PM PDT 24 May 19 01:52:26 PM PDT 24 59055557 ps
T200 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2818295309 May 19 01:52:14 PM PDT 24 May 19 01:52:22 PM PDT 24 73119895 ps
T1383 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1989425526 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 20662496 ps
T1384 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1740011120 May 19 01:52:09 PM PDT 24 May 19 01:52:14 PM PDT 24 1290781608 ps
T1385 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1541594219 May 19 01:52:30 PM PDT 24 May 19 01:52:31 PM PDT 24 26138143 ps
T1386 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2970266512 May 19 01:52:44 PM PDT 24 May 19 01:52:45 PM PDT 24 25730013 ps
T1387 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1962690456 May 19 01:52:10 PM PDT 24 May 19 01:52:16 PM PDT 24 538154634 ps
T1388 /workspace/coverage/cover_reg_top/41.i2c_intr_test.956087963 May 19 01:52:21 PM PDT 24 May 19 01:52:25 PM PDT 24 57648637 ps
T1389 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3671744429 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 46498032 ps
T122 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2676941656 May 19 01:52:14 PM PDT 24 May 19 01:52:21 PM PDT 24 43297655 ps
T1390 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2705929156 May 19 01:52:10 PM PDT 24 May 19 01:52:25 PM PDT 24 107612421 ps
T1391 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.607043760 May 19 01:52:18 PM PDT 24 May 19 01:52:24 PM PDT 24 37779348 ps
T1392 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3850634216 May 19 01:52:19 PM PDT 24 May 19 01:52:26 PM PDT 24 101879294 ps
T1393 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1941068279 May 19 01:52:14 PM PDT 24 May 19 01:52:24 PM PDT 24 16271856 ps
T201 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4002826457 May 19 01:52:11 PM PDT 24 May 19 01:52:18 PM PDT 24 166058598 ps
T219 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3426642605 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 25707312 ps
T1394 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2136039403 May 19 01:52:15 PM PDT 24 May 19 01:52:21 PM PDT 24 27370807 ps
T1395 /workspace/coverage/cover_reg_top/45.i2c_intr_test.3599002698 May 19 01:52:30 PM PDT 24 May 19 01:52:31 PM PDT 24 15580372 ps
T1396 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2541449061 May 19 01:52:20 PM PDT 24 May 19 01:52:25 PM PDT 24 136249105 ps
T220 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2353730769 May 19 01:52:02 PM PDT 24 May 19 01:52:06 PM PDT 24 83898883 ps
T1397 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3667066639 May 19 01:52:42 PM PDT 24 May 19 01:52:43 PM PDT 24 99056285 ps
T1398 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.589928347 May 19 01:52:17 PM PDT 24 May 19 01:52:24 PM PDT 24 48853307 ps
T1399 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1224947092 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 32206933 ps
T1400 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.234930453 May 19 01:52:29 PM PDT 24 May 19 01:52:30 PM PDT 24 195891523 ps
T1401 /workspace/coverage/cover_reg_top/2.i2c_intr_test.90554519 May 19 01:52:15 PM PDT 24 May 19 01:52:21 PM PDT 24 21424586 ps
T1402 /workspace/coverage/cover_reg_top/1.i2c_intr_test.2752331605 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 24479793 ps
T1403 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1371717147 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 51375768 ps
T1404 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3623954423 May 19 01:52:18 PM PDT 24 May 19 01:52:25 PM PDT 24 39271178 ps
T1405 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1968241326 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 31105963 ps
T1406 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3332512407 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 21111411 ps
T1407 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1477977607 May 19 01:52:10 PM PDT 24 May 19 01:52:15 PM PDT 24 15794882 ps
T1408 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1279569258 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 17974864 ps
T1409 /workspace/coverage/cover_reg_top/37.i2c_intr_test.809433682 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 31371051 ps
T1410 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.217210522 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 19154723 ps
T1411 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3663726096 May 19 01:52:13 PM PDT 24 May 19 01:52:22 PM PDT 24 326341449 ps
T1412 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2527674757 May 19 01:52:21 PM PDT 24 May 19 01:52:25 PM PDT 24 91057333 ps
T1413 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1379242585 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 21200947 ps
T1414 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3366244144 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 38892039 ps
T1415 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1115907396 May 19 01:52:09 PM PDT 24 May 19 01:52:14 PM PDT 24 84389306 ps
T1416 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4027459781 May 19 01:52:14 PM PDT 24 May 19 01:52:23 PM PDT 24 858138937 ps
T221 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3112232351 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 301240591 ps
T208 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1936162123 May 19 01:52:15 PM PDT 24 May 19 01:52:23 PM PDT 24 106153371 ps
T1417 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.134249368 May 19 01:52:12 PM PDT 24 May 19 01:52:18 PM PDT 24 87460714 ps
T1418 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1268970069 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 46476102 ps
T203 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.744340096 May 19 01:52:15 PM PDT 24 May 19 01:52:24 PM PDT 24 155691123 ps
T1419 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4204609537 May 19 01:52:22 PM PDT 24 May 19 01:52:25 PM PDT 24 28989963 ps
T1420 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2672007667 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 23623011 ps
T1421 /workspace/coverage/cover_reg_top/3.i2c_intr_test.4137858806 May 19 01:52:10 PM PDT 24 May 19 01:52:14 PM PDT 24 19285699 ps
T202 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.674185825 May 19 01:52:14 PM PDT 24 May 19 01:52:22 PM PDT 24 75839518 ps
T1422 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1826457947 May 19 01:52:11 PM PDT 24 May 19 01:52:24 PM PDT 24 67187641 ps
T1423 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1723549563 May 19 01:52:11 PM PDT 24 May 19 01:52:19 PM PDT 24 932926225 ps
T1424 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1355497046 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 131415964 ps
T1425 /workspace/coverage/cover_reg_top/27.i2c_intr_test.157218700 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 19412632 ps
T1426 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.171173249 May 19 01:52:12 PM PDT 24 May 19 01:52:19 PM PDT 24 143165105 ps
T1427 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1706736202 May 19 01:52:11 PM PDT 24 May 19 01:52:17 PM PDT 24 87574456 ps
T1428 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2024899115 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 26870605 ps
T1429 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2503951010 May 19 01:52:13 PM PDT 24 May 19 01:52:19 PM PDT 24 34790181 ps
T1430 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.10517003 May 19 01:52:32 PM PDT 24 May 19 01:52:34 PM PDT 24 55326003 ps
T1431 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3287616170 May 19 01:52:15 PM PDT 24 May 19 01:52:22 PM PDT 24 51420520 ps
T1432 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3256589861 May 19 01:52:36 PM PDT 24 May 19 01:52:38 PM PDT 24 58938336 ps
T1433 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2251059716 May 19 01:52:07 PM PDT 24 May 19 01:52:11 PM PDT 24 83778824 ps
T1434 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3773027477 May 19 01:52:13 PM PDT 24 May 19 01:52:22 PM PDT 24 138897780 ps
T1435 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.829364303 May 19 01:52:27 PM PDT 24 May 19 01:52:28 PM PDT 24 29748329 ps
T1436 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1910492106 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 59452273 ps
T1437 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.233396692 May 19 01:52:16 PM PDT 24 May 19 01:52:24 PM PDT 24 470093377 ps
T1438 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3786534257 May 19 01:52:29 PM PDT 24 May 19 01:52:30 PM PDT 24 17822809 ps
T1439 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2612292491 May 19 01:52:12 PM PDT 24 May 19 01:52:21 PM PDT 24 804872201 ps
T1440 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2305347523 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 74300023 ps
T209 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1219544713 May 19 01:52:15 PM PDT 24 May 19 01:52:23 PM PDT 24 303545799 ps
T1441 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2448256956 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 47367094 ps
T1442 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1985541124 May 19 01:52:39 PM PDT 24 May 19 01:52:42 PM PDT 24 936713205 ps
T205 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2870088345 May 19 01:52:30 PM PDT 24 May 19 01:52:32 PM PDT 24 107079095 ps
T1443 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2364326159 May 19 01:52:25 PM PDT 24 May 19 01:52:29 PM PDT 24 613242241 ps
T1444 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2269346512 May 19 01:52:13 PM PDT 24 May 19 01:52:21 PM PDT 24 776287357 ps
T1445 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1149675192 May 19 01:52:13 PM PDT 24 May 19 01:52:21 PM PDT 24 28136860 ps
T1446 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1510895792 May 19 01:52:18 PM PDT 24 May 19 01:52:26 PM PDT 24 82020144 ps
T1447 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2420999138 May 19 01:52:09 PM PDT 24 May 19 01:52:24 PM PDT 24 24694352 ps
T1448 /workspace/coverage/cover_reg_top/24.i2c_intr_test.59228593 May 19 01:52:16 PM PDT 24 May 19 01:52:23 PM PDT 24 23800673 ps
T1449 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3125496120 May 19 01:52:05 PM PDT 24 May 19 01:52:09 PM PDT 24 29754761 ps
T206 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1044517615 May 19 01:52:13 PM PDT 24 May 19 01:52:22 PM PDT 24 323150808 ps
T1450 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3570508150 May 19 01:52:13 PM PDT 24 May 19 01:52:21 PM PDT 24 42125019 ps
T1451 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.740029754 May 19 01:52:09 PM PDT 24 May 19 01:52:13 PM PDT 24 40485136 ps
T1452 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.299929304 May 19 01:52:23 PM PDT 24 May 19 01:52:25 PM PDT 24 67738696 ps
T1453 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3581005508 May 19 01:52:34 PM PDT 24 May 19 01:52:35 PM PDT 24 152958644 ps
T1454 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.310004218 May 19 01:52:17 PM PDT 24 May 19 01:52:25 PM PDT 24 88762419 ps
T1455 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1525105136 May 19 01:52:17 PM PDT 24 May 19 01:52:23 PM PDT 24 38752498 ps
T1456 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3472574688 May 19 01:52:02 PM PDT 24 May 19 01:52:06 PM PDT 24 18482853 ps
T1457 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3868488845 May 19 01:52:13 PM PDT 24 May 19 01:52:20 PM PDT 24 33942738 ps
T1458 /workspace/coverage/cover_reg_top/19.i2c_intr_test.809268896 May 19 01:52:15 PM PDT 24 May 19 01:52:21 PM PDT 24 44163373 ps
T1459 /workspace/coverage/cover_reg_top/0.i2c_intr_test.866952127 May 19 01:52:08 PM PDT 24 May 19 01:52:12 PM PDT 24 59992010 ps

Test location /workspace/coverage/default/44.i2c_host_may_nack.610967858
Short name T2
Test name
Test status
Simulation time 227775576 ps
CPU time 3.25 seconds
Started May 19 01:59:48 PM PDT 24
Finished May 19 01:59:53 PM PDT 24
Peak memory 204968 kb
Host smart-0e1ec54b-bd14-4616-a505-7034677587aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610967858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.610967858
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1921075285
Short name T8
Test name
Test status
Simulation time 3689980989 ps
CPU time 5.13 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 208168 kb
Host smart-e492a40a-dc42-4474-b665-9cb6b720961b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921075285 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1921075285
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.4211850903
Short name T37
Test name
Test status
Simulation time 28760083116 ps
CPU time 334.67 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 02:04:45 PM PDT 24
Peak memory 1526148 kb
Host smart-835b839f-61ed-4e19-93ac-b12d3dc4b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211850903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.4211850903
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1174302243
Short name T15
Test name
Test status
Simulation time 9126102379 ps
CPU time 11.56 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 213716 kb
Host smart-12016d2b-160e-48c8-9adc-e185c7bfb824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174302243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1174302243
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2042202678
Short name T98
Test name
Test status
Simulation time 128386832 ps
CPU time 0.97 seconds
Started May 19 01:52:34 PM PDT 24
Finished May 19 01:52:35 PM PDT 24
Peak memory 203744 kb
Host smart-a6a08f3f-a51f-469c-881b-93d0abf543ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042202678 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2042202678
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.515936277
Short name T57
Test name
Test status
Simulation time 26045459440 ps
CPU time 2419.99 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 02:39:50 PM PDT 24
Peak memory 2727204 kb
Host smart-f1cc13f6-da9a-4860-94e4-4fabab197bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515936277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.515936277
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3420116278
Short name T175
Test name
Test status
Simulation time 78474057 ps
CPU time 1.56 seconds
Started May 19 01:52:00 PM PDT 24
Finished May 19 01:52:04 PM PDT 24
Peak memory 203796 kb
Host smart-b4450c1c-ecdb-4fd4-b464-a499aeb75092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420116278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3420116278
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/21.i2c_host_override.3139143108
Short name T118
Test name
Test status
Simulation time 30862679 ps
CPU time 0.68 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 204704 kb
Host smart-dfe8320e-2fc5-42fa-9dcb-0178642503f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139143108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3139143108
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1837077153
Short name T28
Test name
Test status
Simulation time 48597081426 ps
CPU time 30.71 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:41 PM PDT 24
Peak memory 618084 kb
Host smart-c3ab442e-c18f-4d90-abe2-86f20bc9ccbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837077153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1837077153
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3093550186
Short name T74
Test name
Test status
Simulation time 10215949257 ps
CPU time 32.94 seconds
Started May 19 01:57:49 PM PDT 24
Finished May 19 01:58:23 PM PDT 24
Peak memory 310440 kb
Host smart-9d2fa8fa-30ed-4321-88be-6e00dde44666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093550186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3093550186
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.4116662858
Short name T53
Test name
Test status
Simulation time 15408663024 ps
CPU time 152.89 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 02:02:20 PM PDT 24
Peak memory 626248 kb
Host smart-584ab3c4-7a26-47e7-bf58-2b9c83faa2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116662858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4116662858
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_alert_test.459984562
Short name T393
Test name
Test status
Simulation time 52946552 ps
CPU time 0.63 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:57:36 PM PDT 24
Peak memory 204860 kb
Host smart-85b5df06-8fee-46cc-8980-074e10955884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459984562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.459984562
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3095852349
Short name T97
Test name
Test status
Simulation time 53939416 ps
CPU time 0.8 seconds
Started May 19 01:52:29 PM PDT 24
Finished May 19 01:52:31 PM PDT 24
Peak memory 203656 kb
Host smart-318674c4-2d2d-43ef-b57b-b7cc8e18a1e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095852349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3095852349
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1208429152
Short name T32
Test name
Test status
Simulation time 5517099778 ps
CPU time 7.86 seconds
Started May 19 01:59:03 PM PDT 24
Finished May 19 01:59:13 PM PDT 24
Peak memory 221328 kb
Host smart-3ffad4b0-c8b4-4549-a319-b3d32905712a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208429152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1208429152
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3537021913
Short name T56
Test name
Test status
Simulation time 714721850 ps
CPU time 1.08 seconds
Started May 19 01:58:44 PM PDT 24
Finished May 19 01:58:46 PM PDT 24
Peak memory 204996 kb
Host smart-e5105fa0-2527-4e66-abf9-4800bcc211dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537021913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3537021913
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.380013553
Short name T180
Test name
Test status
Simulation time 63097697 ps
CPU time 0.96 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 223152 kb
Host smart-8581469b-1b54-408a-bbd1-05d7dd4a4e9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380013553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.380013553
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3908807044
Short name T48
Test name
Test status
Simulation time 82272422004 ps
CPU time 227.52 seconds
Started May 19 01:57:51 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 1831472 kb
Host smart-651464f7-d8f6-43db-be9b-1997bf8ffbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908807044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3908807044
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2613888269
Short name T274
Test name
Test status
Simulation time 834890141 ps
CPU time 3.01 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:28 PM PDT 24
Peak memory 205128 kb
Host smart-bb3aad41-9a8c-4ed0-b060-ac994e73744e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613888269 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2613888269
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.582435587
Short name T47
Test name
Test status
Simulation time 409429534 ps
CPU time 17.44 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:59:03 PM PDT 24
Peak memory 204804 kb
Host smart-cdf08160-3595-431d-9e91-4e869490e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582435587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.582435587
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4089629730
Short name T192
Test name
Test status
Simulation time 48522698 ps
CPU time 2.25 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203812 kb
Host smart-bdc0eed4-936d-4b45-b14a-0f658efb3d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089629730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.4089629730
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.439661253
Short name T49
Test name
Test status
Simulation time 7170434276 ps
CPU time 39.7 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 01:58:38 PM PDT 24
Peak memory 213336 kb
Host smart-d0bfd0fc-b730-4e12-81b3-389945323dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439661253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.439661253
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.3013346110
Short name T111
Test name
Test status
Simulation time 70284972143 ps
CPU time 660.05 seconds
Started May 19 01:57:28 PM PDT 24
Finished May 19 02:08:30 PM PDT 24
Peak memory 2384108 kb
Host smart-8d69d46a-829a-4900-a5d2-8af4fc00ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013346110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.3013346110
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3597045118
Short name T79
Test name
Test status
Simulation time 14709650998 ps
CPU time 81.25 seconds
Started May 19 01:57:25 PM PDT 24
Finished May 19 01:58:46 PM PDT 24
Peak memory 791180 kb
Host smart-9440e2be-86b0-420c-abd4-45593ab491b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597045118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3597045118
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3652050693
Short name T63
Test name
Test status
Simulation time 6130904186 ps
CPU time 33.93 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:34 PM PDT 24
Peak memory 332504 kb
Host smart-ea435b26-b0e2-434f-9f5c-077028477599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652050693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3652050693
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.1373502621
Short name T81
Test name
Test status
Simulation time 10130465577 ps
CPU time 80.25 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:58:15 PM PDT 24
Peak memory 521956 kb
Host smart-5844009a-a96b-445f-91f8-a3c50a27e8dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373502621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.1373502621
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2527742235
Short name T485
Test name
Test status
Simulation time 146172744 ps
CPU time 4.23 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 229320 kb
Host smart-b8d9a61e-d6ab-4496-b6e3-9e36a4c1c3fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527742235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2527742235
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4002826457
Short name T201
Test name
Test status
Simulation time 166058598 ps
CPU time 2.35 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:18 PM PDT 24
Peak memory 203792 kb
Host smart-07cfc7a0-d6e1-43e8-b8aa-beb6b0d02eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002826457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4002826457
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_override.2818279811
Short name T131
Test name
Test status
Simulation time 24865661 ps
CPU time 0.68 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:32 PM PDT 24
Peak memory 204652 kb
Host smart-9ec17796-6127-4f6b-b652-f6c1e4643a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818279811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2818279811
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1816745884
Short name T266
Test name
Test status
Simulation time 16249091978 ps
CPU time 246.48 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 02:01:43 PM PDT 24
Peak memory 705432 kb
Host smart-cbb2abb7-de63-4fa4-9d17-81e6b209a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816745884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1816745884
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.717016459
Short name T894
Test name
Test status
Simulation time 139508035 ps
CPU time 1.21 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 204988 kb
Host smart-f61f6626-049f-4cf3-96a5-2837259a1a07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717016459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.717016459
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1109456238
Short name T233
Test name
Test status
Simulation time 152741349 ps
CPU time 1.15 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 204928 kb
Host smart-8f742a9e-470c-4591-8a9a-e5f555cb3d5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109456238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1109456238
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.864660693
Short name T127
Test name
Test status
Simulation time 211323488992 ps
CPU time 908.37 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 02:14:35 PM PDT 24
Peak memory 3362356 kb
Host smart-6264eaa0-e9d6-41cf-bd81-3f7ff36275e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864660693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.864660693
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2391622118
Short name T227
Test name
Test status
Simulation time 10479511965 ps
CPU time 15.94 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 01:59:49 PM PDT 24
Peak memory 269644 kb
Host smart-1ada72ec-0860-4a53-9bb0-5a819332a91f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391622118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2391622118
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2870088345
Short name T205
Test name
Test status
Simulation time 107079095 ps
CPU time 1.6 seconds
Started May 19 01:52:30 PM PDT 24
Finished May 19 01:52:32 PM PDT 24
Peak memory 203792 kb
Host smart-e7931966-286c-446d-b53a-73bf8c8916dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870088345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2870088345
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1669957161
Short name T199
Test name
Test status
Simulation time 102926077 ps
CPU time 1.45 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203808 kb
Host smart-36086771-a282-489d-b83f-0b62f1b28aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669957161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1669957161
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.360885586
Short name T41
Test name
Test status
Simulation time 299181147 ps
CPU time 11.38 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:56 PM PDT 24
Peak memory 213252 kb
Host smart-986b506c-2dd7-43a5-a1f0-bd9e0a781ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360885586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.360885586
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.918647463
Short name T36
Test name
Test status
Simulation time 2485422652 ps
CPU time 61 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 01:59:06 PM PDT 24
Peak memory 297128 kb
Host smart-f83485aa-4824-4b3c-b8db-305157a5ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918647463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.918647463
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.754955889
Short name T83
Test name
Test status
Simulation time 10079397947 ps
CPU time 75.05 seconds
Started May 19 02:00:08 PM PDT 24
Finished May 19 02:01:24 PM PDT 24
Peak memory 506456 kb
Host smart-38c95784-b1a5-400c-a062-aca474cabb83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754955889 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.754955889
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1985541124
Short name T1442
Test name
Test status
Simulation time 936713205 ps
CPU time 2.7 seconds
Started May 19 01:52:39 PM PDT 24
Finished May 19 01:52:42 PM PDT 24
Peak memory 203824 kb
Host smart-cfde2416-fe9a-4afc-b11e-eb45e824d2aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985541124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1985541124
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.563372247
Short name T1200
Test name
Test status
Simulation time 10068178830 ps
CPU time 74.76 seconds
Started May 19 01:56:32 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 549420 kb
Host smart-12695ea5-6b16-49fb-88b3-e6bfe72aa225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563372247 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.563372247
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.3395141968
Short name T126
Test name
Test status
Simulation time 46868879522 ps
CPU time 522.54 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 1232204 kb
Host smart-8ba58c07-9e04-4c10-aa18-3ebde41dca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395141968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.3395141968
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2891427086
Short name T458
Test name
Test status
Simulation time 10152165006 ps
CPU time 73.82 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:58:25 PM PDT 24
Peak memory 494800 kb
Host smart-daed58dd-2e88-49e5-90c7-b42f851b6ba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891427086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2891427086
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.378878331
Short name T700
Test name
Test status
Simulation time 2860630621 ps
CPU time 27.49 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:34 PM PDT 24
Peak memory 219984 kb
Host smart-0423760c-dba7-47b3-b40d-4f76d0ea6024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378878331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.378878331
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4116085823
Short name T1093
Test name
Test status
Simulation time 2514994376 ps
CPU time 90.31 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:58:47 PM PDT 24
Peak memory 374712 kb
Host smart-33035647-c869-4eb2-a17c-bf9b054b75d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116085823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4116085823
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.820643435
Short name T21
Test name
Test status
Simulation time 856477338 ps
CPU time 2.57 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 01:57:31 PM PDT 24
Peak memory 205088 kb
Host smart-541c8330-b0cd-4162-96cd-6a3ce00f4465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820643435 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.820643435
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3274267294
Short name T1163
Test name
Test status
Simulation time 3659586438 ps
CPU time 16.13 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 221500 kb
Host smart-dda77f38-2c86-470d-bc4f-218779e4f8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274267294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3274267294
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3963367754
Short name T257
Test name
Test status
Simulation time 3676056921 ps
CPU time 74.51 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:57:44 PM PDT 24
Peak memory 908828 kb
Host smart-f63845ff-213c-4f3c-a2d7-b81b9d57658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963367754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3963367754
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.379996803
Short name T242
Test name
Test status
Simulation time 1290476669 ps
CPU time 24.79 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 219236 kb
Host smart-c2b17163-8dfb-47bc-a6a2-eb6cd184d407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379996803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.379996803
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1044517615
Short name T206
Test name
Test status
Simulation time 323150808 ps
CPU time 2.2 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203828 kb
Host smart-bcf4822a-ba50-492c-9259-6f68acf2b349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044517615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1044517615
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2818295309
Short name T200
Test name
Test status
Simulation time 73119895 ps
CPU time 1.55 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203812 kb
Host smart-4f044c22-8e52-4cdd-8859-294d3492e32b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818295309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2818295309
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2879738009
Short name T61
Test name
Test status
Simulation time 4366649903 ps
CPU time 24.08 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 205104 kb
Host smart-a98a761b-8371-43bc-a0dd-d70ba9904e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879738009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2879738009
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3826713353
Short name T216
Test name
Test status
Simulation time 6862451908 ps
CPU time 14.81 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:33 PM PDT 24
Peak memory 203860 kb
Host smart-d177a8b1-7313-4ab2-a56b-8b064b101347
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826713353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3826713353
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.516087333
Short name T1350
Test name
Test status
Simulation time 1749201505 ps
CPU time 5.88 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203756 kb
Host smart-d53b6011-be3b-45d1-822e-d9ec7473a719
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516087333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.516087333
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2105311338
Short name T1359
Test name
Test status
Simulation time 127681552 ps
CPU time 0.69 seconds
Started May 19 01:51:59 PM PDT 24
Finished May 19 01:52:02 PM PDT 24
Peak memory 203828 kb
Host smart-2acdf1fc-c509-4fc5-ad3b-5f508d1ed7a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105311338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2105311338
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1706736202
Short name T1427
Test name
Test status
Simulation time 87574456 ps
CPU time 1.12 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203964 kb
Host smart-89f28901-9610-4524-a177-6679e89f3d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706736202 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1706736202
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3860596057
Short name T215
Test name
Test status
Simulation time 135709960 ps
CPU time 0.74 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203656 kb
Host smart-517a33ef-a73e-4e47-8ee5-f9cda848ab26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860596057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3860596057
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.866952127
Short name T1459
Test name
Test status
Simulation time 59992010 ps
CPU time 0.68 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 203580 kb
Host smart-6b874632-2339-423c-9ca1-8b8c30750aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866952127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.866952127
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2560487398
Short name T1380
Test name
Test status
Simulation time 117515735 ps
CPU time 0.87 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 203664 kb
Host smart-2be2c796-262b-45b8-b58a-c6978c2de15b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560487398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2560487398
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.389011725
Short name T207
Test name
Test status
Simulation time 71347992 ps
CPU time 1.7 seconds
Started May 19 01:52:06 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 203792 kb
Host smart-94401ed8-1686-4063-9d49-46eaeebccac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389011725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.389011725
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2725199818
Short name T217
Test name
Test status
Simulation time 199883567 ps
CPU time 1.4 seconds
Started May 19 01:52:03 PM PDT 24
Finished May 19 01:52:07 PM PDT 24
Peak memory 203704 kb
Host smart-d48130c9-5e6f-430f-ad47-1490ba7da096
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725199818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2725199818
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1510895792
Short name T1446
Test name
Test status
Simulation time 82020144 ps
CPU time 2.97 seconds
Started May 19 01:52:18 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 203796 kb
Host smart-b6510601-4675-4a97-97cc-c5821329fb74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510895792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1510895792
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2251059716
Short name T1433
Test name
Test status
Simulation time 83778824 ps
CPU time 0.79 seconds
Started May 19 01:52:07 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 203688 kb
Host smart-51db3f54-4669-4b79-8135-013476eb4143
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251059716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2251059716
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.171173249
Short name T1426
Test name
Test status
Simulation time 143165105 ps
CPU time 0.98 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203796 kb
Host smart-3d988394-0513-40a7-8a67-a37f309a00dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171173249 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.171173249
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1820369767
Short name T224
Test name
Test status
Simulation time 19508081 ps
CPU time 0.71 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 203544 kb
Host smart-49e6eaf6-8ab0-41a2-bb31-83539a00f828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820369767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1820369767
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2752331605
Short name T1402
Test name
Test status
Simulation time 24479793 ps
CPU time 0.65 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203636 kb
Host smart-e40c3904-3dee-40f8-ba57-94aad7a97bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752331605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2752331605
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.4183471934
Short name T1356
Test name
Test status
Simulation time 455944030 ps
CPU time 1.28 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203660 kb
Host smart-7eb71a8c-bb01-42bc-9fc7-afed6a97b22b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183471934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.4183471934
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1723549563
Short name T1423
Test name
Test status
Simulation time 932926225 ps
CPU time 2.66 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203428 kb
Host smart-6ce8fda9-36b0-4f38-993f-1c0bdae60c57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723549563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1723549563
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2705929156
Short name T1390
Test name
Test status
Simulation time 107612421 ps
CPU time 0.96 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203820 kb
Host smart-e87ba72a-c33f-42ce-b017-784b3f666840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705929156 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2705929156
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2888266138
Short name T214
Test name
Test status
Simulation time 30441687 ps
CPU time 0.78 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203600 kb
Host smart-cd074feb-a9c9-427e-911b-e4002357e1b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888266138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2888266138
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1334295931
Short name T1382
Test name
Test status
Simulation time 59055557 ps
CPU time 0.69 seconds
Started May 19 01:52:24 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 203644 kb
Host smart-c76b5247-79ea-450e-ba47-9f054f9a565f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334295931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1334295931
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3332512407
Short name T1406
Test name
Test status
Simulation time 21111411 ps
CPU time 0.84 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203252 kb
Host smart-52a26420-e99f-4de6-8346-08f3c36768b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332512407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3332512407
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1115907396
Short name T1415
Test name
Test status
Simulation time 84389306 ps
CPU time 1.47 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 203768 kb
Host smart-86aee4b3-00a0-4d66-9ab6-bf61fa731056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115907396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1115907396
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3787724887
Short name T195
Test name
Test status
Simulation time 20525603 ps
CPU time 0.92 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203732 kb
Host smart-d21e20d7-34ca-45f8-9522-6ef0cea709f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787724887 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3787724887
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1379242585
Short name T1413
Test name
Test status
Simulation time 21200947 ps
CPU time 0.69 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203692 kb
Host smart-e3d0676e-54d5-4dfa-a7c5-b9a3ddb7610b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379242585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1379242585
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3570508150
Short name T1450
Test name
Test status
Simulation time 42125019 ps
CPU time 0.68 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203668 kb
Host smart-ea5f48bc-19bb-4707-924d-b9cc493dec2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570508150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3570508150
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2541449061
Short name T1396
Test name
Test status
Simulation time 136249105 ps
CPU time 0.84 seconds
Started May 19 01:52:20 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203616 kb
Host smart-f8263efd-0e40-4cf5-b31a-e133cedd3ac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541449061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2541449061
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1838310749
Short name T1379
Test name
Test status
Simulation time 72690677 ps
CPU time 1.15 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 203800 kb
Host smart-85f845ed-1203-484c-a6f3-1173674bf022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838310749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1838310749
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1740011120
Short name T1384
Test name
Test status
Simulation time 1290781608 ps
CPU time 2.23 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 203876 kb
Host smart-f8ef1481-c74d-4fd9-b56c-ec582e9c3d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740011120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1740011120
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1371717147
Short name T1403
Test name
Test status
Simulation time 51375768 ps
CPU time 0.8 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203648 kb
Host smart-e6ca8df6-e9a5-4027-9dee-86a4efc6124f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371717147 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1371717147
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.9677825
Short name T1358
Test name
Test status
Simulation time 185171123 ps
CPU time 0.68 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:18 PM PDT 24
Peak memory 203636 kb
Host smart-21d2ce68-dace-4e3e-8a4e-f722b8df2a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9677825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.9677825
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2448256956
Short name T1441
Test name
Test status
Simulation time 47367094 ps
CPU time 0.62 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203648 kb
Host smart-d5a7476a-546d-4e60-8c9d-6e3c780d9bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448256956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2448256956
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2676941656
Short name T122
Test name
Test status
Simulation time 43297655 ps
CPU time 0.91 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203728 kb
Host smart-c55750e7-fdd3-4c10-b2f5-f235338d7f17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676941656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2676941656
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2364326159
Short name T1443
Test name
Test status
Simulation time 613242241 ps
CPU time 2.7 seconds
Started May 19 01:52:25 PM PDT 24
Finished May 19 01:52:29 PM PDT 24
Peak memory 203828 kb
Host smart-e26777d8-849b-4334-ab72-351b655963df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364326159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2364326159
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1547233988
Short name T198
Test name
Test status
Simulation time 66634957 ps
CPU time 0.8 seconds
Started May 19 01:52:22 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203784 kb
Host smart-51ca647d-9db9-488a-9246-410770330966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547233988 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1547233988
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.589928347
Short name T1398
Test name
Test status
Simulation time 48853307 ps
CPU time 0.75 seconds
Started May 19 01:52:17 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203920 kb
Host smart-dea0caf3-25d3-47ba-abdd-51859ea9df3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589928347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.589928347
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.723673551
Short name T1348
Test name
Test status
Simulation time 14935953 ps
CPU time 0.7 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203652 kb
Host smart-cbd0cb56-4b89-46e9-bd41-f9cd415f1d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723673551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.723673551
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1968241326
Short name T1405
Test name
Test status
Simulation time 31105963 ps
CPU time 1.14 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203788 kb
Host smart-91f6aa94-7b1a-4eaf-be5d-377c278238d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968241326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1968241326
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2612292491
Short name T1439
Test name
Test status
Simulation time 804872201 ps
CPU time 2.7 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203800 kb
Host smart-bc687bb4-e376-4210-b00b-2caba1691ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612292491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2612292491
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4108635456
Short name T176
Test name
Test status
Simulation time 277473699 ps
CPU time 2.21 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203788 kb
Host smart-13f05bda-13dd-4a8d-a002-64f5a9e6cf87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108635456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4108635456
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1370958593
Short name T212
Test name
Test status
Simulation time 25416652 ps
CPU time 1.09 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203672 kb
Host smart-c2189409-0d4a-4392-b33e-1f82871f26f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370958593 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1370958593
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2947042298
Short name T222
Test name
Test status
Simulation time 21468813 ps
CPU time 0.71 seconds
Started May 19 01:52:34 PM PDT 24
Finished May 19 01:52:36 PM PDT 24
Peak memory 203636 kb
Host smart-110cb3eb-d177-4f6d-8381-f786661dfdfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947042298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2947042298
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1941068279
Short name T1393
Test name
Test status
Simulation time 16271856 ps
CPU time 0.67 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203592 kb
Host smart-500cb276-402c-4e20-8bb1-4324847811ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941068279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1941068279
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3581005508
Short name T1453
Test name
Test status
Simulation time 152958644 ps
CPU time 0.91 seconds
Started May 19 01:52:34 PM PDT 24
Finished May 19 01:52:35 PM PDT 24
Peak memory 203700 kb
Host smart-1333f05e-6dab-47e9-ac6b-fcaf64a8e461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581005508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3581005508
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.442088315
Short name T1363
Test name
Test status
Simulation time 58419974 ps
CPU time 1.47 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 204004 kb
Host smart-44b8bc71-3adb-44c8-b344-d0fcff13778e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442088315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.442088315
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2136039403
Short name T1394
Test name
Test status
Simulation time 27370807 ps
CPU time 0.66 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203588 kb
Host smart-93b7441e-b538-47b8-81d5-a9bbed4395af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136039403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2136039403
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3773027477
Short name T1434
Test name
Test status
Simulation time 138897780 ps
CPU time 2.32 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203776 kb
Host smart-784805ee-29ac-40a8-8e4f-4671a5a737bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773027477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3773027477
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1326590532
Short name T194
Test name
Test status
Simulation time 406413639 ps
CPU time 2.29 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203740 kb
Host smart-f1ec19c8-037e-4986-9001-e7ae54c33747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326590532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1326590532
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.10517003
Short name T1430
Test name
Test status
Simulation time 55326003 ps
CPU time 1.14 seconds
Started May 19 01:52:32 PM PDT 24
Finished May 19 01:52:34 PM PDT 24
Peak memory 203888 kb
Host smart-3b54167f-afd8-496c-988d-9844f6db7a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517003 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.10517003
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1793283278
Short name T103
Test name
Test status
Simulation time 29825081 ps
CPU time 0.8 seconds
Started May 19 01:52:24 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 203880 kb
Host smart-dd7bd04c-242d-4267-9ca0-21c525274bff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793283278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1793283278
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1541594219
Short name T1385
Test name
Test status
Simulation time 26138143 ps
CPU time 0.65 seconds
Started May 19 01:52:30 PM PDT 24
Finished May 19 01:52:31 PM PDT 24
Peak memory 203680 kb
Host smart-d06d585b-8e31-477e-ba40-8f128c2d77ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541594219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1541594219
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1683249493
Short name T148
Test name
Test status
Simulation time 58264029 ps
CPU time 1.2 seconds
Started May 19 01:52:45 PM PDT 24
Finished May 19 01:52:47 PM PDT 24
Peak memory 203772 kb
Host smart-3dc22ff0-a6a0-432b-a15e-e0e1ffe42ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683249493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1683249493
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.156799881
Short name T1377
Test name
Test status
Simulation time 46241501 ps
CPU time 2.23 seconds
Started May 19 01:52:29 PM PDT 24
Finished May 19 01:52:31 PM PDT 24
Peak memory 203780 kb
Host smart-e3a2a99a-11b3-496d-a998-da27c3fc1dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156799881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.156799881
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1910492106
Short name T1436
Test name
Test status
Simulation time 59452273 ps
CPU time 0.93 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203992 kb
Host smart-896dce1c-79e5-4dc2-a9d4-52e4521638ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910492106 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1910492106
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2356857076
Short name T147
Test name
Test status
Simulation time 16241815 ps
CPU time 0.68 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203596 kb
Host smart-ccf8b78e-130c-4749-81b8-2d956409352d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356857076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2356857076
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1979924258
Short name T1372
Test name
Test status
Simulation time 57511385 ps
CPU time 0.66 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203664 kb
Host smart-5dd1c8c5-a10d-4a5d-aff6-00e895d984eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979924258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1979924258
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3868488845
Short name T1457
Test name
Test status
Simulation time 33942738 ps
CPU time 0.84 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203704 kb
Host smart-f2a41bef-152f-4d46-838f-681520419697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868488845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3868488845
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3623954423
Short name T1404
Test name
Test status
Simulation time 39271178 ps
CPU time 1.13 seconds
Started May 19 01:52:18 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203844 kb
Host smart-ecffb080-1740-447d-bab4-35294f251915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623954423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3623954423
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1936162123
Short name T208
Test name
Test status
Simulation time 106153371 ps
CPU time 1.47 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 204024 kb
Host smart-76006f2c-e215-4cad-bc36-95fde00e8f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936162123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1936162123
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3667066639
Short name T1397
Test name
Test status
Simulation time 99056285 ps
CPU time 0.78 seconds
Started May 19 01:52:42 PM PDT 24
Finished May 19 01:52:43 PM PDT 24
Peak memory 203820 kb
Host smart-b3ae7837-99e0-497c-81a5-a609a75ac629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667066639 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3667066639
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3112232351
Short name T221
Test name
Test status
Simulation time 301240591 ps
CPU time 0.75 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203924 kb
Host smart-5ab4dab4-67dc-4a56-9e24-3d61f2cb72f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112232351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3112232351
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.259325799
Short name T1366
Test name
Test status
Simulation time 39724875 ps
CPU time 0.62 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203612 kb
Host smart-802ee729-6280-418a-8d01-89998bdd9a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259325799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.259325799
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4252766807
Short name T96
Test name
Test status
Simulation time 71035920 ps
CPU time 1.22 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203816 kb
Host smart-547a5faa-3dc5-47e9-808f-8f88990749dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252766807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.4252766807
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3256589861
Short name T1432
Test name
Test status
Simulation time 58938336 ps
CPU time 1.56 seconds
Started May 19 01:52:36 PM PDT 24
Finished May 19 01:52:38 PM PDT 24
Peak memory 203780 kb
Host smart-d58aea78-9f7d-4bcf-88d3-79db85f05f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256589861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3256589861
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.234930453
Short name T1400
Test name
Test status
Simulation time 195891523 ps
CPU time 0.95 seconds
Started May 19 01:52:29 PM PDT 24
Finished May 19 01:52:30 PM PDT 24
Peak memory 203676 kb
Host smart-d3a1f757-45a0-4521-858a-a5a2ebf2c6dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234930453 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.234930453
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3376889763
Short name T218
Test name
Test status
Simulation time 125155010 ps
CPU time 0.65 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203576 kb
Host smart-2c4e9f45-080b-4972-9d39-443b39f1de99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376889763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3376889763
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.809268896
Short name T1458
Test name
Test status
Simulation time 44163373 ps
CPU time 0.68 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203636 kb
Host smart-ef6fdb0b-9b1f-4e48-97f2-254d51033e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809268896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.809268896
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2585667125
Short name T1369
Test name
Test status
Simulation time 129063205 ps
CPU time 0.86 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203672 kb
Host smart-bdcee49a-ef8c-4f1c-b74e-a1d3da678d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585667125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2585667125
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3663726096
Short name T1411
Test name
Test status
Simulation time 326341449 ps
CPU time 2.4 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203808 kb
Host smart-4fe0e315-f138-4ca7-9705-1bf39b7711fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663726096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3663726096
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.674185825
Short name T202
Test name
Test status
Simulation time 75839518 ps
CPU time 1.46 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203796 kb
Host smart-489955f6-bcf2-4628-8f03-48b1b48ad87e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674185825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.674185825
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.233396692
Short name T1437
Test name
Test status
Simulation time 470093377 ps
CPU time 2.18 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203820 kb
Host smart-24e9cd94-50df-4c47-80ec-81913c322348
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233396692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.233396692
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.725034174
Short name T1374
Test name
Test status
Simulation time 227070804 ps
CPU time 3.29 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203824 kb
Host smart-f0b34ec7-d365-44ce-9046-281d45e3a5f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725034174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.725034174
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4204609537
Short name T1419
Test name
Test status
Simulation time 28989963 ps
CPU time 0.68 seconds
Started May 19 01:52:22 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203588 kb
Host smart-8a481aab-03eb-4199-abe4-2a18e5572353
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204609537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4204609537
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.607043760
Short name T1391
Test name
Test status
Simulation time 37779348 ps
CPU time 1 seconds
Started May 19 01:52:18 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203800 kb
Host smart-b39a49bc-ccee-4ac1-a5c5-f30fa87a7b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607043760 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.607043760
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2353730769
Short name T220
Test name
Test status
Simulation time 83898883 ps
CPU time 0.79 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 203736 kb
Host smart-09d18836-aa53-4c2c-b35b-faffcc295357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353730769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2353730769
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.90554519
Short name T1401
Test name
Test status
Simulation time 21424586 ps
CPU time 0.63 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203640 kb
Host smart-10d7c252-2660-4813-9d64-555a0e344565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90554519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.90554519
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.21188361
Short name T1355
Test name
Test status
Simulation time 120276175 ps
CPU time 0.86 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203616 kb
Host smart-46c99a3c-eab8-4c2d-b00a-c4f6a8575ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21188361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outs
tanding.21188361
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1318887480
Short name T197
Test name
Test status
Simulation time 273620171 ps
CPU time 1.89 seconds
Started May 19 01:52:22 PM PDT 24
Finished May 19 01:52:29 PM PDT 24
Peak memory 203812 kb
Host smart-642222e0-ac90-4b66-a498-a8fbc920b437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318887480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1318887480
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1219544713
Short name T209
Test name
Test status
Simulation time 303545799 ps
CPU time 1.47 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203820 kb
Host smart-c0068f8b-61a7-4f4c-88f1-3e300829df38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219544713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1219544713
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1224947092
Short name T1399
Test name
Test status
Simulation time 32206933 ps
CPU time 0.7 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203620 kb
Host smart-4b6782cd-9b9c-45ae-901c-90c493a43795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224947092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1224947092
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2606506577
Short name T1381
Test name
Test status
Simulation time 38661993 ps
CPU time 0.65 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203660 kb
Host smart-f53c1eb7-8f58-42e3-aed6-b285fbad55da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606506577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2606506577
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3287616170
Short name T1431
Test name
Test status
Simulation time 51420520 ps
CPU time 0.71 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203628 kb
Host smart-a45ad74a-fe6d-4345-b7d0-aba0ffaf95c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287616170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3287616170
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1544427492
Short name T1378
Test name
Test status
Simulation time 26067517 ps
CPU time 0.66 seconds
Started May 19 01:52:35 PM PDT 24
Finished May 19 01:52:37 PM PDT 24
Peak memory 203656 kb
Host smart-a8f622a4-e1e5-46ac-8a75-bcb62a096ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544427492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1544427492
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.59228593
Short name T1448
Test name
Test status
Simulation time 23800673 ps
CPU time 0.66 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203636 kb
Host smart-9dae9c04-8be9-4c03-bb86-f6611078f9fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59228593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.59228593
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.577739004
Short name T1352
Test name
Test status
Simulation time 22758272 ps
CPU time 0.63 seconds
Started May 19 01:52:39 PM PDT 24
Finished May 19 01:52:40 PM PDT 24
Peak memory 203656 kb
Host smart-cdd754ab-303d-4696-b74f-35b671ce9e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577739004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.577739004
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2539681584
Short name T1361
Test name
Test status
Simulation time 44884368 ps
CPU time 0.64 seconds
Started May 19 01:52:25 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 203672 kb
Host smart-255813a6-5cbd-44fa-a9b7-7c53b94eefd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539681584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2539681584
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.157218700
Short name T1425
Test name
Test status
Simulation time 19412632 ps
CPU time 0.7 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203640 kb
Host smart-b8a85b3e-e6b6-45fd-8851-1a7ba7690d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157218700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.157218700
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3671744429
Short name T1389
Test name
Test status
Simulation time 46498032 ps
CPU time 0.67 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203588 kb
Host smart-4e6bb6be-4544-40d7-a3b9-e8dc65cab5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671744429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3671744429
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2305347523
Short name T1440
Test name
Test status
Simulation time 74300023 ps
CPU time 0.67 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203624 kb
Host smart-60bb3fe2-d1e2-4348-bb97-0ca85962a4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305347523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2305347523
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1826457947
Short name T1422
Test name
Test status
Simulation time 67187641 ps
CPU time 1.37 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203772 kb
Host smart-520e9a5e-a824-4e21-b881-91e4a0709461
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826457947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1826457947
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3920302242
Short name T1353
Test name
Test status
Simulation time 144348318 ps
CPU time 3.07 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203744 kb
Host smart-b66863dd-6d4e-4b1c-bc79-b732ae4c16b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920302242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3920302242
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3426642605
Short name T219
Test name
Test status
Simulation time 25707312 ps
CPU time 0.76 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203736 kb
Host smart-bf50b723-ce8a-487b-b405-1bc104ee441d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426642605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3426642605
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2420999138
Short name T1447
Test name
Test status
Simulation time 24694352 ps
CPU time 0.96 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203816 kb
Host smart-271ac028-2fbf-48da-958d-b0f3a19b287f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420999138 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2420999138
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1616398408
Short name T213
Test name
Test status
Simulation time 45608356 ps
CPU time 0.77 seconds
Started May 19 01:52:18 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203736 kb
Host smart-1f19ad48-1587-42c6-b662-8d789c9e7130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616398408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1616398408
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.4137858806
Short name T1421
Test name
Test status
Simulation time 19285699 ps
CPU time 0.69 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:14 PM PDT 24
Peak memory 203624 kb
Host smart-ad7c807a-2500-4ac7-ba68-6c19f7d0267e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137858806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4137858806
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3500599413
Short name T1370
Test name
Test status
Simulation time 114368462 ps
CPU time 0.84 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203672 kb
Host smart-9fea6d1f-5469-4bdd-a43b-13be7cb7c730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500599413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3500599413
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4242526253
Short name T193
Test name
Test status
Simulation time 488818835 ps
CPU time 2.44 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203808 kb
Host smart-1c181b9d-11da-48d7-8cfa-28e805095f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242526253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4242526253
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.4031351681
Short name T1364
Test name
Test status
Simulation time 38392349 ps
CPU time 0.68 seconds
Started May 19 01:52:32 PM PDT 24
Finished May 19 01:52:33 PM PDT 24
Peak memory 203620 kb
Host smart-a2c301bd-51c5-4822-a79f-d9b84330ff37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031351681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.4031351681
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3919582212
Short name T1362
Test name
Test status
Simulation time 239593755 ps
CPU time 0.69 seconds
Started May 19 01:52:21 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203808 kb
Host smart-1df240e9-6bf4-4de0-851f-399debdb02c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919582212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3919582212
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1268970069
Short name T1418
Test name
Test status
Simulation time 46476102 ps
CPU time 0.66 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203592 kb
Host smart-b936ae50-c1d3-41de-a70b-5c138840cf4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268970069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1268970069
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.179941028
Short name T1368
Test name
Test status
Simulation time 27521544 ps
CPU time 0.63 seconds
Started May 19 01:52:39 PM PDT 24
Finished May 19 01:52:40 PM PDT 24
Peak memory 202972 kb
Host smart-60d5b2a6-18cc-428f-92fd-6aa116de7675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179941028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.179941028
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2672007667
Short name T1420
Test name
Test status
Simulation time 23623011 ps
CPU time 0.64 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203632 kb
Host smart-7f38b542-334b-4c19-9159-97e028a05050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672007667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2672007667
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1477977607
Short name T1407
Test name
Test status
Simulation time 15794882 ps
CPU time 0.68 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:15 PM PDT 24
Peak memory 203640 kb
Host smart-82b181a7-7e93-4ad5-96ba-173aec302329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477977607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1477977607
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.321629840
Short name T1349
Test name
Test status
Simulation time 17930667 ps
CPU time 0.68 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203616 kb
Host smart-22be0efe-606d-4866-9c9b-2746807a4d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321629840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.321629840
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.809433682
Short name T1409
Test name
Test status
Simulation time 31371051 ps
CPU time 0.7 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203640 kb
Host smart-cf887972-4f2f-4cd0-8bb4-c47cb082350a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809433682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.809433682
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3366244144
Short name T1414
Test name
Test status
Simulation time 38892039 ps
CPU time 0.63 seconds
Started May 19 01:52:11 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203652 kb
Host smart-81af00b2-5989-40d4-830d-adb8684ba30d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366244144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3366244144
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3392796318
Short name T1360
Test name
Test status
Simulation time 34553811 ps
CPU time 0.65 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203640 kb
Host smart-b4663586-78f1-429e-a5ab-6db16d2aa5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392796318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3392796318
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3298184003
Short name T94
Test name
Test status
Simulation time 68300485 ps
CPU time 1.42 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203788 kb
Host smart-6dbb4c6e-0fe6-48be-b80e-c9e66e603136
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298184003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3298184003
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4027459781
Short name T1416
Test name
Test status
Simulation time 858138937 ps
CPU time 3.3 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203824 kb
Host smart-ce71301f-f3a3-4b8b-834b-b80e22ec22c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027459781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4027459781
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1989425526
Short name T1383
Test name
Test status
Simulation time 20662496 ps
CPU time 0.74 seconds
Started May 19 01:52:14 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203744 kb
Host smart-3d197576-e486-4ce8-ad26-bdf6103c714a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989425526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1989425526
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.134249368
Short name T1417
Test name
Test status
Simulation time 87460714 ps
CPU time 0.77 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:18 PM PDT 24
Peak memory 203772 kb
Host smart-48830e0e-869e-4d03-8ce2-6fbb26ecd79c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134249368 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.134249368
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2404024013
Short name T225
Test name
Test status
Simulation time 50905947 ps
CPU time 0.75 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203700 kb
Host smart-cb4693fd-9552-4bc3-b0db-255743b96be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404024013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2404024013
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3629886927
Short name T1373
Test name
Test status
Simulation time 115302174 ps
CPU time 0.65 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203804 kb
Host smart-e1c0a3b4-190a-4e7e-a821-436c1d6e1487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629886927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3629886927
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1149675192
Short name T1445
Test name
Test status
Simulation time 28136860 ps
CPU time 1.11 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203724 kb
Host smart-3d6b7b43-a5dd-4002-a383-4487f805f428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149675192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1149675192
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.257744083
Short name T177
Test name
Test status
Simulation time 280085697 ps
CPU time 1.94 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:10 PM PDT 24
Peak memory 203776 kb
Host smart-87489fdd-a3a2-4b24-ad1b-1559b711fcda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257744083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.257744083
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2024899115
Short name T1428
Test name
Test status
Simulation time 26870605 ps
CPU time 0.68 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203608 kb
Host smart-36b2dd4e-ed2e-449e-b3c9-04404ecec456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024899115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2024899115
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.956087963
Short name T1388
Test name
Test status
Simulation time 57648637 ps
CPU time 0.69 seconds
Started May 19 01:52:21 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203820 kb
Host smart-4cb52a73-f34e-41a0-a427-968b4614e4a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956087963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.956087963
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2503951010
Short name T1429
Test name
Test status
Simulation time 34790181 ps
CPU time 0.63 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:19 PM PDT 24
Peak memory 203548 kb
Host smart-9554716f-ce6e-489d-877c-27a56d4b6fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503951010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2503951010
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3246672252
Short name T1365
Test name
Test status
Simulation time 20226861 ps
CPU time 0.7 seconds
Started May 19 01:52:19 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203652 kb
Host smart-198396e9-691a-4802-8d4e-418e46075171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246672252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3246672252
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.353007306
Short name T1376
Test name
Test status
Simulation time 58456143 ps
CPU time 0.69 seconds
Started May 19 01:52:12 PM PDT 24
Finished May 19 01:52:18 PM PDT 24
Peak memory 203624 kb
Host smart-e33ed242-b8f4-4aa8-8a62-5186dd2fc6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353007306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.353007306
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3599002698
Short name T1395
Test name
Test status
Simulation time 15580372 ps
CPU time 0.65 seconds
Started May 19 01:52:30 PM PDT 24
Finished May 19 01:52:31 PM PDT 24
Peak memory 203820 kb
Host smart-bfab9db1-a022-4ccb-bd25-fedb10a1bbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599002698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3599002698
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1627575691
Short name T1375
Test name
Test status
Simulation time 17699857 ps
CPU time 0.7 seconds
Started May 19 01:52:43 PM PDT 24
Finished May 19 01:52:45 PM PDT 24
Peak memory 203648 kb
Host smart-2f897347-1324-49dc-88cf-ef976af314a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627575691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1627575691
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3786534257
Short name T1438
Test name
Test status
Simulation time 17822809 ps
CPU time 0.64 seconds
Started May 19 01:52:29 PM PDT 24
Finished May 19 01:52:30 PM PDT 24
Peak memory 203620 kb
Host smart-86654f7a-50ba-4084-a444-263de2e5f630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786534257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3786534257
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2970266512
Short name T1386
Test name
Test status
Simulation time 25730013 ps
CPU time 0.66 seconds
Started May 19 01:52:44 PM PDT 24
Finished May 19 01:52:45 PM PDT 24
Peak memory 203608 kb
Host smart-fafade29-827e-4dee-876c-73a19270d5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970266512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2970266512
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1037567629
Short name T1357
Test name
Test status
Simulation time 43609028 ps
CPU time 0.64 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203644 kb
Host smart-802ff0ab-318e-4243-9988-6584dfa81355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037567629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1037567629
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.49172025
Short name T196
Test name
Test status
Simulation time 48023896 ps
CPU time 1.26 seconds
Started May 19 01:52:18 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203896 kb
Host smart-107ad890-cdcc-4b44-ad64-a0b464445b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49172025 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.49172025
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3125496120
Short name T1449
Test name
Test status
Simulation time 29754761 ps
CPU time 0.69 seconds
Started May 19 01:52:05 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203732 kb
Host smart-3a022254-6858-4afa-bb3c-32318d373909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125496120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3125496120
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1137469992
Short name T1371
Test name
Test status
Simulation time 18947230 ps
CPU time 0.7 seconds
Started May 19 01:52:07 PM PDT 24
Finished May 19 01:52:11 PM PDT 24
Peak memory 203624 kb
Host smart-1d7c9497-36ea-424b-a4bd-e5266e84625f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137469992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1137469992
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1267025375
Short name T223
Test name
Test status
Simulation time 722724341 ps
CPU time 1.08 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203772 kb
Host smart-f232b769-f631-438b-b1b2-238e4666224a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267025375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1267025375
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2453480240
Short name T102
Test name
Test status
Simulation time 612444966 ps
CPU time 2.96 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 203844 kb
Host smart-97980657-67a6-4186-9417-e36b50a5d08a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453480240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2453480240
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1994246926
Short name T99
Test name
Test status
Simulation time 147199305 ps
CPU time 2.44 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203768 kb
Host smart-54b8a440-d7ff-4df3-9925-aeef88c544f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994246926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1994246926
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.217210522
Short name T1410
Test name
Test status
Simulation time 19154723 ps
CPU time 0.78 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203684 kb
Host smart-75079e22-5dfa-481f-ae70-23537159bb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217210522 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.217210522
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2527674757
Short name T1412
Test name
Test status
Simulation time 91057333 ps
CPU time 0.78 seconds
Started May 19 01:52:21 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203704 kb
Host smart-c3f76c58-aed4-4c5b-88e6-da0552a8c3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527674757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2527674757
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.4100904638
Short name T1354
Test name
Test status
Simulation time 28412565 ps
CPU time 0.68 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:22 PM PDT 24
Peak memory 203644 kb
Host smart-b5a8b6b5-b7b4-443e-80c7-0dde41f6d238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100904638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.4100904638
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.299929304
Short name T1452
Test name
Test status
Simulation time 67738696 ps
CPU time 0.85 seconds
Started May 19 01:52:23 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203720 kb
Host smart-2c59d282-db77-4230-ab63-70f5440b915c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299929304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.299929304
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1962690456
Short name T1387
Test name
Test status
Simulation time 538154634 ps
CPU time 1.31 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:16 PM PDT 24
Peak memory 203828 kb
Host smart-bfd2c736-b0df-48e0-9fb3-ed50b63405ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962690456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1962690456
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.744340096
Short name T203
Test name
Test status
Simulation time 155691123 ps
CPU time 2.18 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 203724 kb
Host smart-d973ef59-05bd-41f2-965d-54bbb8cdd44d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744340096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.744340096
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1355497046
Short name T1424
Test name
Test status
Simulation time 131415964 ps
CPU time 1 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203820 kb
Host smart-8967b52b-dee1-4fdc-a359-3fe1f19a72ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355497046 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1355497046
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1441318968
Short name T101
Test name
Test status
Simulation time 86673180 ps
CPU time 0.82 seconds
Started May 19 01:52:31 PM PDT 24
Finished May 19 01:52:32 PM PDT 24
Peak memory 203640 kb
Host smart-909ad69b-5059-46b6-9551-a3fb6470b872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441318968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1441318968
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1279569258
Short name T1408
Test name
Test status
Simulation time 17974864 ps
CPU time 0.66 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 203656 kb
Host smart-dec9ae76-9f7a-4b15-b8ce-218b474abab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279569258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1279569258
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.740029754
Short name T1451
Test name
Test status
Simulation time 40485136 ps
CPU time 0.88 seconds
Started May 19 01:52:09 PM PDT 24
Finished May 19 01:52:13 PM PDT 24
Peak memory 203656 kb
Host smart-de391da9-e750-44e7-bf9d-33ac20339e0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740029754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.740029754
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.797014285
Short name T204
Test name
Test status
Simulation time 192974726 ps
CPU time 1.57 seconds
Started May 19 01:52:10 PM PDT 24
Finished May 19 01:52:16 PM PDT 24
Peak memory 203796 kb
Host smart-0eb5305c-9b59-4c5f-af81-036eb6e0a3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797014285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.797014285
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2269346512
Short name T1444
Test name
Test status
Simulation time 776287357 ps
CPU time 2.45 seconds
Started May 19 01:52:13 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203820 kb
Host smart-ec14b576-26d6-47a7-9f26-689c7ea83cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269346512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2269346512
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4150231997
Short name T1367
Test name
Test status
Simulation time 52180807 ps
CPU time 0.8 seconds
Started May 19 01:52:08 PM PDT 24
Finished May 19 01:52:12 PM PDT 24
Peak memory 203656 kb
Host smart-b21fd317-1840-41c8-ba07-12f3a2e1e33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150231997 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4150231997
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.829364303
Short name T1435
Test name
Test status
Simulation time 29748329 ps
CPU time 0.68 seconds
Started May 19 01:52:27 PM PDT 24
Finished May 19 01:52:28 PM PDT 24
Peak memory 203752 kb
Host smart-a1ba515c-b60d-4602-ad1e-297fe6a71e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829364303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.829364303
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.962504122
Short name T1351
Test name
Test status
Simulation time 16691584 ps
CPU time 0.65 seconds
Started May 19 01:52:15 PM PDT 24
Finished May 19 01:52:21 PM PDT 24
Peak memory 203676 kb
Host smart-83b1d3a9-09cd-46c1-9712-5346283dbc5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962504122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.962504122
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.310004218
Short name T1454
Test name
Test status
Simulation time 88762419 ps
CPU time 1.64 seconds
Started May 19 01:52:17 PM PDT 24
Finished May 19 01:52:25 PM PDT 24
Peak memory 203800 kb
Host smart-ef9be514-bf8a-4dfe-a844-a7ac27898497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310004218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.310004218
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1894387221
Short name T100
Test name
Test status
Simulation time 106162261 ps
CPU time 0.95 seconds
Started May 19 01:52:16 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203776 kb
Host smart-da0d3153-cbd0-4d3c-9dfe-ebde0745a51d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894387221 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1894387221
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1525105136
Short name T1455
Test name
Test status
Simulation time 38752498 ps
CPU time 0.68 seconds
Started May 19 01:52:17 PM PDT 24
Finished May 19 01:52:23 PM PDT 24
Peak memory 203680 kb
Host smart-bb83fe7b-2b50-45fd-b834-3e8b9d884370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525105136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1525105136
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3472574688
Short name T1456
Test name
Test status
Simulation time 18482853 ps
CPU time 0.67 seconds
Started May 19 01:52:02 PM PDT 24
Finished May 19 01:52:06 PM PDT 24
Peak memory 203636 kb
Host smart-1aee7527-4957-4223-9453-725fdb95e0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472574688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3472574688
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.890751698
Short name T95
Test name
Test status
Simulation time 127379209 ps
CPU time 0.87 seconds
Started May 19 01:52:04 PM PDT 24
Finished May 19 01:52:09 PM PDT 24
Peak memory 203736 kb
Host smart-2e6995bd-4e29-485e-8b07-7c15a2e732c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890751698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.890751698
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3850634216
Short name T1392
Test name
Test status
Simulation time 101879294 ps
CPU time 2.2 seconds
Started May 19 01:52:19 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 203812 kb
Host smart-93198893-b278-4389-be30-d7b68d595b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850634216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3850634216
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4012007287
Short name T121
Test name
Test status
Simulation time 157784845 ps
CPU time 1.46 seconds
Started May 19 01:52:26 PM PDT 24
Finished May 19 01:52:29 PM PDT 24
Peak memory 203860 kb
Host smart-d588f699-1318-453b-a2fd-cda442a2de47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012007287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.4012007287
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3013776179
Short name T529
Test name
Test status
Simulation time 18244801 ps
CPU time 0.62 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 204632 kb
Host smart-78668829-4842-4905-856d-843f84e31990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013776179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3013776179
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.513681380
Short name T515
Test name
Test status
Simulation time 238977412 ps
CPU time 1.98 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 219480 kb
Host smart-eac78fc6-7bb8-4102-b51a-b87a3943877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513681380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.513681380
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1418031911
Short name T1021
Test name
Test status
Simulation time 1173908226 ps
CPU time 6.67 seconds
Started May 19 01:56:20 PM PDT 24
Finished May 19 01:56:28 PM PDT 24
Peak memory 256844 kb
Host smart-5037d23d-65ee-4630-a1c7-cecb357ab006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418031911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1418031911
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3563829863
Short name T173
Test name
Test status
Simulation time 1509965942 ps
CPU time 40.05 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 449392 kb
Host smart-3254273d-e221-4212-a624-8c793b6048b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563829863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3563829863
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1127011982
Short name T115
Test name
Test status
Simulation time 15787193225 ps
CPU time 83.82 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 757944 kb
Host smart-3c0a53ef-c19e-4f90-833b-bf3843430b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127011982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1127011982
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3507278767
Short name T228
Test name
Test status
Simulation time 1658352594 ps
CPU time 0.87 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 204780 kb
Host smart-ea2b6662-77db-467e-b190-9e14c9387b76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507278767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3507278767
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3517344701
Short name T314
Test name
Test status
Simulation time 199434865 ps
CPU time 5.73 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 240052 kb
Host smart-f65a697a-b651-4da2-a812-a29478559804
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517344701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3517344701
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3017503484
Short name T263
Test name
Test status
Simulation time 13960046048 ps
CPU time 316.13 seconds
Started May 19 01:56:31 PM PDT 24
Finished May 19 02:01:48 PM PDT 24
Peak memory 1088084 kb
Host smart-ca644a51-57ff-45d4-8d40-59dac20ceef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017503484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3017503484
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2050140520
Short name T804
Test name
Test status
Simulation time 1920128205 ps
CPU time 3.17 seconds
Started May 19 01:56:28 PM PDT 24
Finished May 19 01:56:32 PM PDT 24
Peak memory 205016 kb
Host smart-a04eba9d-d650-4fef-ae80-3e01445ed5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050140520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2050140520
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3580301566
Short name T460
Test name
Test status
Simulation time 8362702000 ps
CPU time 90.29 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 383136 kb
Host smart-510203a2-1476-4796-b3cf-5031aeab8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580301566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3580301566
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.541352958
Short name T860
Test name
Test status
Simulation time 48335457 ps
CPU time 0.66 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 204536 kb
Host smart-23123a5b-b287-4da0-aa66-cf84fd910505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541352958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.541352958
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1854354955
Short name T656
Test name
Test status
Simulation time 12412384682 ps
CPU time 735.33 seconds
Started May 19 01:56:23 PM PDT 24
Finished May 19 02:08:39 PM PDT 24
Peak memory 765096 kb
Host smart-a01ab361-db80-48d0-95c8-a3198aa5c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854354955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1854354955
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.4015474766
Short name T899
Test name
Test status
Simulation time 2440277987 ps
CPU time 59.66 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:57:25 PM PDT 24
Peak memory 306052 kb
Host smart-8bc15633-4b07-4a8e-8138-b1c1efeb30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015474766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.4015474766
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3891457510
Short name T265
Test name
Test status
Simulation time 22772488707 ps
CPU time 410.16 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 02:03:15 PM PDT 24
Peak memory 1009908 kb
Host smart-3b19508e-653d-4828-a37a-d34334aad79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891457510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3891457510
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.289377136
Short name T1218
Test name
Test status
Simulation time 12793817754 ps
CPU time 19.81 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 229600 kb
Host smart-77e9df9f-d244-4072-a9f0-ae621e827cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289377136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.289377136
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.4196219759
Short name T1313
Test name
Test status
Simulation time 10507665808 ps
CPU time 5.43 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 233316 kb
Host smart-ad716802-7df3-4de9-b7bd-70db32609190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196219759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.4196219759
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1556220126
Short name T16
Test name
Test status
Simulation time 3241790889 ps
CPU time 12.12 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 213796 kb
Host smart-d1e4d8bc-09c2-41fb-a592-702b76822faf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556220126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1556220126
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1499654840
Short name T91
Test name
Test status
Simulation time 1692883138 ps
CPU time 2.63 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 205092 kb
Host smart-6294a10a-aed4-4032-a0c2-710bcc7811c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499654840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1499654840
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.2672467734
Short name T488
Test name
Test status
Simulation time 23398833361 ps
CPU time 63.01 seconds
Started May 19 01:56:20 PM PDT 24
Finished May 19 01:57:25 PM PDT 24
Peak memory 1282496 kb
Host smart-a7ee9339-2f4a-464f-a0e1-9b1ef020a291
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672467734 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.2672467734
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.987656438
Short name T486
Test name
Test status
Simulation time 3834278729 ps
CPU time 44.51 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:57:08 PM PDT 24
Peak memory 205304 kb
Host smart-e44008e2-e096-41aa-9684-4b70fe6c9590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987656438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.987656438
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1048713104
Short name T278
Test name
Test status
Simulation time 6408640297 ps
CPU time 31.21 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 222108 kb
Host smart-855a3d41-9119-4253-9d8b-5f2db8a4dea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048713104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1048713104
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.654835064
Short name T825
Test name
Test status
Simulation time 19113722065 ps
CPU time 10.75 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:56:41 PM PDT 24
Peak memory 205016 kb
Host smart-975dee70-b23a-4b44-82b4-4d02cc259ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654835064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.654835064
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3569555060
Short name T587
Test name
Test status
Simulation time 11573540201 ps
CPU time 53.5 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 840396 kb
Host smart-65909cc5-4737-46a7-b725-bc8974deb087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569555060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3569555060
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2388266684
Short name T1285
Test name
Test status
Simulation time 1201338839 ps
CPU time 7.57 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:52 PM PDT 24
Peak memory 221488 kb
Host smart-8d5b0546-f8b0-458c-87c9-ea99fb085d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388266684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2388266684
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1326062928
Short name T459
Test name
Test status
Simulation time 38936390 ps
CPU time 0.6 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 204524 kb
Host smart-e1d40911-6b57-4b42-a5a0-828c584f8a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326062928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1326062928
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1500368884
Short name T824
Test name
Test status
Simulation time 1806208387 ps
CPU time 3.54 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:50 PM PDT 24
Peak memory 216908 kb
Host smart-1d293bff-e14f-431e-8145-def12b240ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500368884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1500368884
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3107981243
Short name T648
Test name
Test status
Simulation time 6557716556 ps
CPU time 9.43 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 295900 kb
Host smart-310d91ef-8182-490f-b195-c85bc16d2fc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107981243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3107981243
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3245048355
Short name T1247
Test name
Test status
Simulation time 2244633386 ps
CPU time 149.94 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 630052 kb
Host smart-b6fefb75-7c5c-4d37-a54d-1b8cdec02adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245048355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3245048355
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2684361949
Short name T800
Test name
Test status
Simulation time 6921605913 ps
CPU time 43.23 seconds
Started May 19 01:56:37 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 556032 kb
Host smart-20bc2f18-689a-4cc2-810b-18f9114d356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684361949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2684361949
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1976873011
Short name T353
Test name
Test status
Simulation time 370713090 ps
CPU time 0.96 seconds
Started May 19 01:56:34 PM PDT 24
Finished May 19 01:56:36 PM PDT 24
Peak memory 204932 kb
Host smart-1497a517-5eab-465a-9489-92b827fc4599
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976873011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1976873011
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2980055256
Short name T1335
Test name
Test status
Simulation time 16121781851 ps
CPU time 108.97 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:58:20 PM PDT 24
Peak memory 1167260 kb
Host smart-7a45fa24-152a-4c91-bfe8-6073e4a08d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980055256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2980055256
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3857432931
Short name T1156
Test name
Test status
Simulation time 374063927 ps
CPU time 4.56 seconds
Started May 19 01:56:37 PM PDT 24
Finished May 19 01:56:45 PM PDT 24
Peak memory 205024 kb
Host smart-46a6e2b3-f740-4775-8214-42997d66de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857432931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3857432931
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1994290391
Short name T35
Test name
Test status
Simulation time 4505592536 ps
CPU time 49.99 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 475812 kb
Host smart-1153b90c-659c-40f5-81e1-3286a59eb9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994290391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1994290391
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2606097073
Short name T528
Test name
Test status
Simulation time 1377004117 ps
CPU time 4.46 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 213276 kb
Host smart-e6f56e99-42e7-471f-a1a5-370e7eda490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606097073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2606097073
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1262384880
Short name T624
Test name
Test status
Simulation time 3997341561 ps
CPU time 43.75 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:57:17 PM PDT 24
Peak memory 415468 kb
Host smart-a6f796f7-6947-416b-86e1-caa065c6fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262384880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1262384880
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3404162842
Short name T397
Test name
Test status
Simulation time 638057850 ps
CPU time 12.77 seconds
Started May 19 01:56:32 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 214696 kb
Host smart-d3baa159-1b5d-4fb1-a81e-004039d8965e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404162842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3404162842
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.650925963
Short name T178
Test name
Test status
Simulation time 39942237 ps
CPU time 0.83 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 222096 kb
Host smart-a0a344b7-96ac-414e-8307-8dbdc0608a35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650925963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.650925963
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1687472322
Short name T1059
Test name
Test status
Simulation time 1314998839 ps
CPU time 2.25 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:44 PM PDT 24
Peak memory 204996 kb
Host smart-4b096e5c-c845-4cb0-aaff-a442fa4fddd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687472322 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1687472322
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3221286187
Short name T771
Test name
Test status
Simulation time 10333882832 ps
CPU time 13.34 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:58 PM PDT 24
Peak memory 250060 kb
Host smart-e02e472b-12f1-4fdb-8eba-2dbb6c1c3f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221286187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3221286187
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3138423318
Short name T743
Test name
Test status
Simulation time 10047400547 ps
CPU time 85.84 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 478344 kb
Host smart-fbc1621f-8c64-451a-b2be-055b088de1c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138423318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3138423318
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.961298095
Short name T452
Test name
Test status
Simulation time 401265504 ps
CPU time 2.61 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 205032 kb
Host smart-9b7a73f8-880b-4e9d-97af-3229452d19f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961298095 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.961298095
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1302656995
Short name T12
Test name
Test status
Simulation time 1782137097 ps
CPU time 5.21 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 205296 kb
Host smart-f4579b86-670d-4a26-bab6-3a2fb0fda5ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302656995 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1302656995
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3297009202
Short name T888
Test name
Test status
Simulation time 1633487441 ps
CPU time 5.35 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:48 PM PDT 24
Peak memory 339488 kb
Host smart-c5939196-620d-4187-ad0a-a731cb21786b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297009202 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3297009202
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2518113282
Short name T987
Test name
Test status
Simulation time 3088134964 ps
CPU time 6.19 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:48 PM PDT 24
Peak memory 205032 kb
Host smart-9ba38ac6-49ea-48a3-9b8b-ea92bc67a2d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518113282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2518113282
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.638267042
Short name T466
Test name
Test status
Simulation time 933588032 ps
CPU time 17.74 seconds
Started May 19 01:56:23 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 213220 kb
Host smart-0aa3b92d-ef70-4922-b118-3a3a5911334d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638267042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.638267042
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2501009504
Short name T1139
Test name
Test status
Simulation time 23817407198 ps
CPU time 21.35 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 433068 kb
Host smart-d80a7082-61da-449c-8521-91193199b8b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501009504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2501009504
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.766900710
Short name T332
Test name
Test status
Simulation time 25024150792 ps
CPU time 1536.75 seconds
Started May 19 01:56:27 PM PDT 24
Finished May 19 02:22:05 PM PDT 24
Peak memory 3050044 kb
Host smart-07bcadd7-1ddf-4a12-a7ab-b7e3097a4980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766900710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.766900710
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1611758949
Short name T534
Test name
Test status
Simulation time 5680875491 ps
CPU time 6.87 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 213296 kb
Host smart-01914c64-1b0b-4c83-95a6-9e0e97ee3ebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611758949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1611758949
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.725975719
Short name T1042
Test name
Test status
Simulation time 20202882 ps
CPU time 0.61 seconds
Started May 19 01:57:17 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 204520 kb
Host smart-ba3f6a74-f046-4914-92a1-c49ca57f1546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725975719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.725975719
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2632469926
Short name T238
Test name
Test status
Simulation time 275376941 ps
CPU time 4.07 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 231248 kb
Host smart-a25c02b1-30a8-438e-b083-701915d2d6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632469926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2632469926
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1885332482
Short name T1217
Test name
Test status
Simulation time 1420400367 ps
CPU time 20.57 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 287636 kb
Host smart-e19d2a9e-9ad0-4073-bc5f-b5300104a029
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885332482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1885332482
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3456207390
Short name T672
Test name
Test status
Simulation time 10969775113 ps
CPU time 100.78 seconds
Started May 19 01:56:58 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 861384 kb
Host smart-69fa1066-74ae-4ce2-a17a-d3e45500d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456207390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3456207390
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3062548820
Short name T1337
Test name
Test status
Simulation time 3981067488 ps
CPU time 72.22 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 01:58:15 PM PDT 24
Peak memory 689976 kb
Host smart-f0a2ad1f-903c-4ef4-8dea-eecbad26a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062548820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3062548820
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.92109220
Short name T411
Test name
Test status
Simulation time 123491174 ps
CPU time 1.16 seconds
Started May 19 01:57:00 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 204952 kb
Host smart-6a991709-2a0d-4521-8e9a-848d497af3b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92109220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt
.92109220
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.837366210
Short name T914
Test name
Test status
Simulation time 783675420 ps
CPU time 5.82 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:57:13 PM PDT 24
Peak memory 204912 kb
Host smart-1a2f4c44-c636-42d6-a30b-b3c4b6bd2696
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837366210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
837366210
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2075879758
Short name T783
Test name
Test status
Simulation time 18218846208 ps
CPU time 305.92 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 02:02:12 PM PDT 24
Peak memory 1201336 kb
Host smart-225cdf4c-8261-4ee8-9a4d-f7c67406ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075879758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2075879758
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.269896496
Short name T621
Test name
Test status
Simulation time 499180393 ps
CPU time 20.14 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:36 PM PDT 24
Peak memory 204920 kb
Host smart-4adf94e5-76f2-4fb7-a15a-44595819e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269896496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.269896496
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.781398556
Short name T807
Test name
Test status
Simulation time 2552998393 ps
CPU time 81.79 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 340040 kb
Host smart-d659c1aa-33d5-4fd4-8e29-4af73fba0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781398556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.781398556
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2853420910
Short name T73
Test name
Test status
Simulation time 82824011 ps
CPU time 0.64 seconds
Started May 19 01:57:08 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 204672 kb
Host smart-fb43790c-1f56-4df9-938a-51f3be291190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853420910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2853420910
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1333321284
Short name T981
Test name
Test status
Simulation time 17592066607 ps
CPU time 288.87 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 1247732 kb
Host smart-f7876312-74af-4288-9474-98e214f5d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333321284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1333321284
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.993713258
Short name T1193
Test name
Test status
Simulation time 5111002529 ps
CPU time 19.21 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:57:26 PM PDT 24
Peak memory 295616 kb
Host smart-d728b257-910e-4965-a763-2b678ff07f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993713258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.993713258
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1934701002
Short name T52
Test name
Test status
Simulation time 57763909662 ps
CPU time 2170.34 seconds
Started May 19 01:57:00 PM PDT 24
Finished May 19 02:33:12 PM PDT 24
Peak memory 2395596 kb
Host smart-693d8a16-62cc-4146-80c3-3b53e61f253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934701002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1934701002
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1564592492
Short name T1329
Test name
Test status
Simulation time 629549615 ps
CPU time 30.06 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:57:41 PM PDT 24
Peak memory 213164 kb
Host smart-5f862910-857a-46a5-a2ef-32a8d3c3b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564592492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1564592492
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2488013216
Short name T605
Test name
Test status
Simulation time 2912093245 ps
CPU time 3.32 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 205156 kb
Host smart-3b19efc7-f411-47d7-9f5f-c3a0fa76e065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488013216 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2488013216
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3643908458
Short name T968
Test name
Test status
Simulation time 10088543309 ps
CPU time 77.59 seconds
Started May 19 01:57:09 PM PDT 24
Finished May 19 01:58:28 PM PDT 24
Peak memory 557312 kb
Host smart-d8636f82-f3eb-4f8b-ab93-48b65b173923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643908458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3643908458
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1233337240
Short name T142
Test name
Test status
Simulation time 334084902 ps
CPU time 2.28 seconds
Started May 19 01:57:15 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 205048 kb
Host smart-14b32e66-ad3c-40b8-952a-933c31faa5aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233337240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1233337240
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2413963445
Short name T1234
Test name
Test status
Simulation time 2025103355 ps
CPU time 6.98 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 01:57:15 PM PDT 24
Peak memory 204980 kb
Host smart-f9061df2-31d8-45fd-aa06-3659c6175261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413963445 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2413963445
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2886046993
Short name T1282
Test name
Test status
Simulation time 18219572518 ps
CPU time 389.34 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 02:03:36 PM PDT 24
Peak memory 4313576 kb
Host smart-a34b536f-4ba3-4407-ab61-43984b9b75c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886046993 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2886046993
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1940394577
Short name T923
Test name
Test status
Simulation time 1423946571 ps
CPU time 54.94 seconds
Started May 19 01:57:01 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 204980 kb
Host smart-c07f00e6-93c3-4f64-a8bd-5742d3f207a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940394577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1940394577
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2694708434
Short name T442
Test name
Test status
Simulation time 48676377181 ps
CPU time 1110.78 seconds
Started May 19 01:57:00 PM PDT 24
Finished May 19 02:15:32 PM PDT 24
Peak memory 7294136 kb
Host smart-ee388914-00bf-47e1-825b-7fd2509ba620
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694708434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2694708434
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1900873156
Short name T372
Test name
Test status
Simulation time 40359847419 ps
CPU time 740.17 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 02:09:32 PM PDT 24
Peak memory 3902396 kb
Host smart-03602a39-ed9a-4b85-b8a3-79b47beebd91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900873156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1900873156
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.817615647
Short name T1246
Test name
Test status
Simulation time 1374357285 ps
CPU time 7.06 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 204968 kb
Host smart-9189e8e6-ca04-4764-a980-ec9b57e10ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817615647 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.817615647
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.230504247
Short name T973
Test name
Test status
Simulation time 58519071 ps
CPU time 0.64 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 204632 kb
Host smart-77839451-a1a3-48b4-bd5d-05bcfbe431d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230504247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.230504247
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2239211883
Short name T547
Test name
Test status
Simulation time 99501412 ps
CPU time 2 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:57:17 PM PDT 24
Peak memory 213248 kb
Host smart-367d1f28-bcac-4a76-97db-572ed76a45d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239211883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2239211883
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.4177455731
Short name T520
Test name
Test status
Simulation time 2502204643 ps
CPU time 28.67 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:57:44 PM PDT 24
Peak memory 319964 kb
Host smart-201af929-f703-49be-8f4b-868308b63844
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177455731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.4177455731
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.141413277
Short name T1324
Test name
Test status
Simulation time 2980722189 ps
CPU time 102.01 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 569360 kb
Host smart-d752a244-4ee6-4324-8db5-c2943e336b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141413277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.141413277
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2600374044
Short name T1321
Test name
Test status
Simulation time 5427207214 ps
CPU time 96.43 seconds
Started May 19 01:57:11 PM PDT 24
Finished May 19 01:58:48 PM PDT 24
Peak memory 544088 kb
Host smart-5891e2d8-f11b-4675-80d4-2ecc1abeac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600374044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2600374044
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1579395789
Short name T1106
Test name
Test status
Simulation time 214133853 ps
CPU time 1.03 seconds
Started May 19 01:57:08 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 204784 kb
Host smart-a7db8046-c71b-47e3-8a4e-626f0e7661a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579395789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1579395789
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3332654134
Short name T721
Test name
Test status
Simulation time 492959547 ps
CPU time 4.22 seconds
Started May 19 01:57:13 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 227988 kb
Host smart-e8e4304d-d6e2-4e64-9d3e-405e51e9b885
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332654134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3332654134
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3206935836
Short name T1346
Test name
Test status
Simulation time 2877137926 ps
CPU time 57.19 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 772780 kb
Host smart-3c1e8e9a-4e34-4b49-a6a3-d1301d2caa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206935836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3206935836
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.442942873
Short name T678
Test name
Test status
Simulation time 345000106 ps
CPU time 14.67 seconds
Started May 19 01:57:15 PM PDT 24
Finished May 19 01:57:30 PM PDT 24
Peak memory 205016 kb
Host smart-b9686cae-a6dc-4b0e-b735-a8fa26b454bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442942873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.442942873
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.694646636
Short name T960
Test name
Test status
Simulation time 25741091 ps
CPU time 0.67 seconds
Started May 19 01:57:15 PM PDT 24
Finished May 19 01:57:16 PM PDT 24
Peak memory 204700 kb
Host smart-d3767c34-6bd1-4cdc-8a49-309d6cb73e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694646636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.694646636
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.4239478683
Short name T1278
Test name
Test status
Simulation time 800241287 ps
CPU time 11.13 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 275864 kb
Host smart-45cd7104-32db-400a-a7a5-93419f4ff105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239478683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.4239478683
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.153547772
Short name T883
Test name
Test status
Simulation time 1527342185 ps
CPU time 71.77 seconds
Started May 19 01:57:13 PM PDT 24
Finished May 19 01:58:25 PM PDT 24
Peak memory 278040 kb
Host smart-ca4acd2f-9134-4195-845a-6c9dd44b6dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153547772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.153547772
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3091403256
Short name T1170
Test name
Test status
Simulation time 66603952844 ps
CPU time 316.21 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 02:02:25 PM PDT 24
Peak memory 1186248 kb
Host smart-c6e43ccd-3add-4583-805e-35794dbf163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091403256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3091403256
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2001990768
Short name T549
Test name
Test status
Simulation time 515263590 ps
CPU time 9.18 seconds
Started May 19 01:57:00 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 213172 kb
Host smart-6ffe2645-438a-4048-a8d7-557c784ff6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001990768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2001990768
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3142269907
Short name T911
Test name
Test status
Simulation time 826853986 ps
CPU time 4.45 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:25 PM PDT 24
Peak memory 213156 kb
Host smart-9b7afc62-3e0c-4e3c-b89b-5d4069088f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142269907 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3142269907
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2024851128
Short name T1274
Test name
Test status
Simulation time 10156702249 ps
CPU time 12.17 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:29 PM PDT 24
Peak memory 275804 kb
Host smart-f65c68bf-c86c-47a2-8d50-09316b564236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024851128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2024851128
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3812040962
Short name T615
Test name
Test status
Simulation time 10330155318 ps
CPU time 14.25 seconds
Started May 19 01:57:12 PM PDT 24
Finished May 19 01:57:27 PM PDT 24
Peak memory 316180 kb
Host smart-26896c4d-566a-4077-8e8f-f722b6a96810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812040962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3812040962
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3450329955
Short name T381
Test name
Test status
Simulation time 602311977 ps
CPU time 3.28 seconds
Started May 19 01:57:32 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 205044 kb
Host smart-2598b4be-9b0a-4574-983d-f4d50bda70c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450329955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3450329955
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2375598261
Short name T718
Test name
Test status
Simulation time 1089862415 ps
CPU time 5.69 seconds
Started May 19 01:57:13 PM PDT 24
Finished May 19 01:57:20 PM PDT 24
Peak memory 214392 kb
Host smart-a01d045b-2047-42e2-bfe6-bdc798139a9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375598261 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2375598261
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3352865299
Short name T597
Test name
Test status
Simulation time 6988776808 ps
CPU time 5.38 seconds
Started May 19 01:57:12 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 205004 kb
Host smart-699cb331-48ae-4525-8697-c8d4cd9cc23d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352865299 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3352865299
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1231240363
Short name T1052
Test name
Test status
Simulation time 2126169098 ps
CPU time 42 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 204940 kb
Host smart-ebf1cc84-e667-49a2-9031-39bebcd09268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231240363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1231240363
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.327383496
Short name T1293
Test name
Test status
Simulation time 1160875719 ps
CPU time 37.77 seconds
Started May 19 01:57:10 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 204944 kb
Host smart-8102dc0d-b236-4869-855f-a5fb02647334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327383496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.327383496
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.4029272717
Short name T926
Test name
Test status
Simulation time 22614428333 ps
CPU time 12.9 seconds
Started May 19 01:57:13 PM PDT 24
Finished May 19 01:57:27 PM PDT 24
Peak memory 227584 kb
Host smart-1b695a36-4fa3-4d14-bce5-ea606ba96ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029272717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.4029272717
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.32957880
Short name T1131
Test name
Test status
Simulation time 26679820222 ps
CPU time 172.11 seconds
Started May 19 01:57:12 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 1631792 kb
Host smart-849389e4-a4b4-47ce-acfd-aace5ec4f5dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_stretch.32957880
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1252562068
Short name T69
Test name
Test status
Simulation time 7311421419 ps
CPU time 6.47 seconds
Started May 19 01:57:17 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 213220 kb
Host smart-2cda0727-093b-4186-a3b8-524e615c054b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252562068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1252562068
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1659546393
Short name T369
Test name
Test status
Simulation time 40956134 ps
CPU time 0.59 seconds
Started May 19 01:57:23 PM PDT 24
Finished May 19 01:57:25 PM PDT 24
Peak memory 204672 kb
Host smart-16587142-e61f-4a50-a0ae-51c5f4bc6ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659546393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1659546393
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.778316166
Short name T1191
Test name
Test status
Simulation time 1421655672 ps
CPU time 3.85 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 213312 kb
Host smart-1c3ff4eb-9286-445d-bc3c-9359c63763ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778316166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.778316166
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2646727316
Short name T567
Test name
Test status
Simulation time 669340871 ps
CPU time 17.6 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 277024 kb
Host smart-9dde6a81-743f-4d5d-b93f-7d886d4ca9ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646727316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2646727316
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.517090638
Short name T186
Test name
Test status
Simulation time 2582028564 ps
CPU time 102.36 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:59:02 PM PDT 24
Peak memory 846248 kb
Host smart-2de05958-255f-4432-bee0-9e6480394947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517090638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.517090638
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.296777699
Short name T116
Test name
Test status
Simulation time 344216774 ps
CPU time 0.8 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 01:57:29 PM PDT 24
Peak memory 204732 kb
Host smart-a9ba6692-24b6-4472-9450-66d1303d69f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296777699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.296777699
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3657136473
Short name T367
Test name
Test status
Simulation time 437402747 ps
CPU time 8.05 seconds
Started May 19 01:57:22 PM PDT 24
Finished May 19 01:57:30 PM PDT 24
Peak memory 204980 kb
Host smart-2b14af36-e745-4096-be77-21b54354508a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657136473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3657136473
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1169030457
Short name T465
Test name
Test status
Simulation time 24924590597 ps
CPU time 133.73 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:59:33 PM PDT 24
Peak memory 1195308 kb
Host smart-3c3749bf-0ee9-4c65-b621-86cbc9de65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169030457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1169030457
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3081737865
Short name T44
Test name
Test status
Simulation time 1521335732 ps
CPU time 16.1 seconds
Started May 19 01:57:17 PM PDT 24
Finished May 19 01:57:34 PM PDT 24
Peak memory 204928 kb
Host smart-5833c9e0-5cc1-4252-b496-6f2db1f77a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081737865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3081737865
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1303068009
Short name T991
Test name
Test status
Simulation time 11058832685 ps
CPU time 25.81 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 318324 kb
Host smart-94e80653-ad6f-4039-9bb8-617b2acea50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303068009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1303068009
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.420621934
Short name T305
Test name
Test status
Simulation time 27337401 ps
CPU time 0.73 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:21 PM PDT 24
Peak memory 204892 kb
Host smart-3cebf66a-9606-4272-b144-674649d4532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420621934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.420621934
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2509119972
Short name T58
Test name
Test status
Simulation time 2694888587 ps
CPU time 119.42 seconds
Started May 19 01:57:15 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 240860 kb
Host smart-d3796f55-7e4a-40dc-9381-ce51db650562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509119972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2509119972
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3304705244
Short name T471
Test name
Test status
Simulation time 37917682353 ps
CPU time 45.48 seconds
Started May 19 01:57:23 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 461496 kb
Host smart-249924c8-b609-4965-9ef7-101c9ea36cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304705244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3304705244
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.790958740
Short name T264
Test name
Test status
Simulation time 36259449644 ps
CPU time 494.17 seconds
Started May 19 01:57:24 PM PDT 24
Finished May 19 02:05:39 PM PDT 24
Peak memory 1688268 kb
Host smart-8ff6db82-fb8c-4dc7-b809-26af11f992b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790958740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.790958740
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.281941630
Short name T740
Test name
Test status
Simulation time 2739847989 ps
CPU time 19.07 seconds
Started May 19 01:57:22 PM PDT 24
Finished May 19 01:57:42 PM PDT 24
Peak memory 213296 kb
Host smart-973296da-766b-4aaf-ac01-56e85a3972c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281941630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.281941630
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2670564919
Short name T688
Test name
Test status
Simulation time 4288994684 ps
CPU time 4.67 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 213560 kb
Host smart-dbf2a44f-ca25-4e58-a4b6-5cf5a47d024b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670564919 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2670564919
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2399739122
Short name T168
Test name
Test status
Simulation time 10126691792 ps
CPU time 79.08 seconds
Started May 19 01:57:15 PM PDT 24
Finished May 19 01:58:35 PM PDT 24
Peak memory 544796 kb
Host smart-489af544-d30d-478b-bd27-308c8147c141
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399739122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2399739122
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.865006194
Short name T1203
Test name
Test status
Simulation time 10075389642 ps
CPU time 84.18 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 550140 kb
Host smart-00d3226e-d787-41c3-8dae-20160ec64d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865006194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.865006194
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1842520381
Short name T1264
Test name
Test status
Simulation time 1849354765 ps
CPU time 2.65 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:57:21 PM PDT 24
Peak memory 205156 kb
Host smart-15796369-1cb1-4590-9fbc-d9e47cbfb6f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842520381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1842520381
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4112624966
Short name T276
Test name
Test status
Simulation time 12470271089 ps
CPU time 4.9 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 204988 kb
Host smart-d7019dff-98a9-4b83-8a95-d416c85f96e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112624966 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4112624966
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2319548904
Short name T1197
Test name
Test status
Simulation time 24182718060 ps
CPU time 64.82 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:58:20 PM PDT 24
Peak memory 1292244 kb
Host smart-8246da60-d21f-4270-8616-0919cdb01705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319548904 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2319548904
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.741983173
Short name T378
Test name
Test status
Simulation time 1324989845 ps
CPU time 48.46 seconds
Started May 19 01:57:11 PM PDT 24
Finished May 19 01:58:00 PM PDT 24
Peak memory 204992 kb
Host smart-922113f9-7085-4033-89ee-b1518b570708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741983173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.741983173
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2520585879
Short name T1275
Test name
Test status
Simulation time 7220356562 ps
CPU time 29.79 seconds
Started May 19 01:57:28 PM PDT 24
Finished May 19 01:57:58 PM PDT 24
Peak memory 232980 kb
Host smart-45151048-fec8-4992-836a-88bf85ff0527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520585879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2520585879
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3747277048
Short name T298
Test name
Test status
Simulation time 9395713411 ps
CPU time 10.38 seconds
Started May 19 01:57:20 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 205116 kb
Host smart-511b13b1-29cb-455f-9418-bc7bb3727f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747277048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3747277048
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2567184420
Short name T1
Test name
Test status
Simulation time 12537239385 ps
CPU time 169.65 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 02:00:08 PM PDT 24
Peak memory 1533456 kb
Host smart-0934b61b-e546-4ac6-a2a0-9c17ba086909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567184420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2567184420
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3939230757
Short name T1121
Test name
Test status
Simulation time 2829705699 ps
CPU time 7.7 seconds
Started May 19 01:57:23 PM PDT 24
Finished May 19 01:57:31 PM PDT 24
Peak memory 213332 kb
Host smart-4ce46c2e-beb4-4292-95c9-157e4e00506a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939230757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3939230757
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.455572383
Short name T453
Test name
Test status
Simulation time 829747504 ps
CPU time 3.06 seconds
Started May 19 01:57:22 PM PDT 24
Finished May 19 01:57:26 PM PDT 24
Peak memory 213304 kb
Host smart-2b013848-20a0-4edd-9555-3d874380c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455572383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.455572383
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1145091796
Short name T1129
Test name
Test status
Simulation time 1158491858 ps
CPU time 14.44 seconds
Started May 19 01:57:25 PM PDT 24
Finished May 19 01:57:40 PM PDT 24
Peak memory 263656 kb
Host smart-a86727d3-d8de-43af-89c7-9b21b72ab6bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145091796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1145091796
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1628888389
Short name T151
Test name
Test status
Simulation time 1794846284 ps
CPU time 55.62 seconds
Started May 19 01:57:20 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 649128 kb
Host smart-f6885fd0-cfc6-4e80-b2b7-730a7a0208b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628888389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1628888389
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3965920719
Short name T778
Test name
Test status
Simulation time 3291393109 ps
CPU time 52.04 seconds
Started May 19 01:57:21 PM PDT 24
Finished May 19 01:58:14 PM PDT 24
Peak memory 581428 kb
Host smart-b2cb1892-04de-431b-9544-db03d1644413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965920719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3965920719
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1070747168
Short name T1272
Test name
Test status
Simulation time 691960066 ps
CPU time 1.1 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 204900 kb
Host smart-b450ba09-c6c2-49e3-aa0d-3f49fba1cb26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070747168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1070747168
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.236460632
Short name T1260
Test name
Test status
Simulation time 808021057 ps
CPU time 4.84 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 241676 kb
Host smart-4085dde2-981d-483c-b4a3-b3b41860c0fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236460632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
236460632
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2840066026
Short name T75
Test name
Test status
Simulation time 3315656453 ps
CPU time 167.44 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 806780 kb
Host smart-e0ea265b-e3aa-4a69-97b0-d8e5c70b8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840066026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2840066026
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3528938391
Short name T315
Test name
Test status
Simulation time 350431834 ps
CPU time 14.76 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:44 PM PDT 24
Peak memory 204900 kb
Host smart-2435486c-bfa2-4a24-9e12-92196d9222fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528938391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3528938391
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1932004330
Short name T1144
Test name
Test status
Simulation time 1601776500 ps
CPU time 32.24 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:58:00 PM PDT 24
Peak memory 340224 kb
Host smart-5c94de29-6485-47c6-9805-d006ddb4f6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932004330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1932004330
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2839992881
Short name T961
Test name
Test status
Simulation time 15983167 ps
CPU time 0.65 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:21 PM PDT 24
Peak memory 204536 kb
Host smart-2136faa5-127e-4201-918a-b66a00980e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839992881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2839992881
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1512377409
Short name T566
Test name
Test status
Simulation time 28364444622 ps
CPU time 139.62 seconds
Started May 19 01:57:28 PM PDT 24
Finished May 19 01:59:49 PM PDT 24
Peak memory 854016 kb
Host smart-e7aacc16-2bbb-4ecd-abb6-c3f5be9cc5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512377409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1512377409
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.998437297
Short name T503
Test name
Test status
Simulation time 1270798788 ps
CPU time 27.53 seconds
Started May 19 01:57:19 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 358676 kb
Host smart-5275abf6-7694-49a6-bd63-d5cba9a2c270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998437297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.998437297
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1302557443
Short name T152
Test name
Test status
Simulation time 16102416340 ps
CPU time 718.36 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 02:09:35 PM PDT 24
Peak memory 2396088 kb
Host smart-5edac7f5-c4f1-4024-a0d7-9cdf84410035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302557443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1302557443
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1346518493
Short name T877
Test name
Test status
Simulation time 2787425068 ps
CPU time 9.61 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:57:29 PM PDT 24
Peak memory 221172 kb
Host smart-da7d98af-8acd-4c73-a80c-91d07b81066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346518493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1346518493
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1811518339
Short name T440
Test name
Test status
Simulation time 719605484 ps
CPU time 4.2 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 204976 kb
Host smart-f71e92ad-b37b-4c6a-9d4f-8f33db184e91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811518339 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1811518339
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3661317143
Short name T838
Test name
Test status
Simulation time 10033951783 ps
CPU time 70.02 seconds
Started May 19 01:57:20 PM PDT 24
Finished May 19 01:58:31 PM PDT 24
Peak memory 415984 kb
Host smart-f8437bad-a71f-4ffd-b331-af03c8a1d113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661317143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3661317143
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3484654865
Short name T1171
Test name
Test status
Simulation time 10043144663 ps
CPU time 87.4 seconds
Started May 19 01:57:24 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 564128 kb
Host smart-2b839a1b-eae8-4e26-a7dd-4986cd625adf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484654865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3484654865
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2054790911
Short name T876
Test name
Test status
Simulation time 2372899018 ps
CPU time 3.77 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:57:22 PM PDT 24
Peak memory 205064 kb
Host smart-4531a615-3d0c-4b22-8c04-0dab4805768e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054790911 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2054790911
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.928417646
Short name T719
Test name
Test status
Simulation time 9727039016 ps
CPU time 18.76 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 633400 kb
Host smart-cf2b20dd-9da2-4557-be28-e886cfdb1079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928417646 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.928417646
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.228927503
Short name T143
Test name
Test status
Simulation time 1608926220 ps
CPU time 11.96 seconds
Started May 19 01:57:17 PM PDT 24
Finished May 19 01:57:30 PM PDT 24
Peak memory 204956 kb
Host smart-02fdbd40-0b89-4fe7-9de4-0c3492306c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228927503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.228927503
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1618738913
Short name T368
Test name
Test status
Simulation time 5639467713 ps
CPU time 14.65 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 209628 kb
Host smart-e954c94a-c0d0-4bcb-b70a-40452a5773d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618738913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1618738913
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1603100864
Short name T1038
Test name
Test status
Simulation time 10312962542 ps
CPU time 22.1 seconds
Started May 19 01:57:16 PM PDT 24
Finished May 19 01:57:39 PM PDT 24
Peak memory 205100 kb
Host smart-7ba9710b-93e2-4b0a-9ac4-3e3c68603399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603100864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1603100864
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2458158030
Short name T406
Test name
Test status
Simulation time 32963993699 ps
CPU time 1132.78 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 02:16:29 PM PDT 24
Peak memory 2564104 kb
Host smart-4f578450-0b35-43be-93a3-89f238c0252f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458158030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2458158030
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.864761872
Short name T777
Test name
Test status
Simulation time 4490977311 ps
CPU time 6.79 seconds
Started May 19 01:57:22 PM PDT 24
Finished May 19 01:57:29 PM PDT 24
Peak memory 204908 kb
Host smart-21383fa8-62ab-412c-b075-8c0e15d9030e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864761872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.864761872
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2742160531
Short name T633
Test name
Test status
Simulation time 18387808 ps
CPU time 0.61 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 204624 kb
Host smart-a081a2b7-274d-4834-b19c-d85d86c58619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742160531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2742160531
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.704243647
Short name T1345
Test name
Test status
Simulation time 114543202 ps
CPU time 2.02 seconds
Started May 19 01:57:28 PM PDT 24
Finished May 19 01:57:31 PM PDT 24
Peak memory 213236 kb
Host smart-b14f7165-78dc-4679-bb30-e80331d5e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704243647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.704243647
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.586891630
Short name T1328
Test name
Test status
Simulation time 314253981 ps
CPU time 5.46 seconds
Started May 19 01:57:31 PM PDT 24
Finished May 19 01:57:37 PM PDT 24
Peak memory 258260 kb
Host smart-5740a057-7686-476a-a0fd-c3e820a91a1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586891630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.586891630
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2820232756
Short name T1190
Test name
Test status
Simulation time 1650208494 ps
CPU time 95.24 seconds
Started May 19 01:57:20 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 462576 kb
Host smart-771e2f84-c8f2-49be-b1ea-17cb3c6fd347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820232756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2820232756
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2797982343
Short name T1152
Test name
Test status
Simulation time 18600184532 ps
CPU time 155.11 seconds
Started May 19 01:57:18 PM PDT 24
Finished May 19 01:59:55 PM PDT 24
Peak memory 689264 kb
Host smart-fbed0253-ca4c-488f-ab10-68bab646fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797982343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2797982343
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.4013297154
Short name T895
Test name
Test status
Simulation time 211531650 ps
CPU time 0.93 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 204768 kb
Host smart-64b17d62-42b7-4c2a-b67d-342f5d75fe9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013297154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.4013297154
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3751066951
Short name T189
Test name
Test status
Simulation time 325756378 ps
CPU time 3.64 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:34 PM PDT 24
Peak memory 205008 kb
Host smart-89f9fac2-f2ca-489e-9823-06f788710629
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751066951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3751066951
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2216446383
Short name T651
Test name
Test status
Simulation time 3264248566 ps
CPU time 225.32 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 02:01:21 PM PDT 24
Peak memory 957940 kb
Host smart-5c9e0085-72e2-48b9-9429-bdae3984e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216446383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2216446383
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2713107721
Short name T682
Test name
Test status
Simulation time 1827203805 ps
CPU time 29.26 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 337060 kb
Host smart-24e378ca-7716-4288-8110-2326439db5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713107721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2713107721
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.29864196
Short name T517
Test name
Test status
Simulation time 21561348 ps
CPU time 0.67 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 204700 kb
Host smart-173fc20b-3e5c-4ced-aad0-5c9c70b9ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29864196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.29864196
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.4188081781
Short name T540
Test name
Test status
Simulation time 1822025841 ps
CPU time 6.49 seconds
Started May 19 01:57:32 PM PDT 24
Finished May 19 01:57:40 PM PDT 24
Peak memory 253396 kb
Host smart-e51ed9f7-0888-4ed7-bec7-9a3d61fe8382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188081781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.4188081781
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.162655069
Short name T583
Test name
Test status
Simulation time 4488714126 ps
CPU time 50.52 seconds
Started May 19 01:57:32 PM PDT 24
Finished May 19 01:58:23 PM PDT 24
Peak memory 277736 kb
Host smart-f10cadc2-b35a-4072-a696-2520eb237181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162655069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.162655069
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.4240400229
Short name T1177
Test name
Test status
Simulation time 878562583 ps
CPU time 16.77 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 215032 kb
Host smart-ce33c258-98ae-47e6-b930-0731a056731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240400229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.4240400229
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2874461443
Short name T797
Test name
Test status
Simulation time 2645874695 ps
CPU time 3.31 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 205144 kb
Host smart-d1d66307-05ad-47e4-b6f6-e7225f56e14e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874461443 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2874461443
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.653434274
Short name T866
Test name
Test status
Simulation time 10087116048 ps
CPU time 74.49 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 487052 kb
Host smart-e50cb94f-8d4d-40c8-bd01-b33a329953f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653434274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.653434274
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1582304906
Short name T703
Test name
Test status
Simulation time 10135530313 ps
CPU time 81.25 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 470952 kb
Host smart-15a4c058-cc52-41a6-acdb-b4eff4e55c20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582304906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1582304906
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1500332505
Short name T165
Test name
Test status
Simulation time 987464854 ps
CPU time 2.72 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:42 PM PDT 24
Peak memory 205028 kb
Host smart-ee2052dd-d832-48e5-9aeb-9e48a0274a6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500332505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1500332505
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.755287638
Short name T539
Test name
Test status
Simulation time 1689744114 ps
CPU time 4.85 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:43 PM PDT 24
Peak memory 206064 kb
Host smart-54681d63-04ec-4454-bbc0-78865e3dbc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755287638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.755287638
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2674667771
Short name T478
Test name
Test status
Simulation time 19559855589 ps
CPU time 24.34 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 666188 kb
Host smart-7e64aaeb-2e76-41e4-bad8-dbb25fb9af17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674667771 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2674667771
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.537048086
Short name T248
Test name
Test status
Simulation time 2719054359 ps
CPU time 8.81 seconds
Started May 19 01:57:28 PM PDT 24
Finished May 19 01:57:38 PM PDT 24
Peak memory 205052 kb
Host smart-1898c299-e884-405e-92fa-b9a8e273bd1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537048086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.537048086
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3701889440
Short name T787
Test name
Test status
Simulation time 2141089949 ps
CPU time 21.22 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 215956 kb
Host smart-30f032af-ffc3-4e2a-abc9-89761bf7bec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701889440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3701889440
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.833674615
Short name T462
Test name
Test status
Simulation time 16240059856 ps
CPU time 32.56 seconds
Started May 19 01:57:20 PM PDT 24
Finished May 19 01:57:54 PM PDT 24
Peak memory 205088 kb
Host smart-ce83bc50-d027-4be9-84d0-20537c572c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833674615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.833674615
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1826708882
Short name T1183
Test name
Test status
Simulation time 29380758594 ps
CPU time 1760.12 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 5787324 kb
Host smart-a7f94aaa-b254-4daf-9f8d-51f0b97afb92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826708882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1826708882
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1670955173
Short name T1036
Test name
Test status
Simulation time 1434758957 ps
CPU time 7.77 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 213220 kb
Host smart-948bb7b5-a461-49ea-8f4b-b94a7deacd64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670955173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1670955173
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.545784654
Short name T764
Test name
Test status
Simulation time 27026057 ps
CPU time 0.61 seconds
Started May 19 01:57:45 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 204644 kb
Host smart-14bbaae3-a8ea-4ea2-8f4a-a66329d5c8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545784654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.545784654
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1877418493
Short name T531
Test name
Test status
Simulation time 349567392 ps
CPU time 1.59 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 213252 kb
Host smart-c5baae06-cca5-48be-ad81-186e7b44431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877418493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1877418493
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.405065341
Short name T1198
Test name
Test status
Simulation time 663646140 ps
CPU time 6.66 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 278448 kb
Host smart-6d5f0c50-3f8b-49a1-b8ca-e23f47afd10c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405065341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.405065341
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1589934618
Short name T1327
Test name
Test status
Simulation time 2268079238 ps
CPU time 140.91 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:59:52 PM PDT 24
Peak memory 627024 kb
Host smart-f674964a-f69c-4a76-bd89-3489d65f7042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589934618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1589934618
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.4174658634
Short name T782
Test name
Test status
Simulation time 3510826279 ps
CPU time 60.42 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 640656 kb
Host smart-2419e23d-db8a-4042-8cb7-1835f782904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174658634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.4174658634
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2550564311
Short name T1237
Test name
Test status
Simulation time 209569388 ps
CPU time 5.26 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 204812 kb
Host smart-8adc92fd-f9b8-4b1b-9774-9e953978c11b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550564311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2550564311
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3412517816
Short name T107
Test name
Test status
Simulation time 11233385023 ps
CPU time 65.39 seconds
Started May 19 01:57:30 PM PDT 24
Finished May 19 01:58:36 PM PDT 24
Peak memory 902116 kb
Host smart-3bb4688d-8206-45ff-8330-27777513e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412517816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3412517816
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2771816011
Short name T464
Test name
Test status
Simulation time 1841974347 ps
CPU time 17.1 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:18 PM PDT 24
Peak memory 204960 kb
Host smart-484c621f-8814-4d32-90a8-2ca39ce45c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771816011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2771816011
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1980505336
Short name T705
Test name
Test status
Simulation time 2173564408 ps
CPU time 38.96 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:58:17 PM PDT 24
Peak memory 451324 kb
Host smart-6d86f3dd-58b8-40c1-bc88-5a401bd5cee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980505336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1980505336
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2116272118
Short name T936
Test name
Test status
Simulation time 59086522 ps
CPU time 0.66 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 204680 kb
Host smart-60bc621d-b9da-41c2-8b23-5c8d9bc30808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116272118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2116272118
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2375126069
Short name T749
Test name
Test status
Simulation time 12878564478 ps
CPU time 265.93 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 02:02:05 PM PDT 24
Peak memory 260040 kb
Host smart-e30b467f-dfa4-4ec6-8730-8d6f976eca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375126069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2375126069
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2349513569
Short name T1015
Test name
Test status
Simulation time 1698595898 ps
CPU time 32.82 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 328520 kb
Host smart-b744d073-6c00-43a9-b3f6-c23bff12d503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349513569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2349513569
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.3431124947
Short name T124
Test name
Test status
Simulation time 5746188151 ps
CPU time 149.76 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 944272 kb
Host smart-9f62bb84-343b-4b6a-afbe-1a77f3336f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431124947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.3431124947
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2631212759
Short name T840
Test name
Test status
Simulation time 1011590750 ps
CPU time 9.88 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 213028 kb
Host smart-1ddf8634-0cfa-4847-ae44-a4a8a76d7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631212759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2631212759
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2334619355
Short name T1135
Test name
Test status
Simulation time 3783867986 ps
CPU time 4.96 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 215928 kb
Host smart-50c5dbd4-7c5d-4054-9f70-251fbee52c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334619355 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2334619355
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2443051497
Short name T424
Test name
Test status
Simulation time 10459340754 ps
CPU time 12.97 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 279088 kb
Host smart-3c9d6b2f-444b-431b-b9c8-b08126f37c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443051497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2443051497
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3040295894
Short name T608
Test name
Test status
Simulation time 1008812976 ps
CPU time 3.17 seconds
Started May 19 01:57:31 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 205072 kb
Host smart-7050332f-40a1-4dfb-8e40-51520a195020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040295894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3040295894
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2087583069
Short name T1079
Test name
Test status
Simulation time 875452983 ps
CPU time 4.66 seconds
Started May 19 01:57:26 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 204952 kb
Host smart-c5c034b3-33b0-4ff5-9cab-f62c507b60bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087583069 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2087583069
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.951648834
Short name T951
Test name
Test status
Simulation time 3874922141 ps
CPU time 4.89 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:40 PM PDT 24
Peak memory 205116 kb
Host smart-e694e424-551c-491a-ae63-9f6b0aab7267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951648834 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.951648834
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1983678090
Short name T996
Test name
Test status
Simulation time 2504893972 ps
CPU time 17.68 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 205056 kb
Host smart-424aa9f3-92d3-401b-89f8-70817304869c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983678090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1983678090
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3841791206
Short name T1169
Test name
Test status
Simulation time 12489807668 ps
CPU time 46.04 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 207808 kb
Host smart-675e8f10-c20f-4a20-b7e0-3f040e5c6cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841791206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3841791206
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1803279694
Short name T1294
Test name
Test status
Simulation time 46174860589 ps
CPU time 974.05 seconds
Started May 19 01:57:27 PM PDT 24
Finished May 19 02:13:42 PM PDT 24
Peak memory 6815508 kb
Host smart-5d4f8fa3-a696-4b97-8393-ce1ef382cad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803279694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1803279694
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3737274568
Short name T586
Test name
Test status
Simulation time 25333172630 ps
CPU time 492.65 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 02:05:52 PM PDT 24
Peak memory 1462232 kb
Host smart-0f5a113c-cbea-481e-acfd-f9fd93b8c337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737274568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3737274568
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.611257005
Short name T1077
Test name
Test status
Simulation time 1235584163 ps
CPU time 6.44 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 204992 kb
Host smart-46cfb21b-1a27-4119-9e4f-33b6a2ce1e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611257005 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.611257005
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1220374071
Short name T550
Test name
Test status
Simulation time 21897225 ps
CPU time 0.61 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 204644 kb
Host smart-7c352a3b-d735-471d-982b-847c7bae3ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220374071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1220374071
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.800609134
Short name T348
Test name
Test status
Simulation time 1462909705 ps
CPU time 1.56 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:57:38 PM PDT 24
Peak memory 213312 kb
Host smart-bc766cc9-c05f-419d-b94b-6c6ff01dc72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800609134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.800609134
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3658754488
Short name T335
Test name
Test status
Simulation time 450643891 ps
CPU time 22.39 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:57:58 PM PDT 24
Peak memory 277596 kb
Host smart-d8de8cc8-7b7b-43ac-a895-df2d0e45fdcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658754488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3658754488
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.868460184
Short name T1209
Test name
Test status
Simulation time 1484145799 ps
CPU time 50.78 seconds
Started May 19 01:57:29 PM PDT 24
Finished May 19 01:58:22 PM PDT 24
Peak memory 560108 kb
Host smart-16e4e784-8d95-438f-8958-d672d0e1a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868460184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.868460184
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.214006403
Short name T1322
Test name
Test status
Simulation time 35955057680 ps
CPU time 81.79 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:59:01 PM PDT 24
Peak memory 807160 kb
Host smart-7fa30424-c7ac-4e8d-9ec4-2dabe795dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214006403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.214006403
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.979078429
Short name T1009
Test name
Test status
Simulation time 84195956 ps
CPU time 0.94 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 204740 kb
Host smart-d14bbf92-300c-4e56-ad78-31a731e52420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979078429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.979078429
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3339043591
Short name T593
Test name
Test status
Simulation time 157888097 ps
CPU time 4.14 seconds
Started May 19 01:57:56 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 230984 kb
Host smart-4a38a9d9-d653-4667-9deb-8a6d7f71074b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339043591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3339043591
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.479642715
Short name T106
Test name
Test status
Simulation time 21488245348 ps
CPU time 152.59 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 1570148 kb
Host smart-90645541-a469-4331-ba5e-c3d32cbc42e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479642715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.479642715
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3582669124
Short name T1120
Test name
Test status
Simulation time 1012840164 ps
CPU time 10.69 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 204984 kb
Host smart-ce520a1a-8f3e-4448-b8b6-0862473381c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582669124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3582669124
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3671966120
Short name T958
Test name
Test status
Simulation time 11068576131 ps
CPU time 150.44 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 02:00:12 PM PDT 24
Peak memory 524104 kb
Host smart-09c93337-0810-420c-ac8d-c4d17f2a82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671966120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3671966120
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3008785901
Short name T560
Test name
Test status
Simulation time 27509905 ps
CPU time 0.69 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:57:42 PM PDT 24
Peak memory 204636 kb
Host smart-1aad8e8c-f181-4cb7-a0bd-328cdecf1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008785901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3008785901
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2422257970
Short name T691
Test name
Test status
Simulation time 948601412 ps
CPU time 2.63 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:57:39 PM PDT 24
Peak memory 229572 kb
Host smart-0a2984bb-924e-4b35-a37f-bd87ddbb8ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422257970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2422257970
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3111393033
Short name T1284
Test name
Test status
Simulation time 1513215927 ps
CPU time 32.78 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:58:11 PM PDT 24
Peak memory 378708 kb
Host smart-5980d3ce-7878-42f7-959e-64452adcb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111393033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3111393033
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.4139603396
Short name T1280
Test name
Test status
Simulation time 1214634535 ps
CPU time 9.88 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 229584 kb
Host smart-5de4591b-cab7-4a90-b39e-c42162aaa9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139603396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.4139603396
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2809627227
Short name T999
Test name
Test status
Simulation time 6872320450 ps
CPU time 4.73 seconds
Started May 19 01:57:54 PM PDT 24
Finished May 19 01:58:00 PM PDT 24
Peak memory 205128 kb
Host smart-feceefcd-8fc7-4679-b317-ac391eda238a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809627227 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2809627227
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3991967709
Short name T85
Test name
Test status
Simulation time 10066615884 ps
CPU time 18.62 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 293040 kb
Host smart-59058505-df2f-4c20-8a7c-8520be99af0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991967709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3991967709
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.830454962
Short name T930
Test name
Test status
Simulation time 10068258958 ps
CPU time 65.99 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 443072 kb
Host smart-c50d6a28-bfe8-4ee1-98b8-a4167f8e8011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830454962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.830454962
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4068923583
Short name T306
Test name
Test status
Simulation time 1660559200 ps
CPU time 2.83 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 204964 kb
Host smart-adb8e25a-d303-4c89-b4a4-f8111285c9bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068923583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4068923583
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2732018172
Short name T394
Test name
Test status
Simulation time 2570928590 ps
CPU time 4.14 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:57:41 PM PDT 24
Peak memory 205036 kb
Host smart-24032162-a8ac-4928-a1ce-3bed315c5796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732018172 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2732018172
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3768184460
Short name T1307
Test name
Test status
Simulation time 7795607882 ps
CPU time 96.22 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 2032952 kb
Host smart-b72caa8e-f587-426b-bc22-7f98002f43bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768184460 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3768184460
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3951558219
Short name T1178
Test name
Test status
Simulation time 2017481223 ps
CPU time 41.19 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:58:18 PM PDT 24
Peak memory 204916 kb
Host smart-3a68e4a1-3f34-4bba-872e-0f55a3b46220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951558219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3951558219
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2683295038
Short name T965
Test name
Test status
Simulation time 3346625744 ps
CPU time 31.48 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 229996 kb
Host smart-b8815e7b-a1ef-45c1-8449-6773ac8b9f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683295038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2683295038
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.4087612075
Short name T1078
Test name
Test status
Simulation time 26561473199 ps
CPU time 53.16 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 910788 kb
Host smart-39dedd57-0eba-4158-ab39-ef722300ae0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087612075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.4087612075
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2815935909
Short name T848
Test name
Test status
Simulation time 36455502422 ps
CPU time 318.84 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 02:03:03 PM PDT 24
Peak memory 2062724 kb
Host smart-bc3d09a9-b51e-4728-be98-2e8c88994db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815935909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2815935909
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2805959441
Short name T1033
Test name
Test status
Simulation time 4661413076 ps
CPU time 6.78 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 205128 kb
Host smart-bec3492c-5ca4-4a95-a4d0-d6fcfe79fe5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805959441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2805959441
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2148573108
Short name T689
Test name
Test status
Simulation time 18090874 ps
CPU time 0.66 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 204628 kb
Host smart-61f72f62-ce28-444e-81ad-00cec1cdc3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148573108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2148573108
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.937720108
Short name T405
Test name
Test status
Simulation time 627919154 ps
CPU time 4.83 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:40 PM PDT 24
Peak memory 213272 kb
Host smart-1688bea9-f2d3-40ea-a76b-4a87b15bfb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937720108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.937720108
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1126162142
Short name T341
Test name
Test status
Simulation time 397401486 ps
CPU time 8.76 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 285736 kb
Host smart-b4d064b0-33e7-433a-a134-aabaa4300958
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126162142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1126162142
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3429376575
Short name T78
Test name
Test status
Simulation time 2859221419 ps
CPU time 234.53 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 02:01:41 PM PDT 24
Peak memory 906268 kb
Host smart-7bb38442-688e-46b9-94bb-60e8853c44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429376575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3429376575
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1736494658
Short name T536
Test name
Test status
Simulation time 6131162818 ps
CPU time 101.08 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 514616 kb
Host smart-40eb3b43-1515-43b1-aebb-5103862fe83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736494658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1736494658
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1688314705
Short name T1147
Test name
Test status
Simulation time 107992434 ps
CPU time 1.03 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 01:57:43 PM PDT 24
Peak memory 204720 kb
Host smart-cc4b8364-551d-47a2-8e50-c688a20e8465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688314705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1688314705
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2876674436
Short name T1022
Test name
Test status
Simulation time 1837240985 ps
CPU time 4.67 seconds
Started May 19 01:57:33 PM PDT 24
Finished May 19 01:57:38 PM PDT 24
Peak memory 239280 kb
Host smart-0f6b10ba-efd9-497e-bfd2-fb5527e0e238
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876674436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2876674436
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.995806083
Short name T1011
Test name
Test status
Simulation time 21398670964 ps
CPU time 96.05 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 1137788 kb
Host smart-9f507f65-5741-4187-ae56-c5451dddb4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995806083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.995806083
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1542790425
Short name T600
Test name
Test status
Simulation time 1459867209 ps
CPU time 4.97 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:57:42 PM PDT 24
Peak memory 205260 kb
Host smart-b665f892-adc9-489d-9202-4192aca8182c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542790425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1542790425
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2300813760
Short name T1133
Test name
Test status
Simulation time 1340011550 ps
CPU time 17.36 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:55 PM PDT 24
Peak memory 292544 kb
Host smart-9873b61e-d376-42d7-ad6f-58c192de9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300813760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2300813760
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2598623476
Short name T415
Test name
Test status
Simulation time 33436015 ps
CPU time 0.64 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 204696 kb
Host smart-79cc3920-13af-4dc6-bc99-2be4b86a73ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598623476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2598623476
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.4289815850
Short name T338
Test name
Test status
Simulation time 2757459449 ps
CPU time 83.27 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:59:01 PM PDT 24
Peak memory 835352 kb
Host smart-240f252a-2025-4603-9534-40c30652f2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289815850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.4289815850
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.572051286
Short name T833
Test name
Test status
Simulation time 1230406342 ps
CPU time 20.13 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 314744 kb
Host smart-27498185-3a16-4db2-8406-f6f438bdcb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572051286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.572051286
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2075910475
Short name T125
Test name
Test status
Simulation time 31813313585 ps
CPU time 1086.66 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 02:15:49 PM PDT 24
Peak memory 3651704 kb
Host smart-8efc675c-a79e-4522-8de2-32ae561008c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075910475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2075910475
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.4102226811
Short name T1063
Test name
Test status
Simulation time 10519967068 ps
CPU time 15.49 seconds
Started May 19 01:57:35 PM PDT 24
Finished May 19 01:57:53 PM PDT 24
Peak memory 218308 kb
Host smart-b6f5c67f-a31e-4ccb-a120-b22f8dc3c31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102226811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.4102226811
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2451475923
Short name T455
Test name
Test status
Simulation time 1963501842 ps
CPU time 4.97 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 213128 kb
Host smart-3a56dd6b-7d74-4f26-8f48-965b16b6d3d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451475923 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2451475923
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1959301206
Short name T544
Test name
Test status
Simulation time 10127314246 ps
CPU time 12.58 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 255448 kb
Host smart-83199f18-5c79-4f07-a8af-65f30ff22c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959301206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1959301206
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.124581524
Short name T387
Test name
Test status
Simulation time 10116325387 ps
CPU time 34.63 seconds
Started May 19 01:57:54 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 344660 kb
Host smart-5792200f-d33a-416f-be86-4ed27154ea35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124581524 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.124581524
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1122198104
Short name T13
Test name
Test status
Simulation time 466150263 ps
CPU time 2.69 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 205060 kb
Host smart-9e9bd4e9-5218-4c08-90aa-9da4e6d3887b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122198104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1122198104
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1846777655
Short name T511
Test name
Test status
Simulation time 1556101227 ps
CPU time 4.53 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 205080 kb
Host smart-1d4dcc84-7f26-4819-a552-cbff8de1224b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846777655 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1846777655
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1343805830
Short name T1347
Test name
Test status
Simulation time 16848820039 ps
CPU time 313.44 seconds
Started May 19 01:57:38 PM PDT 24
Finished May 19 02:02:55 PM PDT 24
Peak memory 4012784 kb
Host smart-18b8c405-0935-4b94-9051-60af727dec36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343805830 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1343805830
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1155271725
Short name T546
Test name
Test status
Simulation time 1010816866 ps
CPU time 14.95 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:55 PM PDT 24
Peak memory 204900 kb
Host smart-98d3a2a8-ab28-4fa6-b94d-708528231a00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155271725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1155271725
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1794988808
Short name T1320
Test name
Test status
Simulation time 231674574 ps
CPU time 3.56 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 204976 kb
Host smart-831eb640-a4dc-497e-acc3-6c2ffc30d7bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794988808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1794988808
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.562530082
Short name T612
Test name
Test status
Simulation time 63224130889 ps
CPU time 2192.23 seconds
Started May 19 01:57:34 PM PDT 24
Finished May 19 02:34:08 PM PDT 24
Peak memory 10997220 kb
Host smart-150582e5-325f-480e-933c-3f9cd753dfaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562530082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.562530082
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3785543507
Short name T571
Test name
Test status
Simulation time 27460321405 ps
CPU time 201 seconds
Started May 19 01:58:00 PM PDT 24
Finished May 19 02:01:22 PM PDT 24
Peak memory 1773388 kb
Host smart-4ee6652a-65a0-42fa-89e4-214817e65997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785543507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3785543507
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.587014871
Short name T253
Test name
Test status
Simulation time 6557139445 ps
CPU time 7.94 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:10 PM PDT 24
Peak memory 213284 kb
Host smart-0271f5da-3ba6-405c-b44c-72d5088297f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587014871 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.587014871
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1611388491
Short name T1232
Test name
Test status
Simulation time 34629760 ps
CPU time 0.64 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 204656 kb
Host smart-a203e580-bd00-4757-bfc1-79b3403aa897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611388491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1611388491
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.190450963
Short name T435
Test name
Test status
Simulation time 281375504 ps
CPU time 7.2 seconds
Started May 19 01:58:00 PM PDT 24
Finished May 19 01:58:08 PM PDT 24
Peak memory 221044 kb
Host smart-a75bebde-ef14-44fd-9933-63e4108120d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190450963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.190450963
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2963184316
Short name T1150
Test name
Test status
Simulation time 646749884 ps
CPU time 5.4 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 257912 kb
Host smart-8b942aa3-4145-45f0-9d83-b147f976cf00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963184316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2963184316
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1205227695
Short name T185
Test name
Test status
Simulation time 2293923055 ps
CPU time 167.39 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 02:00:46 PM PDT 24
Peak memory 730676 kb
Host smart-b13ae689-7b74-42b5-a18e-31baf5b98ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205227695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1205227695
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3023043574
Short name T158
Test name
Test status
Simulation time 10817853670 ps
CPU time 86.52 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:59:07 PM PDT 24
Peak memory 732872 kb
Host smart-2440e865-3aff-4099-9a17-7ed6a3addcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023043574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3023043574
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2356310638
Short name T773
Test name
Test status
Simulation time 332371856 ps
CPU time 0.85 seconds
Started May 19 01:57:36 PM PDT 24
Finished May 19 01:57:39 PM PDT 24
Peak memory 204748 kb
Host smart-966756bd-62f8-4d24-ba40-714da788d7fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356310638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2356310638
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2209382402
Short name T113
Test name
Test status
Simulation time 485488868 ps
CPU time 3.61 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 224636 kb
Host smart-4decd59e-438f-45a6-92f4-4096cb0a0936
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209382402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2209382402
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3877683429
Short name T766
Test name
Test status
Simulation time 30791573380 ps
CPU time 134.47 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:59:55 PM PDT 24
Peak memory 1214784 kb
Host smart-c04600c9-cd92-4c4b-bb72-d44cb6bb33bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877683429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3877683429
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1318105429
Short name T484
Test name
Test status
Simulation time 383029924 ps
CPU time 5.24 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 204928 kb
Host smart-af41e2b6-8d51-40fe-9f3e-f2501cdac6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318105429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1318105429
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.733503948
Short name T847
Test name
Test status
Simulation time 3560436558 ps
CPU time 29.51 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 359176 kb
Host smart-1d14443b-cdbd-4718-a1dc-098148c9a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733503948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.733503948
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1467378034
Short name T581
Test name
Test status
Simulation time 114108827 ps
CPU time 0.68 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 204652 kb
Host smart-52b36782-5232-482c-8a44-e290121d7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467378034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1467378034
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.124805579
Short name T1290
Test name
Test status
Simulation time 27278881124 ps
CPU time 449.32 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 02:05:11 PM PDT 24
Peak memory 425396 kb
Host smart-f5860446-b031-4dda-8b37-bce87327d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124805579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.124805579
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3561094064
Short name T1308
Test name
Test status
Simulation time 16227893312 ps
CPU time 33.54 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 327144 kb
Host smart-f978bd76-03de-4f64-ae2e-43b4f176ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561094064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3561094064
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1990383939
Short name T963
Test name
Test status
Simulation time 2673430429 ps
CPU time 17.78 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 213208 kb
Host smart-370f3db1-11e7-41f2-b8de-1fe065b3a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990383939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1990383939
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.4147857857
Short name T739
Test name
Test status
Simulation time 2820489325 ps
CPU time 3.63 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 205100 kb
Host smart-fb73f167-cf0e-4145-9c4b-a6a310f3faa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147857857 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.4147857857
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.425289118
Short name T516
Test name
Test status
Simulation time 10048199850 ps
CPU time 82.56 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 01:59:05 PM PDT 24
Peak memory 543252 kb
Host smart-29370e73-de44-492f-b92d-8713414c0495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425289118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.425289118
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3864492986
Short name T510
Test name
Test status
Simulation time 10145718353 ps
CPU time 18.23 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:58:04 PM PDT 24
Peak memory 299540 kb
Host smart-2721dac1-3823-4cf1-8ae7-6f830dbcd494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864492986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3864492986
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.791370378
Short name T535
Test name
Test status
Simulation time 481102263 ps
CPU time 2.71 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 205068 kb
Host smart-a15dc815-0a6b-4e2a-9c9e-47068499316c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791370378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.791370378
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1301182992
Short name T388
Test name
Test status
Simulation time 2370216335 ps
CPU time 6.25 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 213256 kb
Host smart-76f8235d-07a2-41fc-aace-13147907ac57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301182992 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1301182992
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3615354045
Short name T789
Test name
Test status
Simulation time 8186535708 ps
CPU time 20.49 seconds
Started May 19 01:57:48 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 365336 kb
Host smart-6d1ffa3f-92e2-489a-bf99-0337da664a98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615354045 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3615354045
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3541336162
Short name T1094
Test name
Test status
Simulation time 2159914542 ps
CPU time 42.34 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 01:58:24 PM PDT 24
Peak memory 205036 kb
Host smart-e325ecf9-439e-4075-88eb-db0625bd40f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541336162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3541336162
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.587369958
Short name T1095
Test name
Test status
Simulation time 1434991102 ps
CPU time 6.76 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:11 PM PDT 24
Peak memory 204968 kb
Host smart-aa880fdb-472a-4111-a2bb-27b532563460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587369958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.587369958
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.2987416811
Short name T474
Test name
Test status
Simulation time 12327092830 ps
CPU time 7.8 seconds
Started May 19 01:57:37 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 205056 kb
Host smart-ed6ab314-7f89-4901-a0d0-d37c0ee63d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987416811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.2987416811
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4001057158
Short name T422
Test name
Test status
Simulation time 15531525513 ps
CPU time 149.44 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 723292 kb
Host smart-e0ea5923-6545-4cdb-a07c-7f9a0c570641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001057158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4001057158
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3299139417
Short name T994
Test name
Test status
Simulation time 6406737971 ps
CPU time 8.44 seconds
Started May 19 01:57:40 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 220040 kb
Host smart-1f9c8ffc-69cc-4f57-863a-7889634c3438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299139417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3299139417
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2557338400
Short name T171
Test name
Test status
Simulation time 17950153 ps
CPU time 0.63 seconds
Started May 19 01:57:50 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 204596 kb
Host smart-7d28919f-0423-4f51-ac62-754b81bfe085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557338400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2557338400
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.653422874
Short name T897
Test name
Test status
Simulation time 1042408631 ps
CPU time 13.99 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 256312 kb
Host smart-f22348ba-7488-46d6-adce-906c7a8a3e43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653422874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.653422874
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.719144556
Short name T260
Test name
Test status
Simulation time 6263529993 ps
CPU time 48.83 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 594064 kb
Host smart-2ed646c2-e065-4c12-8c58-012658413ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719144556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.719144556
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3328088249
Short name T573
Test name
Test status
Simulation time 2232844698 ps
CPU time 69.68 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 01:58:54 PM PDT 24
Peak memory 755100 kb
Host smart-8d371940-3b5c-438f-a44c-09d1722e048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328088249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3328088249
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1290367035
Short name T637
Test name
Test status
Simulation time 770523325 ps
CPU time 1.01 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 204860 kb
Host smart-7b87b6da-826c-4b92-99ac-e7cdd0b290c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290367035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1290367035
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.33135564
Short name T1241
Test name
Test status
Simulation time 1213714181 ps
CPU time 8.07 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:57:54 PM PDT 24
Peak memory 204976 kb
Host smart-379d1f6d-0a10-47db-8da8-91ca484c0295
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.33135564
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.696860947
Short name T907
Test name
Test status
Simulation time 10058021038 ps
CPU time 140.25 seconds
Started May 19 01:57:39 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 1255124 kb
Host smart-080eb74b-9d16-4793-bb61-730153637ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696860947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.696860947
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2905334747
Short name T492
Test name
Test status
Simulation time 1262905501 ps
CPU time 13.56 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:58:00 PM PDT 24
Peak memory 204980 kb
Host smart-224198c5-eea4-4dc2-b4bf-b449142666a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905334747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2905334747
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2826070239
Short name T468
Test name
Test status
Simulation time 2806219669 ps
CPU time 23.7 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 297980 kb
Host smart-da937fe6-b4bd-4b8c-9963-d275a539f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826070239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2826070239
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1384936885
Short name T400
Test name
Test status
Simulation time 29971275 ps
CPU time 0.69 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 204704 kb
Host smart-1e03f6bb-e5e6-4a98-90c2-88bff0a3e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384936885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1384936885
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2435259971
Short name T795
Test name
Test status
Simulation time 18267354527 ps
CPU time 226.95 seconds
Started May 19 01:57:41 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 518592 kb
Host smart-8d382ec0-5d8c-498a-99be-f0b4da4a29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435259971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2435259971
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.72819402
Short name T769
Test name
Test status
Simulation time 1271469597 ps
CPU time 14.55 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:00 PM PDT 24
Peak memory 296084 kb
Host smart-5e8f8b48-0eca-4a15-b810-2d6b2e0311db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72819402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.72819402
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.686277264
Short name T603
Test name
Test status
Simulation time 19376994766 ps
CPU time 2831.35 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 02:44:58 PM PDT 24
Peak memory 3214188 kb
Host smart-aee0f4bc-96cb-4c1a-8c51-083bc69d2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686277264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.686277264
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.593648293
Short name T523
Test name
Test status
Simulation time 3740322515 ps
CPU time 4.89 seconds
Started May 19 01:57:49 PM PDT 24
Finished May 19 01:57:55 PM PDT 24
Peak memory 205084 kb
Host smart-19ca5c56-ff9b-4853-b81d-4c1c9b50ee86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593648293 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.593648293
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2755133698
Short name T1303
Test name
Test status
Simulation time 10060826600 ps
CPU time 65.7 seconds
Started May 19 01:57:53 PM PDT 24
Finished May 19 01:59:00 PM PDT 24
Peak memory 413116 kb
Host smart-c4c09ba8-bbe9-402f-ab58-54283b2a1b3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755133698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2755133698
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.4043779089
Short name T853
Test name
Test status
Simulation time 10030157022 ps
CPU time 88.49 seconds
Started May 19 01:57:49 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 464132 kb
Host smart-29da5c5e-4ebf-4d75-897f-e205d6723863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043779089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.4043779089
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1833492137
Short name T518
Test name
Test status
Simulation time 814536154 ps
CPU time 2.68 seconds
Started May 19 01:57:45 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 205048 kb
Host smart-8b3e4d26-0d16-47e3-81a1-dfbd79b35c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833492137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1833492137
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4223428511
Short name T300
Test name
Test status
Simulation time 3469011015 ps
CPU time 4.57 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 207588 kb
Host smart-6819f7c5-4755-4e53-8b40-830b8ebc8853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223428511 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4223428511
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2385209616
Short name T1159
Test name
Test status
Simulation time 11425188252 ps
CPU time 11.84 seconds
Started May 19 01:58:00 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 342776 kb
Host smart-6367dc45-2429-4636-a90d-dd8d433b2c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385209616 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2385209616
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1502563007
Short name T1071
Test name
Test status
Simulation time 1492388442 ps
CPU time 58.54 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:43 PM PDT 24
Peak memory 204924 kb
Host smart-2500ff38-40dd-4028-aea0-912e423b64db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502563007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1502563007
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1173564026
Short name T243
Test name
Test status
Simulation time 2012197907 ps
CPU time 17.31 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:02 PM PDT 24
Peak memory 213292 kb
Host smart-c53bb6b7-404b-48a3-9e4f-506b3a7bc0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173564026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1173564026
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1114188029
Short name T19
Test name
Test status
Simulation time 31149931307 ps
CPU time 294.54 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 02:02:55 PM PDT 24
Peak memory 2843232 kb
Host smart-789bbab9-e537-403e-bbac-686d30c0fcc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114188029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1114188029
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3069953519
Short name T867
Test name
Test status
Simulation time 6467231210 ps
CPU time 20.69 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 546668 kb
Host smart-7af5d021-d02f-4c58-bade-dd9a82a6a892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069953519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3069953519
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2659158430
Short name T164
Test name
Test status
Simulation time 1144956495 ps
CPU time 6.17 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:57:53 PM PDT 24
Peak memory 211420 kb
Host smart-c0d26e7e-0da3-4178-9327-a413cec7af5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659158430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2659158430
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2849504385
Short name T356
Test name
Test status
Simulation time 121142157 ps
CPU time 0.62 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 204608 kb
Host smart-63dc8a21-10bf-46c0-adbd-22743abbe23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849504385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2849504385
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.941446083
Short name T1176
Test name
Test status
Simulation time 70749810 ps
CPU time 1.29 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:56:31 PM PDT 24
Peak memory 221524 kb
Host smart-5cf4456c-4a48-46f6-95d1-9e6162e95dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941446083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.941446083
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.596871895
Short name T780
Test name
Test status
Simulation time 748699938 ps
CPU time 28.18 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:56:58 PM PDT 24
Peak memory 303512 kb
Host smart-bbeae0ab-b7b2-408f-a1c5-df4fb21cceec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596871895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.596871895
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.352118061
Short name T1037
Test name
Test status
Simulation time 8583626820 ps
CPU time 137.91 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:59:05 PM PDT 24
Peak memory 638020 kb
Host smart-96a00fe9-4c5f-4205-ada0-77913ce52592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352118061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.352118061
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.4121444000
Short name T54
Test name
Test status
Simulation time 2487411696 ps
CPU time 169.67 seconds
Started May 19 01:56:34 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 729356 kb
Host smart-b392aaf5-1351-42d3-9631-a3979eba7a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121444000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.4121444000
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.391286733
Short name T489
Test name
Test status
Simulation time 127106507 ps
CPU time 1.07 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 204940 kb
Host smart-4674b084-3afb-41e7-86d9-f2b0a1d825c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391286733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.391286733
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2050910267
Short name T1344
Test name
Test status
Simulation time 3935489443 ps
CPU time 5.61 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 242364 kb
Host smart-1ff62298-e70c-4a4f-85ef-cf7bd84b4898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050910267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2050910267
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3976434272
Short name T660
Test name
Test status
Simulation time 288924199 ps
CPU time 3.8 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 204992 kb
Host smart-9a09946e-96c4-4dfa-9484-79fd75dc25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976434272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3976434272
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.4045300019
Short name T584
Test name
Test status
Simulation time 2583653741 ps
CPU time 52.44 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:57:34 PM PDT 24
Peak memory 388432 kb
Host smart-e9a49dc4-27d0-4bba-9abc-9e0702d7d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045300019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.4045300019
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1720310009
Short name T1072
Test name
Test status
Simulation time 148436992 ps
CPU time 0.66 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:47 PM PDT 24
Peak memory 204668 kb
Host smart-ea0b3f94-894b-49cb-8886-e6bfaa53e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720310009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1720310009
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1129123955
Short name T502
Test name
Test status
Simulation time 49217274784 ps
CPU time 465.14 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 02:04:30 PM PDT 24
Peak memory 205120 kb
Host smart-2b749b1d-ff48-4f0b-872e-92fc2cc6addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129123955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1129123955
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2779256214
Short name T1010
Test name
Test status
Simulation time 1100049647 ps
CPU time 48.38 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:57:26 PM PDT 24
Peak memory 251980 kb
Host smart-e536dce2-27e6-40b4-8f20-5a057d844079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779256214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2779256214
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.2675137787
Short name T1223
Test name
Test status
Simulation time 24874222981 ps
CPU time 1519.9 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 02:22:08 PM PDT 24
Peak memory 2407940 kb
Host smart-c54cbd9f-ff6e-4d87-b189-f601cca7edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675137787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.2675137787
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1437585002
Short name T344
Test name
Test status
Simulation time 1861443516 ps
CPU time 44.34 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:57:27 PM PDT 24
Peak memory 214276 kb
Host smart-924cf52f-5552-45b0-bc05-f07def172326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437585002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1437585002
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.16512864
Short name T182
Test name
Test status
Simulation time 91526544 ps
CPU time 0.99 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:43 PM PDT 24
Peak memory 222968 kb
Host smart-7a68b871-5dfe-4ac0-af70-271f0003afd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16512864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.16512864
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2457148719
Short name T1298
Test name
Test status
Simulation time 573037165 ps
CPU time 3.1 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 204976 kb
Host smart-028781a0-6230-4fd8-8aad-78db837a6160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457148719 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2457148719
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.4214885914
Short name T962
Test name
Test status
Simulation time 10810819411 ps
CPU time 12.67 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 247380 kb
Host smart-58c2bc3a-6235-44af-aaac-beb7d5fa635c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214885914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.4214885914
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2643983811
Short name T752
Test name
Test status
Simulation time 10031326842 ps
CPU time 72.63 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 550772 kb
Host smart-72ebd92e-746d-4571-a349-8e63a2755a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643983811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2643983811
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2320087153
Short name T289
Test name
Test status
Simulation time 450348399 ps
CPU time 2.67 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:47 PM PDT 24
Peak memory 205040 kb
Host smart-71e7f02d-d8cf-47c0-94d4-bc6ab2788b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320087153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2320087153
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3501276377
Short name T498
Test name
Test status
Simulation time 601135554 ps
CPU time 3.9 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 205012 kb
Host smart-1569d5cc-b545-45ba-b056-a4abb18f0477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501276377 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3501276377
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.757225856
Short name T841
Test name
Test status
Simulation time 14728071891 ps
CPU time 116.64 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:58:30 PM PDT 24
Peak memory 1724868 kb
Host smart-7aa1cb63-a0fa-48a3-b943-f5c25e51bd1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757225856 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.757225856
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.660711738
Short name T141
Test name
Test status
Simulation time 2142239462 ps
CPU time 16.17 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 204968 kb
Host smart-f8b1059d-9d0b-43c8-8b5b-b0e98bea2a9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660711738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.660711738
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3531286221
Short name T862
Test name
Test status
Simulation time 5592756786 ps
CPU time 23.14 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 233804 kb
Host smart-962c3b64-ed9b-4137-a7d7-04bc27634e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531286221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3531286221
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.4227826565
Short name T17
Test name
Test status
Simulation time 22604512064 ps
CPU time 24.69 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 398192 kb
Host smart-90e18324-fdba-47aa-8926-4a239d72143c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227826565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.4227826565
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.4252747684
Short name T279
Test name
Test status
Simulation time 5579207152 ps
CPU time 167.57 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:59:35 PM PDT 24
Peak memory 1522600 kb
Host smart-983d58ee-7cf5-4771-86f5-3dab992f84e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252747684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.4252747684
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.4236808450
Short name T1289
Test name
Test status
Simulation time 1283764637 ps
CPU time 7.27 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:50 PM PDT 24
Peak memory 213192 kb
Host smart-0689c4dd-5be7-4ae1-99e2-535ab21b1272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236808450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.4236808450
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1761656854
Short name T794
Test name
Test status
Simulation time 15322717 ps
CPU time 0.63 seconds
Started May 19 01:57:48 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 204628 kb
Host smart-13069d71-5881-45b6-9ec0-90823d62f886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761656854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1761656854
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.178110345
Short name T594
Test name
Test status
Simulation time 229034949 ps
CPU time 2.96 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 213212 kb
Host smart-be4f7253-70e6-461c-9dc2-511027fea252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178110345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.178110345
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1802693086
Short name T786
Test name
Test status
Simulation time 346469198 ps
CPU time 8 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:57:54 PM PDT 24
Peak memory 273136 kb
Host smart-50076708-ca35-472d-a589-6d182219223f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802693086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1802693086
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2795579742
Short name T1064
Test name
Test status
Simulation time 5695586033 ps
CPU time 94.6 seconds
Started May 19 01:57:46 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 741964 kb
Host smart-cfaaa56b-e943-4a22-b283-50df39d5ef23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795579742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2795579742
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1088530151
Short name T288
Test name
Test status
Simulation time 6927509441 ps
CPU time 49.91 seconds
Started May 19 01:57:56 PM PDT 24
Finished May 19 01:58:47 PM PDT 24
Peak memory 516376 kb
Host smart-54121d0f-37e2-4efe-816e-9d4139742b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088530151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1088530151
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3013638449
Short name T1253
Test name
Test status
Simulation time 457587025 ps
CPU time 0.95 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 204764 kb
Host smart-ff5fec4a-015d-45d1-a5df-35c16a3e5145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013638449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3013638449
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2251449806
Short name T748
Test name
Test status
Simulation time 239579507 ps
CPU time 7.16 seconds
Started May 19 01:58:00 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 224912 kb
Host smart-c62f95a0-2053-430c-8aed-064fbbaf3973
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251449806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2251449806
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.322267918
Short name T110
Test name
Test status
Simulation time 6658476139 ps
CPU time 67.46 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 886300 kb
Host smart-b664a524-bf08-4024-ad4f-44228509abbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322267918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.322267918
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1663359374
Short name T473
Test name
Test status
Simulation time 850281321 ps
CPU time 3.75 seconds
Started May 19 01:57:51 PM PDT 24
Finished May 19 01:57:56 PM PDT 24
Peak memory 205020 kb
Host smart-607139ae-ea77-4c38-8b0a-73d6441ffe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663359374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1663359374
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.100755958
Short name T68
Test name
Test status
Simulation time 1865208504 ps
CPU time 102.51 seconds
Started May 19 01:57:53 PM PDT 24
Finished May 19 01:59:36 PM PDT 24
Peak memory 431608 kb
Host smart-36ac8c10-1c22-47f6-9ec2-72470b21244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100755958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.100755958
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2469106920
Short name T132
Test name
Test status
Simulation time 18061430 ps
CPU time 0.65 seconds
Started May 19 01:57:48 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 204644 kb
Host smart-d9384e2c-342c-47b0-a54d-466f6345d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469106920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2469106920
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3363236857
Short name T1309
Test name
Test status
Simulation time 3094967586 ps
CPU time 33.63 seconds
Started May 19 01:57:42 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 221312 kb
Host smart-fc9035f0-3582-46a0-829f-0bebb1be1d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363236857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3363236857
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2311880080
Short name T681
Test name
Test status
Simulation time 6452868079 ps
CPU time 90.55 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:59:17 PM PDT 24
Peak memory 356460 kb
Host smart-887212bb-340d-4939-b5c0-50f3b9bf30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311880080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2311880080
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.111340080
Short name T269
Test name
Test status
Simulation time 16113076612 ps
CPU time 361.14 seconds
Started May 19 01:57:46 PM PDT 24
Finished May 19 02:03:48 PM PDT 24
Peak memory 831920 kb
Host smart-e3e2746f-2f49-494f-9640-f0ec071d6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111340080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.111340080
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.410964134
Short name T1268
Test name
Test status
Simulation time 938162503 ps
CPU time 7.72 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 214608 kb
Host smart-85095951-6e14-4de5-ae84-59131bbb1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410964134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.410964134
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2734473703
Short name T1005
Test name
Test status
Simulation time 6379122578 ps
CPU time 2.77 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 205112 kb
Host smart-1726a311-6065-418b-a4b5-d69d01414ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734473703 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2734473703
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3418178160
Short name T271
Test name
Test status
Simulation time 10113169820 ps
CPU time 14.61 seconds
Started May 19 01:57:48 PM PDT 24
Finished May 19 01:58:04 PM PDT 24
Peak memory 256040 kb
Host smart-9cebabd5-fcdc-4ace-82e1-4ecd5eb212fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418178160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3418178160
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1069432735
Short name T837
Test name
Test status
Simulation time 10180139296 ps
CPU time 14.76 seconds
Started May 19 01:57:47 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 258768 kb
Host smart-1af23171-7922-4a0c-92d5-e839717814b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069432735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1069432735
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3002787589
Short name T1291
Test name
Test status
Simulation time 292503873 ps
CPU time 2.12 seconds
Started May 19 01:57:49 PM PDT 24
Finished May 19 01:57:52 PM PDT 24
Peak memory 205036 kb
Host smart-fb812292-1c10-4fc1-9115-a125f780ab5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002787589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3002787589
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1477459331
Short name T983
Test name
Test status
Simulation time 3723877404 ps
CPU time 5.18 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 205016 kb
Host smart-bc596d7a-d6d7-42c8-84e7-c9e82eeb7477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477459331 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1477459331
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2647089723
Short name T643
Test name
Test status
Simulation time 15281174097 ps
CPU time 162.03 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 02:00:42 PM PDT 24
Peak memory 2077200 kb
Host smart-d56efd95-f6f0-4933-974a-b19e105af2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647089723 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2647089723
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.705836975
Short name T832
Test name
Test status
Simulation time 2602828401 ps
CPU time 12.66 seconds
Started May 19 01:57:43 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 205084 kb
Host smart-2853f814-9f62-4d2e-a101-cc3d8f9c08b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705836975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.705836975
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2412596855
Short name T799
Test name
Test status
Simulation time 21722892872 ps
CPU time 47.26 seconds
Started May 19 01:57:44 PM PDT 24
Finished May 19 01:58:34 PM PDT 24
Peak memory 443116 kb
Host smart-fc2222f3-5df9-414d-b1aa-f1ecfb5091ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412596855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2412596855
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.785243085
Short name T565
Test name
Test status
Simulation time 22718462517 ps
CPU time 1034.62 seconds
Started May 19 01:57:50 PM PDT 24
Finished May 19 02:15:06 PM PDT 24
Peak memory 4507228 kb
Host smart-48fc04a0-9c96-41e6-bfef-c25e9cfc6650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785243085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.785243085
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.109177649
Short name T948
Test name
Test status
Simulation time 1648871312 ps
CPU time 7.07 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 205020 kb
Host smart-3485f10f-5df0-4398-addc-628e39531bb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109177649 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.109177649
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.640844577
Short name T1074
Test name
Test status
Simulation time 16772283 ps
CPU time 0.63 seconds
Started May 19 01:58:06 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 204596 kb
Host smart-5c565cf8-af57-4e3b-a675-f9fe2fd3d6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640844577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.640844577
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1755662175
Short name T592
Test name
Test status
Simulation time 1601369805 ps
CPU time 4.7 seconds
Started May 19 01:57:51 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 213292 kb
Host smart-83dc73c6-99f0-45b3-945b-a1c4a11e693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755662175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1755662175
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3195713508
Short name T304
Test name
Test status
Simulation time 1371643594 ps
CPU time 6.09 seconds
Started May 19 01:57:50 PM PDT 24
Finished May 19 01:57:57 PM PDT 24
Peak memory 246344 kb
Host smart-4ab22237-bcd8-43e5-be13-c54254ddc095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195713508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3195713508
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.448076059
Short name T211
Test name
Test status
Simulation time 2637160253 ps
CPU time 87.34 seconds
Started May 19 01:57:51 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 830024 kb
Host smart-c91d5295-7b32-4fec-8fba-ed0f4b6974e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448076059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.448076059
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.4177619303
Short name T318
Test name
Test status
Simulation time 21542254000 ps
CPU time 49.67 seconds
Started May 19 01:57:54 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 597136 kb
Host smart-da3f41c8-65b5-4409-8e32-e7835bbe2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177619303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4177619303
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.103310230
Short name T230
Test name
Test status
Simulation time 78383768 ps
CPU time 0.89 seconds
Started May 19 01:57:50 PM PDT 24
Finished May 19 01:57:52 PM PDT 24
Peak memory 204776 kb
Host smart-b8495082-c8b6-4d92-b894-0f663ccc0656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103310230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.103310230
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1067190400
Short name T1031
Test name
Test status
Simulation time 203118481 ps
CPU time 5.01 seconds
Started May 19 01:57:53 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 239620 kb
Host smart-dde59e8c-9fc8-481f-834d-e6668b119187
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067190400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1067190400
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3611525536
Short name T1125
Test name
Test status
Simulation time 20804575087 ps
CPU time 426.29 seconds
Started May 19 01:58:06 PM PDT 24
Finished May 19 02:05:13 PM PDT 24
Peak memory 1475784 kb
Host smart-f20f7ba5-6083-4aca-b4e8-bca4c2d6d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611525536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3611525536
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1880968949
Short name T713
Test name
Test status
Simulation time 1877654375 ps
CPU time 20.19 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:30 PM PDT 24
Peak memory 205164 kb
Host smart-d473a260-156e-4d29-a159-6d0b5d4b5f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880968949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1880968949
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3005075926
Short name T34
Test name
Test status
Simulation time 1614165600 ps
CPU time 82.27 seconds
Started May 19 01:57:52 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 427628 kb
Host smart-e6689844-9fbf-4c83-963b-7bb31e27de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005075926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3005075926
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_perf.936601907
Short name T428
Test name
Test status
Simulation time 1649147843 ps
CPU time 2.2 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 221392 kb
Host smart-45a0535c-49fe-4237-8b91-343ed3071cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936601907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.936601907
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3064553326
Short name T281
Test name
Test status
Simulation time 3593706641 ps
CPU time 43.38 seconds
Started May 19 01:57:50 PM PDT 24
Finished May 19 01:58:34 PM PDT 24
Peak memory 282856 kb
Host smart-0fb37388-379a-4834-ab9a-f177b1806a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064553326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3064553326
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1466139683
Short name T1067
Test name
Test status
Simulation time 4738512736 ps
CPU time 13.68 seconds
Started May 19 01:57:59 PM PDT 24
Finished May 19 01:58:14 PM PDT 24
Peak memory 219264 kb
Host smart-640e5e32-2d29-45e7-90fa-bdae8ce009c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466139683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1466139683
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1540929941
Short name T677
Test name
Test status
Simulation time 855003311 ps
CPU time 3.34 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 205016 kb
Host smart-3788f09c-8646-4adc-97a5-e24d806c10cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540929941 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1540929941
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1248659740
Short name T153
Test name
Test status
Simulation time 10562024577 ps
CPU time 8.1 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 227588 kb
Host smart-0a01489b-8b95-401a-8b80-4d2ddab13218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248659740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1248659740
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.114421130
Short name T87
Test name
Test status
Simulation time 10150780819 ps
CPU time 15.72 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 282228 kb
Host smart-a7b8af01-2bec-4d2f-94e0-cfc05487be7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114421130 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.114421130
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1104859797
Short name T683
Test name
Test status
Simulation time 334612473 ps
CPU time 2.49 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 205040 kb
Host smart-eca58fc8-7c7b-4376-8d15-5b475322a404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104859797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1104859797
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3340635763
Short name T606
Test name
Test status
Simulation time 1117329286 ps
CPU time 5.86 seconds
Started May 19 01:58:05 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 207908 kb
Host smart-78b7f010-4768-438c-b3a8-3bc5b26bec42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340635763 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3340635763
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.4042664352
Short name T932
Test name
Test status
Simulation time 26691069733 ps
CPU time 7.53 seconds
Started May 19 01:57:54 PM PDT 24
Finished May 19 01:58:02 PM PDT 24
Peak memory 205084 kb
Host smart-d5c8292e-5848-4cd0-89a5-765015e6c2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042664352 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.4042664352
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.313503345
Short name T119
Test name
Test status
Simulation time 5423609332 ps
CPU time 21.45 seconds
Started May 19 01:57:52 PM PDT 24
Finished May 19 01:58:14 PM PDT 24
Peak memory 205332 kb
Host smart-cd7ceaed-f1b7-4433-8f5e-c69723c0c49f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313503345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.313503345
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2634392568
Short name T284
Test name
Test status
Simulation time 2235264070 ps
CPU time 10.55 seconds
Started May 19 01:58:05 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 207144 kb
Host smart-01766e78-927d-4b62-9cbd-3bdd202a294a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634392568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2634392568
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1897335634
Short name T496
Test name
Test status
Simulation time 54921960074 ps
CPU time 127.87 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 1669860 kb
Host smart-022e01cb-02fa-46be-8cb2-ee8e3d0e9efa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897335634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1897335634
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2994476912
Short name T805
Test name
Test status
Simulation time 17227028597 ps
CPU time 2944.51 seconds
Started May 19 01:58:10 PM PDT 24
Finished May 19 02:47:16 PM PDT 24
Peak memory 4220692 kb
Host smart-781a5896-0517-4ed8-a29d-4a6cb6a05b9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994476912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2994476912
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1397009278
Short name T1047
Test name
Test status
Simulation time 1261865642 ps
CPU time 7.41 seconds
Started May 19 01:57:53 PM PDT 24
Finished May 19 01:58:02 PM PDT 24
Peak memory 219720 kb
Host smart-99900832-42e6-4e3d-84c7-c721a78e1cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397009278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1397009278
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1146230062
Short name T574
Test name
Test status
Simulation time 38096194 ps
CPU time 0.62 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 204536 kb
Host smart-9ba37906-6546-4983-965f-20462fc7bb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146230062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1146230062
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.653225250
Short name T724
Test name
Test status
Simulation time 905641151 ps
CPU time 3.49 seconds
Started May 19 01:58:15 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 213316 kb
Host smart-8da69bc7-1ef6-4bfd-b2f6-47c7556410b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653225250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.653225250
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1818078828
Short name T162
Test name
Test status
Simulation time 170191246 ps
CPU time 8.53 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 232196 kb
Host smart-f65beadc-786d-4072-9b81-673e39d46a1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818078828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1818078828
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.26174616
Short name T391
Test name
Test status
Simulation time 2602831067 ps
CPU time 204.84 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 814968 kb
Host smart-2ef61063-dff6-48b1-8d93-a06134c23a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26174616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.26174616
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3064670428
Short name T514
Test name
Test status
Simulation time 2734346588 ps
CPU time 109.58 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 887100 kb
Host smart-b339042a-743e-4fb3-97aa-ea8cb0b500ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064670428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3064670428
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2270752351
Short name T956
Test name
Test status
Simulation time 123052345 ps
CPU time 0.96 seconds
Started May 19 01:57:57 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 204780 kb
Host smart-86230c26-5d32-4e50-b650-e3c9b91e22f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270752351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2270752351
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2822394158
Short name T1331
Test name
Test status
Simulation time 1157296882 ps
CPU time 9.85 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 204932 kb
Host smart-f020457f-54f6-44f8-992e-c1f4a2baff36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822394158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2822394158
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1226482013
Short name T661
Test name
Test status
Simulation time 2770493302 ps
CPU time 183.16 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 866272 kb
Host smart-d20a5582-64f2-4781-adfc-d3645f5b853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226482013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1226482013
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2659628762
Short name T467
Test name
Test status
Simulation time 603583286 ps
CPU time 6.36 seconds
Started May 19 01:58:09 PM PDT 24
Finished May 19 01:58:17 PM PDT 24
Peak memory 204864 kb
Host smart-a46052a2-fe64-4168-9c21-ba3dd6d9d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659628762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2659628762
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.1010930289
Short name T1251
Test name
Test status
Simulation time 2117231755 ps
CPU time 40.41 seconds
Started May 19 01:58:12 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 499872 kb
Host smart-73f73579-1b16-41bc-9435-c758462ea433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010930289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.1010930289
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1884921257
Short name T130
Test name
Test status
Simulation time 52087560 ps
CPU time 0.65 seconds
Started May 19 01:57:55 PM PDT 24
Finished May 19 01:57:56 PM PDT 24
Peak memory 204700 kb
Host smart-22077136-bd1a-4d16-8de5-e04d34394c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884921257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1884921257
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1237266957
Short name T62
Test name
Test status
Simulation time 204181867 ps
CPU time 1.54 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 213252 kb
Host smart-9335b3e2-46ce-4456-b5c1-8793f1113ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237266957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1237266957
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3713219481
Short name T731
Test name
Test status
Simulation time 7114708068 ps
CPU time 29.89 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 286072 kb
Host smart-a4a23c0e-6b63-45e8-9d7b-60ec54d8d771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713219481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3713219481
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.133928683
Short name T984
Test name
Test status
Simulation time 15787468460 ps
CPU time 355.18 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 1320184 kb
Host smart-67ab9c76-fbc9-4f86-9f4e-f283fd252d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133928683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.133928683
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2067597263
Short name T1252
Test name
Test status
Simulation time 458690404 ps
CPU time 2.63 seconds
Started May 19 01:58:08 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 205040 kb
Host smart-c2a12c0b-b30b-465c-8df9-a5e7e6157a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067597263 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2067597263
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1516339439
Short name T501
Test name
Test status
Simulation time 10050027514 ps
CPU time 30.04 seconds
Started May 19 01:58:06 PM PDT 24
Finished May 19 01:58:38 PM PDT 24
Peak memory 315716 kb
Host smart-b0eb18d0-101f-41cf-937c-71793578f930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516339439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1516339439
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3916311036
Short name T551
Test name
Test status
Simulation time 10545082658 ps
CPU time 11 seconds
Started May 19 01:57:58 PM PDT 24
Finished May 19 01:58:10 PM PDT 24
Peak memory 262716 kb
Host smart-477db4b0-135b-49b8-85ae-6936a8880db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916311036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3916311036
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3689743389
Short name T1208
Test name
Test status
Simulation time 662875640 ps
CPU time 2.29 seconds
Started May 19 01:58:15 PM PDT 24
Finished May 19 01:58:18 PM PDT 24
Peak memory 205264 kb
Host smart-9f4492a2-3cf8-47b2-a4c7-9f2d3212fdef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689743389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3689743389
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2609052749
Short name T537
Test name
Test status
Simulation time 4386218325 ps
CPU time 5.58 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:10 PM PDT 24
Peak memory 213740 kb
Host smart-1234910f-1c6b-4c0f-8ede-9156b940bbd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609052749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2609052749
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1648679983
Short name T438
Test name
Test status
Simulation time 4362909766 ps
CPU time 6.07 seconds
Started May 19 01:58:12 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 204972 kb
Host smart-86dc8144-1436-40d7-8902-0dd1100c080a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648679983 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1648679983
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1915494454
Short name T640
Test name
Test status
Simulation time 1148794512 ps
CPU time 14.26 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:58:34 PM PDT 24
Peak memory 204928 kb
Host smart-513ff661-6524-43a7-bc38-c665497f85dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915494454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1915494454
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.973961896
Short name T1034
Test name
Test status
Simulation time 1600317178 ps
CPU time 66.81 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 210192 kb
Host smart-a38c86f7-ae12-406a-8739-6c97567b3b08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973961896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.973961896
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1818155964
Short name T446
Test name
Test status
Simulation time 17606621863 ps
CPU time 37.01 seconds
Started May 19 01:58:10 PM PDT 24
Finished May 19 01:58:48 PM PDT 24
Peak memory 204956 kb
Host smart-58811048-d478-4404-b352-19fb0118ba08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818155964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1818155964
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.4229186067
Short name T1205
Test name
Test status
Simulation time 5029645012 ps
CPU time 41.42 seconds
Started May 19 01:58:16 PM PDT 24
Finished May 19 01:58:58 PM PDT 24
Peak memory 695064 kb
Host smart-c9dc5606-126c-4c5e-868d-eafddd36c490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229186067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.4229186067
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3348804720
Short name T1240
Test name
Test status
Simulation time 2877330263 ps
CPU time 6.81 seconds
Started May 19 01:57:56 PM PDT 24
Finished May 19 01:58:04 PM PDT 24
Peak memory 211832 kb
Host smart-cd63f869-38f3-48db-b2f1-a703f3ca063f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348804720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3348804720
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.687585343
Short name T1221
Test name
Test status
Simulation time 57033188 ps
CPU time 0.63 seconds
Started May 19 01:58:13 PM PDT 24
Finished May 19 01:58:15 PM PDT 24
Peak memory 204648 kb
Host smart-de7c6278-3022-4c65-a366-c433f8cbe9fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687585343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.687585343
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1398430015
Short name T730
Test name
Test status
Simulation time 64463577 ps
CPU time 1.41 seconds
Started May 19 01:58:14 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 213280 kb
Host smart-acbc4a81-e61d-4a2f-9458-80f74bb89655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398430015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1398430015
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2820445551
Short name T1187
Test name
Test status
Simulation time 1430300825 ps
CPU time 18.19 seconds
Started May 19 01:58:09 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 266152 kb
Host smart-3e97135c-df92-40e4-9cfe-31a9fc8461fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820445551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2820445551
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3410951331
Short name T1134
Test name
Test status
Simulation time 2088449193 ps
CPU time 75.54 seconds
Started May 19 01:58:12 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 712548 kb
Host smart-c67c1e58-3fbd-4db4-9f31-5686a01385ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410951331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3410951331
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.446044341
Short name T1249
Test name
Test status
Simulation time 3103672462 ps
CPU time 33.08 seconds
Started May 19 01:58:14 PM PDT 24
Finished May 19 01:58:48 PM PDT 24
Peak memory 378468 kb
Host smart-a94d4e8d-360d-435e-a9a8-33896e31bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446044341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.446044341
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2407478210
Short name T663
Test name
Test status
Simulation time 73749674 ps
CPU time 0.89 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:04 PM PDT 24
Peak memory 204780 kb
Host smart-fa13ace0-6ad5-4e6f-8411-aa238ffa39e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407478210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2407478210
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.4077934935
Short name T441
Test name
Test status
Simulation time 585818064 ps
CPU time 3.4 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:07 PM PDT 24
Peak memory 204972 kb
Host smart-7d001fe4-7eb5-4bb3-8f0d-506e48a71627
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077934935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.4077934935
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.4068670414
Short name T105
Test name
Test status
Simulation time 2942016318 ps
CPU time 68.63 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 869216 kb
Host smart-8155765c-21e9-4979-bfe4-eff6b63000fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068670414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.4068670414
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1336623152
Short name T869
Test name
Test status
Simulation time 945244417 ps
CPU time 7.8 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:58:26 PM PDT 24
Peak memory 204980 kb
Host smart-f867a67d-6366-4160-9f6e-6e1fdce78e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336623152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1336623152
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.1473872490
Short name T331
Test name
Test status
Simulation time 55305732 ps
CPU time 0.65 seconds
Started May 19 01:58:11 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 204704 kb
Host smart-fb197f87-feb6-4e9b-b459-8a747570104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473872490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1473872490
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3603115812
Short name T39
Test name
Test status
Simulation time 50651544572 ps
CPU time 373.27 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 02:04:19 PM PDT 24
Peak memory 299000 kb
Host smart-5bada17a-c731-4c7b-ad12-673db525e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603115812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3603115812
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.914390896
Short name T403
Test name
Test status
Simulation time 1830434716 ps
CPU time 29.08 seconds
Started May 19 01:58:12 PM PDT 24
Finished May 19 01:58:42 PM PDT 24
Peak memory 318404 kb
Host smart-4b2ac0a0-387a-4f70-8602-313a13a8b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914390896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.914390896
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3000797066
Short name T375
Test name
Test status
Simulation time 774566628 ps
CPU time 35.86 seconds
Started May 19 01:58:13 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 213168 kb
Host smart-12cc356c-e963-424e-ac3c-df11086c587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000797066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3000797066
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3252928066
Short name T940
Test name
Test status
Simulation time 4051307737 ps
CPU time 4.95 seconds
Started May 19 01:58:17 PM PDT 24
Finished May 19 01:58:23 PM PDT 24
Peak memory 213296 kb
Host smart-959dde3b-95d6-42ff-a3ab-3ebe87042264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252928066 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3252928066
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3366340046
Short name T576
Test name
Test status
Simulation time 10140289281 ps
CPU time 12.77 seconds
Started May 19 01:58:02 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 261864 kb
Host smart-ed730221-6cfa-431b-ae2b-bf01fb9ce67c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366340046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3366340046
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1761139787
Short name T1338
Test name
Test status
Simulation time 10175023024 ps
CPU time 29.42 seconds
Started May 19 01:58:10 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 326908 kb
Host smart-7e54f28c-b198-413f-a71f-6125fc82bbf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761139787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1761139787
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3656392989
Short name T463
Test name
Test status
Simulation time 5511998339 ps
CPU time 2.54 seconds
Started May 19 01:58:01 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 205116 kb
Host smart-0f0fa972-0cc5-4bf4-b2b6-de76d46c0e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656392989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3656392989
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2902495661
Short name T330
Test name
Test status
Simulation time 2767630605 ps
CPU time 4.08 seconds
Started May 19 01:58:14 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 205076 kb
Host smart-919e4f19-1850-4edb-a2a3-07b06db94449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902495661 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2902495661
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1630563923
Short name T922
Test name
Test status
Simulation time 16714297634 ps
CPU time 39.03 seconds
Started May 19 01:58:04 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 998556 kb
Host smart-f22f9fdc-d42b-484a-96a1-cd0efd84f6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630563923 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1630563923
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1454218
Short name T379
Test name
Test status
Simulation time 13508519566 ps
CPU time 41.26 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 01:59:01 PM PDT 24
Peak memory 205008 kb
Host smart-64721019-7c12-408f-b952-198fa5c4fd06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_targe
t_smoke.1454218
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.622499658
Short name T1302
Test name
Test status
Simulation time 3529118576 ps
CPU time 16.11 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:21 PM PDT 24
Peak memory 212032 kb
Host smart-dcd95f26-8f61-4662-a707-fceae507d00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622499658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.622499658
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3810953158
Short name T1162
Test name
Test status
Simulation time 45540022629 ps
CPU time 297.12 seconds
Started May 19 01:58:08 PM PDT 24
Finished May 19 02:03:08 PM PDT 24
Peak memory 3251180 kb
Host smart-5459d259-2957-46f3-a1ee-860c18ddeb10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810953158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3810953158
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2179071608
Short name T842
Test name
Test status
Simulation time 19530569914 ps
CPU time 179.35 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 02:01:04 PM PDT 24
Peak memory 1372564 kb
Host smart-f7adad0d-c111-44f2-8d58-81103a1913af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179071608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2179071608
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.551485174
Short name T392
Test name
Test status
Simulation time 2515442129 ps
CPU time 6.99 seconds
Started May 19 01:58:03 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 221340 kb
Host smart-e70300d4-0a18-4f0d-9289-977cfd8d65b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551485174 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.551485174
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2901787627
Short name T364
Test name
Test status
Simulation time 37050640 ps
CPU time 0.65 seconds
Started May 19 01:58:09 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 204648 kb
Host smart-85af5b73-5a21-4da9-b41a-d5ad683fb8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901787627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2901787627
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1447159767
Short name T40
Test name
Test status
Simulation time 742221834 ps
CPU time 3.82 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 234800 kb
Host smart-87a255a8-5db5-471c-b3af-6a6bc51bec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447159767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1447159767
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3232805006
Short name T410
Test name
Test status
Simulation time 1437969483 ps
CPU time 8.24 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 283988 kb
Host smart-7a8a1584-e4f6-4421-87e9-c1f033eea621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232805006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3232805006
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2463826196
Short name T1046
Test name
Test status
Simulation time 1706222946 ps
CPU time 90.59 seconds
Started May 19 01:58:13 PM PDT 24
Finished May 19 01:59:44 PM PDT 24
Peak memory 227348 kb
Host smart-0c7d4590-daba-4775-a5b5-179ef327e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463826196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2463826196
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.342655450
Short name T1104
Test name
Test status
Simulation time 1250492083 ps
CPU time 84.78 seconds
Started May 19 01:58:06 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 503320 kb
Host smart-0d803608-da3f-43c9-b84d-a2f82c578385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342655450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.342655450
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.485100742
Short name T1261
Test name
Test status
Simulation time 435247530 ps
CPU time 1.05 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 204952 kb
Host smart-8fcb6e0d-78ea-4ae2-a987-f3b28a0a991f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485100742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.485100742
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.856344980
Short name T686
Test name
Test status
Simulation time 271858614 ps
CPU time 3.79 seconds
Started May 19 01:58:09 PM PDT 24
Finished May 19 01:58:15 PM PDT 24
Peak memory 228440 kb
Host smart-1e8e5655-43cb-4819-83b7-2e4738a10049
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856344980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
856344980
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1765348790
Short name T259
Test name
Test status
Simulation time 22841542826 ps
CPU time 428.54 seconds
Started May 19 01:58:06 PM PDT 24
Finished May 19 02:05:16 PM PDT 24
Peak memory 1485664 kb
Host smart-6ff0dbcc-7b03-467d-ba8e-92c05a0d4efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765348790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1765348790
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1938821318
Short name T390
Test name
Test status
Simulation time 197627544 ps
CPU time 2.84 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 204956 kb
Host smart-3ca119d0-3956-44cc-b38e-93807298115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938821318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1938821318
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1686458189
Short name T1004
Test name
Test status
Simulation time 8746317577 ps
CPU time 27.02 seconds
Started May 19 01:58:13 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 367024 kb
Host smart-cdd9c76d-59df-4e01-82d4-35778ece7754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686458189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1686458189
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1837654180
Short name T135
Test name
Test status
Simulation time 27649999 ps
CPU time 0.67 seconds
Started May 19 01:58:14 PM PDT 24
Finished May 19 01:58:16 PM PDT 24
Peak memory 204672 kb
Host smart-5291b571-8e0b-4547-b354-960109f905e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837654180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1837654180
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2467221714
Short name T578
Test name
Test status
Simulation time 3309118823 ps
CPU time 20.5 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 381524 kb
Host smart-26bd3983-e326-4f33-afcf-2947e2aea007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467221714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2467221714
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2771640019
Short name T970
Test name
Test status
Simulation time 1454445890 ps
CPU time 29.74 seconds
Started May 19 01:58:09 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 335680 kb
Host smart-45798703-d0ab-4a8f-a5ef-7df361898631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771640019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2771640019
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3253725783
Short name T60
Test name
Test status
Simulation time 49783994004 ps
CPU time 1671.37 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 2698388 kb
Host smart-962ba008-ee99-41ff-99af-8dc4cbf2d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253725783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3253725783
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2335226514
Short name T839
Test name
Test status
Simulation time 595089871 ps
CPU time 11.12 seconds
Started May 19 01:58:14 PM PDT 24
Finished May 19 01:58:26 PM PDT 24
Peak memory 213192 kb
Host smart-56e811aa-ed32-4839-bbf2-3554f1a1f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335226514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2335226514
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2654615147
Short name T1279
Test name
Test status
Simulation time 2305656403 ps
CPU time 3.15 seconds
Started May 19 01:58:08 PM PDT 24
Finished May 19 01:58:14 PM PDT 24
Peak memory 205072 kb
Host smart-cb6cdee1-8c7a-4a1e-9be6-3fb632345771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654615147 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2654615147
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.4056420964
Short name T432
Test name
Test status
Simulation time 10125521258 ps
CPU time 34.15 seconds
Started May 19 01:58:08 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 310064 kb
Host smart-6669bfbe-39b6-471d-af6b-df9fbc552f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056420964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.4056420964
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.372496970
Short name T1258
Test name
Test status
Simulation time 10375800226 ps
CPU time 14.47 seconds
Started May 19 01:58:08 PM PDT 24
Finished May 19 01:58:24 PM PDT 24
Peak memory 287412 kb
Host smart-1fcf618d-6bb5-4b70-be54-c91d2fe730ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372496970 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.372496970
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.412482146
Short name T1192
Test name
Test status
Simulation time 487431635 ps
CPU time 2.81 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 205028 kb
Host smart-9ce98a2b-6acc-4957-9e03-8367972856b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412482146 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.412482146
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2913929940
Short name T285
Test name
Test status
Simulation time 3568766263 ps
CPU time 4.85 seconds
Started May 19 01:58:15 PM PDT 24
Finished May 19 01:58:20 PM PDT 24
Peak memory 204988 kb
Host smart-8c9ca677-534d-45db-87d5-7e410984d5c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913929940 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2913929940
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.821908433
Short name T149
Test name
Test status
Simulation time 6743745832 ps
CPU time 8.96 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:18 PM PDT 24
Peak memory 205080 kb
Host smart-9cb1528c-cd02-4a39-86de-d9c371a4f34a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821908433 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.821908433
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.291046462
Short name T457
Test name
Test status
Simulation time 1643568898 ps
CPU time 12.56 seconds
Started May 19 01:58:16 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 204660 kb
Host smart-578e1da1-eb02-4316-95eb-5c32d41be9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291046462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.291046462
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.444374022
Short name T1089
Test name
Test status
Simulation time 34737565367 ps
CPU time 32.37 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 230680 kb
Host smart-7d026432-f973-45c0-a3be-838211f5790f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444374022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.444374022
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.2381559088
Short name T698
Test name
Test status
Simulation time 49944232776 ps
CPU time 424.85 seconds
Started May 19 01:58:16 PM PDT 24
Finished May 19 02:05:22 PM PDT 24
Peak memory 3831972 kb
Host smart-67dab5a8-557b-4fa5-b77d-87dd566ceb0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381559088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.2381559088
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1943149268
Short name T1220
Test name
Test status
Simulation time 18744197743 ps
CPU time 77.44 seconds
Started May 19 01:58:10 PM PDT 24
Finished May 19 01:59:29 PM PDT 24
Peak memory 905396 kb
Host smart-1ec5d615-63de-4920-800f-7e1a794239cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943149268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1943149268
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1320643373
Short name T595
Test name
Test status
Simulation time 2817373705 ps
CPU time 8.07 seconds
Started May 19 01:58:07 PM PDT 24
Finished May 19 01:58:17 PM PDT 24
Peak memory 221356 kb
Host smart-70caa9cb-409d-49c5-8a30-fd5b2faedcf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320643373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1320643373
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.615247659
Short name T582
Test name
Test status
Simulation time 18780117 ps
CPU time 0.7 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 01:58:21 PM PDT 24
Peak memory 204620 kb
Host smart-1d5313b0-b3d0-4a1c-b800-cddb7dfcd5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615247659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.615247659
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.343823956
Short name T50
Test name
Test status
Simulation time 219032434 ps
CPU time 1.88 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:58:20 PM PDT 24
Peak memory 213312 kb
Host smart-7ba5491a-362d-43a1-9d22-ce0161ff8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343823956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.343823956
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.827418392
Short name T1039
Test name
Test status
Simulation time 250109889 ps
CPU time 5.02 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:58:23 PM PDT 24
Peak memory 253736 kb
Host smart-b546e22d-68a2-4750-84e3-c8a3756e315c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827418392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.827418392
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.4245166943
Short name T456
Test name
Test status
Simulation time 3732133163 ps
CPU time 66.67 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 652524 kb
Host smart-bb80efc4-a244-4dfa-8102-431e1f211bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245166943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.4245166943
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1375333941
Short name T414
Test name
Test status
Simulation time 6582999664 ps
CPU time 85.49 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:59:44 PM PDT 24
Peak memory 749324 kb
Host smart-48c8cf7d-9e55-4d6d-b5fc-9d8005a7c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375333941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1375333941
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3515874168
Short name T461
Test name
Test status
Simulation time 701182874 ps
CPU time 1.07 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 01:58:21 PM PDT 24
Peak memory 204776 kb
Host smart-f5f83505-b2a9-4657-8aae-df96b48ff2bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515874168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3515874168
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.4273307724
Short name T311
Test name
Test status
Simulation time 1026196085 ps
CPU time 4.53 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 01:58:28 PM PDT 24
Peak memory 236760 kb
Host smart-c7595fa4-27e5-439e-9527-6aee75c30b2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273307724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.4273307724
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3384523305
Short name T345
Test name
Test status
Simulation time 14419052592 ps
CPU time 125.94 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 02:00:31 PM PDT 24
Peak memory 1175348 kb
Host smart-4f65df84-fc4b-40d6-a54d-3b4ef61aadef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384523305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3384523305
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.333248768
Short name T753
Test name
Test status
Simulation time 414402817 ps
CPU time 16.91 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:58:46 PM PDT 24
Peak memory 204996 kb
Host smart-c26e472c-6c7b-4ef1-99b7-9c14f5f82c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333248768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.333248768
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.879634831
Short name T1257
Test name
Test status
Simulation time 1448800597 ps
CPU time 30.25 seconds
Started May 19 01:58:25 PM PDT 24
Finished May 19 01:58:58 PM PDT 24
Peak memory 345424 kb
Host smart-a8d7af95-1a80-4328-8a5e-6a2738ef64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879634831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.879634831
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.553565873
Short name T1003
Test name
Test status
Simulation time 57232483 ps
CPU time 0.68 seconds
Started May 19 01:58:12 PM PDT 24
Finished May 19 01:58:14 PM PDT 24
Peak memory 204712 kb
Host smart-3d2d3009-2d6e-48bc-9ca5-f9978f93df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553565873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.553565873
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3236000206
Short name T421
Test name
Test status
Simulation time 5052533566 ps
CPU time 298.14 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 02:03:28 PM PDT 24
Peak memory 622440 kb
Host smart-c1213485-bee9-4869-97b6-6f16d9db3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236000206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3236000206
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.459395345
Short name T857
Test name
Test status
Simulation time 1652185181 ps
CPU time 31.85 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 328304 kb
Host smart-df3b9913-9586-4a03-8931-4e29c04c0ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459395345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.459395345
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2669272288
Short name T1045
Test name
Test status
Simulation time 20981693986 ps
CPU time 148.51 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 02:00:47 PM PDT 24
Peak memory 1226440 kb
Host smart-37bc05bc-d8c2-4cd4-8644-0a195589b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669272288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2669272288
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1251425887
Short name T645
Test name
Test status
Simulation time 1060091162 ps
CPU time 7.71 seconds
Started May 19 01:58:16 PM PDT 24
Finished May 19 01:58:25 PM PDT 24
Peak memory 213136 kb
Host smart-d887d1a8-6958-436c-9ea1-b3c2bea7ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251425887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1251425887
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1012214154
Short name T611
Test name
Test status
Simulation time 3892155655 ps
CPU time 4.58 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:31 PM PDT 24
Peak memory 213292 kb
Host smart-93eb94b9-3527-47e9-bebd-fb680ae6c645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012214154 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1012214154
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2912250010
Short name T1019
Test name
Test status
Simulation time 10214239306 ps
CPU time 16.22 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 257812 kb
Host smart-672dd8b1-72ba-4828-b0ef-2308ceedb7ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912250010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2912250010
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3379940907
Short name T530
Test name
Test status
Simulation time 10341902738 ps
CPU time 7.55 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 01:58:36 PM PDT 24
Peak memory 239800 kb
Host smart-7996754e-7f82-4b0e-a05c-8f7dae972810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379940907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3379940907
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1701926228
Short name T505
Test name
Test status
Simulation time 381611814 ps
CPU time 2.75 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:58:31 PM PDT 24
Peak memory 204908 kb
Host smart-9ee74807-6c5f-4ac9-8d1e-3536921c6b84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701926228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1701926228
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.125562491
Short name T377
Test name
Test status
Simulation time 1053557661 ps
CPU time 5.52 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 209860 kb
Host smart-cfc48cf1-5185-4cbd-bb53-b23a24c1a6e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125562491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.125562491
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1535749154
Short name T513
Test name
Test status
Simulation time 30108674272 ps
CPU time 30.99 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:59:02 PM PDT 24
Peak memory 759808 kb
Host smart-c3df3cbe-d8d6-4897-9adb-1691f3752ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535749154 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1535749154
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2539169445
Short name T988
Test name
Test status
Simulation time 1999274527 ps
CPU time 16.84 seconds
Started May 19 01:58:25 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 204916 kb
Host smart-229460b1-21c9-4cd7-99b0-63d58433ad4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539169445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2539169445
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1846590428
Short name T494
Test name
Test status
Simulation time 7399701256 ps
CPU time 57.72 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 01:59:21 PM PDT 24
Peak memory 208552 kb
Host smart-4271693c-3b11-4203-830c-346ee9b6304a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846590428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1846590428
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.713767231
Short name T18
Test name
Test status
Simulation time 30715780967 ps
CPU time 38.1 seconds
Started May 19 01:58:17 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 723912 kb
Host smart-7b81aff6-0dfe-4dbf-9b59-3f6d1bd9c218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713767231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.713767231
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3527306039
Short name T957
Test name
Test status
Simulation time 6782916668 ps
CPU time 15.12 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 356024 kb
Host smart-b03acac7-2e79-4ff4-afd8-a49aa3279194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527306039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3527306039
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2950517437
Short name T1017
Test name
Test status
Simulation time 4261290864 ps
CPU time 6.29 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:58:35 PM PDT 24
Peak memory 220176 kb
Host smart-2bceffa4-bf85-44a6-a1cd-9ac7c74ccfc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950517437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2950517437
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.391336933
Short name T763
Test name
Test status
Simulation time 49049493 ps
CPU time 0.63 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 01:58:30 PM PDT 24
Peak memory 204564 kb
Host smart-abf293e6-c962-44f9-8727-eee869496a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391336933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.391336933
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.937058930
Short name T383
Test name
Test status
Simulation time 149050539 ps
CPU time 1.55 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 01:58:31 PM PDT 24
Peak memory 213232 kb
Host smart-4c303862-3dc5-4908-8042-7337dff6dcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937058930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.937058930
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1955059260
Short name T321
Test name
Test status
Simulation time 382504710 ps
CPU time 9.14 seconds
Started May 19 01:58:28 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 240208 kb
Host smart-850b3aa4-0de2-49d2-b05a-19b4b7a85924
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955059260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1955059260
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1308751611
Short name T711
Test name
Test status
Simulation time 5249825843 ps
CPU time 73.35 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:59:42 PM PDT 24
Peak memory 703312 kb
Host smart-aa70151f-870d-4f72-a927-0165821bbed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308751611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1308751611
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1877307959
Short name T156
Test name
Test status
Simulation time 4122456260 ps
CPU time 66.33 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:59:38 PM PDT 24
Peak memory 647668 kb
Host smart-bce0c647-2adb-40ad-8912-4f9cbec8747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877307959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1877307959
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2816013772
Short name T652
Test name
Test status
Simulation time 256350303 ps
CPU time 0.97 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 01:58:30 PM PDT 24
Peak memory 204784 kb
Host smart-c01bb774-c9aa-4b82-acf5-3d123fa194a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816013772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2816013772
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1234605518
Short name T3
Test name
Test status
Simulation time 145264119 ps
CPU time 3.54 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:36 PM PDT 24
Peak memory 204968 kb
Host smart-99567c38-0cf5-4fe1-ace5-83d92015fa72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234605518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1234605518
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3954663734
Short name T882
Test name
Test status
Simulation time 3668405611 ps
CPU time 114.45 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 02:00:23 PM PDT 24
Peak memory 1090604 kb
Host smart-94a622c6-a58d-4e53-8970-575c105ee551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954663734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3954663734
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3535766907
Short name T1128
Test name
Test status
Simulation time 235136459 ps
CPU time 3.61 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:58:32 PM PDT 24
Peak memory 204852 kb
Host smart-6d9828eb-cb18-4ba8-94ce-d092ee839f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535766907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3535766907
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.177553100
Short name T674
Test name
Test status
Simulation time 1368633581 ps
CPU time 20.34 seconds
Started May 19 01:58:20 PM PDT 24
Finished May 19 01:58:42 PM PDT 24
Peak memory 331984 kb
Host smart-11e366b9-82d0-4175-a256-acde7aaabf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177553100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.177553100
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3955753926
Short name T477
Test name
Test status
Simulation time 78817408 ps
CPU time 0.66 seconds
Started May 19 01:58:25 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 204552 kb
Host smart-c52a7774-81eb-4e26-bce0-20d58a99cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955753926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3955753926
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1583518141
Short name T398
Test name
Test status
Simulation time 5312813457 ps
CPU time 53.16 seconds
Started May 19 01:58:19 PM PDT 24
Finished May 19 01:59:14 PM PDT 24
Peak memory 229516 kb
Host smart-9e52f980-3704-4f4f-8cfa-cf5e186ca5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583518141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1583518141
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.641429080
Short name T450
Test name
Test status
Simulation time 3111676343 ps
CPU time 70.76 seconds
Started May 19 01:58:27 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 318684 kb
Host smart-fc4cda3c-aaaf-4f9d-8e5c-11aac1c9a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641429080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.641429080
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.620722802
Short name T1254
Test name
Test status
Simulation time 17812821514 ps
CPU time 1241.47 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 02:19:06 PM PDT 24
Peak memory 3140708 kb
Host smart-5b4f9358-3b00-409f-a161-6b89ebf096a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620722802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.620722802
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2983528789
Short name T339
Test name
Test status
Simulation time 646493856 ps
CPU time 29.52 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 01:58:58 PM PDT 24
Peak memory 213108 kb
Host smart-a97817c9-2538-460b-b6ee-18412f405425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983528789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2983528789
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4180293361
Short name T1029
Test name
Test status
Simulation time 1359099666 ps
CPU time 6.51 seconds
Started May 19 01:58:20 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 213232 kb
Host smart-79264f8f-66a3-4af9-9a3b-248e1bf1bad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180293361 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4180293361
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.848472416
Short name T183
Test name
Test status
Simulation time 10637619195 ps
CPU time 7.31 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 234084 kb
Host smart-146c857e-0007-49b5-986f-9a455364b8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848472416 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.848472416
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4254761406
Short name T1213
Test name
Test status
Simulation time 10079697722 ps
CPU time 79.84 seconds
Started May 19 01:58:20 PM PDT 24
Finished May 19 01:59:42 PM PDT 24
Peak memory 539252 kb
Host smart-fb02fa4a-6b98-4504-b19b-230881baf927
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254761406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4254761406
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.891428162
Short name T977
Test name
Test status
Simulation time 539119836 ps
CPU time 3.11 seconds
Started May 19 01:58:25 PM PDT 24
Finished May 19 01:58:31 PM PDT 24
Peak memory 204984 kb
Host smart-78880523-9d69-40be-a6fe-453c2f51a388
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891428162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.891428162
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1325456808
Short name T20
Test name
Test status
Simulation time 912780360 ps
CPU time 5.03 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:58:36 PM PDT 24
Peak memory 209488 kb
Host smart-cb503554-6b22-4487-9399-bdf04c0ae928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325456808 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1325456808
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1162455838
Short name T245
Test name
Test status
Simulation time 11530954529 ps
CPU time 10.81 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:58:42 PM PDT 24
Peak memory 305868 kb
Host smart-6a023b56-1d5d-40d6-ba24-c513957aa8dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162455838 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1162455838
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1967082715
Short name T1325
Test name
Test status
Simulation time 1317354312 ps
CPU time 43.61 seconds
Started May 19 01:58:18 PM PDT 24
Finished May 19 01:59:03 PM PDT 24
Peak memory 204916 kb
Host smart-ecd8f4f1-1c73-4713-a431-a43bc8646547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967082715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1967082715
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2697277229
Short name T493
Test name
Test status
Simulation time 566329821 ps
CPU time 4.77 seconds
Started May 19 01:58:20 PM PDT 24
Finished May 19 01:58:26 PM PDT 24
Peak memory 204964 kb
Host smart-e658eeb9-76dc-4a07-b25e-23baca011582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697277229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2697277229
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2039293100
Short name T244
Test name
Test status
Simulation time 32472991679 ps
CPU time 302.46 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 02:03:27 PM PDT 24
Peak memory 3231284 kb
Host smart-b427abe0-26cd-473b-8a9b-4358c67df3fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039293100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2039293100
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.2808498319
Short name T1181
Test name
Test status
Simulation time 7685902743 ps
CPU time 99.06 seconds
Started May 19 01:58:26 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 578664 kb
Host smart-911be8d2-24cd-4246-8fd8-adb78cddc610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808498319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.2808498319
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2589121577
Short name T952
Test name
Test status
Simulation time 3344014633 ps
CPU time 7.49 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 217316 kb
Host smart-e2f8f958-c1ad-4c9a-97f1-01ba4920dcea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589121577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2589121577
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2034049704
Short name T1341
Test name
Test status
Simulation time 15241586 ps
CPU time 0.63 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:58:48 PM PDT 24
Peak memory 204600 kb
Host smart-d3fbf0d7-26a4-46ea-8299-50852fe294a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034049704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2034049704
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.45319924
Short name T671
Test name
Test status
Simulation time 365330096 ps
CPU time 5.86 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:32 PM PDT 24
Peak memory 232852 kb
Host smart-ba7452b2-b0c5-4d78-ae46-472775b6e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45319924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.45319924
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1942586304
Short name T280
Test name
Test status
Simulation time 1164871435 ps
CPU time 6.34 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 277280 kb
Host smart-b98916fb-190d-44f3-a9e5-fe09ebac61b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942586304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1942586304
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3811364993
Short name T188
Test name
Test status
Simulation time 2603821071 ps
CPU time 207.29 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 02:01:53 PM PDT 24
Peak memory 814648 kb
Host smart-00600e12-752a-48d8-9f46-99ad30f5ed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811364993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3811364993
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3689199304
Short name T834
Test name
Test status
Simulation time 5747103494 ps
CPU time 42.61 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:59:10 PM PDT 24
Peak memory 507668 kb
Host smart-8796f9c0-d339-4ba4-b82c-6dcc533933ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689199304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3689199304
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2402609579
Short name T942
Test name
Test status
Simulation time 426144419 ps
CPU time 1.17 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 01:58:26 PM PDT 24
Peak memory 204956 kb
Host smart-4bfa5117-bde9-4316-83a5-fbdea8b84e4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402609579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2402609579
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3857655696
Short name T821
Test name
Test status
Simulation time 361682837 ps
CPU time 10.59 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:58:37 PM PDT 24
Peak memory 239896 kb
Host smart-1b983f8f-a3db-4561-a269-d45b9575b566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857655696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3857655696
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2045666496
Short name T1333
Test name
Test status
Simulation time 4522065057 ps
CPU time 74.63 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:00:08 PM PDT 24
Peak memory 993608 kb
Host smart-fb0e969d-9fc7-4353-b3d7-5678418ed0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045666496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2045666496
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2276977312
Short name T46
Test name
Test status
Simulation time 263276365 ps
CPU time 10.46 seconds
Started May 19 01:58:25 PM PDT 24
Finished May 19 01:58:38 PM PDT 24
Peak memory 204920 kb
Host smart-c57fc3d6-1ed1-4186-8000-3a33b8901181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276977312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2276977312
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3047229948
Short name T1201
Test name
Test status
Simulation time 8708809861 ps
CPU time 105.88 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 02:00:11 PM PDT 24
Peak memory 390184 kb
Host smart-6b019aa5-dde7-4687-ac78-cd9916410285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047229948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3047229948
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1283240159
Short name T924
Test name
Test status
Simulation time 91837674 ps
CPU time 0.68 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 204704 kb
Host smart-0119401b-c21c-412d-96a8-3e2663a6debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283240159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1283240159
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2511078294
Short name T558
Test name
Test status
Simulation time 6971010856 ps
CPU time 79.35 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:59:52 PM PDT 24
Peak memory 362324 kb
Host smart-d36af67e-ce93-41db-800e-4189ecd861f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511078294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2511078294
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2230611883
Short name T166
Test name
Test status
Simulation time 11242426368 ps
CPU time 109.84 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 02:00:40 PM PDT 24
Peak memory 330436 kb
Host smart-b842321c-9616-44dc-8709-eeb34501b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230611883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2230611883
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.183554402
Short name T226
Test name
Test status
Simulation time 16219451756 ps
CPU time 965.21 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 02:14:31 PM PDT 24
Peak memory 2884616 kb
Host smart-8c7c7263-a0c1-473d-b1c2-7e97a4c33629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183554402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.183554402
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1902842573
Short name T938
Test name
Test status
Simulation time 764505501 ps
CPU time 11.56 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 215540 kb
Host smart-c2ad5d10-4645-4c7d-9e47-e968ac8b6017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902842573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1902842573
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1688717285
Short name T525
Test name
Test status
Simulation time 466277596 ps
CPU time 2.82 seconds
Started May 19 01:58:24 PM PDT 24
Finished May 19 01:58:30 PM PDT 24
Peak memory 204852 kb
Host smart-e8d39a7e-efce-4cb1-8c32-63bce8d2b053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688717285 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1688717285
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3750694109
Short name T1304
Test name
Test status
Simulation time 10044089290 ps
CPU time 70.29 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 412696 kb
Host smart-e087fad1-5337-4b1e-ae51-5ab8aa649bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750694109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3750694109
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1947744860
Short name T342
Test name
Test status
Simulation time 10128710221 ps
CPU time 75.74 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 545640 kb
Host smart-7b6f2327-fa7b-4cf5-af5b-21dfa4be9104
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947744860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1947744860
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1276204127
Short name T33
Test name
Test status
Simulation time 1326297094 ps
CPU time 2.38 seconds
Started May 19 01:58:21 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 205016 kb
Host smart-9c9256e6-800d-4c2c-bf34-20e31abc7893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276204127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1276204127
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1543316452
Short name T590
Test name
Test status
Simulation time 3053598263 ps
CPU time 4.26 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 205252 kb
Host smart-ea7e33d9-6b95-47c4-b1ab-7c3c7774f9eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543316452 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1543316452
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.341818606
Short name T277
Test name
Test status
Simulation time 20534009701 ps
CPU time 15.43 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 489556 kb
Host smart-ae994afa-6109-4e63-8329-86aeaf176e92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341818606 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.341818606
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.449072419
Short name T413
Test name
Test status
Simulation time 1186202589 ps
CPU time 16.3 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 204876 kb
Host smart-b13c6dc9-1e5e-4c66-9f54-9467b235aa81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449072419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.449072419
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.4057895333
Short name T627
Test name
Test status
Simulation time 321145169 ps
CPU time 5.5 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 204972 kb
Host smart-30d16b35-6af4-43b7-86fe-06bc76418cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057895333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.4057895333
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1350454429
Short name T580
Test name
Test status
Simulation time 62333914458 ps
CPU time 342.03 seconds
Started May 19 01:58:20 PM PDT 24
Finished May 19 02:04:04 PM PDT 24
Peak memory 3069212 kb
Host smart-93502bca-d5cd-4848-82d7-7e063c3760eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350454429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1350454429
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.423963764
Short name T1212
Test name
Test status
Simulation time 5619579762 ps
CPU time 6.15 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:58:54 PM PDT 24
Peak memory 221292 kb
Host smart-d90d25fd-66d4-4a05-8976-7d23933b7119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423963764 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.423963764
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3338663591
Short name T828
Test name
Test status
Simulation time 30805562 ps
CPU time 0.68 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:58:32 PM PDT 24
Peak memory 204624 kb
Host smart-f74d8637-6325-433e-a670-31017060dd4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338663591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3338663591
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3917411790
Short name T1296
Test name
Test status
Simulation time 943941491 ps
CPU time 1.9 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 213272 kb
Host smart-d3e26388-edbb-4369-9dc8-55741d4d1743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917411790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3917411790
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3137356689
Short name T903
Test name
Test status
Simulation time 262544584 ps
CPU time 4.7 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:37 PM PDT 24
Peak memory 250724 kb
Host smart-14370ace-c631-459a-b513-e6018484baf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137356689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3137356689
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.349000046
Short name T667
Test name
Test status
Simulation time 9322990193 ps
CPU time 84.59 seconds
Started May 19 01:58:32 PM PDT 24
Finished May 19 01:59:58 PM PDT 24
Peak memory 690648 kb
Host smart-7c15f1a9-bca3-4820-ac00-b64e58cb831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349000046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.349000046
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3671140446
Short name T66
Test name
Test status
Simulation time 11936550153 ps
CPU time 174.82 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 739464 kb
Host smart-6675c827-6f19-43c2-bd46-be22649a1f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671140446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3671140446
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.4246371731
Short name T1141
Test name
Test status
Simulation time 374383096 ps
CPU time 1.04 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 204912 kb
Host smart-967f7e97-77e2-4453-b25f-1cdd7f8721fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246371731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.4246371731
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1621374429
Short name T154
Test name
Test status
Simulation time 427994321 ps
CPU time 4.09 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:37 PM PDT 24
Peak memory 232812 kb
Host smart-18811291-37ba-45c2-a15d-0ef5971dc801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621374429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1621374429
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2010254315
Short name T929
Test name
Test status
Simulation time 4404163911 ps
CPU time 111.49 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 02:00:29 PM PDT 24
Peak memory 1290408 kb
Host smart-ffee313c-dccd-4f75-8684-a55ea28535d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010254315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2010254315
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1927354320
Short name T64
Test name
Test status
Simulation time 2407063311 ps
CPU time 21.67 seconds
Started May 19 01:58:29 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 263844 kb
Host smart-d8e67b01-dbdc-448d-94bf-6ab974b3c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927354320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1927354320
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1869911430
Short name T886
Test name
Test status
Simulation time 28144803 ps
CPU time 0.67 seconds
Started May 19 01:58:23 PM PDT 24
Finished May 19 01:58:26 PM PDT 24
Peak memory 204704 kb
Host smart-32cab03b-289a-4f92-ba61-385c33fbc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869911430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1869911430
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1191322572
Short name T1339
Test name
Test status
Simulation time 7047118272 ps
CPU time 248.97 seconds
Started May 19 01:58:38 PM PDT 24
Finished May 19 02:02:48 PM PDT 24
Peak memory 1016772 kb
Host smart-bb88511c-ba06-4ef9-8e26-b5bfc1f965ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191322572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1191322572
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3878607402
Short name T892
Test name
Test status
Simulation time 1208266270 ps
CPU time 58.64 seconds
Started May 19 01:58:22 PM PDT 24
Finished May 19 01:59:23 PM PDT 24
Peak memory 318220 kb
Host smart-466f25f6-6f57-4219-a9a3-ccbce4d5f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878607402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3878607402
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.415819986
Short name T77
Test name
Test status
Simulation time 113533318344 ps
CPU time 480.13 seconds
Started May 19 01:58:32 PM PDT 24
Finished May 19 02:06:34 PM PDT 24
Peak memory 1886372 kb
Host smart-fb8d8623-c5db-419f-ba08-f2bd479d198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415819986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.415819986
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3560852388
Short name T975
Test name
Test status
Simulation time 13284147802 ps
CPU time 14.17 seconds
Started May 19 01:58:28 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 219092 kb
Host smart-d1ea7acb-eca7-47b2-8c98-9ced649bd977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560852388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3560852388
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3903595210
Short name T1088
Test name
Test status
Simulation time 894224467 ps
CPU time 4.79 seconds
Started May 19 01:58:32 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 213164 kb
Host smart-485248da-c1e5-4fe4-b4ba-bb6f7f1a5678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903595210 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3903595210
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.66620899
Short name T702
Test name
Test status
Simulation time 10326914392 ps
CPU time 15.42 seconds
Started May 19 01:58:33 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 265424 kb
Host smart-b787797a-7fd6-4c0b-9455-fdb66c3f8c1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66620899 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_acq.66620899
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.4270895983
Short name T901
Test name
Test status
Simulation time 10730567770 ps
CPU time 4.53 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:38 PM PDT 24
Peak memory 220156 kb
Host smart-4f451123-14e7-4b3c-b9ea-d740377359fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270895983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.4270895983
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.4055968959
Short name T1112
Test name
Test status
Simulation time 1304921751 ps
CPU time 2.18 seconds
Started May 19 01:58:40 PM PDT 24
Finished May 19 01:58:43 PM PDT 24
Peak memory 205044 kb
Host smart-6b61de13-85c6-492a-b4d6-7cb4e0d534b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055968959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.4055968959
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.422107153
Short name T1229
Test name
Test status
Simulation time 2843968007 ps
CPU time 4.04 seconds
Started May 19 01:58:33 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 205124 kb
Host smart-331ca252-dd7a-4522-97bf-e9bab3b02e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422107153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.422107153
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3615199526
Short name T632
Test name
Test status
Simulation time 16582979995 ps
CPU time 210.61 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 2427960 kb
Host smart-44fb1bdf-8b5c-4b90-b06a-8055990aa277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615199526 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3615199526
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.933734842
Short name T370
Test name
Test status
Simulation time 3042482744 ps
CPU time 16.94 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 205056 kb
Host smart-ad822293-d608-49ef-852b-9e097e378d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933734842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.933734842
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3109965856
Short name T114
Test name
Test status
Simulation time 3780733872 ps
CPU time 18.2 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 211344 kb
Host smart-2edecdb5-1160-4309-b7ba-241b1efee46d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109965856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3109965856
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3458773086
Short name T252
Test name
Test status
Simulation time 48889729186 ps
CPU time 119.7 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 02:00:33 PM PDT 24
Peak memory 1660272 kb
Host smart-7c6a65be-1a6c-4a9d-be4e-f843e28acfa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458773086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3458773086
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1480003462
Short name T1287
Test name
Test status
Simulation time 7212117727 ps
CPU time 50.33 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 397416 kb
Host smart-cafa1a82-7ebd-4b30-809a-3e30eed5663a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480003462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1480003462
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.4265085153
Short name T382
Test name
Test status
Simulation time 2309869607 ps
CPU time 7.08 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 213336 kb
Host smart-35bb8a92-5931-4d04-bfc3-4e993b6978b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265085153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.4265085153
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2920365943
Short name T1259
Test name
Test status
Simulation time 25007343 ps
CPU time 0.62 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 01:58:39 PM PDT 24
Peak memory 204632 kb
Host smart-086f4a0d-9584-4c8e-8d7f-3a212ce5b1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920365943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2920365943
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1701919313
Short name T323
Test name
Test status
Simulation time 361954611 ps
CPU time 2.87 seconds
Started May 19 01:58:34 PM PDT 24
Finished May 19 01:58:38 PM PDT 24
Peak memory 215636 kb
Host smart-68752491-cb71-46c6-850d-f78d4c792aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701919313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1701919313
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.4172729899
Short name T433
Test name
Test status
Simulation time 340103870 ps
CPU time 8.16 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:42 PM PDT 24
Peak memory 232052 kb
Host smart-56f92c72-18a8-4022-a6dc-bbdb0477a886
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172729899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.4172729899
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2489381229
Short name T817
Test name
Test status
Simulation time 3432358632 ps
CPU time 93.5 seconds
Started May 19 01:58:35 PM PDT 24
Finished May 19 02:00:09 PM PDT 24
Peak memory 342992 kb
Host smart-d3284e27-6e44-4c50-97e1-8b5dd15e8f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489381229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2489381229
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2959667815
Short name T849
Test name
Test status
Simulation time 17023339801 ps
CPU time 43.05 seconds
Started May 19 01:58:33 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 477880 kb
Host smart-2240835c-d3b0-439b-976f-780fd5bf5df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959667815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2959667815
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1320320552
Short name T1048
Test name
Test status
Simulation time 80595795 ps
CPU time 0.87 seconds
Started May 19 01:58:35 PM PDT 24
Finished May 19 01:58:36 PM PDT 24
Peak memory 204784 kb
Host smart-e8e55be9-b8e1-45db-811a-7d3f62dd455d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320320552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1320320552
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2367915954
Short name T1179
Test name
Test status
Simulation time 2601280170 ps
CPU time 10.7 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 205088 kb
Host smart-35f5e3e5-fcfe-4123-b034-4745afb829d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367915954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2367915954
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1972679650
Short name T1306
Test name
Test status
Simulation time 3213352645 ps
CPU time 215.95 seconds
Started May 19 01:58:30 PM PDT 24
Finished May 19 02:02:08 PM PDT 24
Peak memory 972552 kb
Host smart-6c5a48bf-c0ef-48b3-86ef-7aa341cb300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972679650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1972679650
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.873137211
Short name T1115
Test name
Test status
Simulation time 322188519 ps
CPU time 13.88 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 204924 kb
Host smart-19d35043-3fc0-4e26-a7bc-2d859ef8b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873137211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.873137211
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2532442055
Short name T1083
Test name
Test status
Simulation time 1547517497 ps
CPU time 79.58 seconds
Started May 19 01:58:38 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 423592 kb
Host smart-928e569c-dee4-4e06-9ae3-54b64875b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532442055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2532442055
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3174066434
Short name T134
Test name
Test status
Simulation time 18253332 ps
CPU time 0.71 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:34 PM PDT 24
Peak memory 204700 kb
Host smart-55a82091-6de0-4abc-b8f9-ba954c48fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174066434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3174066434
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.945432005
Short name T759
Test name
Test status
Simulation time 2518474840 ps
CPU time 65.09 seconds
Started May 19 01:58:33 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 712092 kb
Host smart-153ce859-a50c-46fc-94f1-425176c8c756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945432005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.945432005
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2399195459
Short name T449
Test name
Test status
Simulation time 3063587090 ps
CPU time 73.01 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 300952 kb
Host smart-14a550ef-cb33-404c-b0b5-379d6ed4dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399195459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2399195459
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.565172534
Short name T920
Test name
Test status
Simulation time 17228690845 ps
CPU time 223.57 seconds
Started May 19 01:58:33 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 677388 kb
Host smart-ca89f625-4386-4c39-a755-1441a0a2f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565172534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.565172534
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1751479527
Short name T784
Test name
Test status
Simulation time 1369214637 ps
CPU time 11.38 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 221316 kb
Host smart-da80e7a3-25ab-4c12-ba7a-f5c751d44996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751479527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1751479527
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3180043247
Short name T878
Test name
Test status
Simulation time 1918331663 ps
CPU time 4.96 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:42 PM PDT 24
Peak memory 213136 kb
Host smart-7ebf1362-7639-4f88-8a62-b86d10725a82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180043247 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3180043247
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3935369543
Short name T82
Test name
Test status
Simulation time 10074073148 ps
CPU time 65.29 seconds
Started May 19 01:58:31 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 494952 kb
Host smart-e1bf500a-1217-4e8c-b93a-35945497c1d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935369543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3935369543
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.698678280
Short name T609
Test name
Test status
Simulation time 10146056849 ps
CPU time 33.09 seconds
Started May 19 01:58:34 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 326148 kb
Host smart-498d15eb-1141-410c-b61d-9161553ee369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698678280 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.698678280
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1990972500
Short name T945
Test name
Test status
Simulation time 622559036 ps
CPU time 2.6 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 205060 kb
Host smart-a09cd560-2fb7-438c-ad5f-acb068413bcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990972500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1990972500
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1479881846
Short name T717
Test name
Test status
Simulation time 1635557277 ps
CPU time 8.69 seconds
Started May 19 01:58:49 PM PDT 24
Finished May 19 01:58:59 PM PDT 24
Peak memory 219620 kb
Host smart-7bc6d639-c24c-4e0a-a997-28c4cda54025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479881846 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1479881846
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3982970397
Short name T1194
Test name
Test status
Simulation time 17864757854 ps
CPU time 390.83 seconds
Started May 19 01:58:35 PM PDT 24
Finished May 19 02:05:07 PM PDT 24
Peak memory 4305100 kb
Host smart-bee0f548-278b-48fe-9369-4ce31e5561d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982970397 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3982970397
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2952795165
Short name T1343
Test name
Test status
Simulation time 3986650373 ps
CPU time 36.57 seconds
Started May 19 01:58:41 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 205080 kb
Host smart-88fef0da-b06a-4c64-bff0-31f306d4c990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952795165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2952795165
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.931135052
Short name T451
Test name
Test status
Simulation time 374372261 ps
CPU time 6.2 seconds
Started May 19 01:58:34 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 205168 kb
Host smart-1f94dc7d-519d-462f-8165-35d2436e3b54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931135052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.931135052
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2629090298
Short name T1231
Test name
Test status
Simulation time 12016542946 ps
CPU time 21.34 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:59 PM PDT 24
Peak memory 205060 kb
Host smart-be90bd74-9ede-454f-9a2f-7533a96ded87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629090298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2629090298
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1579626342
Short name T497
Test name
Test status
Simulation time 4605351259 ps
CPU time 113.5 seconds
Started May 19 01:58:35 PM PDT 24
Finished May 19 02:00:29 PM PDT 24
Peak memory 1220908 kb
Host smart-4ad651cc-6ab3-40b6-912b-340b991a3e9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579626342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1579626342
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4160511735
Short name T1242
Test name
Test status
Simulation time 1325227283 ps
CPU time 7.03 seconds
Started May 19 01:58:35 PM PDT 24
Finished May 19 01:58:43 PM PDT 24
Peak memory 219604 kb
Host smart-fe107308-5e4b-4c81-9ece-e573a9e4d8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160511735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4160511735
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.999395335
Short name T673
Test name
Test status
Simulation time 24819368 ps
CPU time 0.61 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 204648 kb
Host smart-8d522bed-aaa6-40ef-9618-0c7753ecb70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999395335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.999395335
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2408205492
Short name T371
Test name
Test status
Simulation time 190429608 ps
CPU time 6.24 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:56:45 PM PDT 24
Peak memory 216208 kb
Host smart-a7522b32-a5aa-494d-8912-28a233716f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408205492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2408205492
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1435391873
Short name T548
Test name
Test status
Simulation time 321466736 ps
CPU time 7.27 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 268996 kb
Host smart-f10ddf4e-191e-431d-b456-1a257db86ac5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435391873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1435391873
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2190599155
Short name T418
Test name
Test status
Simulation time 2938367297 ps
CPU time 99.63 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:58:24 PM PDT 24
Peak memory 902396 kb
Host smart-29f2aada-208d-4a24-9441-5ccd27f08f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190599155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2190599155
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2967281166
Short name T736
Test name
Test status
Simulation time 28329255143 ps
CPU time 188.3 seconds
Started May 19 01:56:32 PM PDT 24
Finished May 19 01:59:42 PM PDT 24
Peak memory 745516 kb
Host smart-6070108a-3814-4ff9-9f28-7c8d4defcc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967281166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2967281166
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2767004757
Short name T900
Test name
Test status
Simulation time 291930264 ps
CPU time 3.51 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 204912 kb
Host smart-5c862fef-4d2d-4682-b25e-ec65acf28959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767004757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2767004757
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.840513683
Short name T117
Test name
Test status
Simulation time 44145793103 ps
CPU time 424.29 seconds
Started May 19 01:56:37 PM PDT 24
Finished May 19 02:03:44 PM PDT 24
Peak memory 1361876 kb
Host smart-87b5b306-a008-4b88-98f9-b4d60441ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840513683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.840513683
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2898865497
Short name T404
Test name
Test status
Simulation time 545865257 ps
CPU time 15.27 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:57:06 PM PDT 24
Peak memory 204908 kb
Host smart-1b227d14-e0dd-4d56-a705-241168276d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898865497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2898865497
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1490628904
Short name T246
Test name
Test status
Simulation time 4075776491 ps
CPU time 32.82 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 311268 kb
Host smart-1c7752e4-9624-496a-865d-876da33fb5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490628904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1490628904
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1030062638
Short name T145
Test name
Test status
Simulation time 81038423 ps
CPU time 0.64 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 204612 kb
Host smart-ec4dcd7a-5ab7-4ec0-892d-280d489272fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030062638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1030062638
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1026217202
Short name T617
Test name
Test status
Simulation time 2520768486 ps
CPU time 10.9 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:58 PM PDT 24
Peak memory 221768 kb
Host smart-6eb9ebb5-6ec1-46fa-ae25-442874c7b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026217202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1026217202
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.716197837
Short name T337
Test name
Test status
Simulation time 9881601792 ps
CPU time 99.76 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:58:33 PM PDT 24
Peak memory 281724 kb
Host smart-684adc72-3ef0-4bf8-8629-c6062d6f5e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716197837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.716197837
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3065699787
Short name T234
Test name
Test status
Simulation time 28969628656 ps
CPU time 1217.64 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 02:17:08 PM PDT 24
Peak memory 1600484 kb
Host smart-310a43fd-bdef-4b9b-99d2-2d45d4642934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065699787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3065699787
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1535961455
Short name T254
Test name
Test status
Simulation time 1228011276 ps
CPU time 12.3 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 215304 kb
Host smart-ef76efa5-0db1-4995-90c1-c61b767d4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535961455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1535961455
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.102533199
Short name T181
Test name
Test status
Simulation time 41025906 ps
CPU time 0.85 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 222168 kb
Host smart-e57eea1d-d539-4915-8010-d5d4badfbeac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102533199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.102533199
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2764039055
Short name T1316
Test name
Test status
Simulation time 735102385 ps
CPU time 3.89 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:48 PM PDT 24
Peak memory 213204 kb
Host smart-fd734086-6491-4fc1-b566-ec40252b0d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764039055 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2764039055
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3405740518
Short name T690
Test name
Test status
Simulation time 10504934720 ps
CPU time 9.28 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 248636 kb
Host smart-ab8dffa0-56de-4d4b-bac1-0f64f13930c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405740518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3405740518
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2044417492
Short name T687
Test name
Test status
Simulation time 10069366141 ps
CPU time 73.34 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:58:08 PM PDT 24
Peak memory 449460 kb
Host smart-c9fc5e92-f8ad-4df6-a750-746d5c7d2dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044417492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2044417492
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2479555028
Short name T933
Test name
Test status
Simulation time 759331169 ps
CPU time 2.38 seconds
Started May 19 01:56:37 PM PDT 24
Finished May 19 01:56:43 PM PDT 24
Peak memory 204996 kb
Host smart-06198c6e-29d1-4e93-bb7c-75cce800540f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479555028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2479555028
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.893157927
Short name T607
Test name
Test status
Simulation time 5057648791 ps
CPU time 5.96 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 221356 kb
Host smart-6840e9a8-b764-4fc9-b6ed-87a3ceede0f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893157927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.893157927
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3666392470
Short name T734
Test name
Test status
Simulation time 19452054486 ps
CPU time 52.73 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:41 PM PDT 24
Peak memory 1173008 kb
Host smart-d971f87f-4370-4fd0-ba31-1c21bbaf73de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666392470 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3666392470
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2134770097
Short name T1305
Test name
Test status
Simulation time 2994947376 ps
CPU time 32.31 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 204984 kb
Host smart-6d1992d8-4482-40f5-9f10-7c7673ca597a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134770097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2134770097
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1797170216
Short name T1314
Test name
Test status
Simulation time 401459867 ps
CPU time 9.03 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:57:04 PM PDT 24
Peak memory 204844 kb
Host smart-d7c46255-9db5-477e-9119-3f32257b0e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797170216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1797170216
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1780331400
Short name T742
Test name
Test status
Simulation time 12611639503 ps
CPU time 6.72 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 205076 kb
Host smart-e1c1f3a9-e20d-45e1-acda-4a6d0effe77f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780331400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1780331400
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.709838604
Short name T160
Test name
Test status
Simulation time 36667270290 ps
CPU time 3116.84 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 02:48:49 PM PDT 24
Peak memory 8833936 kb
Host smart-03fee8d7-7d18-4b9a-ac0c-024ead793beb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709838604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.709838604
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.287153111
Short name T487
Test name
Test status
Simulation time 4936481413 ps
CPU time 7.72 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 221332 kb
Host smart-b2ca23b0-9db1-4ecc-b183-dd3152b19181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287153111 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.287153111
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2688730532
Short name T950
Test name
Test status
Simulation time 18142247 ps
CPU time 0.65 seconds
Started May 19 01:59:02 PM PDT 24
Finished May 19 01:59:04 PM PDT 24
Peak memory 204640 kb
Host smart-cb8cc1ba-5bd9-4441-9ba8-8daba951ed89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688730532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2688730532
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.247082427
Short name T504
Test name
Test status
Simulation time 523999189 ps
CPU time 4.93 seconds
Started May 19 01:58:38 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 213292 kb
Host smart-e5cd593c-1f85-463a-a0fe-c0a2626aa798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247082427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.247082427
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.271789436
Short name T1085
Test name
Test status
Simulation time 1659689633 ps
CPU time 8.14 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 01:58:46 PM PDT 24
Peak memory 262432 kb
Host smart-3b0bcdfc-d667-4626-af03-ef8f5a2f7879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271789436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.271789436
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2017856183
Short name T362
Test name
Test status
Simulation time 6216056335 ps
CPU time 115.21 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 02:00:38 PM PDT 24
Peak memory 566720 kb
Host smart-394c1c01-83a9-4e32-be68-b102b78ac53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017856183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2017856183
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2840971303
Short name T1207
Test name
Test status
Simulation time 4845139301 ps
CPU time 208.95 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 02:02:07 PM PDT 24
Peak memory 806532 kb
Host smart-18fbc02c-49d2-43aa-a93f-79f577e751c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840971303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2840971303
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3832770814
Short name T361
Test name
Test status
Simulation time 98017020 ps
CPU time 0.94 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:37 PM PDT 24
Peak memory 204756 kb
Host smart-58d89ebd-afd8-40ab-ae87-36206c0e62ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832770814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3832770814
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.900960662
Short name T1195
Test name
Test status
Simulation time 267904201 ps
CPU time 2.89 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 204976 kb
Host smart-7838b3b6-bbfb-4ec5-aa54-f04b95dd8e06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900960662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
900960662
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1125290709
Short name T1326
Test name
Test status
Simulation time 13552034498 ps
CPU time 466.14 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 02:06:24 PM PDT 24
Peak memory 1548136 kb
Host smart-2f67ada2-6b53-40d2-8fe8-033a8af59db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125290709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1125290709
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.4017380973
Short name T43
Test name
Test status
Simulation time 499582395 ps
CPU time 8.27 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 204980 kb
Host smart-1d981223-4234-4bd5-97de-1be73dcc9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017380973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.4017380973
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1213970937
Short name T1108
Test name
Test status
Simulation time 7952245590 ps
CPU time 67.98 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:59:45 PM PDT 24
Peak memory 342792 kb
Host smart-74470145-db1b-4f9b-956a-fb39e4375d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213970937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1213970937
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.925794072
Short name T657
Test name
Test status
Simulation time 41720265 ps
CPU time 0.7 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:58:46 PM PDT 24
Peak memory 204660 kb
Host smart-7e868f4a-83e5-4ca4-b8fc-5da7f33209fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925794072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.925794072
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.4136134943
Short name T625
Test name
Test status
Simulation time 11719266412 ps
CPU time 46.53 seconds
Started May 19 01:58:40 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 205128 kb
Host smart-73c18cd5-d755-4cb8-9241-9c18a063d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136134943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.4136134943
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2814058357
Short name T1053
Test name
Test status
Simulation time 5203483349 ps
CPU time 21.75 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 292388 kb
Host smart-bd1ee962-ef69-4215-9611-c331202ef18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814058357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2814058357
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3517835267
Short name T483
Test name
Test status
Simulation time 18799198514 ps
CPU time 1834.36 seconds
Started May 19 01:58:37 PM PDT 24
Finished May 19 02:29:13 PM PDT 24
Peak memory 4370632 kb
Host smart-161c54e9-1c57-4359-80b1-693937ed806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517835267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3517835267
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.729987118
Short name T854
Test name
Test status
Simulation time 434548293 ps
CPU time 8.22 seconds
Started May 19 01:58:38 PM PDT 24
Finished May 19 01:58:47 PM PDT 24
Peak memory 213192 kb
Host smart-fcaef507-b337-429e-b09b-c50f26c287f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729987118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.729987118
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2824287651
Short name T27
Test name
Test status
Simulation time 931743521 ps
CPU time 4.25 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 01:58:48 PM PDT 24
Peak memory 205028 kb
Host smart-844e0aa8-0fc3-4cf1-a0ca-d0bf40bd132c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824287651 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2824287651
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.113431820
Short name T974
Test name
Test status
Simulation time 10073282997 ps
CPU time 33.97 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 315304 kb
Host smart-0f0457d9-440a-4ac9-b345-fc9e45fd2117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113431820 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.113431820
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2283363226
Short name T1062
Test name
Test status
Simulation time 10038250633 ps
CPU time 84.95 seconds
Started May 19 01:58:56 PM PDT 24
Finished May 19 02:00:22 PM PDT 24
Peak memory 461180 kb
Host smart-f2d21c09-0d18-47dd-b8dc-0c32323d053b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283363226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2283363226
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.644998399
Short name T1151
Test name
Test status
Simulation time 531511274 ps
CPU time 2.17 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 205072 kb
Host smart-a323e627-7b9f-4317-ba83-b7fbae192317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644998399 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.644998399
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.807932835
Short name T297
Test name
Test status
Simulation time 6336389974 ps
CPU time 3.6 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 205060 kb
Host smart-2b960c54-d69b-448f-ac2c-162b860d79c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807932835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.807932835
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.767493880
Short name T326
Test name
Test status
Simulation time 17026854846 ps
CPU time 25.01 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 713892 kb
Host smart-7183f171-28c3-421d-bfd2-ff502537a3fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767493880 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.767493880
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1986460936
Short name T10
Test name
Test status
Simulation time 4706941783 ps
CPU time 15.47 seconds
Started May 19 01:58:38 PM PDT 24
Finished May 19 01:58:54 PM PDT 24
Peak memory 205056 kb
Host smart-0388be9f-af13-480f-ad79-9d9ab80ffacf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986460936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1986460936
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.877895694
Short name T664
Test name
Test status
Simulation time 337300638 ps
CPU time 5.3 seconds
Started May 19 01:58:39 PM PDT 24
Finished May 19 01:58:45 PM PDT 24
Peak memory 205628 kb
Host smart-16866fe0-2d1c-43a8-841c-b36bf5f91b1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877895694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.877895694
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.988435674
Short name T469
Test name
Test status
Simulation time 11373180214 ps
CPU time 2.97 seconds
Started May 19 01:58:36 PM PDT 24
Finished May 19 01:58:41 PM PDT 24
Peak memory 205068 kb
Host smart-e85fe440-8eb0-4c14-8a73-be33854581ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988435674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.988435674
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.791245033
Short name T881
Test name
Test status
Simulation time 32397001829 ps
CPU time 253.26 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:03:06 PM PDT 24
Peak memory 1791144 kb
Host smart-b71022f9-15e1-4e26-913e-12eb1e49b471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791245033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.791245033
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.299174972
Short name T887
Test name
Test status
Simulation time 17487151216 ps
CPU time 7.64 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 221372 kb
Host smart-f40d6590-f653-4206-8e6b-6d944e060066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299174972 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.299174972
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3452740837
Short name T626
Test name
Test status
Simulation time 21329079 ps
CPU time 0.63 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 204588 kb
Host smart-fd26f687-db71-45d1-8a51-0be8754b643b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452740837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3452740837
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1773261251
Short name T120
Test name
Test status
Simulation time 630713611 ps
CPU time 4.6 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 213292 kb
Host smart-d0eb02be-34de-4a8c-a6cb-8c2a43d787ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773261251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1773261251
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2200938859
Short name T928
Test name
Test status
Simulation time 639910693 ps
CPU time 6.31 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:59:00 PM PDT 24
Peak memory 275612 kb
Host smart-9eb7e17d-1c2b-44e3-83c4-83ee1381112b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200938859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2200938859
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2372507604
Short name T88
Test name
Test status
Simulation time 7406468784 ps
CPU time 59.97 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 584068 kb
Host smart-00239aee-1a62-424d-8a24-3c21c64da27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372507604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2372507604
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2225252162
Short name T519
Test name
Test status
Simulation time 6952618143 ps
CPU time 49.18 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:59:44 PM PDT 24
Peak memory 622160 kb
Host smart-27581cd6-d536-4708-b3cf-8d72a23cf72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225252162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2225252162
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.434430376
Short name T542
Test name
Test status
Simulation time 731428123 ps
CPU time 10.42 seconds
Started May 19 01:58:43 PM PDT 24
Finished May 19 01:58:54 PM PDT 24
Peak memory 204948 kb
Host smart-e474fc56-aeb7-4049-8689-cb013b895995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434430376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
434430376
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3962277877
Short name T255
Test name
Test status
Simulation time 4413730674 ps
CPU time 139.92 seconds
Started May 19 01:58:50 PM PDT 24
Finished May 19 02:01:11 PM PDT 24
Peak memory 1250088 kb
Host smart-fd0e5064-d84c-40f8-ae8f-a94a24de604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962277877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3962277877
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.432754203
Short name T1248
Test name
Test status
Simulation time 916355491 ps
CPU time 7.4 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:59:01 PM PDT 24
Peak memory 204960 kb
Host smart-620f334b-85f0-427e-9e56-a42b3f0d21eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432754203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.432754203
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3533897958
Short name T768
Test name
Test status
Simulation time 1345010723 ps
CPU time 21.32 seconds
Started May 19 01:58:44 PM PDT 24
Finished May 19 01:59:06 PM PDT 24
Peak memory 232480 kb
Host smart-8ceded81-3008-49f3-b70b-e8a793e0b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533897958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3533897958
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2158438637
Short name T917
Test name
Test status
Simulation time 211760296 ps
CPU time 0.68 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 204716 kb
Host smart-c56f8545-7021-4edd-ae7e-1a5c2ef210d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158438637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2158438637
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1174803245
Short name T693
Test name
Test status
Simulation time 29132976593 ps
CPU time 281.04 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 02:03:30 PM PDT 24
Peak memory 289892 kb
Host smart-df9958dc-16b8-4d4a-955a-9d3ddcc701ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174803245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1174803245
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3787665993
Short name T1000
Test name
Test status
Simulation time 2807794119 ps
CPU time 27.36 seconds
Started May 19 01:58:49 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 331676 kb
Host smart-c73de600-8e39-4a73-b940-5307a8454160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787665993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3787665993
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3800535587
Short name T104
Test name
Test status
Simulation time 17644114496 ps
CPU time 903.15 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:13:56 PM PDT 24
Peak memory 2297872 kb
Host smart-5285f582-1803-4dc9-ab0c-126181380e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800535587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3800535587
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1246987231
Short name T745
Test name
Test status
Simulation time 6621729470 ps
CPU time 24.63 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 213308 kb
Host smart-f39b516b-cf6c-4bce-a6a8-e5ba1cacb251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246987231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1246987231
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3208556697
Short name T1245
Test name
Test status
Simulation time 483608665 ps
CPU time 2.85 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:58:49 PM PDT 24
Peak memory 204980 kb
Host smart-d2eac05a-91a2-407f-93a2-1277f5e777ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208556697 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3208556697
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2541300333
Short name T978
Test name
Test status
Simulation time 10070547493 ps
CPU time 66.91 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 427940 kb
Host smart-3465e5cc-4f24-4cd3-af9a-120f94390aa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541300333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2541300333
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.369686777
Short name T921
Test name
Test status
Simulation time 10051217568 ps
CPU time 65.74 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 464844 kb
Host smart-1d474cb7-fdc0-4ae4-bb94-540e53be84be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369686777 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.369686777
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3906799229
Short name T1109
Test name
Test status
Simulation time 785039492 ps
CPU time 3.04 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 205072 kb
Host smart-846b02fd-5e23-4544-a2ce-0ab70728f4cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906799229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3906799229
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1431945496
Short name T964
Test name
Test status
Simulation time 2893425859 ps
CPU time 6.52 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 205104 kb
Host smart-aa8c5ef3-6176-4d6b-8b18-9fbfee908552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431945496 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1431945496
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3988605446
Short name T360
Test name
Test status
Simulation time 14331985502 ps
CPU time 20.92 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 466352 kb
Host smart-8a1479d7-7115-44ba-9ef4-64728dc397e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988605446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3988605446
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2564625457
Short name T93
Test name
Test status
Simulation time 2379769601 ps
CPU time 12.86 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:58:59 PM PDT 24
Peak memory 205088 kb
Host smart-68450445-9263-4138-8944-d3818923f500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564625457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2564625457
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.379555812
Short name T772
Test name
Test status
Simulation time 573560415 ps
CPU time 10.19 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 01:58:54 PM PDT 24
Peak memory 206360 kb
Host smart-4c51ff8e-acc5-46fe-aee1-123ea5d5a87b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379555812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.379555812
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1725710367
Short name T29
Test name
Test status
Simulation time 52737038510 ps
CPU time 272.74 seconds
Started May 19 01:58:44 PM PDT 24
Finished May 19 02:03:17 PM PDT 24
Peak memory 2784712 kb
Host smart-c4dd0ca7-09c6-4b75-99ab-7c455bb0a17f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725710367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1725710367
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2295608818
Short name T1049
Test name
Test status
Simulation time 6759632761 ps
CPU time 530.18 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 02:07:39 PM PDT 24
Peak memory 1708664 kb
Host smart-7166cbaf-07aa-464d-8012-8254100634e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295608818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2295608818
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4144325729
Short name T1318
Test name
Test status
Simulation time 1243637117 ps
CPU time 6.46 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 213176 kb
Host smart-c53fecba-f4f1-4449-aa63-4d26238a0e75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144325729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.4144325729
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.4256207560
Short name T407
Test name
Test status
Simulation time 26127252 ps
CPU time 0.65 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 204600 kb
Host smart-3ba661f4-40a3-45b8-ac30-aa1ce77d9f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256207560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.4256207560
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3637631833
Short name T320
Test name
Test status
Simulation time 1067894443 ps
CPU time 4.59 seconds
Started May 19 01:58:45 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 229528 kb
Host smart-63abe11c-320b-46d6-a3a8-dc7f04bf55d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637631833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3637631833
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3444790679
Short name T482
Test name
Test status
Simulation time 1571343415 ps
CPU time 7.79 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 01:59:04 PM PDT 24
Peak memory 288620 kb
Host smart-7bc179af-c01c-479f-a084-9921047c1654
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444790679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3444790679
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1798240787
Short name T1277
Test name
Test status
Simulation time 1291967341 ps
CPU time 69.54 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 294076 kb
Host smart-cd903cc7-7d5b-4065-a38d-a29e23ae1b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798240787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1798240787
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2971581409
Short name T490
Test name
Test status
Simulation time 11059403887 ps
CPU time 90.73 seconds
Started May 19 01:58:44 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 868100 kb
Host smart-d3e07223-bee7-4e80-940d-cbaa5c6ad0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971581409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2971581409
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1673386653
Short name T1173
Test name
Test status
Simulation time 718991125 ps
CPU time 1.24 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 01:58:57 PM PDT 24
Peak memory 204968 kb
Host smart-aaf39e06-e2be-4911-a4b2-5bdfc2dcb788
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673386653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1673386653
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1239177403
Short name T831
Test name
Test status
Simulation time 493055388 ps
CPU time 3.42 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 204864 kb
Host smart-471f81f2-d5b8-406d-8e5b-f4ce1fa9aee8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239177403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1239177403
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2595477808
Short name T1126
Test name
Test status
Simulation time 4707479546 ps
CPU time 389.62 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 02:05:24 PM PDT 24
Peak memory 1350972 kb
Host smart-ee4cff52-ba10-4efd-b014-c838c3940655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595477808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2595477808
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1186594851
Short name T1243
Test name
Test status
Simulation time 3381799118 ps
CPU time 32.2 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:41 PM PDT 24
Peak memory 205080 kb
Host smart-451253a8-98bd-468f-ae1b-ff9988cef48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186594851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1186594851
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1462826554
Short name T585
Test name
Test status
Simulation time 1595913363 ps
CPU time 18.43 seconds
Started May 19 01:58:49 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 286836 kb
Host smart-1a5c2414-beda-461a-8732-7c39f3884d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462826554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1462826554
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.680748519
Short name T915
Test name
Test status
Simulation time 50658249 ps
CPU time 0.64 seconds
Started May 19 01:58:42 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 204724 kb
Host smart-0a312feb-7b55-4c7c-98c4-3297b30632ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680748519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.680748519
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2429010518
Short name T42
Test name
Test status
Simulation time 4623839953 ps
CPU time 64.33 seconds
Started May 19 01:58:40 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 205068 kb
Host smart-652b5370-af7d-4996-be3b-aff1fe5647ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429010518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2429010518
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3121617305
Short name T1155
Test name
Test status
Simulation time 1689871260 ps
CPU time 26.99 seconds
Started May 19 01:58:41 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 311192 kb
Host smart-494e1d45-4576-47be-9ba3-405956a4d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121617305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3121617305
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2243269000
Short name T885
Test name
Test status
Simulation time 41794940881 ps
CPU time 422.53 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 02:05:50 PM PDT 24
Peak memory 1927824 kb
Host smart-c4d8440b-2fef-423e-8ef5-36bf5485c07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243269000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2243269000
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.437514500
Short name T642
Test name
Test status
Simulation time 1579742756 ps
CPU time 12.9 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:59:07 PM PDT 24
Peak memory 230388 kb
Host smart-1706e2ab-ecf0-43eb-82a1-c615177fd95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437514500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.437514500
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1244416965
Short name T1211
Test name
Test status
Simulation time 797009869 ps
CPU time 3.83 seconds
Started May 19 01:58:54 PM PDT 24
Finished May 19 01:59:00 PM PDT 24
Peak memory 213268 kb
Host smart-910235e4-aef6-42b8-a458-1820d7b787e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244416965 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1244416965
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.625566397
Short name T84
Test name
Test status
Simulation time 10323190964 ps
CPU time 10.03 seconds
Started May 19 01:58:57 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 258164 kb
Host smart-7b3f87b8-07f3-4092-bfd1-03d2cc0dcfd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625566397 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.625566397
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2748422438
Short name T614
Test name
Test status
Simulation time 10184704269 ps
CPU time 14.77 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:17 PM PDT 24
Peak memory 314536 kb
Host smart-9f263955-1b6c-413d-8cf3-5987801acce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748422438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2748422438
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.4248463618
Short name T140
Test name
Test status
Simulation time 484536999 ps
CPU time 2.86 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:05 PM PDT 24
Peak memory 205032 kb
Host smart-7caa917f-093f-43b5-91c4-6b9f1595426d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248463618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.4248463618
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.34529646
Short name T1222
Test name
Test status
Simulation time 1953843192 ps
CPU time 5.33 seconds
Started May 19 01:59:02 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 213772 kb
Host smart-4b81120e-314e-4bc4-9f67-161d4daf3d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529646 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.34529646
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1468333902
Short name T293
Test name
Test status
Simulation time 20412664063 ps
CPU time 21.88 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:59:10 PM PDT 24
Peak memory 659340 kb
Host smart-c49d151c-9fa5-4184-90f6-696bfd2f2b8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468333902 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1468333902
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.50958347
Short name T499
Test name
Test status
Simulation time 1940214856 ps
CPU time 7.54 seconds
Started May 19 01:59:03 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 205004 kb
Host smart-d92c11f5-c7ee-4901-9ab0-1767b8fea400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50958347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_targ
et_smoke.50958347
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.834062134
Short name T241
Test name
Test status
Simulation time 1532484938 ps
CPU time 60.07 seconds
Started May 19 01:58:48 PM PDT 24
Finished May 19 01:59:50 PM PDT 24
Peak memory 207604 kb
Host smart-72ce7de0-7671-4664-93b0-a316a249b26e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834062134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.834062134
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1804753886
Short name T296
Test name
Test status
Simulation time 42165085941 ps
CPU time 96.84 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 02:00:26 PM PDT 24
Peak memory 1530512 kb
Host smart-fc7dd639-5b88-4e6c-87b8-bb3a64eb01d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804753886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1804753886
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.25571909
Short name T310
Test name
Test status
Simulation time 30519682098 ps
CPU time 1964.84 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:31:38 PM PDT 24
Peak memory 3452636 kb
Host smart-20d7c809-ff51-403e-bf86-666e72a2365e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25571909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_stretch.25571909
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1744735428
Short name T1084
Test name
Test status
Simulation time 1282465307 ps
CPU time 7.77 seconds
Started May 19 01:58:47 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 219076 kb
Host smart-7f90e7f1-8681-47c5-8cf9-e7084215338d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744735428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1744735428
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1136546347
Short name T556
Test name
Test status
Simulation time 138465360 ps
CPU time 0.66 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 204868 kb
Host smart-3930ef92-1350-41f3-838c-5bba5d42ab1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136546347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1136546347
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.902195480
Short name T1044
Test name
Test status
Simulation time 504639265 ps
CPU time 2.06 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:58:57 PM PDT 24
Peak memory 213304 kb
Host smart-55db333b-3ac5-4adc-a2b5-2d52bd9cdf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902195480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.902195480
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2889723759
Short name T943
Test name
Test status
Simulation time 1425653460 ps
CPU time 19.33 seconds
Started May 19 01:58:49 PM PDT 24
Finished May 19 01:59:10 PM PDT 24
Peak memory 280416 kb
Host smart-235e69df-9b3c-422f-817f-7073a8010635
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889723759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2889723759
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2774484135
Short name T545
Test name
Test status
Simulation time 3387426670 ps
CPU time 51.45 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 636540 kb
Host smart-36553e98-bc0d-41db-a2c2-814c012c67e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774484135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2774484135
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.497153273
Short name T716
Test name
Test status
Simulation time 10825693098 ps
CPU time 70.21 seconds
Started May 19 01:58:55 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 692292 kb
Host smart-fa83ec86-e96c-4016-9a84-833415be46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497153273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.497153273
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2334645260
Short name T946
Test name
Test status
Simulation time 100059632 ps
CPU time 0.9 seconds
Started May 19 01:58:55 PM PDT 24
Finished May 19 01:58:57 PM PDT 24
Peak memory 204776 kb
Host smart-39f46a15-97d9-4087-b848-02d4a000ea57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334645260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2334645260
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2852610005
Short name T836
Test name
Test status
Simulation time 166670469 ps
CPU time 3.85 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:13 PM PDT 24
Peak memory 204892 kb
Host smart-26447443-04a5-4d24-a964-f407cf96b0e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852610005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2852610005
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3364828256
Short name T727
Test name
Test status
Simulation time 15628054671 ps
CPU time 308.6 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 02:04:07 PM PDT 24
Peak memory 1178392 kb
Host smart-06eff57e-73d9-438a-9061-bbf23304251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364828256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3364828256
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.716861555
Short name T1273
Test name
Test status
Simulation time 1782017652 ps
CPU time 9.92 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 204948 kb
Host smart-3fdc529e-85b3-46ad-bfd1-8a96d657604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716861555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.716861555
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2956830384
Short name T912
Test name
Test status
Simulation time 3818809526 ps
CPU time 92.87 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:00:26 PM PDT 24
Peak memory 351124 kb
Host smart-d7638326-0fe2-477e-a2ef-955c1a084982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956830384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2956830384
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3597242608
Short name T1188
Test name
Test status
Simulation time 52188368 ps
CPU time 0.66 seconds
Started May 19 01:58:49 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 204668 kb
Host smart-da3504c4-30bc-48fa-8853-28607c7e7026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597242608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3597242608
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2630041567
Short name T562
Test name
Test status
Simulation time 1366735066 ps
CPU time 55.13 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:59:43 PM PDT 24
Peak memory 350512 kb
Host smart-b7c39866-d7a7-40ac-8eef-045f3ef7ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630041567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2630041567
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1539927855
Short name T267
Test name
Test status
Simulation time 214771830098 ps
CPU time 1919.15 seconds
Started May 19 01:59:03 PM PDT 24
Finished May 19 02:31:04 PM PDT 24
Peak memory 1564736 kb
Host smart-4a378dac-de30-41e7-ac89-972173a48b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539927855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1539927855
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2353476768
Short name T628
Test name
Test status
Simulation time 931917627 ps
CPU time 17.02 seconds
Started May 19 01:58:50 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 221240 kb
Host smart-2ae35010-89c9-4f8d-9d77-3c25aa43e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353476768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2353476768
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3234874183
Short name T1342
Test name
Test status
Simulation time 818126911 ps
CPU time 4.97 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 213164 kb
Host smart-197e58cf-ae8e-4fdb-9308-28c351486335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234874183 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3234874183
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3305646530
Short name T187
Test name
Test status
Simulation time 10052746508 ps
CPU time 77.63 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:00:10 PM PDT 24
Peak memory 448084 kb
Host smart-5cc579c4-8f64-49f4-80ad-3e2080bd3b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305646530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3305646530
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3071830667
Short name T634
Test name
Test status
Simulation time 10125760776 ps
CPU time 71.14 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 02:00:10 PM PDT 24
Peak memory 481868 kb
Host smart-31a3bb44-606c-4f23-bfc0-bf80077bf8f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071830667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3071830667
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1807135982
Short name T966
Test name
Test status
Simulation time 3226838116 ps
CPU time 2.52 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 01:59:02 PM PDT 24
Peak memory 205164 kb
Host smart-63b18e37-9e06-4fa2-95d0-67d0504dab77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807135982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1807135982
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3752323591
Short name T747
Test name
Test status
Simulation time 2375525684 ps
CPU time 4.01 seconds
Started May 19 01:58:59 PM PDT 24
Finished May 19 01:59:04 PM PDT 24
Peak memory 205980 kb
Host smart-0bef7541-d3e8-443b-9d1f-10d8d7e56132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752323591 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3752323591
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2123196042
Short name T844
Test name
Test status
Simulation time 16826637468 ps
CPU time 233.98 seconds
Started May 19 01:58:51 PM PDT 24
Finished May 19 02:02:47 PM PDT 24
Peak memory 2528200 kb
Host smart-20be60ff-b95c-41a9-91cb-bc47a3832d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123196042 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2123196042
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.507887335
Short name T613
Test name
Test status
Simulation time 995236995 ps
CPU time 36.35 seconds
Started May 19 01:59:00 PM PDT 24
Finished May 19 01:59:37 PM PDT 24
Peak memory 204964 kb
Host smart-85154ee8-8a0e-464d-8780-ccc98218a2d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507887335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.507887335
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1104175197
Short name T1167
Test name
Test status
Simulation time 2517432459 ps
CPU time 11.74 seconds
Started May 19 01:59:03 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 208704 kb
Host smart-892c7443-ea2e-42c2-adcb-e4e90a2b7746
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104175197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1104175197
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3169221989
Short name T90
Test name
Test status
Simulation time 10535813334 ps
CPU time 3.36 seconds
Started May 19 01:58:46 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 205108 kb
Host smart-269a029d-eb83-4deb-b1aa-782ec2afb8d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169221989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3169221989
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2622733932
Short name T785
Test name
Test status
Simulation time 41449440995 ps
CPU time 1127.06 seconds
Started May 19 01:58:50 PM PDT 24
Finished May 19 02:17:39 PM PDT 24
Peak memory 4858840 kb
Host smart-1283608f-25a9-48d6-8f0a-21fce3825954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622733932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2622733932
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1843571370
Short name T589
Test name
Test status
Simulation time 1523044834 ps
CPU time 8.48 seconds
Started May 19 01:58:55 PM PDT 24
Finished May 19 01:59:05 PM PDT 24
Peak memory 221264 kb
Host smart-4e439bf5-3229-4798-9a35-41fb2544d7bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843571370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1843571370
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.325603140
Short name T1219
Test name
Test status
Simulation time 18453660 ps
CPU time 0.65 seconds
Started May 19 01:59:12 PM PDT 24
Finished May 19 01:59:14 PM PDT 24
Peak memory 204616 kb
Host smart-3757fcf9-704e-4f4b-92a1-8b4c8c03051a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325603140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.325603140
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.753763771
Short name T1161
Test name
Test status
Simulation time 1349988402 ps
CPU time 1.97 seconds
Started May 19 01:59:12 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 213360 kb
Host smart-12099462-62a2-4d2a-80bb-48b0d5f6c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753763771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.753763771
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3922223697
Short name T430
Test name
Test status
Simulation time 4168830627 ps
CPU time 5.36 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 01:59:05 PM PDT 24
Peak memory 243448 kb
Host smart-003f7f55-a144-414e-a3cd-b6eb5e181c7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922223697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3922223697
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3675897309
Short name T1270
Test name
Test status
Simulation time 4704509464 ps
CPU time 95.32 seconds
Started May 19 01:58:57 PM PDT 24
Finished May 19 02:00:33 PM PDT 24
Peak memory 790168 kb
Host smart-e0a82916-1eca-46b2-a65c-3d5eac4a0873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675897309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3675897309
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2559620894
Short name T402
Test name
Test status
Simulation time 2000263679 ps
CPU time 61.45 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 02:00:03 PM PDT 24
Peak memory 593656 kb
Host smart-ca67d60d-8a99-45e2-8d89-910e3695187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559620894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2559620894
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2438392931
Short name T851
Test name
Test status
Simulation time 279664462 ps
CPU time 0.91 seconds
Started May 19 01:59:05 PM PDT 24
Finished May 19 01:59:08 PM PDT 24
Peak memory 204780 kb
Host smart-1b120ff9-fa82-4d60-8cf4-59707391e25a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438392931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2438392931
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2280323105
Short name T1027
Test name
Test status
Simulation time 612336061 ps
CPU time 3.28 seconds
Started May 19 01:59:04 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 225264 kb
Host smart-61bb1685-ac96-4440-9527-c5dcb77f7bde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280323105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2280323105
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2069443255
Short name T109
Test name
Test status
Simulation time 14855529837 ps
CPU time 64.64 seconds
Started May 19 01:59:00 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 875172 kb
Host smart-041a5722-364f-4e06-b2a7-f9b0396cb6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069443255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2069443255
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.709440091
Short name T349
Test name
Test status
Simulation time 432352078 ps
CPU time 4.66 seconds
Started May 19 01:59:00 PM PDT 24
Finished May 19 01:59:06 PM PDT 24
Peak memory 205036 kb
Host smart-f5638277-787a-491b-84d3-83f9a9c824b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709440091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.709440091
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1968667026
Short name T918
Test name
Test status
Simulation time 7139228699 ps
CPU time 30.9 seconds
Started May 19 01:58:57 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 398676 kb
Host smart-1f6117b5-496b-42a8-b4d8-2a1c96f23304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968667026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1968667026
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.2742592933
Short name T336
Test name
Test status
Simulation time 72893245 ps
CPU time 0.68 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 01:58:56 PM PDT 24
Peak memory 204716 kb
Host smart-ca108228-0bf8-43b5-b194-08204d94f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742592933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2742592933
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3008387565
Short name T919
Test name
Test status
Simulation time 26962463755 ps
CPU time 354.9 seconds
Started May 19 01:58:53 PM PDT 24
Finished May 19 02:04:50 PM PDT 24
Peak memory 214004 kb
Host smart-61534f13-2462-4a3d-8d56-89709b570bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008387565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3008387565
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2092857885
Short name T781
Test name
Test status
Simulation time 4220507299 ps
CPU time 21.23 seconds
Started May 19 01:58:52 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 318704 kb
Host smart-f873203b-32d8-4a1b-bfac-a48b1c4f87c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092857885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2092857885
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2931683907
Short name T128
Test name
Test status
Simulation time 17820790774 ps
CPU time 434.95 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 02:06:14 PM PDT 24
Peak memory 2095196 kb
Host smart-72cbdda9-0291-4c0b-8f56-2bb9140d8cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931683907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2931683907
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3000424440
Short name T1202
Test name
Test status
Simulation time 13057628899 ps
CPU time 38.03 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 213280 kb
Host smart-710de575-bb84-4e71-94c9-de38b862c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000424440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3000424440
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.971133781
Short name T25
Test name
Test status
Simulation time 644957067 ps
CPU time 3.26 seconds
Started May 19 01:59:04 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 213100 kb
Host smart-5cf2902c-66e7-44ee-837d-abce4b5b4f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971133781 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.971133781
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1869358287
Short name T779
Test name
Test status
Simulation time 10300090529 ps
CPU time 16.78 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:26 PM PDT 24
Peak memory 285300 kb
Host smart-b45bf35f-dabd-4b1b-8132-f820f1a821b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869358287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1869358287
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3480304874
Short name T1060
Test name
Test status
Simulation time 10048490009 ps
CPU time 71.14 seconds
Started May 19 01:58:56 PM PDT 24
Finished May 19 02:00:08 PM PDT 24
Peak memory 472996 kb
Host smart-e1848266-0ad8-4300-9162-f38860af5abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480304874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3480304874
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2500739336
Short name T190
Test name
Test status
Simulation time 464047984 ps
CPU time 2.85 seconds
Started May 19 01:58:59 PM PDT 24
Finished May 19 01:59:03 PM PDT 24
Peak memory 205064 kb
Host smart-79eec47a-9da4-4df0-a158-48420de37c89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500739336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2500739336
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2391303560
Short name T1244
Test name
Test status
Simulation time 6270755160 ps
CPU time 7.96 seconds
Started May 19 01:59:04 PM PDT 24
Finished May 19 01:59:14 PM PDT 24
Peak memory 217160 kb
Host smart-da13db6c-1f23-451c-8756-7cec8c4b1183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391303560 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2391303560
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2086369450
Short name T735
Test name
Test status
Simulation time 8617139221 ps
CPU time 6.01 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 204960 kb
Host smart-04b5072b-767d-4185-90da-4ba530012142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086369450 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2086369450
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2604513111
Short name T733
Test name
Test status
Simulation time 2378311264 ps
CPU time 15.6 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 205084 kb
Host smart-832512fa-4032-48fe-acac-c4432ddbd495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604513111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2604513111
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.627414217
Short name T1087
Test name
Test status
Simulation time 2916101074 ps
CPU time 18.45 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:21 PM PDT 24
Peak memory 205068 kb
Host smart-af470302-c585-4181-93b9-b3fd1b3abfca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627414217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.627414217
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3463811921
Short name T312
Test name
Test status
Simulation time 13286585521 ps
CPU time 7.55 seconds
Started May 19 01:59:04 PM PDT 24
Finished May 19 01:59:13 PM PDT 24
Peak memory 205076 kb
Host smart-6375bc5a-b68b-4a80-b8e4-90a7b5e1c0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463811921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3463811921
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3348763059
Short name T408
Test name
Test status
Simulation time 30865790656 ps
CPU time 2722.16 seconds
Started May 19 01:58:58 PM PDT 24
Finished May 19 02:44:21 PM PDT 24
Peak memory 7754596 kb
Host smart-c1a348c8-4058-4bd4-a0a0-ddbef7885d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348763059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3348763059
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.748974237
Short name T655
Test name
Test status
Simulation time 4055745242 ps
CPU time 6.78 seconds
Started May 19 01:59:14 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 221168 kb
Host smart-748a379b-c79f-4992-974e-bfede69085ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748974237 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.748974237
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1722870207
Short name T822
Test name
Test status
Simulation time 46603139 ps
CPU time 0.61 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 204640 kb
Host smart-c41dc39b-e132-4332-abda-15748397fd5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722870207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1722870207
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1372643281
Short name T512
Test name
Test status
Simulation time 670963526 ps
CPU time 2.56 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:04 PM PDT 24
Peak memory 215644 kb
Host smart-bcb402de-c540-4ea4-bdda-470f7d17dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372643281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1372643281
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3460453156
Short name T286
Test name
Test status
Simulation time 852882275 ps
CPU time 22.43 seconds
Started May 19 01:59:02 PM PDT 24
Finished May 19 01:59:26 PM PDT 24
Peak memory 292344 kb
Host smart-b3ab0246-0928-4fc6-8c87-fdbc74872fb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460453156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3460453156
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3920126312
Short name T1225
Test name
Test status
Simulation time 2300355914 ps
CPU time 178.42 seconds
Started May 19 01:59:00 PM PDT 24
Finished May 19 02:01:59 PM PDT 24
Peak memory 774836 kb
Host smart-d28dce92-d86c-43f4-82ec-a766a2ca8d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920126312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3920126312
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3966227235
Short name T998
Test name
Test status
Simulation time 1733427224 ps
CPU time 57.97 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 618100 kb
Host smart-33351877-1091-4a03-bcd6-124c3e1e7b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966227235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3966227235
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4147509294
Short name T898
Test name
Test status
Simulation time 101806620 ps
CPU time 1.05 seconds
Started May 19 01:59:05 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 204728 kb
Host smart-769f7871-dcea-4b62-b3e0-24c3df1d377b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147509294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4147509294
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1005420724
Short name T995
Test name
Test status
Simulation time 940130487 ps
CPU time 13.71 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 250512 kb
Host smart-e353948d-ef14-4ddb-af99-7ead7a3443e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005420724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1005420724
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1740432262
Short name T376
Test name
Test status
Simulation time 25829531663 ps
CPU time 398.96 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 02:05:48 PM PDT 24
Peak memory 1396564 kb
Host smart-8f46094d-e86e-486f-92db-d12d3fec7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740432262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1740432262
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3468029792
Short name T751
Test name
Test status
Simulation time 325948298 ps
CPU time 13.13 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 204932 kb
Host smart-ce15ad37-26c1-428b-be77-b97d1bd464cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468029792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3468029792
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1253267904
Short name T65
Test name
Test status
Simulation time 1327293521 ps
CPU time 22.12 seconds
Started May 19 01:59:03 PM PDT 24
Finished May 19 01:59:26 PM PDT 24
Peak memory 345604 kb
Host smart-563548b2-50e7-491b-b189-84f904740f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253267904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1253267904
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1161707605
Short name T129
Test name
Test status
Simulation time 51407352 ps
CPU time 0.69 seconds
Started May 19 01:59:18 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 204716 kb
Host smart-952051dd-243e-4d7d-9223-184662ca5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161707605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1161707605
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1229400914
Short name T880
Test name
Test status
Simulation time 27536480191 ps
CPU time 335.92 seconds
Started May 19 01:59:00 PM PDT 24
Finished May 19 02:04:37 PM PDT 24
Peak memory 263992 kb
Host smart-1c5e13c5-b0df-4370-85a1-4e84552ccff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229400914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1229400914
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.266107396
Short name T1267
Test name
Test status
Simulation time 5446564340 ps
CPU time 73.39 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 02:00:31 PM PDT 24
Peak memory 334680 kb
Host smart-86b2db3f-c5c0-4a64-b060-eda7ca00d57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266107396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.266107396
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.579656350
Short name T1001
Test name
Test status
Simulation time 13072842403 ps
CPU time 13.15 seconds
Started May 19 01:59:08 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 221368 kb
Host smart-cff5cf0c-78d4-4188-8573-3a2b62b9bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579656350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.579656350
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.4161935135
Short name T26
Test name
Test status
Simulation time 8516721174 ps
CPU time 3.65 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:14 PM PDT 24
Peak memory 213344 kb
Host smart-931ca7ab-f442-49f7-a45d-08318ed964ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161935135 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.4161935135
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.382943367
Short name T270
Test name
Test status
Simulation time 10521990164 ps
CPU time 5.74 seconds
Started May 19 01:59:02 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 232728 kb
Host smart-3b6fbd17-d441-498d-9a42-816c9f687c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382943367 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.382943367
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.436586219
Short name T359
Test name
Test status
Simulation time 10037897043 ps
CPU time 90.23 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 02:00:40 PM PDT 24
Peak memory 561132 kb
Host smart-c0b85663-df63-447d-bba2-9e24567c02b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436586219 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.436586219
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.316455680
Short name T24
Test name
Test status
Simulation time 1619727858 ps
CPU time 2.81 seconds
Started May 19 01:59:02 PM PDT 24
Finished May 19 01:59:07 PM PDT 24
Peak memory 205072 kb
Host smart-e409497c-e786-4be9-bdfc-000a6f7d8899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316455680 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.316455680
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2923931061
Short name T439
Test name
Test status
Simulation time 3385456795 ps
CPU time 5.93 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 205052 kb
Host smart-a4ec42ea-fc4f-477b-980f-6714dada9007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923931061 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2923931061
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.72853879
Short name T476
Test name
Test status
Simulation time 4687365138 ps
CPU time 10.21 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 205088 kb
Host smart-648920ed-6652-4b07-bb53-2ea00a49c7b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72853879 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.72853879
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3195589337
Short name T989
Test name
Test status
Simulation time 1192719650 ps
CPU time 47.19 seconds
Started May 19 01:59:05 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 204936 kb
Host smart-4bb44db2-5ed4-4344-9a8c-8cdd23627f49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195589337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3195589337
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1803839551
Short name T618
Test name
Test status
Simulation time 871209940 ps
CPU time 8.27 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 01:59:11 PM PDT 24
Peak memory 204964 kb
Host smart-36bc6b20-89e7-4747-aee6-4b43ca1cb87a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803839551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1803839551
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1864322086
Short name T754
Test name
Test status
Simulation time 35095696713 ps
CPU time 315.85 seconds
Started May 19 01:59:01 PM PDT 24
Finished May 19 02:04:18 PM PDT 24
Peak memory 2095712 kb
Host smart-d11b6ccd-395a-4892-bbc3-10c50bf47f04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864322086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1864322086
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_alert_test.145379731
Short name T809
Test name
Test status
Simulation time 43655172 ps
CPU time 0.66 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:23 PM PDT 24
Peak memory 204536 kb
Host smart-95cb510c-9555-422d-a615-3b6b32ff0448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145379731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.145379731
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.4247559441
Short name T861
Test name
Test status
Simulation time 308335995 ps
CPU time 2.54 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 213440 kb
Host smart-14c759ad-0c34-4c95-a6c9-50207e6277f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247559441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.4247559441
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2299860289
Short name T891
Test name
Test status
Simulation time 270137029 ps
CPU time 13.7 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 01:59:38 PM PDT 24
Peak memory 255940 kb
Host smart-236b5a7c-5d4b-4cdc-a457-ee59dbf7d700
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299860289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2299860289
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2932091000
Short name T506
Test name
Test status
Simulation time 11263568750 ps
CPU time 50.67 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 535404 kb
Host smart-3ee81067-a477-484c-83c8-850be0b8ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932091000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2932091000
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2712421453
Short name T1043
Test name
Test status
Simulation time 20611092924 ps
CPU time 45.52 seconds
Started May 19 01:59:09 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 577400 kb
Host smart-6f77fbd4-68f8-49da-bbc4-fc1852bd309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712421453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2712421453
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3900993903
Short name T491
Test name
Test status
Simulation time 133030733 ps
CPU time 1.01 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 204728 kb
Host smart-be72474f-dc69-4482-85b2-1515f7910f4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900993903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3900993903
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.4061828273
Short name T521
Test name
Test status
Simulation time 1032971987 ps
CPU time 5.16 seconds
Started May 19 01:59:09 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 204912 kb
Host smart-3e12ee03-0550-40ba-af24-e23f9e6551cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061828273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.4061828273
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3952852980
Short name T858
Test name
Test status
Simulation time 4567472183 ps
CPU time 137.75 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 02:01:41 PM PDT 24
Peak memory 1251628 kb
Host smart-ecfc5fa5-7cbd-44be-9a16-67703b4c2dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952852980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3952852980
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.315975681
Short name T732
Test name
Test status
Simulation time 2140261396 ps
CPU time 5.96 seconds
Started May 19 01:59:10 PM PDT 24
Finished May 19 01:59:17 PM PDT 24
Peak memory 204984 kb
Host smart-25d5fbbf-9535-45e2-802c-ebf8f5a8805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315975681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.315975681
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.228987718
Short name T679
Test name
Test status
Simulation time 9546307624 ps
CPU time 34.63 seconds
Started May 19 01:59:11 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 287868 kb
Host smart-ff62d6be-fd60-476d-9087-be948434b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228987718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.228987718
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.912366073
Short name T1199
Test name
Test status
Simulation time 86431220 ps
CPU time 0.72 seconds
Started May 19 01:59:08 PM PDT 24
Finished May 19 01:59:11 PM PDT 24
Peak memory 204676 kb
Host smart-479c07f8-ac9b-4fe2-8aad-c08497d4deb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912366073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.912366073
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.4142877872
Short name T1012
Test name
Test status
Simulation time 6045294454 ps
CPU time 49.13 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 364264 kb
Host smart-69f91cd4-6cf6-450b-a9f2-f56aea9bc64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142877872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.4142877872
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.4081135144
Short name T889
Test name
Test status
Simulation time 2729375004 ps
CPU time 89.6 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 02:00:40 PM PDT 24
Peak memory 344168 kb
Host smart-b3ee7b2f-8425-4c7b-a137-e22a5a465663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081135144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4081135144
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2222506894
Short name T1319
Test name
Test status
Simulation time 46979797107 ps
CPU time 1677.19 seconds
Started May 19 01:59:08 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 1997752 kb
Host smart-49515999-068b-41d7-a87c-8a8cabded866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222506894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2222506894
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1567521688
Short name T1138
Test name
Test status
Simulation time 859869006 ps
CPU time 16.19 seconds
Started May 19 01:59:05 PM PDT 24
Finished May 19 01:59:23 PM PDT 24
Peak memory 216028 kb
Host smart-00e32db3-1cb8-4f52-a384-e858e4321890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567521688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1567521688
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.17824169
Short name T170
Test name
Test status
Simulation time 609834156 ps
CPU time 3.11 seconds
Started May 19 01:59:11 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 204952 kb
Host smart-21a71507-bc4f-4456-838a-7ee0a74f5309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17824169 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_bad_addr.17824169
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2942131944
Short name T250
Test name
Test status
Simulation time 10100645884 ps
CPU time 79.58 seconds
Started May 19 01:59:08 PM PDT 24
Finished May 19 02:00:30 PM PDT 24
Peak memory 524696 kb
Host smart-93ec72ed-783c-4e1d-bde9-d7a8314e375f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942131944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2942131944
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3392660271
Short name T949
Test name
Test status
Simulation time 10101987968 ps
CPU time 39.37 seconds
Started May 19 01:59:09 PM PDT 24
Finished May 19 01:59:50 PM PDT 24
Peak memory 383424 kb
Host smart-e10f16f6-5005-44c7-812f-23eaa55be81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392660271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3392660271
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3652468955
Short name T676
Test name
Test status
Simulation time 384014485 ps
CPU time 2.43 seconds
Started May 19 01:59:12 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 205084 kb
Host smart-13be70cb-e78e-415a-a73c-a27537d447b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652468955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3652468955
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.626584727
Short name T604
Test name
Test status
Simulation time 1392457764 ps
CPU time 5.42 seconds
Started May 19 01:59:09 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 204908 kb
Host smart-a156cceb-937e-4ca5-ba7d-77f0794300f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626584727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.626584727
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1580098031
Short name T532
Test name
Test status
Simulation time 31290931427 ps
CPU time 17.13 seconds
Started May 19 01:59:05 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 486768 kb
Host smart-44720978-70e8-48b3-93e2-2c021dde0aa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580098031 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1580098031
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1873264538
Short name T1101
Test name
Test status
Simulation time 1267328682 ps
CPU time 22.85 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 204956 kb
Host smart-84ddbe60-e011-4beb-854c-015b2cd126c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873264538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1873264538
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1112183481
Short name T357
Test name
Test status
Simulation time 264475791 ps
CPU time 11.14 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:21 PM PDT 24
Peak memory 204964 kb
Host smart-1de1bc86-d7f6-4b13-be14-b3e00d0f83ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112183481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1112183481
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3486024923
Short name T347
Test name
Test status
Simulation time 32736394228 ps
CPU time 17.07 seconds
Started May 19 01:59:08 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 445444 kb
Host smart-c6c48bd1-456e-4e82-b842-08e8eeeb5cd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486024923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3486024923
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.697206235
Short name T665
Test name
Test status
Simulation time 39180246638 ps
CPU time 3198.67 seconds
Started May 19 01:59:06 PM PDT 24
Finished May 19 02:52:27 PM PDT 24
Peak memory 9640176 kb
Host smart-ad391c00-7b91-42df-8dc6-c0c4a08e081a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697206235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.697206235
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1275438748
Short name T1250
Test name
Test status
Simulation time 1548408525 ps
CPU time 7.51 seconds
Started May 19 01:59:07 PM PDT 24
Finished May 19 01:59:17 PM PDT 24
Peak memory 216756 kb
Host smart-f827791a-0378-4e9b-9e92-7c27f13b4106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275438748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1275438748
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2482853419
Short name T622
Test name
Test status
Simulation time 24141573 ps
CPU time 0.61 seconds
Started May 19 01:59:13 PM PDT 24
Finished May 19 01:59:14 PM PDT 24
Peak memory 204636 kb
Host smart-e6b38ad5-7e38-421d-a581-c4146c517c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482853419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2482853419
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1575536128
Short name T538
Test name
Test status
Simulation time 228624087 ps
CPU time 1.26 seconds
Started May 19 01:59:16 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 213220 kb
Host smart-fffe84b9-06f6-442b-a3f2-b493a5652aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575536128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1575536128
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.4108997370
Short name T813
Test name
Test status
Simulation time 1190271966 ps
CPU time 7.3 seconds
Started May 19 01:59:11 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 270936 kb
Host smart-5bdf4c37-b2ff-4a6a-a4c3-7fd88a478966
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108997370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.4108997370
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1600032711
Short name T1266
Test name
Test status
Simulation time 1655203847 ps
CPU time 118.61 seconds
Started May 19 01:59:25 PM PDT 24
Finished May 19 02:01:26 PM PDT 24
Peak memory 600180 kb
Host smart-9ab5dc95-fab7-4e2f-b9f9-c5e4e951ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600032711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1600032711
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.4184296877
Short name T1041
Test name
Test status
Simulation time 4706294892 ps
CPU time 73.57 seconds
Started May 19 01:59:14 PM PDT 24
Finished May 19 02:00:29 PM PDT 24
Peak memory 781300 kb
Host smart-579e9eab-218c-4450-a2df-62e39a39a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184296877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.4184296877
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.718888589
Short name T316
Test name
Test status
Simulation time 299999992 ps
CPU time 0.84 seconds
Started May 19 01:59:11 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 204720 kb
Host smart-8b6f1283-af87-4ea9-b890-c31dd5d93977
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718888589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.718888589
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3807510312
Short name T906
Test name
Test status
Simulation time 2241414756 ps
CPU time 5.72 seconds
Started May 19 01:59:18 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 244288 kb
Host smart-b803917c-af39-470f-accb-8c001006e00b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807510312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3807510312
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1766486701
Short name T552
Test name
Test status
Simulation time 5022200894 ps
CPU time 176.17 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 1471468 kb
Host smart-cd932856-5c93-488f-8003-f7fc2da07332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766486701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1766486701
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1029341558
Short name T235
Test name
Test status
Simulation time 315311091 ps
CPU time 5.37 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 205012 kb
Host smart-36bf7882-0af3-46d9-848b-0742bcb4aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029341558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1029341558
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.4188710547
Short name T1116
Test name
Test status
Simulation time 6945047727 ps
CPU time 30.47 seconds
Started May 19 01:59:16 PM PDT 24
Finished May 19 01:59:47 PM PDT 24
Peak memory 299672 kb
Host smart-84078364-e237-49c6-9902-982e6a594448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188710547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.4188710547
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4182599425
Short name T133
Test name
Test status
Simulation time 48740387 ps
CPU time 0.67 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 204716 kb
Host smart-6c0f7dc4-8392-44a7-bd7b-bc4207562bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182599425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4182599425
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2099242559
Short name T563
Test name
Test status
Simulation time 72166891735 ps
CPU time 1101.12 seconds
Started May 19 01:59:16 PM PDT 24
Finished May 19 02:17:38 PM PDT 24
Peak memory 901192 kb
Host smart-8ac22a51-13a2-4da9-a772-d1ffdd95b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099242559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2099242559
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.4021484183
Short name T437
Test name
Test status
Simulation time 2679845630 ps
CPU time 27.15 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 363656 kb
Host smart-4fe63fab-9de5-4043-b191-9ddb0a19aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021484183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.4021484183
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.2768731343
Short name T646
Test name
Test status
Simulation time 70261034221 ps
CPU time 1623.58 seconds
Started May 19 01:59:12 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 3250888 kb
Host smart-b5b5b66c-39d7-4413-888c-89b5d60cc064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768731343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2768731343
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.119762858
Short name T1142
Test name
Test status
Simulation time 1471182633 ps
CPU time 5.79 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 213164 kb
Host smart-e602c8c6-ea48-4e82-ad80-d2d02985d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119762858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.119762858
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2451173008
Short name T904
Test name
Test status
Simulation time 1756094956 ps
CPU time 3.05 seconds
Started May 19 01:59:13 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 205020 kb
Host smart-c36151a6-8610-4564-8c0d-6f261bb446ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451173008 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2451173008
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.344627814
Short name T846
Test name
Test status
Simulation time 10122307295 ps
CPU time 12.16 seconds
Started May 19 01:59:15 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 263788 kb
Host smart-15e895c2-9bad-4894-a6b7-7cf163aba08b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344627814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.344627814
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.547222178
Short name T1185
Test name
Test status
Simulation time 10098956903 ps
CPU time 80.53 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 02:00:38 PM PDT 24
Peak memory 541152 kb
Host smart-559cd78d-6c2d-48b2-8b80-8d65a95e5303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547222178 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_tx.547222178
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.2980170279
Short name T23
Test name
Test status
Simulation time 299947237 ps
CPU time 2.34 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 01:59:27 PM PDT 24
Peak memory 205020 kb
Host smart-74945603-040f-4e4a-a006-8d67e2d96262
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980170279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.2980170279
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.4234752944
Short name T294
Test name
Test status
Simulation time 979129220 ps
CPU time 5.71 seconds
Started May 19 01:59:12 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 217764 kb
Host smart-ef51879e-23ef-4294-b5f0-deaf2d346e74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234752944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.4234752944
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.684475696
Short name T1228
Test name
Test status
Simulation time 5738164302 ps
CPU time 10.09 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:33 PM PDT 24
Peak memory 458900 kb
Host smart-ce5235af-1de8-45f8-aedc-f813f65b69a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684475696 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.684475696
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1023171607
Short name T1051
Test name
Test status
Simulation time 676543935 ps
CPU time 11.12 seconds
Started May 19 01:59:11 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 204944 kb
Host smart-4fdd9113-4ade-45b6-9cc3-8878aa0b658e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023171607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1023171607
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2456656035
Short name T159
Test name
Test status
Simulation time 3815544388 ps
CPU time 14.72 seconds
Started May 19 01:59:13 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 215404 kb
Host smart-b088f38a-e6f3-4d6f-a645-0d84f8e98ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456656035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2456656035
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1975435391
Short name T599
Test name
Test status
Simulation time 31290255923 ps
CPU time 247.95 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 02:03:34 PM PDT 24
Peak memory 2819860 kb
Host smart-9c3ba481-f411-4e63-abfa-efb028ddcebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975435391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1975435391
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3067643731
Short name T146
Test name
Test status
Simulation time 14734373375 ps
CPU time 167.02 seconds
Started May 19 01:59:14 PM PDT 24
Finished May 19 02:02:03 PM PDT 24
Peak memory 1387168 kb
Host smart-2c55ca23-ff8b-4aa1-8ec5-4b046993848d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067643731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3067643731
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.112535798
Short name T879
Test name
Test status
Simulation time 4950163154 ps
CPU time 6.59 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 220480 kb
Host smart-ef572492-df01-4ff4-aaf3-2fecb11c8c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112535798 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.112535798
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3153158838
Short name T630
Test name
Test status
Simulation time 18520876 ps
CPU time 0.67 seconds
Started May 19 01:59:16 PM PDT 24
Finished May 19 01:59:18 PM PDT 24
Peak memory 204640 kb
Host smart-15b37147-3b54-4232-91fc-efbec9db0aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153158838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3153158838
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1852953817
Short name T1330
Test name
Test status
Simulation time 116037008 ps
CPU time 2.05 seconds
Started May 19 01:59:16 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 213252 kb
Host smart-3ba54510-a814-4354-a1b8-430e8ceb97d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852953817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1852953817
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.323769428
Short name T714
Test name
Test status
Simulation time 354985895 ps
CPU time 8.03 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 281620 kb
Host smart-6107db75-6c28-4856-bbb7-11873db5372a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323769428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.323769428
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2998726674
Short name T1323
Test name
Test status
Simulation time 8618510524 ps
CPU time 62.18 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 02:00:26 PM PDT 24
Peak memory 679728 kb
Host smart-d7b2888f-5852-43c3-87d5-7edb2617aaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998726674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2998726674
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3796366938
Short name T654
Test name
Test status
Simulation time 50300993521 ps
CPU time 63.44 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 636032 kb
Host smart-a080898f-3531-419f-8746-413c91494fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796366938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3796366938
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.616981954
Short name T1050
Test name
Test status
Simulation time 140090957 ps
CPU time 0.79 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 204748 kb
Host smart-9c810ef5-367a-4617-b670-9d662127cdb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616981954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.616981954
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3031026643
Short name T815
Test name
Test status
Simulation time 1201049791 ps
CPU time 4.8 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 235764 kb
Host smart-3bb809d0-b465-4957-81b9-f331827660fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031026643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3031026643
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2190792275
Short name T706
Test name
Test status
Simulation time 3341559986 ps
CPU time 232.94 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 1008940 kb
Host smart-d1135b4c-312a-414f-9817-1ad17adcbd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190792275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2190792275
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.890221649
Short name T668
Test name
Test status
Simulation time 356392167 ps
CPU time 4.61 seconds
Started May 19 01:59:15 PM PDT 24
Finished May 19 01:59:21 PM PDT 24
Peak memory 204984 kb
Host smart-ffaf2a8a-5f42-467a-bf85-1991f1287c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890221649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.890221649
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4018319883
Short name T1073
Test name
Test status
Simulation time 15793260454 ps
CPU time 41.28 seconds
Started May 19 01:59:23 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 361188 kb
Host smart-82640318-44e5-4961-aa2f-f0f34090161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018319883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4018319883
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.622600647
Short name T1055
Test name
Test status
Simulation time 18698080 ps
CPU time 0.67 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 204680 kb
Host smart-5e121712-7046-4250-992f-85184a2c6391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622600647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.622600647
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2625483876
Short name T299
Test name
Test status
Simulation time 3164900211 ps
CPU time 22.18 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 01:59:43 PM PDT 24
Peak memory 229536 kb
Host smart-30f286b8-2254-4cc8-801e-b28b60411721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625483876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2625483876
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3078036300
Short name T396
Test name
Test status
Simulation time 6813657499 ps
CPU time 27.4 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:51 PM PDT 24
Peak memory 278324 kb
Host smart-caa15454-9f32-47ce-a27f-88d41c5b255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078036300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3078036300
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.4124477968
Short name T112
Test name
Test status
Simulation time 13311489468 ps
CPU time 740.62 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 02:11:45 PM PDT 24
Peak memory 2923984 kb
Host smart-31e6fe55-4e1f-4a3c-8fd3-b7bed4d09363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124477968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.4124477968
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3619116709
Short name T290
Test name
Test status
Simulation time 834542498 ps
CPU time 18.44 seconds
Started May 19 01:59:15 PM PDT 24
Finished May 19 01:59:34 PM PDT 24
Peak memory 213144 kb
Host smart-ac597fbd-1f06-4c5f-95fc-e35a2166e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619116709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3619116709
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2461912379
Short name T1210
Test name
Test status
Simulation time 1048177986 ps
CPU time 5.18 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 01:59:23 PM PDT 24
Peak memory 204980 kb
Host smart-8764ae22-fcb7-4621-91dc-d39a51915d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461912379 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2461912379
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3224924331
Short name T802
Test name
Test status
Simulation time 10307843990 ps
CPU time 12.99 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 255632 kb
Host smart-faecda6e-fdca-42ad-a7e1-651325b3019e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224924331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3224924331
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3452930267
Short name T445
Test name
Test status
Simulation time 10140246179 ps
CPU time 68.98 seconds
Started May 19 01:59:15 PM PDT 24
Finished May 19 02:00:25 PM PDT 24
Peak memory 464460 kb
Host smart-8fbc96ac-dfaf-4833-a917-dc41758c520d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452930267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3452930267
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.2519993027
Short name T14
Test name
Test status
Simulation time 6835228391 ps
CPU time 2.56 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 205128 kb
Host smart-00e0881a-09a1-46d5-b492-a7edc9a02613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519993027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.2519993027
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.986465685
Short name T944
Test name
Test status
Simulation time 2003914683 ps
CPU time 3.69 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 204900 kb
Host smart-d67e0760-3c5e-47e9-adea-941aa6c6af98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986465685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.986465685
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3309523598
Short name T644
Test name
Test status
Simulation time 17745547451 ps
CPU time 382.56 seconds
Started May 19 01:59:14 PM PDT 24
Finished May 19 02:05:38 PM PDT 24
Peak memory 4369572 kb
Host smart-cd55b7a2-eb61-40e8-885b-9321e5e42a20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309523598 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3309523598
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3776645410
Short name T1184
Test name
Test status
Simulation time 1383999493 ps
CPU time 22.88 seconds
Started May 19 01:59:17 PM PDT 24
Finished May 19 01:59:41 PM PDT 24
Peak memory 204900 kb
Host smart-89ee6d09-5a10-442d-a28e-2c2d53f8e3c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776645410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3776645410
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3916822926
Short name T619
Test name
Test status
Simulation time 891476632 ps
CPU time 10.7 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:35 PM PDT 24
Peak memory 204984 kb
Host smart-b13eb3dd-e9f0-4a6e-a7c7-4d77cc04af25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916822926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3916822926
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.955864717
Short name T871
Test name
Test status
Simulation time 39320796520 ps
CPU time 182.74 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 2271356 kb
Host smart-a0f3cbde-a036-4327-8e62-a6428c13360f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955864717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.955864717
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3350512712
Short name T249
Test name
Test status
Simulation time 7693740485 ps
CPU time 164.61 seconds
Started May 19 01:59:18 PM PDT 24
Finished May 19 02:02:04 PM PDT 24
Peak memory 818360 kb
Host smart-8d5800f0-14a3-4547-8bd5-62b4bbbf6fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350512712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3350512712
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2990184995
Short name T856
Test name
Test status
Simulation time 4866399112 ps
CPU time 7.5 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:34 PM PDT 24
Peak memory 221340 kb
Host smart-add69de6-4b20-4779-ad2a-957f7a6d6444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990184995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2990184995
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2635471188
Short name T1082
Test name
Test status
Simulation time 200866739 ps
CPU time 0.65 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 01:59:30 PM PDT 24
Peak memory 204608 kb
Host smart-75cdca4e-645f-4459-afab-3c9f5489f01c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635471188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2635471188
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.745829511
Short name T240
Test name
Test status
Simulation time 3389252380 ps
CPU time 7.46 seconds
Started May 19 01:59:25 PM PDT 24
Finished May 19 01:59:35 PM PDT 24
Peak memory 277704 kb
Host smart-5e11a0bb-afa3-489d-afa6-9b11d694830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745829511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.745829511
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.263892032
Short name T1262
Test name
Test status
Simulation time 1073579666 ps
CPU time 4.31 seconds
Started May 19 01:59:25 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 250072 kb
Host smart-6c44e7f9-0693-4d7e-9e06-b40fb1a2bb2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263892032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.263892032
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.927122599
Short name T1265
Test name
Test status
Simulation time 11777299953 ps
CPU time 111.45 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 880076 kb
Host smart-9b58a647-048b-4465-be05-776558f7848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927122599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.927122599
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1259560583
Short name T167
Test name
Test status
Simulation time 5759428655 ps
CPU time 105.48 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 02:01:14 PM PDT 24
Peak memory 841196 kb
Host smart-f397cadf-d063-42bf-a68b-c956b7c4bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259560583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1259560583
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.267401862
Short name T1149
Test name
Test status
Simulation time 116128123 ps
CPU time 1.1 seconds
Started May 19 01:59:23 PM PDT 24
Finished May 19 01:59:27 PM PDT 24
Peak memory 205128 kb
Host smart-d4f03fa8-9e31-4497-afa9-7de48a323fea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267401862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.267401862
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.795437409
Short name T972
Test name
Test status
Simulation time 214490231 ps
CPU time 8.57 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 204916 kb
Host smart-3e9b5d51-bd1d-48f4-b3d6-02b53f8d96fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795437409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
795437409
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2465965321
Short name T524
Test name
Test status
Simulation time 32806963341 ps
CPU time 122.3 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 1184204 kb
Host smart-7526f7de-23e4-4f22-86b0-85437f933a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465965321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2465965321
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.4288437310
Short name T1157
Test name
Test status
Simulation time 2230257524 ps
CPU time 9.89 seconds
Started May 19 01:59:33 PM PDT 24
Finished May 19 01:59:44 PM PDT 24
Peak memory 205024 kb
Host smart-6dd4ab59-4a7a-44c0-923d-2f3304358f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288437310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.4288437310
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1861910190
Short name T985
Test name
Test status
Simulation time 5841934155 ps
CPU time 24.95 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 286032 kb
Host smart-a0c790bc-4a76-4e5a-8996-98d65242ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861910190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1861910190
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.433250125
Short name T776
Test name
Test status
Simulation time 28279413 ps
CPU time 0.69 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 204724 kb
Host smart-f2ac6df7-2940-4684-9bec-8bd5e401dac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433250125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.433250125
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1167935070
Short name T631
Test name
Test status
Simulation time 51157728508 ps
CPU time 530.79 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 02:08:13 PM PDT 24
Peak memory 281420 kb
Host smart-d5d87e28-0cc7-4a45-924f-301853db0dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167935070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1167935070
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3923821134
Short name T161
Test name
Test status
Simulation time 3577903302 ps
CPU time 92.14 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 02:00:55 PM PDT 24
Peak memory 388496 kb
Host smart-1b0837df-35f0-4b0c-aeb6-42092ff9cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923821134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3923821134
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.572434018
Short name T708
Test name
Test status
Simulation time 2931144272 ps
CPU time 18.79 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 01:59:47 PM PDT 24
Peak memory 229452 kb
Host smart-1f905533-9b86-430d-bc05-4315bada2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572434018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.572434018
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.4090836738
Short name T1153
Test name
Test status
Simulation time 1020338026 ps
CPU time 5.38 seconds
Started May 19 01:59:25 PM PDT 24
Finished May 19 01:59:33 PM PDT 24
Peak memory 213208 kb
Host smart-187cdfda-bc85-4a70-a774-8d82db93712f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090836738 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.4090836738
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3958742242
Short name T564
Test name
Test status
Simulation time 10227399024 ps
CPU time 14.45 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:37 PM PDT 24
Peak memory 255108 kb
Host smart-e2d1d4bb-e1ea-4b2b-b48f-f4772b020147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958742242 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3958742242
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3161899678
Short name T1136
Test name
Test status
Simulation time 10395560239 ps
CPU time 15.5 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 279060 kb
Host smart-2e731f42-36e2-490a-ae71-50b704703758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161899678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3161899678
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2735954699
Short name T526
Test name
Test status
Simulation time 466739093 ps
CPU time 2.78 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:29 PM PDT 24
Peak memory 204944 kb
Host smart-fcff3ef1-3047-46c0-9d21-78546a35cf9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735954699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2735954699
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.630586257
Short name T859
Test name
Test status
Simulation time 736004843 ps
CPU time 4.27 seconds
Started May 19 01:59:21 PM PDT 24
Finished May 19 01:59:28 PM PDT 24
Peak memory 204956 kb
Host smart-04e41c5e-113f-4257-9e20-a763ebd24d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630586257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.630586257
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2153758288
Short name T1189
Test name
Test status
Simulation time 4426229353 ps
CPU time 42.13 seconds
Started May 19 01:59:25 PM PDT 24
Finished May 19 02:00:10 PM PDT 24
Peak memory 1175168 kb
Host smart-13fa9d1b-18b1-4cb8-8d6e-b06e3df86915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153758288 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2153758288
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1173782189
Short name T1160
Test name
Test status
Simulation time 4601050875 ps
CPU time 45.99 seconds
Started May 19 01:59:19 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 205080 kb
Host smart-451ca72b-a82e-4650-9692-794f18fd5df2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173782189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1173782189
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1257140183
Short name T1105
Test name
Test status
Simulation time 321599297 ps
CPU time 14 seconds
Started May 19 01:59:42 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 204988 kb
Host smart-d98f4562-1cf6-441b-9aaf-76d8ee0f8939
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257140183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1257140183
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3208177735
Short name T1091
Test name
Test status
Simulation time 35225532451 ps
CPU time 25.78 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 01:59:48 PM PDT 24
Peak memory 564448 kb
Host smart-01a11931-774d-4f3c-9c52-a23e3361a174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208177735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3208177735
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.738666876
Short name T694
Test name
Test status
Simulation time 10600027358 ps
CPU time 50.31 seconds
Started May 19 01:59:20 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 753252 kb
Host smart-38dd4d6b-43bc-4034-a605-9fa5219e2263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738666876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.738666876
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.340287961
Short name T835
Test name
Test status
Simulation time 1376476306 ps
CPU time 7.63 seconds
Started May 19 01:59:22 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 221252 kb
Host smart-2baac017-5be8-4454-8672-59de0947c2b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340287961 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.340287961
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3359146712
Short name T363
Test name
Test status
Simulation time 48006909 ps
CPU time 0.63 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 204616 kb
Host smart-0427bbb5-5bc6-4d17-b45c-02043c04b7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359146712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3359146712
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.388262501
Short name T1286
Test name
Test status
Simulation time 1367305022 ps
CPU time 9.01 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:58 PM PDT 24
Peak memory 251800 kb
Host smart-407782b7-5eb3-4dd3-8eb1-6640d17c9313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388262501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.388262501
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1861686553
Short name T774
Test name
Test status
Simulation time 1868942644 ps
CPU time 26.76 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:15 PM PDT 24
Peak memory 313252 kb
Host smart-f1337c39-0648-4f19-ba88-b18419e3cf17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861686553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1861686553
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1620366286
Short name T261
Test name
Test status
Simulation time 2286349602 ps
CPU time 70.56 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:57:55 PM PDT 24
Peak memory 746336 kb
Host smart-19c06b6d-7615-4d9a-8f97-67ae3fd643ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620366286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1620366286
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.186863240
Short name T976
Test name
Test status
Simulation time 3854399143 ps
CPU time 140.86 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:59:03 PM PDT 24
Peak memory 666712 kb
Host smart-2b264d91-41e9-4fbe-8b17-ed23daa2c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186863240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.186863240
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2078568540
Short name T647
Test name
Test status
Simulation time 199955641 ps
CPU time 0.96 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:56:52 PM PDT 24
Peak memory 204656 kb
Host smart-94fd2249-3fd7-48f8-817f-dd7d9f523db6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078568540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2078568540
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3374287097
Short name T925
Test name
Test status
Simulation time 228894951 ps
CPU time 10.77 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 204864 kb
Host smart-feac723c-fae1-46c9-8513-acda6659cb62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374287097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3374287097
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1419087379
Short name T803
Test name
Test status
Simulation time 3527864720 ps
CPU time 233.83 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 02:00:38 PM PDT 24
Peak memory 979936 kb
Host smart-c975ac8f-47da-43b3-94c2-1f6d064ba335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419087379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1419087379
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2394024339
Short name T319
Test name
Test status
Simulation time 310790910 ps
CPU time 4.63 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 205000 kb
Host smart-4e12ff66-07ab-4b47-abe2-9be91a6f3004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394024339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2394024339
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3478877773
Short name T352
Test name
Test status
Simulation time 11350484725 ps
CPU time 33.38 seconds
Started May 19 01:56:59 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 351360 kb
Host smart-02bc2358-edc3-4750-926d-f03bcd0fabaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478877773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3478877773
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3227882995
Short name T138
Test name
Test status
Simulation time 39949861 ps
CPU time 0.65 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 204716 kb
Host smart-d6688381-21f5-4bf6-881c-32b0d3879886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227882995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3227882995
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3069620282
Short name T374
Test name
Test status
Simulation time 46996585932 ps
CPU time 1005.34 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 02:13:35 PM PDT 24
Peak memory 2934032 kb
Host smart-7f2e155d-e0ec-48dd-85b8-cfde5beace1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069620282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3069620282
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1558437903
Short name T872
Test name
Test status
Simulation time 43137980112 ps
CPU time 42.38 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:57:33 PM PDT 24
Peak memory 449072 kb
Host smart-82c43658-371d-4db5-b2ae-b42334feab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558437903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1558437903
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3204604190
Short name T1158
Test name
Test status
Simulation time 2876874037 ps
CPU time 31.92 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:20 PM PDT 24
Peak memory 213336 kb
Host smart-7e78f879-1726-42cd-92bf-47e47654193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204604190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3204604190
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3051526864
Short name T179
Test name
Test status
Simulation time 40609485 ps
CPU time 0.84 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 222116 kb
Host smart-137d74d5-ef92-416f-a479-7bd2800bff26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051526864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3051526864
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1440247369
Short name T935
Test name
Test status
Simulation time 752495660 ps
CPU time 3.92 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 204940 kb
Host smart-ca264152-e6b1-4820-a0c9-4b67bcb39896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440247369 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1440247369
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2515209721
Short name T508
Test name
Test status
Simulation time 10109416949 ps
CPU time 14.19 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 261808 kb
Host smart-b61f0da1-1312-4b45-a1c3-50b28a55c783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515209721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2515209721
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3520774450
Short name T756
Test name
Test status
Simulation time 10048333864 ps
CPU time 71.62 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 472688 kb
Host smart-99c2d9e1-d0a1-408c-aec3-1bd5842ed80c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520774450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3520774450
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3902865903
Short name T669
Test name
Test status
Simulation time 353265396 ps
CPU time 2.49 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:56:45 PM PDT 24
Peak memory 205088 kb
Host smart-b1331874-ca81-4c5a-b248-ad2479cc6942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902865903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3902865903
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1844250640
Short name T808
Test name
Test status
Simulation time 4148029300 ps
CPU time 5.17 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 217776 kb
Host smart-702a6fcc-b29f-4139-8b31-199c37d96909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844250640 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1844250640
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1316751981
Short name T1065
Test name
Test status
Simulation time 10805178685 ps
CPU time 63.85 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 1065628 kb
Host smart-29a20ae9-ca43-4177-a96a-287f30b50336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316751981 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1316751981
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3659322632
Short name T675
Test name
Test status
Simulation time 3083499871 ps
CPU time 9.93 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 205044 kb
Host smart-db34812b-6b2c-4d10-bf37-afdaabcca12a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659322632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3659322632
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2152382350
Short name T350
Test name
Test status
Simulation time 6864964774 ps
CPU time 26.65 seconds
Started May 19 01:56:36 PM PDT 24
Finished May 19 01:57:05 PM PDT 24
Peak memory 232732 kb
Host smart-44cf129a-2ae5-49a9-8489-8132ad4de7cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152382350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2152382350
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3364795081
Short name T295
Test name
Test status
Simulation time 28262906926 ps
CPU time 152.28 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:59:15 PM PDT 24
Peak memory 2148408 kb
Host smart-3e5d06f1-941f-4c8a-bb5f-cc7d891d26de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364795081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3364795081
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2465170966
Short name T191
Test name
Test status
Simulation time 23909967979 ps
CPU time 193.62 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 1365220 kb
Host smart-89330a09-ff07-4290-91b4-99ada19e454a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465170966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2465170966
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.841443642
Short name T725
Test name
Test status
Simulation time 5520132407 ps
CPU time 7.37 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 213276 kb
Host smart-bab68203-0220-4ee0-8a0a-cb9216348c9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841443642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.841443642
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1257871056
Short name T993
Test name
Test status
Simulation time 20388241 ps
CPU time 0.64 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 01:59:55 PM PDT 24
Peak memory 204612 kb
Host smart-6ee4b170-9c18-40d0-b0f2-91943dc7662b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257871056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1257871056
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1492618520
Short name T816
Test name
Test status
Simulation time 106834493 ps
CPU time 2.88 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 01:59:30 PM PDT 24
Peak memory 213392 kb
Host smart-8e46ce65-2cf3-4608-a04a-0061a11abe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492618520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1492618520
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.8719379
Short name T1102
Test name
Test status
Simulation time 241429323 ps
CPU time 4.94 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 01:59:35 PM PDT 24
Peak memory 236676 kb
Host smart-07102a82-c0ee-4df8-8650-6a05a216646f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8719379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.8719379
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3275358274
Short name T699
Test name
Test status
Simulation time 9429748965 ps
CPU time 224.31 seconds
Started May 19 01:59:24 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 887608 kb
Host smart-d5002188-fe1e-4e28-b06c-301ce13164b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275358274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3275358274
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.203175373
Short name T292
Test name
Test status
Simulation time 9665633437 ps
CPU time 59.7 seconds
Started May 19 01:59:28 PM PDT 24
Finished May 19 02:00:33 PM PDT 24
Peak memory 656568 kb
Host smart-97b62318-14da-442b-a11d-830757e7f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203175373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.203175373
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3081757103
Short name T559
Test name
Test status
Simulation time 109769807 ps
CPU time 1.1 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 204952 kb
Host smart-7b6b2436-1e87-4745-8ee4-766297925e7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081757103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3081757103
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1356552919
Short name T909
Test name
Test status
Simulation time 255889279 ps
CPU time 2.83 seconds
Started May 19 01:59:28 PM PDT 24
Finished May 19 01:59:33 PM PDT 24
Peak memory 204932 kb
Host smart-c19b2ae6-0c45-41fa-b7ad-1398362f6b2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356552919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1356552919
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1039403694
Short name T1332
Test name
Test status
Simulation time 36510180605 ps
CPU time 383.54 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 02:05:52 PM PDT 24
Peak memory 1321888 kb
Host smart-cc3a3d73-4e5c-484b-bd05-d21317fac20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039403694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1039403694
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1574452022
Short name T910
Test name
Test status
Simulation time 386317957 ps
CPU time 6.12 seconds
Started May 19 01:59:31 PM PDT 24
Finished May 19 01:59:38 PM PDT 24
Peak memory 205020 kb
Host smart-6dc03f04-244d-46e1-be55-4f984e3ebd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574452022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1574452022
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1640800742
Short name T247
Test name
Test status
Simulation time 1183127989 ps
CPU time 23.28 seconds
Started May 19 01:59:30 PM PDT 24
Finished May 19 01:59:55 PM PDT 24
Peak memory 308988 kb
Host smart-54e403b6-2c7b-4d7a-bc20-cd2d0ca62a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640800742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1640800742
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.825498710
Short name T137
Test name
Test status
Simulation time 18298029 ps
CPU time 0.68 seconds
Started May 19 01:59:28 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 204668 kb
Host smart-751eed6b-27ed-4c06-b250-e288e7a96e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825498710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.825498710
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3235760016
Short name T720
Test name
Test status
Simulation time 28236938319 ps
CPU time 376.14 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 02:05:46 PM PDT 24
Peak memory 289744 kb
Host smart-a4682278-e884-4ffb-8d57-1506023bcfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235760016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3235760016
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1735930556
Short name T366
Test name
Test status
Simulation time 5649149678 ps
CPU time 30.22 seconds
Started May 19 01:59:35 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 375060 kb
Host smart-f7bce177-6745-46ce-8e2a-45b6bcf70b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735930556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1735930556
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3024008308
Short name T902
Test name
Test status
Simulation time 612481781 ps
CPU time 10.34 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 213156 kb
Host smart-d5a0a5ae-e03e-407f-9f98-cf1c2ce88bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024008308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3024008308
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3801038113
Short name T1066
Test name
Test status
Simulation time 575980697 ps
CPU time 3.72 seconds
Started May 19 01:59:30 PM PDT 24
Finished May 19 01:59:36 PM PDT 24
Peak memory 204912 kb
Host smart-2dee266d-11dd-4f0c-87af-d443acf1fed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801038113 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3801038113
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2857644299
Short name T273
Test name
Test status
Simulation time 10145341672 ps
CPU time 15.36 seconds
Started May 19 01:59:27 PM PDT 24
Finished May 19 01:59:45 PM PDT 24
Peak memory 253264 kb
Host smart-ca374d16-2d8d-4b89-84bb-1acde8d9bf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857644299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2857644299
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1111427347
Short name T1255
Test name
Test status
Simulation time 10194871746 ps
CPU time 13.38 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 258060 kb
Host smart-a25c6454-de19-44d8-baaf-dae335245fee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111427347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1111427347
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1119145142
Short name T1114
Test name
Test status
Simulation time 5351981659 ps
CPU time 2.7 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 01:59:47 PM PDT 24
Peak memory 205024 kb
Host smart-7c50ccaf-3231-41fa-b5f9-745ffb4b9e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119145142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1119145142
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.843723258
Short name T1233
Test name
Test status
Simulation time 8212509081 ps
CPU time 4.49 seconds
Started May 19 01:59:36 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 205980 kb
Host smart-a53486f0-2800-4011-9606-441bc4b66f09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843723258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.843723258
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4046406236
Short name T1040
Test name
Test status
Simulation time 8964891219 ps
CPU time 27.82 seconds
Started May 19 01:59:40 PM PDT 24
Finished May 19 02:00:08 PM PDT 24
Peak memory 575748 kb
Host smart-6a2f02d9-930f-4e73-acde-627e32e631af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046406236 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4046406236
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1817626107
Short name T354
Test name
Test status
Simulation time 4626882804 ps
CPU time 34.91 seconds
Started May 19 01:59:29 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 205036 kb
Host smart-89f71061-08d1-4356-aec6-e79ef5aac570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817626107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1817626107
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1734770813
Short name T417
Test name
Test status
Simulation time 1860876510 ps
CPU time 75.64 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 02:00:45 PM PDT 24
Peak memory 207736 kb
Host smart-efb93aef-2588-42da-910d-66938eb14920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734770813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1734770813
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.546260509
Short name T291
Test name
Test status
Simulation time 44052980951 ps
CPU time 98.94 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 1442092 kb
Host smart-95373d8e-126a-422b-a959-68e4d7758206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546260509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.546260509
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1772167206
Short name T979
Test name
Test status
Simulation time 2435402542 ps
CPU time 8.88 seconds
Started May 19 01:59:26 PM PDT 24
Finished May 19 01:59:38 PM PDT 24
Peak memory 292728 kb
Host smart-7a9f16a4-0f99-4349-86e7-684cffd31cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772167206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1772167206
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3387840234
Short name T982
Test name
Test status
Simulation time 1583916736 ps
CPU time 8.02 seconds
Started May 19 01:59:41 PM PDT 24
Finished May 19 01:59:50 PM PDT 24
Peak memory 217696 kb
Host smart-7de3f23b-8151-4863-bed7-1d090f64ead9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387840234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3387840234
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2104123129
Short name T163
Test name
Test status
Simulation time 26674861 ps
CPU time 0.66 seconds
Started May 19 01:59:35 PM PDT 24
Finished May 19 01:59:36 PM PDT 24
Peak memory 204864 kb
Host smart-3596686b-920e-4078-b1a0-ab237faf2fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104123129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2104123129
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2726891725
Short name T51
Test name
Test status
Simulation time 167699320 ps
CPU time 1.85 seconds
Started May 19 01:59:41 PM PDT 24
Finished May 19 01:59:44 PM PDT 24
Peak memory 213240 kb
Host smart-913386e8-a93b-45f1-afa9-1113e09bebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726891725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2726891725
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3230130426
Short name T307
Test name
Test status
Simulation time 448908111 ps
CPU time 23.34 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 302548 kb
Host smart-45d69111-d14e-481c-96fe-93a7527ed0b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230130426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3230130426
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.177957664
Short name T80
Test name
Test status
Simulation time 8096306423 ps
CPU time 216.21 seconds
Started May 19 01:59:48 PM PDT 24
Finished May 19 02:03:26 PM PDT 24
Peak memory 871560 kb
Host smart-10f51e91-55c6-40cc-86c6-3f474e621b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177957664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.177957664
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1006908074
Short name T1028
Test name
Test status
Simulation time 7216252553 ps
CPU time 44.49 seconds
Started May 19 01:59:36 PM PDT 24
Finished May 19 02:00:21 PM PDT 24
Peak memory 507364 kb
Host smart-fddc295b-55ab-4d51-b012-78e289f0464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006908074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1006908074
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2135096320
Short name T1070
Test name
Test status
Simulation time 104454907 ps
CPU time 0.86 seconds
Started May 19 01:59:29 PM PDT 24
Finished May 19 01:59:31 PM PDT 24
Peak memory 204764 kb
Host smart-3926b6dd-8fb2-4f0c-9869-d150c4be0ba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135096320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2135096320
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4062008466
Short name T329
Test name
Test status
Simulation time 738013047 ps
CPU time 5.92 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 241908 kb
Host smart-87ab3823-83aa-4d66-92b6-59c92f440c6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062008466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4062008466
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.28114472
Short name T1271
Test name
Test status
Simulation time 5697222580 ps
CPU time 168.75 seconds
Started May 19 01:59:31 PM PDT 24
Finished May 19 02:02:21 PM PDT 24
Peak memory 820564 kb
Host smart-6c21b760-bb08-4691-bf18-14fcb18f56b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28114472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.28114472
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.359956301
Short name T1075
Test name
Test status
Simulation time 489607144 ps
CPU time 6.14 seconds
Started May 19 01:59:34 PM PDT 24
Finished May 19 01:59:41 PM PDT 24
Peak memory 205020 kb
Host smart-96bb2fec-4cf1-442c-be7f-41ff0c891eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359956301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.359956301
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3654037573
Short name T346
Test name
Test status
Simulation time 1460199102 ps
CPU time 62.88 seconds
Started May 19 01:59:36 PM PDT 24
Finished May 19 02:00:40 PM PDT 24
Peak memory 264820 kb
Host smart-c3f0bbd2-bb81-426f-9452-5e3cc43378da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654037573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3654037573
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.56936784
Short name T409
Test name
Test status
Simulation time 16951711 ps
CPU time 0.7 seconds
Started May 19 01:59:30 PM PDT 24
Finished May 19 01:59:32 PM PDT 24
Peak memory 204680 kb
Host smart-01f35ec8-a04c-4611-af67-d9288707fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56936784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.56936784
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2325360195
Short name T324
Test name
Test status
Simulation time 4189427120 ps
CPU time 18.94 seconds
Started May 19 01:59:44 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 415312 kb
Host smart-91f242ab-45cf-43b9-bee2-bd6e058d5e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325360195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2325360195
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2064038145
Short name T1007
Test name
Test status
Simulation time 1324689714 ps
CPU time 62.91 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 02:00:50 PM PDT 24
Peak memory 300092 kb
Host smart-bca1f28d-1942-476c-bfb0-eea0a9366cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064038145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2064038145
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.839259237
Short name T955
Test name
Test status
Simulation time 40068738069 ps
CPU time 3233.94 seconds
Started May 19 01:59:41 PM PDT 24
Finished May 19 02:53:36 PM PDT 24
Peak memory 4981832 kb
Host smart-e1461a47-8463-471b-a95b-81938c4621a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839259237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.839259237
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.247986768
Short name T1224
Test name
Test status
Simulation time 1734892779 ps
CPU time 17.36 seconds
Started May 19 01:59:31 PM PDT 24
Finished May 19 01:59:49 PM PDT 24
Peak memory 213160 kb
Host smart-3c56b326-691d-4830-80f2-9979654dccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247986768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.247986768
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2787308324
Short name T750
Test name
Test status
Simulation time 547839086 ps
CPU time 3.22 seconds
Started May 19 01:59:49 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 204980 kb
Host smart-c080c48e-306b-4908-9fe1-aa226af16e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787308324 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2787308324
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3442408773
Short name T765
Test name
Test status
Simulation time 10156053823 ps
CPU time 14.03 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 02:00:03 PM PDT 24
Peak memory 253072 kb
Host smart-4759859f-4fc3-4c24-b062-b018269b337d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442408773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3442408773
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1392689105
Short name T11
Test name
Test status
Simulation time 1784264381 ps
CPU time 2.62 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 204928 kb
Host smart-efa56b5e-3ca4-4221-9b1b-4e7d4aaaa7f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392689105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1392689105
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2336505691
Short name T913
Test name
Test status
Simulation time 793005376 ps
CPU time 4.31 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 01:59:37 PM PDT 24
Peak memory 204936 kb
Host smart-132c7093-5aef-4bba-8da6-f0ea34ec74bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336505691 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2336505691
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.945936075
Short name T447
Test name
Test status
Simulation time 3641093595 ps
CPU time 7.4 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 205048 kb
Host smart-e458a310-2879-4bb4-bccf-9d0f0e8adf6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945936075 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.945936075
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.380669590
Short name T971
Test name
Test status
Simulation time 2192505248 ps
CPU time 13.12 seconds
Started May 19 01:59:49 PM PDT 24
Finished May 19 02:00:03 PM PDT 24
Peak memory 205064 kb
Host smart-8542f684-3529-4787-9667-e6b28caa75b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380669590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.380669590
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3415156665
Short name T1097
Test name
Test status
Simulation time 227935979 ps
CPU time 3.57 seconds
Started May 19 01:59:31 PM PDT 24
Finished May 19 01:59:36 PM PDT 24
Peak memory 204992 kb
Host smart-0d24cf6f-590e-4fc6-b7a1-6657d4353b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415156665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3415156665
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2898007784
Short name T728
Test name
Test status
Simulation time 57324193514 ps
CPU time 1764.73 seconds
Started May 19 01:59:48 PM PDT 24
Finished May 19 02:29:15 PM PDT 24
Peak memory 9584992 kb
Host smart-194460ee-c109-435b-aebb-175d791b851a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898007784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2898007784
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2400184581
Short name T855
Test name
Test status
Simulation time 6285341010 ps
CPU time 185.04 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 912168 kb
Host smart-b4fd876f-322d-419e-b44c-c157ee3759ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400184581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2400184581
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2278283548
Short name T715
Test name
Test status
Simulation time 6144964580 ps
CPU time 6.67 seconds
Started May 19 01:59:32 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 213312 kb
Host smart-0f2be74d-5dd5-465c-8fd4-f28e4e170873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278283548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2278283548
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3543724286
Short name T1186
Test name
Test status
Simulation time 21243231 ps
CPU time 0.59 seconds
Started May 19 01:59:41 PM PDT 24
Finished May 19 01:59:42 PM PDT 24
Peak memory 204588 kb
Host smart-0cc853c9-b2cc-4649-94b3-4ba7ffd078ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543724286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3543724286
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3175444988
Short name T282
Test name
Test status
Simulation time 287250282 ps
CPU time 4.49 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 01:59:49 PM PDT 24
Peak memory 240840 kb
Host smart-8ff2307a-c693-496f-85a7-e68deb707b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175444988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3175444988
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3048895574
Short name T1140
Test name
Test status
Simulation time 240422485 ps
CPU time 4.84 seconds
Started May 19 01:59:34 PM PDT 24
Finished May 19 01:59:40 PM PDT 24
Peak memory 250468 kb
Host smart-9ced9ab9-1aaf-4b28-8226-c4ee92041b0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048895574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3048895574
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2753756859
Short name T870
Test name
Test status
Simulation time 9806503069 ps
CPU time 81.01 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 02:01:07 PM PDT 24
Peak memory 816012 kb
Host smart-a4a1ea20-5100-48d6-a91e-fc40a43007ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753756859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2753756859
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.802545898
Short name T1030
Test name
Test status
Simulation time 2069861239 ps
CPU time 150.43 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 02:02:18 PM PDT 24
Peak memory 658236 kb
Host smart-85035331-2fc4-4d3b-ae68-f395caa1b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802545898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.802545898
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.879852395
Short name T9
Test name
Test status
Simulation time 77966245 ps
CPU time 0.94 seconds
Started May 19 01:59:35 PM PDT 24
Finished May 19 01:59:37 PM PDT 24
Peak memory 204752 kb
Host smart-2aff61e3-f557-4f72-9387-3eda58550ab6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879852395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.879852395
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3451886171
Short name T157
Test name
Test status
Simulation time 209518146 ps
CPU time 5.75 seconds
Started May 19 01:59:38 PM PDT 24
Finished May 19 01:59:45 PM PDT 24
Peak memory 243304 kb
Host smart-e90d3d89-2631-4b73-b31e-647fd13bf3e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451886171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3451886171
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2480220814
Short name T1020
Test name
Test status
Simulation time 6308468432 ps
CPU time 71.12 seconds
Started May 19 01:59:49 PM PDT 24
Finished May 19 02:01:02 PM PDT 24
Peak memory 954072 kb
Host smart-1d78dc99-7f7c-495b-93bd-8aa89c1c65d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480220814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2480220814
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1561853904
Short name T819
Test name
Test status
Simulation time 1822857500 ps
CPU time 4.72 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 01:59:53 PM PDT 24
Peak memory 204960 kb
Host smart-78e0ece1-1136-448a-b75c-49b1286785b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561853904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1561853904
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3577555789
Short name T744
Test name
Test status
Simulation time 4056170175 ps
CPU time 106.44 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 02:01:31 PM PDT 24
Peak memory 448700 kb
Host smart-0d586fa4-c08e-4870-a0d0-15324cc620a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577555789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3577555789
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.3985787829
Short name T596
Test name
Test status
Simulation time 26291024 ps
CPU time 0.71 seconds
Started May 19 01:59:33 PM PDT 24
Finished May 19 01:59:34 PM PDT 24
Peak memory 204636 kb
Host smart-970618bd-d2bb-4c58-90db-7eafae2cff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985787829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3985787829
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3481779437
Short name T561
Test name
Test status
Simulation time 7622054042 ps
CPU time 279.33 seconds
Started May 19 01:59:48 PM PDT 24
Finished May 19 02:04:29 PM PDT 24
Peak memory 225264 kb
Host smart-acbc0751-af72-44bc-a6cd-7afa88a73602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481779437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3481779437
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2744462594
Short name T287
Test name
Test status
Simulation time 7407219008 ps
CPU time 41.12 seconds
Started May 19 01:59:33 PM PDT 24
Finished May 19 02:00:15 PM PDT 24
Peak memory 382116 kb
Host smart-373658a7-65f7-4fa8-a579-01fa215034c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744462594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2744462594
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.142642460
Short name T830
Test name
Test status
Simulation time 61034956582 ps
CPU time 2926.26 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 02:48:34 PM PDT 24
Peak memory 3513864 kb
Host smart-64cf7eea-31e2-4250-98c4-575b2b47155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142642460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.142642460
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2534023929
Short name T908
Test name
Test status
Simulation time 3436704298 ps
CPU time 9.01 seconds
Started May 19 01:59:35 PM PDT 24
Finished May 19 01:59:45 PM PDT 24
Peak memory 218180 kb
Host smart-0efa4420-6467-451c-a1e0-0cf74bb12db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534023929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2534023929
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3475768188
Short name T937
Test name
Test status
Simulation time 3342928753 ps
CPU time 4.63 seconds
Started May 19 01:59:42 PM PDT 24
Finished May 19 01:59:47 PM PDT 24
Peak memory 205112 kb
Host smart-7ee0ae89-f8f0-4a6c-9f38-66d95e8422fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475768188 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3475768188
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.474978018
Short name T790
Test name
Test status
Simulation time 10814407307 ps
CPU time 8.73 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 247548 kb
Host smart-109542cb-0249-4612-8d45-7b0c5992aaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474978018 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.474978018
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2056752984
Short name T726
Test name
Test status
Simulation time 10393612442 ps
CPU time 8.91 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 254392 kb
Host smart-1df5c715-db3e-4612-9a92-98afc0e3ebce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056752984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2056752984
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3009440696
Short name T22
Test name
Test status
Simulation time 739575780 ps
CPU time 2.54 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 01:59:49 PM PDT 24
Peak memory 205076 kb
Host smart-2006e080-3d50-4890-8605-b93cdbc279a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009440696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3009440696
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.314341133
Short name T761
Test name
Test status
Simulation time 2719286095 ps
CPU time 4.22 seconds
Started May 19 01:59:48 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 204952 kb
Host smart-d1d492dd-a4a3-4357-933b-d3601c92f4e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314341133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.314341133
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2009937919
Short name T712
Test name
Test status
Simulation time 6232620800 ps
CPU time 67.18 seconds
Started May 19 01:59:44 PM PDT 24
Finished May 19 02:00:53 PM PDT 24
Peak memory 1626204 kb
Host smart-6a329025-80d3-41d8-9802-5356722432f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009937919 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2009937919
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2833468521
Short name T1107
Test name
Test status
Simulation time 3328553660 ps
CPU time 11.16 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 205040 kb
Host smart-6ebe5706-b811-4013-9fff-35449a6d8110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833468521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2833468521
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2194502176
Short name T649
Test name
Test status
Simulation time 3162336911 ps
CPU time 14.73 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 210892 kb
Host smart-2ac63b6f-e4c9-43a9-aecd-7a4283b6b5e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194502176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2194502176
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3038284878
Short name T472
Test name
Test status
Simulation time 8778458304 ps
CPU time 9.43 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 205312 kb
Host smart-26817e78-5126-4889-8c32-924a30d536e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038284878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3038284878
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.64418745
Short name T1086
Test name
Test status
Simulation time 6033588842 ps
CPU time 450.15 seconds
Started May 19 01:59:42 PM PDT 24
Finished May 19 02:07:14 PM PDT 24
Peak memory 1553036 kb
Host smart-c5cbe5f8-90b1-4ca4-82b7-01a9576d5769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64418745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_stretch.64418745
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1096951909
Short name T793
Test name
Test status
Simulation time 1545111368 ps
CPU time 7.64 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 221268 kb
Host smart-6c3cf6ef-ffb8-4a9d-9f4c-ddc33e0487a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096951909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1096951909
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1727839271
Short name T1206
Test name
Test status
Simulation time 40791657 ps
CPU time 0.63 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 204596 kb
Host smart-affaf1ac-0c96-4e00-bc6e-56a804bb0c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727839271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1727839271
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.570035973
Short name T313
Test name
Test status
Simulation time 305836248 ps
CPU time 11.79 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 242820 kb
Host smart-9af5585f-b545-4fb5-bfa7-2755766f5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570035973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.570035973
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1032203424
Short name T741
Test name
Test status
Simulation time 405865382 ps
CPU time 18.1 seconds
Started May 19 01:59:39 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 268356 kb
Host smart-51846db9-6108-4717-91ba-30f79dfb0d37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032203424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1032203424
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2211368170
Short name T875
Test name
Test status
Simulation time 2566669711 ps
CPU time 216.24 seconds
Started May 19 01:59:39 PM PDT 24
Finished May 19 02:03:16 PM PDT 24
Peak memory 844148 kb
Host smart-8ceb9cac-645d-46ca-a40e-4eb94520fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211368170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2211368170
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1962157269
Short name T328
Test name
Test status
Simulation time 4824055207 ps
CPU time 73.37 seconds
Started May 19 01:59:39 PM PDT 24
Finished May 19 02:00:53 PM PDT 24
Peak memory 793080 kb
Host smart-9cc33ede-7ba4-410a-8a27-5e90217eba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962157269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1962157269
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.285883379
Short name T232
Test name
Test status
Simulation time 474418349 ps
CPU time 0.94 seconds
Started May 19 01:59:40 PM PDT 24
Finished May 19 01:59:42 PM PDT 24
Peak memory 204740 kb
Host smart-ef0eb1a3-62ed-4bc9-b372-eadd1937e680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285883379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.285883379
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.4294328945
Short name T1238
Test name
Test status
Simulation time 998878888 ps
CPU time 10.42 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:00:09 PM PDT 24
Peak memory 236536 kb
Host smart-437a1103-c1e6-40fe-9468-8a8c78fba37a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294328945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.4294328945
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3032245485
Short name T258
Test name
Test status
Simulation time 3446058181 ps
CPU time 243.2 seconds
Started May 19 01:59:49 PM PDT 24
Finished May 19 02:03:54 PM PDT 24
Peak memory 1034140 kb
Host smart-c31108d5-2ede-49bf-a78d-bbf7004db8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032245485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3032245485
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2533850809
Short name T941
Test name
Test status
Simulation time 821979089 ps
CPU time 5.91 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 01:59:55 PM PDT 24
Peak memory 204992 kb
Host smart-1e700baf-ba9e-425c-99e3-0c96e70439d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533850809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2533850809
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.692364668
Short name T659
Test name
Test status
Simulation time 2187114900 ps
CPU time 39.85 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:00:39 PM PDT 24
Peak memory 317408 kb
Host smart-8dd15cf1-22d8-4e7f-a4ff-1cd6b10cbebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692364668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.692364668
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1959937526
Short name T1301
Test name
Test status
Simulation time 42565925 ps
CPU time 0.67 seconds
Started May 19 01:59:39 PM PDT 24
Finished May 19 01:59:41 PM PDT 24
Peak memory 204684 kb
Host smart-a1aabdcc-6142-4353-a752-e08b83be9868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959937526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1959937526
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3267848925
Short name T59
Test name
Test status
Simulation time 13060489564 ps
CPU time 549.88 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 02:08:57 PM PDT 24
Peak memory 205156 kb
Host smart-29471249-f084-4b30-bdf9-6353a9633594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267848925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3267848925
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3461313011
Short name T947
Test name
Test status
Simulation time 6951801586 ps
CPU time 36.26 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 02:00:21 PM PDT 24
Peak memory 337320 kb
Host smart-d28caab4-7212-41f6-a816-817d7fc348a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461313011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3461313011
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1537662566
Short name T262
Test name
Test status
Simulation time 96484898659 ps
CPU time 995.2 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:16:32 PM PDT 24
Peak memory 1748696 kb
Host smart-b705ff83-0e60-407a-8ea2-84057f9fbdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537662566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1537662566
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2978566800
Short name T1311
Test name
Test status
Simulation time 616519567 ps
CPU time 23.2 seconds
Started May 19 01:59:42 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 213204 kb
Host smart-910ef257-4347-4689-82bf-670df508a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978566800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2978566800
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3699769250
Short name T969
Test name
Test status
Simulation time 1156456957 ps
CPU time 1.99 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 205016 kb
Host smart-df72b649-e71b-4ba6-8b39-679882315283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699769250 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3699769250
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.910960540
Short name T1119
Test name
Test status
Simulation time 10128007224 ps
CPU time 29.1 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 304352 kb
Host smart-2ec57e08-1e99-494a-b694-1599c0d3bcbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910960540 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.910960540
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2982136953
Short name T1008
Test name
Test status
Simulation time 10225214921 ps
CPU time 18.08 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 267136 kb
Host smart-2e02db5f-05bb-4815-9ea8-024a34f2edf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982136953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2982136953
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.131932243
Short name T758
Test name
Test status
Simulation time 461009346 ps
CPU time 3.15 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 01:59:52 PM PDT 24
Peak memory 205004 kb
Host smart-a0664158-44fd-46b2-aea3-75a9ffea03c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131932243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.131932243
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3515845616
Short name T301
Test name
Test status
Simulation time 8042027873 ps
CPU time 8.24 seconds
Started May 19 01:59:44 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 220196 kb
Host smart-60c1a58d-d5eb-4587-8ff5-7d33e0dd6df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515845616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3515845616
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.4177025980
Short name T1315
Test name
Test status
Simulation time 4763561892 ps
CPU time 5.97 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 205108 kb
Host smart-74a5cad2-3329-454e-9a39-b70c93f940ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177025980 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.4177025980
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3339606600
Short name T327
Test name
Test status
Simulation time 2075138700 ps
CPU time 20.2 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 02:00:15 PM PDT 24
Peak memory 204880 kb
Host smart-db6ba512-2b69-42ea-b1a8-1c680049d8f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339606600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3339606600
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3118909917
Short name T139
Test name
Test status
Simulation time 1808007766 ps
CPU time 6.7 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 205828 kb
Host smart-de2ebad0-100f-4d59-bf8a-086a51bf0eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118909917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3118909917
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.49108212
Short name T796
Test name
Test status
Simulation time 55414039622 ps
CPU time 58.13 seconds
Started May 19 01:59:45 PM PDT 24
Finished May 19 02:00:44 PM PDT 24
Peak memory 922488 kb
Host smart-b0ecd887-9657-43a0-a3a6-628e58a8b37d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49108212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stress_wr.49108212
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2031780312
Short name T755
Test name
Test status
Simulation time 8249127800 ps
CPU time 313.86 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 02:05:02 PM PDT 24
Peak memory 2068968 kb
Host smart-a252ff9d-cd02-4507-b907-297c7831ef98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031780312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2031780312
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2829497940
Short name T1317
Test name
Test status
Simulation time 2363471458 ps
CPU time 7.16 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 213304 kb
Host smart-b3b87f37-c0b2-48bc-b92b-d5428233a38d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829497940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2829497940
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.467192535
Short name T325
Test name
Test status
Simulation time 40760176 ps
CPU time 0.62 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 01:59:53 PM PDT 24
Peak memory 204640 kb
Host smart-5d7e4730-36f7-4006-b391-2cea5264c9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467192535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.467192535
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3161537770
Short name T6
Test name
Test status
Simulation time 63927454 ps
CPU time 1.58 seconds
Started May 19 01:59:43 PM PDT 24
Finished May 19 01:59:46 PM PDT 24
Peak memory 213272 kb
Host smart-d2acbafb-793c-47ba-aa84-5d813c720e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161537770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3161537770
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2790099188
Short name T1168
Test name
Test status
Simulation time 184005811 ps
CPU time 3.72 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 240120 kb
Host smart-39748e3d-a806-42b0-8921-69209104c5a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790099188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2790099188
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.403613238
Short name T845
Test name
Test status
Simulation time 11668758814 ps
CPU time 102.95 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 02:01:38 PM PDT 24
Peak memory 905472 kb
Host smart-51025f9f-0d14-4186-90c6-02faa95ab137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403613238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.403613238
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.381953824
Short name T636
Test name
Test status
Simulation time 2474876458 ps
CPU time 183.39 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:03:00 PM PDT 24
Peak memory 738924 kb
Host smart-7906b91c-bd8d-44f9-80a3-36449612c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381953824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.381953824
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.717600169
Short name T1336
Test name
Test status
Simulation time 108427694 ps
CPU time 0.93 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 01:59:50 PM PDT 24
Peak memory 204748 kb
Host smart-37b3fcf0-ae38-4e51-960c-d7790a3d81be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717600169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.717600169
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1407140751
Short name T479
Test name
Test status
Simulation time 598871212 ps
CPU time 3.15 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 01:59:57 PM PDT 24
Peak memory 221804 kb
Host smart-3bdceea4-b243-47b3-9e1f-45938556d6d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407140751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1407140751
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1878903983
Short name T896
Test name
Test status
Simulation time 2716654539 ps
CPU time 164.02 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 02:02:32 PM PDT 24
Peak memory 794276 kb
Host smart-9c9f80b7-193d-4a0c-8739-894a653ce604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878903983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1878903983
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_override.3626554937
Short name T72
Test name
Test status
Simulation time 15952273 ps
CPU time 0.66 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 204720 kb
Host smart-f9af42e7-fc82-48aa-806a-dccb54aee154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626554937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3626554937
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3103428546
Short name T666
Test name
Test status
Simulation time 1046455751 ps
CPU time 11.42 seconds
Started May 19 01:59:46 PM PDT 24
Finished May 19 02:00:00 PM PDT 24
Peak memory 234552 kb
Host smart-3a64ccd5-0d04-42e8-bafe-c3d73b451ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103428546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3103428546
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1077393189
Short name T1204
Test name
Test status
Simulation time 2018547070 ps
CPU time 23.34 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 268564 kb
Host smart-807bbdbc-3dee-40ab-8866-d98e7e2e7d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077393189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1077393189
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2141396524
Short name T1310
Test name
Test status
Simulation time 1488043136 ps
CPU time 35.73 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 02:00:27 PM PDT 24
Peak memory 213152 kb
Host smart-23269e8d-7a96-4bba-bd53-fcd3c5890320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141396524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2141396524
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.199256958
Short name T475
Test name
Test status
Simulation time 1150482611 ps
CPU time 4.76 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 206100 kb
Host smart-7a102fd7-c0d0-40a9-92c3-ee2b88145179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199256958 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.199256958
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.348447066
Short name T775
Test name
Test status
Simulation time 10126028047 ps
CPU time 81.6 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:01:15 PM PDT 24
Peak memory 424140 kb
Host smart-a7750981-ee53-4204-8074-ce4755b916f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348447066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.348447066
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2554366183
Short name T1110
Test name
Test status
Simulation time 10420791815 ps
CPU time 8.24 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 246456 kb
Host smart-9016dbb6-b322-4b12-9728-42632f49264c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554366183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2554366183
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.625917188
Short name T1092
Test name
Test status
Simulation time 445282296 ps
CPU time 2.78 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 01:59:54 PM PDT 24
Peak memory 205012 kb
Host smart-ba0d13c4-07a2-4a86-9da3-bc53e6809628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625917188 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.625917188
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.444659456
Short name T1299
Test name
Test status
Simulation time 2356438311 ps
CPU time 6.61 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 221352 kb
Host smart-7716bb5b-383d-4479-a13d-b974289518a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444659456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.444659456
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.4204787241
Short name T1080
Test name
Test status
Simulation time 10190829592 ps
CPU time 144.41 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:02:24 PM PDT 24
Peak memory 2533864 kb
Host smart-0c59a1a5-6b34-45c6-9aa5-841b77750990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204787241 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.4204787241
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2714315643
Short name T172
Test name
Test status
Simulation time 899047665 ps
CPU time 34.08 seconds
Started May 19 01:59:47 PM PDT 24
Finished May 19 02:00:23 PM PDT 24
Peak memory 204860 kb
Host smart-a910bae3-7005-48b8-b7ee-f86ca2239074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714315643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2714315643
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.65188073
Short name T967
Test name
Test status
Simulation time 1012032928 ps
CPU time 14.4 seconds
Started May 19 01:59:44 PM PDT 24
Finished May 19 02:00:00 PM PDT 24
Peak memory 219092 kb
Host smart-fda6ebe2-79cc-4724-931a-63cc64a599ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65188073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stress_rd.65188073
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.809697765
Short name T1165
Test name
Test status
Simulation time 46610071815 ps
CPU time 809.05 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:13:28 PM PDT 24
Peak memory 6161092 kb
Host smart-c953897c-3e8d-4a36-b194-59681372a727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809697765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.809697765
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1153955931
Short name T874
Test name
Test status
Simulation time 24645773316 ps
CPU time 58 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:56 PM PDT 24
Peak memory 566684 kb
Host smart-cd196dd8-9858-43da-b3d1-2ddfd51d05c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153955931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1153955931
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2846530752
Short name T577
Test name
Test status
Simulation time 1633808045 ps
CPU time 8.54 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 217556 kb
Host smart-f7c19634-95a3-481e-bbe2-85629fdbbe6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846530752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2846530752
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1828742442
Short name T373
Test name
Test status
Simulation time 25237613 ps
CPU time 0.63 seconds
Started May 19 01:59:59 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 204860 kb
Host smart-1200fbbf-9591-4ee9-bb3e-310c7e9d10bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828742442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1828742442
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2055412253
Short name T333
Test name
Test status
Simulation time 256701089 ps
CPU time 5.9 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 01:59:58 PM PDT 24
Peak memory 233416 kb
Host smart-cfe5c889-b3db-457c-a135-82c4a22937ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055412253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2055412253
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.67625078
Short name T1118
Test name
Test status
Simulation time 372954666 ps
CPU time 19.45 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 283052 kb
Host smart-d5b5abeb-3c26-48ba-b1a1-cc3184db3c59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67625078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty
.67625078
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3261541054
Short name T76
Test name
Test status
Simulation time 6550615617 ps
CPU time 95.04 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 418912 kb
Host smart-d8f0c438-35cc-4baf-bcec-0f71b43ace34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261541054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3261541054
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2651816494
Short name T1130
Test name
Test status
Simulation time 6217735172 ps
CPU time 50.21 seconds
Started May 19 02:00:01 PM PDT 24
Finished May 19 02:00:53 PM PDT 24
Peak memory 562520 kb
Host smart-38fce703-4c67-42a8-b0f4-a920bbf341fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651816494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2651816494
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2431872216
Short name T507
Test name
Test status
Simulation time 389393114 ps
CPU time 0.93 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 01:59:53 PM PDT 24
Peak memory 204748 kb
Host smart-94ebaf46-da79-4b1f-8d81-65bedf31746b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431872216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2431872216
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3457996614
Short name T334
Test name
Test status
Simulation time 2925774554 ps
CPU time 7.62 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 205100 kb
Host smart-fdbefc7a-9bd8-4697-ab8f-3f06fa8a317a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457996614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3457996614
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.641645731
Short name T864
Test name
Test status
Simulation time 4935426926 ps
CPU time 122.75 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:02:02 PM PDT 24
Peak memory 1285392 kb
Host smart-e9523e45-e8fc-45dc-a7de-a8ff2ef4950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641645731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.641645731
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2163279090
Short name T770
Test name
Test status
Simulation time 1944444067 ps
CPU time 7.38 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 205000 kb
Host smart-6e3f1a23-ee8c-43c5-a30f-04d13f497bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163279090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2163279090
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.877177529
Short name T237
Test name
Test status
Simulation time 1206003199 ps
CPU time 16.42 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:17 PM PDT 24
Peak memory 269844 kb
Host smart-27c3dde0-be2c-4e38-8639-37bf6b516fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877177529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.877177529
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2981621141
Short name T1288
Test name
Test status
Simulation time 29473619 ps
CPU time 0.71 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 01:59:56 PM PDT 24
Peak memory 204656 kb
Host smart-2459db29-2b29-466e-9c4d-63749938a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981621141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2981621141
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1209761915
Short name T1068
Test name
Test status
Simulation time 632385083 ps
CPU time 3.45 seconds
Started May 19 01:59:52 PM PDT 24
Finished May 19 01:59:58 PM PDT 24
Peak memory 232688 kb
Host smart-f13f9d85-d939-4792-b01c-9688835b10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209761915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1209761915
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2203086103
Short name T798
Test name
Test status
Simulation time 1781706003 ps
CPU time 33.23 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 02:00:25 PM PDT 24
Peak memory 326184 kb
Host smart-2d54ee6f-a468-471f-a58c-f3712b63bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203086103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2203086103
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2712361299
Short name T210
Test name
Test status
Simulation time 3735094839 ps
CPU time 16.32 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 221368 kb
Host smart-b013aec8-6f7a-4ad1-a05d-0d41e9c60b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712361299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2712361299
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3407395829
Short name T767
Test name
Test status
Simulation time 542677052 ps
CPU time 3.38 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 204988 kb
Host smart-28c7181c-6b04-4d21-a0cf-7911081187c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407395829 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3407395829
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.515659429
Short name T572
Test name
Test status
Simulation time 10050033432 ps
CPU time 77.18 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 491128 kb
Host smart-a98a08d8-425a-41ed-b10c-8ec754d3bdc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515659429 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.515659429
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.152502928
Short name T425
Test name
Test status
Simulation time 10168504211 ps
CPU time 15.56 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:13 PM PDT 24
Peak memory 295776 kb
Host smart-645a59ac-3535-4077-83d8-b14540c5718f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152502928 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.152502928
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2057615062
Short name T814
Test name
Test status
Simulation time 329293145 ps
CPU time 2.23 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 205040 kb
Host smart-0cb321a5-12b2-4e88-a48b-0fca0cdc89d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057615062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2057615062
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1777716485
Short name T509
Test name
Test status
Simulation time 6322616914 ps
CPU time 5.71 seconds
Started May 19 02:00:02 PM PDT 24
Finished May 19 02:00:09 PM PDT 24
Peak memory 213268 kb
Host smart-8a23fd78-7b53-49c2-8034-4af132498b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777716485 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1777716485
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2208204340
Short name T429
Test name
Test status
Simulation time 5383463809 ps
CPU time 4 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 205132 kb
Host smart-f3b8c7c6-9fc8-4e91-8fd4-c801be4fad79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208204340 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2208204340
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1910835606
Short name T541
Test name
Test status
Simulation time 1925722761 ps
CPU time 16.69 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 204988 kb
Host smart-230e39cb-d524-4d44-9009-85e98b0ae36c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910835606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1910835606
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.154365105
Short name T1196
Test name
Test status
Simulation time 4909961783 ps
CPU time 52.07 seconds
Started May 19 01:59:50 PM PDT 24
Finished May 19 02:00:44 PM PDT 24
Peak memory 206092 kb
Host smart-6d789a00-fb2d-4e2e-bebf-9dad28db3e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154365105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.154365105
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1145622656
Short name T1124
Test name
Test status
Simulation time 34174557076 ps
CPU time 373.2 seconds
Started May 19 01:59:51 PM PDT 24
Finished May 19 02:06:06 PM PDT 24
Peak memory 3631612 kb
Host smart-30e95962-386a-4664-9a70-883d3650b3d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145622656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1145622656
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1009592861
Short name T184
Test name
Test status
Simulation time 9734120524 ps
CPU time 46 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:46 PM PDT 24
Peak memory 689952 kb
Host smart-7a53880c-f80e-4573-9af2-59e4db03bcef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009592861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1009592861
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.792981618
Short name T863
Test name
Test status
Simulation time 1199167575 ps
CPU time 7.29 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 213168 kb
Host smart-e3de1faa-e611-49c3-ae31-cab9ba487d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792981618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.792981618
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1166093696
Short name T697
Test name
Test status
Simulation time 14897481 ps
CPU time 0.64 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 204588 kb
Host smart-8bdb110f-a5a8-4511-ba16-5fced347fc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166093696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1166093696
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3302382906
Short name T650
Test name
Test status
Simulation time 905010003 ps
CPU time 1.38 seconds
Started May 19 01:59:59 PM PDT 24
Finished May 19 02:00:03 PM PDT 24
Peak memory 213172 kb
Host smart-841f09eb-32a5-436f-ad92-67c937ff167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302382906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3302382906
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3714078250
Short name T1154
Test name
Test status
Simulation time 317933973 ps
CPU time 16.49 seconds
Started May 19 02:00:01 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 273080 kb
Host smart-a8eb7264-bb23-42c6-a54a-07b360ecd9a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714078250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3714078250
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3294895066
Short name T893
Test name
Test status
Simulation time 3096347531 ps
CPU time 130.53 seconds
Started May 19 02:00:02 PM PDT 24
Finished May 19 02:02:14 PM PDT 24
Peak memory 961728 kb
Host smart-fd0bf77c-9b8c-422d-86bb-ff0c0253955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294895066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3294895066
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2791293976
Short name T303
Test name
Test status
Simulation time 1608071084 ps
CPU time 56.11 seconds
Started May 19 02:00:06 PM PDT 24
Finished May 19 02:01:03 PM PDT 24
Peak memory 604472 kb
Host smart-11dc22ba-6924-41eb-a39b-1b9b9e827b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791293976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2791293976
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2877376264
Short name T4
Test name
Test status
Simulation time 143957242 ps
CPU time 1.04 seconds
Started May 19 02:00:03 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 204764 kb
Host smart-6a6b83b7-44db-45cc-ba35-4250cd676be4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877376264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2877376264
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1647881296
Short name T412
Test name
Test status
Simulation time 438278222 ps
CPU time 2.97 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 204976 kb
Host smart-87333889-8dae-4ad8-afeb-ebfeec03f4c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647881296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1647881296
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.281255914
Short name T317
Test name
Test status
Simulation time 9477036228 ps
CPU time 78.24 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 02:01:13 PM PDT 24
Peak memory 889936 kb
Host smart-65523f34-5b3c-4cb7-9630-8ac47aff8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281255914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.281255914
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2627619070
Short name T762
Test name
Test status
Simulation time 867198729 ps
CPU time 5.59 seconds
Started May 19 02:00:08 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 204972 kb
Host smart-276b3a4f-e23b-42e9-b280-0df6ccbac11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627619070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2627619070
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3182120216
Short name T680
Test name
Test status
Simulation time 1435385176 ps
CPU time 74.22 seconds
Started May 19 02:00:08 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 462668 kb
Host smart-60f3b194-e28b-429b-8ea0-2907325109cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182120216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3182120216
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.425065519
Short name T1180
Test name
Test status
Simulation time 21505407 ps
CPU time 0.67 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 204692 kb
Host smart-eb15d9bc-4c72-40d1-917c-5d225aa77243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425065519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.425065519
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1863730013
Short name T788
Test name
Test status
Simulation time 3319683022 ps
CPU time 15.98 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:12 PM PDT 24
Peak memory 364548 kb
Host smart-dfa7675a-2383-46fd-90c1-dda6a0b61880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863730013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1863730013
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1292447656
Short name T1235
Test name
Test status
Simulation time 2450779539 ps
CPU time 21.54 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 249160 kb
Host smart-cf379375-63af-4810-9942-388d2b685648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292447656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1292447656
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.763257144
Short name T268
Test name
Test status
Simulation time 12750211154 ps
CPU time 1591.6 seconds
Started May 19 01:59:57 PM PDT 24
Finished May 19 02:26:31 PM PDT 24
Peak memory 2223812 kb
Host smart-915c12b6-5fc8-475a-8df9-b6b1c54035dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763257144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.763257144
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.888200125
Short name T1292
Test name
Test status
Simulation time 743076754 ps
CPU time 34.39 seconds
Started May 19 02:00:02 PM PDT 24
Finished May 19 02:00:37 PM PDT 24
Peak memory 213152 kb
Host smart-dff84178-2665-4709-9a62-ccfbb44f3fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888200125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.888200125
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2473397647
Short name T959
Test name
Test status
Simulation time 1471903503 ps
CPU time 3.2 seconds
Started May 19 02:00:00 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 204980 kb
Host smart-f23ab04d-34d8-486a-b8e1-74a27551efb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473397647 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2473397647
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.255224905
Short name T272
Test name
Test status
Simulation time 10099558561 ps
CPU time 53.78 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:54 PM PDT 24
Peak memory 467988 kb
Host smart-df836fd1-9571-4867-85d4-a9177b18912c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255224905 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.255224905
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3129126045
Short name T470
Test name
Test status
Simulation time 375959869 ps
CPU time 2.47 seconds
Started May 19 02:00:05 PM PDT 24
Finished May 19 02:00:09 PM PDT 24
Peak memory 205032 kb
Host smart-d0de4a3e-5542-400e-8fa0-160f522a502c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129126045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3129126045
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2978043642
Short name T602
Test name
Test status
Simulation time 2616902812 ps
CPU time 3.36 seconds
Started May 19 01:59:53 PM PDT 24
Finished May 19 01:59:59 PM PDT 24
Peak memory 205084 kb
Host smart-2a29c523-0339-48f7-9317-2cb476f390e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978043642 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2978043642
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4010119698
Short name T444
Test name
Test status
Simulation time 8723032116 ps
CPU time 7.03 seconds
Started May 19 02:00:06 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 205128 kb
Host smart-a1bbb108-b5a5-46a5-8b60-e3afeeb40ee8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010119698 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4010119698
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1471886188
Short name T868
Test name
Test status
Simulation time 5152596687 ps
CPU time 35.45 seconds
Started May 19 01:59:54 PM PDT 24
Finished May 19 02:00:32 PM PDT 24
Peak memory 205048 kb
Host smart-ab3ccdbe-527e-4495-872d-957553e77cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471886188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1471886188
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3401755737
Short name T812
Test name
Test status
Simulation time 222464762 ps
CPU time 4.53 seconds
Started May 19 02:00:16 PM PDT 24
Finished May 19 02:00:22 PM PDT 24
Peak memory 204952 kb
Host smart-46899ec7-4fa4-48c5-a362-26b4fec0ae5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401755737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3401755737
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2302066362
Short name T638
Test name
Test status
Simulation time 57331061783 ps
CPU time 1616.63 seconds
Started May 19 02:00:13 PM PDT 24
Finished May 19 02:27:11 PM PDT 24
Peak memory 8989108 kb
Host smart-aa4538c1-86aa-41ee-a24b-e3428864f68f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302066362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2302066362
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1224743368
Short name T533
Test name
Test status
Simulation time 26896121163 ps
CPU time 194.07 seconds
Started May 19 01:59:55 PM PDT 24
Finished May 19 02:03:12 PM PDT 24
Peak memory 1640400 kb
Host smart-a2956be3-e517-42d2-8d88-d0976d6c1e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224743368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1224743368
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2055230896
Short name T70
Test name
Test status
Simulation time 6425098550 ps
CPU time 8.21 seconds
Started May 19 01:59:56 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 213300 kb
Host smart-8493b2ce-4f3e-4126-a559-771c92b75f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055230896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2055230896
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.4074427712
Short name T174
Test name
Test status
Simulation time 41706703 ps
CPU time 0.62 seconds
Started May 19 02:00:06 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 204624 kb
Host smart-72ce3141-1449-4520-aa37-e5e7ad054adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074427712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.4074427712
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2610953671
Short name T431
Test name
Test status
Simulation time 219352779 ps
CPU time 1.76 seconds
Started May 19 02:00:02 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 213260 kb
Host smart-0593e6a5-5fad-4c5b-8052-751b330119a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610953671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2610953671
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2414380894
Short name T389
Test name
Test status
Simulation time 367044307 ps
CPU time 18.85 seconds
Started May 19 02:00:07 PM PDT 24
Finished May 19 02:00:27 PM PDT 24
Peak memory 277244 kb
Host smart-754fafd9-755e-4960-a8bd-bf55d592dd9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414380894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2414380894
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3226493660
Short name T150
Test name
Test status
Simulation time 8796117626 ps
CPU time 42.01 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:43 PM PDT 24
Peak memory 383036 kb
Host smart-c7e1cefb-e42f-4c7b-b166-b36907afcac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226493660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3226493660
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1014812705
Short name T579
Test name
Test status
Simulation time 3724846013 ps
CPU time 146.53 seconds
Started May 19 02:00:13 PM PDT 24
Finished May 19 02:02:41 PM PDT 24
Peak memory 669756 kb
Host smart-684382e1-d24f-4ff3-a81a-02c8bd87f79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014812705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1014812705
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.758862576
Short name T169
Test name
Test status
Simulation time 90174289 ps
CPU time 0.86 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:01 PM PDT 24
Peak memory 204796 kb
Host smart-9916a22a-55f1-4a17-a311-f549640bf208
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758862576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fm
t.758862576
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3671343038
Short name T155
Test name
Test status
Simulation time 207678811 ps
CPU time 5.94 seconds
Started May 19 02:00:00 PM PDT 24
Finished May 19 02:00:07 PM PDT 24
Peak memory 241856 kb
Host smart-b4e5de8e-4624-4956-ac55-6fbda0b71816
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671343038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3671343038
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2393381826
Short name T256
Test name
Test status
Simulation time 7537183155 ps
CPU time 263.21 seconds
Started May 19 02:00:02 PM PDT 24
Finished May 19 02:04:26 PM PDT 24
Peak memory 1056372 kb
Host smart-15ecc2db-5194-4bdc-81f0-0996d6c76d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393381826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2393381826
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1308775584
Short name T355
Test name
Test status
Simulation time 2122391430 ps
CPU time 6.89 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:00:12 PM PDT 24
Peak memory 204960 kb
Host smart-d7a03f73-4e2e-48d7-88ec-13730fc37fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308775584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1308775584
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2366370280
Short name T629
Test name
Test status
Simulation time 2576719172 ps
CPU time 18.82 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 301944 kb
Host smart-83dbc6f9-c790-4122-b2bc-b84483638614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366370280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2366370280
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.382546576
Short name T136
Test name
Test status
Simulation time 42048284 ps
CPU time 0.65 seconds
Started May 19 02:00:00 PM PDT 24
Finished May 19 02:00:02 PM PDT 24
Peak memory 204692 kb
Host smart-9941dc8b-b466-4b32-8043-7297d9f3dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382546576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.382546576
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2014122727
Short name T1032
Test name
Test status
Simulation time 4209106128 ps
CPU time 17.28 seconds
Started May 19 01:59:59 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 326340 kb
Host smart-b94ca962-f4ad-4538-afc4-507b1a333094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014122727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2014122727
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2832544977
Short name T1113
Test name
Test status
Simulation time 1651532417 ps
CPU time 15.95 seconds
Started May 19 01:59:58 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 214244 kb
Host smart-cc879659-aa73-461c-8f07-ee4fc4100470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832544977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2832544977
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.592685623
Short name T448
Test name
Test status
Simulation time 591331094 ps
CPU time 3.42 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 205156 kb
Host smart-0631ea1b-a35c-4b68-a7ac-fb6aef396dba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592685623 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.592685623
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2043313579
Short name T89
Test name
Test status
Simulation time 10061122159 ps
CPU time 70.37 seconds
Started May 19 02:00:07 PM PDT 24
Finished May 19 02:01:19 PM PDT 24
Peak memory 478224 kb
Host smart-0271b9b3-9fec-4d52-8b38-dc2f9adfb49f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043313579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2043313579
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.680650766
Short name T434
Test name
Test status
Simulation time 10104728536 ps
CPU time 79.12 seconds
Started May 19 02:00:03 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 472452 kb
Host smart-f17db3c0-7bd8-452f-b092-1bc30da79862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680650766 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.680650766
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1737570196
Short name T1214
Test name
Test status
Simulation time 2102003911 ps
CPU time 2.66 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 204960 kb
Host smart-1e133356-9ef2-46b0-a441-d1fa93846aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737570196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1737570196
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.174454040
Short name T722
Test name
Test status
Simulation time 1080650666 ps
CPU time 6.14 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 218504 kb
Host smart-8aa09466-10d2-4905-9eaf-d76981d8a5c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174454040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_intr_smoke.174454040
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.72689410
Short name T427
Test name
Test status
Simulation time 4120529531 ps
CPU time 5.32 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:28 PM PDT 24
Peak memory 205052 kb
Host smart-09ff3619-c4c7-4ff8-b89f-e1adf2ebb7db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72689410 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.72689410
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.584769761
Short name T1026
Test name
Test status
Simulation time 3174832750 ps
CPU time 12.4 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:00:25 PM PDT 24
Peak memory 204980 kb
Host smart-1d682c6b-2bc3-4f80-bd1c-b475ce540c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584769761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.584769761
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1669459859
Short name T554
Test name
Test status
Simulation time 2495584696 ps
CPU time 54.31 seconds
Started May 19 02:00:13 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 208000 kb
Host smart-93e14e30-434d-4158-9939-241b2f5fd5a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669459859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1669459859
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.3776478448
Short name T1076
Test name
Test status
Simulation time 11551858228 ps
CPU time 5.58 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 205088 kb
Host smart-ac2fc518-e154-4a21-b13b-da22f33f3d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776478448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.3776478448
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.423570904
Short name T340
Test name
Test status
Simulation time 7085413347 ps
CPU time 34.98 seconds
Started May 19 02:00:05 PM PDT 24
Finished May 19 02:00:40 PM PDT 24
Peak memory 568900 kb
Host smart-40c7eeaf-2048-4a3a-9b89-3f9c5664ea37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423570904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_t
arget_stretch.423570904
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3326631938
Short name T826
Test name
Test status
Simulation time 4906893820 ps
CPU time 7.13 seconds
Started May 19 02:00:03 PM PDT 24
Finished May 19 02:00:11 PM PDT 24
Peak memory 219392 kb
Host smart-0696042d-ebbc-4039-87ca-43f7ed1c9d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326631938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3326631938
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2654196591
Short name T827
Test name
Test status
Simulation time 50382129 ps
CPU time 0.62 seconds
Started May 19 02:00:14 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 204640 kb
Host smart-f69aaa86-d863-4988-848a-7dd83dc93b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654196591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2654196591
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1995139764
Short name T658
Test name
Test status
Simulation time 287673012 ps
CPU time 1.35 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 215844 kb
Host smart-4d74d04f-0699-4ff8-9a32-483b3161b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995139764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1995139764
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3991100561
Short name T1024
Test name
Test status
Simulation time 2781968703 ps
CPU time 13.6 seconds
Started May 19 02:00:07 PM PDT 24
Finished May 19 02:00:22 PM PDT 24
Peak memory 359836 kb
Host smart-43646082-ce58-48ab-a53f-df9a48874192
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991100561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3991100561
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4233362260
Short name T86
Test name
Test status
Simulation time 8769076418 ps
CPU time 65.03 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:01:10 PM PDT 24
Peak memory 688788 kb
Host smart-9a6f7efb-96ea-4145-a646-72d578f70148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233362260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4233362260
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2377445856
Short name T953
Test name
Test status
Simulation time 9621656695 ps
CPU time 60.1 seconds
Started May 19 02:00:08 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 604436 kb
Host smart-2b9b4e90-3510-470d-8f44-1d319b031289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377445856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2377445856
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1551784367
Short name T639
Test name
Test status
Simulation time 111686199 ps
CPU time 1.07 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 204952 kb
Host smart-8e4c21aa-6ff2-44ba-9d28-63a24fa73aeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551784367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1551784367
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.499250563
Short name T1018
Test name
Test status
Simulation time 204182202 ps
CPU time 5.29 seconds
Started May 19 02:00:16 PM PDT 24
Finished May 19 02:00:23 PM PDT 24
Peak memory 244864 kb
Host smart-68134f5a-e4c5-4192-9734-3df331dd7498
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499250563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
499250563
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.753224199
Short name T1340
Test name
Test status
Simulation time 11345201153 ps
CPU time 162.59 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:02:55 PM PDT 24
Peak memory 769332 kb
Host smart-1c9c4934-d8b5-4114-bbed-60c36c508939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753224199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.753224199
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.150361485
Short name T384
Test name
Test status
Simulation time 341537671 ps
CPU time 4.51 seconds
Started May 19 02:00:11 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 204868 kb
Host smart-df0f8130-6dd3-4817-a0a5-b9223011f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150361485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.150361485
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2697941461
Short name T696
Test name
Test status
Simulation time 11351700433 ps
CPU time 51.04 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 455700 kb
Host smart-34ff311a-7130-4db6-adc6-bb021157c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697941461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2697941461
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.444277875
Short name T1256
Test name
Test status
Simulation time 24954417 ps
CPU time 0.67 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:00:06 PM PDT 24
Peak memory 204704 kb
Host smart-a030a8b1-d91d-4d04-955f-dcc66b9ee388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444277875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.444277875
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1945812815
Short name T1061
Test name
Test status
Simulation time 52002776840 ps
CPU time 1322.5 seconds
Started May 19 02:00:06 PM PDT 24
Finished May 19 02:22:10 PM PDT 24
Peak memory 2649736 kb
Host smart-c98da3c8-78f5-4f9a-b36a-3be21c96bef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945812815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1945812815
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2166803912
Short name T5
Test name
Test status
Simulation time 1769957346 ps
CPU time 37.86 seconds
Started May 19 02:00:04 PM PDT 24
Finished May 19 02:00:43 PM PDT 24
Peak memory 376680 kb
Host smart-b94deebe-c77b-4179-b5a7-03d368ac0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166803912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2166803912
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3617526273
Short name T818
Test name
Test status
Simulation time 67015107728 ps
CPU time 1364.2 seconds
Started May 19 02:00:11 PM PDT 24
Finished May 19 02:22:56 PM PDT 24
Peak memory 3557716 kb
Host smart-eb8648d2-3b62-44db-bee6-a1c68c0367e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617526273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3617526273
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1581185335
Short name T480
Test name
Test status
Simulation time 2370810341 ps
CPU time 12.4 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:31 PM PDT 24
Peak memory 221500 kb
Host smart-4452661d-3863-44b7-9f31-a3f81ae6703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581185335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1581185335
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2262192462
Short name T791
Test name
Test status
Simulation time 818585747 ps
CPU time 3.96 seconds
Started May 19 02:00:09 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 204992 kb
Host smart-b6a29965-cf71-46af-a1ca-168d937e53de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262192462 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2262192462
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2089265569
Short name T1174
Test name
Test status
Simulation time 10027511846 ps
CPU time 84.74 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:01:44 PM PDT 24
Peak memory 431272 kb
Host smart-01baa959-fdf7-447b-bad3-ea3d962d0719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089265569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2089265569
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2992775523
Short name T555
Test name
Test status
Simulation time 10042590623 ps
CPU time 28.64 seconds
Started May 19 02:00:07 PM PDT 24
Finished May 19 02:00:37 PM PDT 24
Peak memory 381744 kb
Host smart-681dd943-428b-447d-80df-2e95554d6b61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992775523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2992775523
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3375952650
Short name T543
Test name
Test status
Simulation time 417276474 ps
CPU time 2.74 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 205060 kb
Host smart-20811cbc-0e26-47bb-87ad-3aa9b9f75090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375952650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3375952650
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2334387349
Short name T1099
Test name
Test status
Simulation time 943450620 ps
CPU time 5.3 seconds
Started May 19 02:00:09 PM PDT 24
Finished May 19 02:00:15 PM PDT 24
Peak memory 204952 kb
Host smart-1baf97ca-f0c3-40c7-8007-6ddff6ac3fd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334387349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2334387349
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2093449490
Short name T1143
Test name
Test status
Simulation time 8871093103 ps
CPU time 27.25 seconds
Started May 19 02:00:07 PM PDT 24
Finished May 19 02:00:35 PM PDT 24
Peak memory 484632 kb
Host smart-ef4dcc97-5b92-44ca-9ea5-9cf3fdbcabcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093449490 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2093449490
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1529498040
Short name T568
Test name
Test status
Simulation time 4695829869 ps
CPU time 30.34 seconds
Started May 19 02:00:06 PM PDT 24
Finished May 19 02:00:37 PM PDT 24
Peak memory 205060 kb
Host smart-bfef8d5c-c168-422f-bc61-2e0f354e9e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529498040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1529498040
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2191473716
Short name T746
Test name
Test status
Simulation time 778262770 ps
CPU time 16.91 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:33 PM PDT 24
Peak memory 204976 kb
Host smart-103600ac-9789-46e1-bafa-b03d8807a63f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191473716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2191473716
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.988569126
Short name T1148
Test name
Test status
Simulation time 16282622062 ps
CPU time 31.28 seconds
Started May 19 02:00:09 PM PDT 24
Finished May 19 02:00:41 PM PDT 24
Peak memory 205120 kb
Host smart-90006d10-b53a-454d-b7a8-1541fe95cbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988569126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.988569126
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.569972037
Short name T760
Test name
Test status
Simulation time 6147355609 ps
CPU time 29.24 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:00:43 PM PDT 24
Peak memory 474788 kb
Host smart-8f8dd760-733d-413d-8a95-d7e93562d6de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569972037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.569972037
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1328925212
Short name T1006
Test name
Test status
Simulation time 6205807704 ps
CPU time 7.85 seconds
Started May 19 02:00:11 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 218700 kb
Host smart-05873520-af05-4c3c-a30b-46e9a2f90dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328925212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1328925212
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2235991594
Short name T709
Test name
Test status
Simulation time 20716742 ps
CPU time 0.63 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 204588 kb
Host smart-4481ff68-f84a-4ba3-afe9-242ca7776bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235991594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2235991594
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2319621334
Short name T1132
Test name
Test status
Simulation time 183923264 ps
CPU time 7.48 seconds
Started May 19 02:00:18 PM PDT 24
Finished May 19 02:00:27 PM PDT 24
Peak memory 237372 kb
Host smart-cd63f13a-34a0-4136-b3b3-73f8b2b38cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319621334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2319621334
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2353824154
Short name T557
Test name
Test status
Simulation time 6157430052 ps
CPU time 9.59 seconds
Started May 19 02:00:16 PM PDT 24
Finished May 19 02:00:27 PM PDT 24
Peak memory 291532 kb
Host smart-76576c1e-5019-4d78-ba76-de340752728f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353824154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2353824154
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3165822533
Short name T992
Test name
Test status
Simulation time 9689159008 ps
CPU time 83.25 seconds
Started May 19 02:00:11 PM PDT 24
Finished May 19 02:01:34 PM PDT 24
Peak memory 810616 kb
Host smart-ab094567-cb39-4e19-9d96-31d6b7d6ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165822533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3165822533
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2876865296
Short name T1103
Test name
Test status
Simulation time 6802704218 ps
CPU time 48.39 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:01:05 PM PDT 24
Peak memory 610668 kb
Host smart-62488ca1-aa9c-4dfa-96f6-ba7e06ff5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876865296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2876865296
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2859212299
Short name T635
Test name
Test status
Simulation time 746669884 ps
CPU time 1.12 seconds
Started May 19 02:00:13 PM PDT 24
Finished May 19 02:00:15 PM PDT 24
Peak memory 204980 kb
Host smart-94e84a57-42c2-4f87-8f6a-a3989a0d6472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859212299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2859212299
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.439074555
Short name T1334
Test name
Test status
Simulation time 748824382 ps
CPU time 9.69 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:29 PM PDT 24
Peak memory 234160 kb
Host smart-6be0f431-9a72-431e-88be-e405094a33b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439074555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
439074555
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3952096343
Short name T701
Test name
Test status
Simulation time 6580604945 ps
CPU time 183.65 seconds
Started May 19 02:00:10 PM PDT 24
Finished May 19 02:03:14 PM PDT 24
Peak memory 1471656 kb
Host smart-eb035292-a75b-4af1-b5b5-895956be6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952096343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3952096343
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1274181722
Short name T236
Test name
Test status
Simulation time 6862783630 ps
CPU time 6.81 seconds
Started May 19 02:00:11 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 205140 kb
Host smart-099f7004-ecfa-400b-84fb-e5fdc961a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274181722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1274181722
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3964672263
Short name T1014
Test name
Test status
Simulation time 2111085283 ps
CPU time 42.62 seconds
Started May 19 02:00:36 PM PDT 24
Finished May 19 02:01:20 PM PDT 24
Peak memory 494544 kb
Host smart-b1fd391e-b3db-426d-8271-3867f978a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964672263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3964672263
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1496625358
Short name T1300
Test name
Test status
Simulation time 108191550 ps
CPU time 0.72 seconds
Started May 19 02:00:15 PM PDT 24
Finished May 19 02:00:18 PM PDT 24
Peak memory 204704 kb
Host smart-96117256-b567-47e8-bd27-2ec805bb4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496625358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1496625358
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2646718593
Short name T38
Test name
Test status
Simulation time 6817116087 ps
CPU time 93.49 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:01:46 PM PDT 24
Peak memory 824452 kb
Host smart-76e20d97-c019-47ef-9ec0-8b25b6767bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646718593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2646718593
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3879459249
Short name T302
Test name
Test status
Simulation time 1656453405 ps
CPU time 32.49 seconds
Started May 19 02:00:16 PM PDT 24
Finished May 19 02:00:50 PM PDT 24
Peak memory 368764 kb
Host smart-dc66d3f9-83f0-4858-aaa5-612bcb755c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879459249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3879459249
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.819712919
Short name T1122
Test name
Test status
Simulation time 10632132339 ps
CPU time 1263.38 seconds
Started May 19 02:00:14 PM PDT 24
Finished May 19 02:21:18 PM PDT 24
Peak memory 2371624 kb
Host smart-7a65b2c6-65d7-4cf2-a032-26d19114d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819712919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.819712919
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2817322835
Short name T850
Test name
Test status
Simulation time 3786895148 ps
CPU time 12.47 seconds
Started May 19 02:00:18 PM PDT 24
Finished May 19 02:00:32 PM PDT 24
Peak memory 220400 kb
Host smart-27d7d544-8fb3-4bcb-8268-71dc6d68f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817322835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2817322835
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3797697637
Short name T684
Test name
Test status
Simulation time 5263951934 ps
CPU time 5.38 seconds
Started May 19 02:00:18 PM PDT 24
Finished May 19 02:00:25 PM PDT 24
Peak memory 205320 kb
Host smart-995c5d2d-a6e5-4879-8bcc-73e29c77f7fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797697637 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3797697637
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3125117655
Short name T426
Test name
Test status
Simulation time 10660735936 ps
CPU time 9.35 seconds
Started May 19 02:00:14 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 237124 kb
Host smart-76f035a4-f4dc-4490-a883-7e5a81940068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125117655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3125117655
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3705613065
Short name T351
Test name
Test status
Simulation time 10148071531 ps
CPU time 31.45 seconds
Started May 19 02:00:16 PM PDT 24
Finished May 19 02:00:49 PM PDT 24
Peak memory 400472 kb
Host smart-0262644c-6221-41d3-bbc6-325e7ed0fe17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705613065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3705613065
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2886509791
Short name T801
Test name
Test status
Simulation time 386921674 ps
CPU time 2.72 seconds
Started May 19 02:00:23 PM PDT 24
Finished May 19 02:00:27 PM PDT 24
Peak memory 205008 kb
Host smart-d401654f-70a8-4d45-afed-ccc01db06cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886509791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2886509791
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3371984787
Short name T685
Test name
Test status
Simulation time 1471583325 ps
CPU time 4.28 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:23 PM PDT 24
Peak memory 205444 kb
Host smart-2a8c3230-eb63-473a-a9a7-85356e74d032
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371984787 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3371984787
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.3424091285
Short name T309
Test name
Test status
Simulation time 15760262201 ps
CPU time 28.42 seconds
Started May 19 02:00:40 PM PDT 24
Finished May 19 02:01:09 PM PDT 24
Peak memory 580108 kb
Host smart-7e297ce9-4dd7-41b4-ac2c-8ee366a8885d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424091285 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3424091285
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.4022006355
Short name T1054
Test name
Test status
Simulation time 2085759697 ps
CPU time 16.81 seconds
Started May 19 02:00:12 PM PDT 24
Finished May 19 02:00:29 PM PDT 24
Peak memory 204900 kb
Host smart-7325ebc1-f6bf-4ffe-8230-6b6931f3c65d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022006355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.4022006355
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4088775658
Short name T1056
Test name
Test status
Simulation time 2980142409 ps
CPU time 11.8 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:00:30 PM PDT 24
Peak memory 213376 kb
Host smart-bbe69dad-49ea-479d-8016-1d6e3be1f8ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088775658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4088775658
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1813785591
Short name T653
Test name
Test status
Simulation time 68441764784 ps
CPU time 835.69 seconds
Started May 19 02:00:17 PM PDT 24
Finished May 19 02:14:15 PM PDT 24
Peak memory 6008976 kb
Host smart-87c10a9e-fc80-4978-8648-71e700a00111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813785591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1813785591
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.931676153
Short name T934
Test name
Test status
Simulation time 2526078186 ps
CPU time 6.35 seconds
Started May 19 02:00:18 PM PDT 24
Finished May 19 02:00:26 PM PDT 24
Peak memory 213292 kb
Host smart-7a3b078b-6cb1-4ab8-9f47-6be04bdb3d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931676153 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.931676153
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1178570007
Short name T1182
Test name
Test status
Simulation time 138487900 ps
CPU time 0.62 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 204636 kb
Host smart-019ceec2-6244-4314-b323-e7ae3e7371b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178570007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1178570007
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1189584028
Short name T1016
Test name
Test status
Simulation time 82812022 ps
CPU time 2.39 seconds
Started May 19 01:56:37 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 213284 kb
Host smart-d966ca32-a1b4-446d-94c2-33c34170239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189584028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1189584028
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1440418501
Short name T1236
Test name
Test status
Simulation time 2179769612 ps
CPU time 9.87 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 317588 kb
Host smart-233d49b8-1a2a-41b2-898d-47141c96a29d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440418501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1440418501
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.4245170879
Short name T1312
Test name
Test status
Simulation time 3509426587 ps
CPU time 63.41 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:51 PM PDT 24
Peak memory 631340 kb
Host smart-5ef1e8fa-ee16-4a7f-b76d-93b4b633dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245170879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.4245170879
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1654354681
Short name T723
Test name
Test status
Simulation time 12960830093 ps
CPU time 71.41 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 748540 kb
Host smart-201320d9-8c62-4fef-9369-78b8cb6cbf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654354681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1654354681
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1765105039
Short name T1227
Test name
Test status
Simulation time 138812953 ps
CPU time 1 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:56:52 PM PDT 24
Peak memory 204896 kb
Host smart-b48aba60-87d3-4554-b437-95b325669e7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765105039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1765105039
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3176402937
Short name T399
Test name
Test status
Simulation time 713887422 ps
CPU time 3.39 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 204908 kb
Host smart-1de16cdf-f3b9-4022-b3cc-dce2bb802b78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176402937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3176402937
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3048420000
Short name T108
Test name
Test status
Simulation time 8182876716 ps
CPU time 98.64 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 01:58:32 PM PDT 24
Peak memory 1145368 kb
Host smart-b9013007-a660-4e05-a41f-fcb252382a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048420000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3048420000
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.4178891874
Short name T980
Test name
Test status
Simulation time 1278832183 ps
CPU time 13.13 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 01:57:07 PM PDT 24
Peak memory 204996 kb
Host smart-4747e8d2-eaf0-405e-91b2-63200c199705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178891874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4178891874
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3904002438
Short name T890
Test name
Test status
Simulation time 7274841093 ps
CPU time 76.6 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:57:59 PM PDT 24
Peak memory 415420 kb
Host smart-b01b4655-22db-4872-a33c-6484d810ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904002438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3904002438
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3527757862
Short name T927
Test name
Test status
Simulation time 17500909 ps
CPU time 0.66 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 204684 kb
Host smart-bc02db12-86a9-496b-b4ed-bd9e32087aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527757862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3527757862
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.126975288
Short name T1297
Test name
Test status
Simulation time 4965553428 ps
CPU time 125.31 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:58:47 PM PDT 24
Peak memory 682268 kb
Host smart-139a93ee-8125-40bd-a99e-33bedab3e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126975288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.126975288
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3969144639
Short name T931
Test name
Test status
Simulation time 10137849260 ps
CPU time 58.59 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:57:49 PM PDT 24
Peak memory 318084 kb
Host smart-db3ffb4d-e731-4aab-9a5d-04d9f0611a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969144639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3969144639
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2134722902
Short name T1023
Test name
Test status
Simulation time 14065177771 ps
CPU time 851.27 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 02:11:05 PM PDT 24
Peak memory 2472000 kb
Host smart-1a4e7adc-cd2b-45bd-8acd-d65140afd0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134722902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2134722902
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2602359264
Short name T1100
Test name
Test status
Simulation time 1035420280 ps
CPU time 23.79 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 213124 kb
Host smart-508314de-39f8-4ed0-b499-c8a3bc001a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602359264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2602359264
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.456999311
Short name T500
Test name
Test status
Simulation time 991306082 ps
CPU time 4.86 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 213184 kb
Host smart-d1335ae4-a515-40f9-9562-0eac512f6d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456999311 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.456999311
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.737775168
Short name T905
Test name
Test status
Simulation time 10140812046 ps
CPU time 14.3 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:57:05 PM PDT 24
Peak memory 252804 kb
Host smart-3ff450b4-46e1-49cd-875c-522f477e0ce6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737775168 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.737775168
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2086960310
Short name T1123
Test name
Test status
Simulation time 10073226400 ps
CPU time 12.9 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:57:04 PM PDT 24
Peak memory 257496 kb
Host smart-9efde170-047d-45da-b3a4-2a6de25509db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086960310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2086960310
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.93402448
Short name T31
Test name
Test status
Simulation time 406343104 ps
CPU time 2.5 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 205032 kb
Host smart-f7d75962-b742-4c7a-b2ff-086c23f7fcd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93402448 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.i2c_target_hrst.93402448
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.4269434290
Short name T865
Test name
Test status
Simulation time 676275544 ps
CPU time 3.76 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 205004 kb
Host smart-91f4a478-d7f8-472c-8967-1553972599cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269434290 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.4269434290
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3083454871
Short name T729
Test name
Test status
Simulation time 20075886963 ps
CPU time 143.98 seconds
Started May 19 01:56:39 PM PDT 24
Finished May 19 01:59:09 PM PDT 24
Peak memory 1766048 kb
Host smart-424bea33-1893-467d-b504-2f5d8a5dd35a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083454871 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3083454871
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3060420667
Short name T570
Test name
Test status
Simulation time 928201913 ps
CPU time 14.75 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:03 PM PDT 24
Peak memory 204916 kb
Host smart-02059cae-170f-447d-96c6-1d94156d9649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060420667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3060420667
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3148370441
Short name T623
Test name
Test status
Simulation time 1142155264 ps
CPU time 22.28 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 218516 kb
Host smart-277a2b6e-2767-4c4a-bff5-8b1200064039
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148370441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3148370441
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1384509238
Short name T322
Test name
Test status
Simulation time 54657481387 ps
CPU time 791.1 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 02:10:06 PM PDT 24
Peak memory 5893860 kb
Host smart-fb628376-0026-438e-9267-e467ae294d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384509238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1384509238
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1248693496
Short name T1281
Test name
Test status
Simulation time 16613045684 ps
CPU time 1072.58 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 02:14:42 PM PDT 24
Peak memory 4082936 kb
Host smart-4d7667be-c8f2-4fa6-bccf-e6aec50a0881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248693496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1248693496
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1382368705
Short name T1146
Test name
Test status
Simulation time 2990883908 ps
CPU time 6.69 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 221276 kb
Host smart-8965e879-4fb3-4a20-a05f-96cb56874e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382368705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1382368705
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2094170782
Short name T810
Test name
Test status
Simulation time 20184100 ps
CPU time 0.61 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 204476 kb
Host smart-b5b03331-cf31-4353-94c0-a18230a47091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094170782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2094170782
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.761429893
Short name T553
Test name
Test status
Simulation time 100933110 ps
CPU time 2.18 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:56:50 PM PDT 24
Peak memory 213260 kb
Host smart-901575cb-0b0f-4fe7-bcd2-766fa15f91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761429893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.761429893
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3922718323
Short name T704
Test name
Test status
Simulation time 1453445980 ps
CPU time 8.06 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 280592 kb
Host smart-06002ae0-1403-497c-bacc-a425ac2a7487
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922718323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3922718323
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3183720931
Short name T385
Test name
Test status
Simulation time 2561734880 ps
CPU time 141.27 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:59:16 PM PDT 24
Peak memory 449340 kb
Host smart-b54334b0-451c-4373-8454-8e8b0635d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183720931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3183720931
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1086635372
Short name T144
Test name
Test status
Simulation time 1901229923 ps
CPU time 137.79 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:59:12 PM PDT 24
Peak memory 675116 kb
Host smart-73d52edc-eff4-427e-91d6-4e192242300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086635372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1086635372
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2438707860
Short name T811
Test name
Test status
Simulation time 491529841 ps
CPU time 1.07 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 205008 kb
Host smart-da1c4937-db21-4294-93c6-14d4e0b3e9c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438707860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2438707860
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.652420415
Short name T308
Test name
Test status
Simulation time 110292620 ps
CPU time 3.25 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 219384 kb
Host smart-ae90d558-226d-4cc3-bed4-2a94e74584bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652420415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.652420415
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1914517897
Short name T738
Test name
Test status
Simulation time 5605177526 ps
CPU time 194.9 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 02:00:04 PM PDT 24
Peak memory 1573380 kb
Host smart-db836c89-26aa-4391-b630-c1f619f07bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914517897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1914517897
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3255179149
Short name T239
Test name
Test status
Simulation time 943946184 ps
CPU time 19.64 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 205176 kb
Host smart-7925353d-b0fd-4c3f-8e06-4c9174986ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255179149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3255179149
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.17377586
Short name T843
Test name
Test status
Simulation time 6129227144 ps
CPU time 26.86 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 284396 kb
Host smart-18eafe04-fa3d-4a48-8952-eff705d089d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17377586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.17377586
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.251609840
Short name T1057
Test name
Test status
Simulation time 61245448 ps
CPU time 0.64 seconds
Started May 19 01:56:48 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 204700 kb
Host smart-2551314f-2d42-47f5-a44e-3edf146193ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251609840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.251609840
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.4103425885
Short name T343
Test name
Test status
Simulation time 1533898877 ps
CPU time 21.34 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:57:14 PM PDT 24
Peak memory 205216 kb
Host smart-b853ff2e-b032-4c5d-832a-0a360a511eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103425885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.4103425885
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2306145032
Short name T1081
Test name
Test status
Simulation time 1107390209 ps
CPU time 18.65 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 355656 kb
Host smart-317b917b-2de6-45bb-af81-95ea1a84f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306145032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2306145032
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.251293019
Short name T45
Test name
Test status
Simulation time 20609038725 ps
CPU time 694.98 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 02:08:43 PM PDT 24
Peak memory 861852 kb
Host smart-e25de6a0-a662-4082-be78-511a96a1f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251293019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.251293019
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1329729426
Short name T67
Test name
Test status
Simulation time 2912917589 ps
CPU time 20.84 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 218556 kb
Host smart-61116a11-6492-4ebb-b280-17d440582302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329729426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1329729426
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.499679941
Short name T1117
Test name
Test status
Simulation time 2713348146 ps
CPU time 3.79 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 205112 kb
Host smart-fffed5f8-20c8-404b-9d04-9b2eed699109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499679941 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.499679941
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2339542351
Short name T1295
Test name
Test status
Simulation time 10083195276 ps
CPU time 82.08 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:58:15 PM PDT 24
Peak memory 423120 kb
Host smart-bc20e378-7922-48e0-9285-3ca265b8137a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339542351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2339542351
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1105041189
Short name T1283
Test name
Test status
Simulation time 955821588 ps
CPU time 2.76 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 205084 kb
Host smart-6f4d62ef-bfed-43e9-bfdf-88c01c928ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105041189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1105041189
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1805897519
Short name T757
Test name
Test status
Simulation time 2990781406 ps
CPU time 3.81 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 206780 kb
Host smart-a4eb8932-01e0-4abf-90cc-f79c38286a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805897519 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1805897519
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.106414334
Short name T365
Test name
Test status
Simulation time 22567789700 ps
CPU time 61.03 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:58:08 PM PDT 24
Peak memory 1259284 kb
Host smart-9834b124-b9e6-49f4-9a1a-9a995213f175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106414334 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.106414334
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2414618041
Short name T522
Test name
Test status
Simulation time 2300226631 ps
CPU time 20.47 seconds
Started May 19 01:56:54 PM PDT 24
Finished May 19 01:57:17 PM PDT 24
Peak memory 205252 kb
Host smart-f226504f-5fdb-4546-9b8d-5b4165779b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414618041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2414618041
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2475523225
Short name T569
Test name
Test status
Simulation time 3671667513 ps
CPU time 25.95 seconds
Started May 19 01:56:57 PM PDT 24
Finished May 19 01:57:23 PM PDT 24
Peak memory 205116 kb
Host smart-314fa0f9-d7d8-494f-a4e5-da22e8139493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475523225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2475523225
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.903529850
Short name T436
Test name
Test status
Simulation time 23409229629 ps
CPU time 74.56 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 991048 kb
Host smart-6be04b41-ded6-4c8f-84e4-4437c3d87ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903529850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_wr.903529850
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.367914110
Short name T598
Test name
Test status
Simulation time 12178097157 ps
CPU time 1494.84 seconds
Started May 19 01:57:01 PM PDT 24
Finished May 19 02:21:57 PM PDT 24
Peak memory 2968668 kb
Host smart-0ab95323-6092-4247-89c6-8229ce46d855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367914110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.367914110
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.160464623
Short name T710
Test name
Test status
Simulation time 1222712504 ps
CPU time 7.13 seconds
Started May 19 01:56:43 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 214764 kb
Host smart-eb1a8242-b2eb-4495-8780-4d07f8a107d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160464623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.160464623
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2783291012
Short name T92
Test name
Test status
Simulation time 31413155 ps
CPU time 0.64 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 204652 kb
Host smart-6c0c1198-d0ac-469f-9c68-c43c2d84a4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783291012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2783291012
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3889556486
Short name T1025
Test name
Test status
Simulation time 223908373 ps
CPU time 3.52 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 231676 kb
Host smart-573d49a9-a0c8-4787-a898-8fa0627a4321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889556486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3889556486
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1064547812
Short name T884
Test name
Test status
Simulation time 1014744560 ps
CPU time 4.49 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 244504 kb
Host smart-002573f8-3a08-4781-a716-2c00d48329ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064547812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1064547812
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.4130376220
Short name T1096
Test name
Test status
Simulation time 1582966874 ps
CPU time 112.97 seconds
Started May 19 01:57:01 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 598792 kb
Host smart-61d372c4-6971-4109-94a8-1c1c864b0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130376220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4130376220
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3557224228
Short name T1069
Test name
Test status
Simulation time 8279921805 ps
CPU time 151.22 seconds
Started May 19 01:57:03 PM PDT 24
Finished May 19 01:59:34 PM PDT 24
Peak memory 652364 kb
Host smart-8e095169-0775-44dc-a9cb-0b1c4dcfdca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557224228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3557224228
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2764825422
Short name T229
Test name
Test status
Simulation time 329749723 ps
CPU time 1.25 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 204996 kb
Host smart-ac385c0e-0aeb-44b0-855a-2487ff8453e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764825422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2764825422
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1755565491
Short name T1230
Test name
Test status
Simulation time 184459622 ps
CPU time 5.12 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 237748 kb
Host smart-87b3a980-d0c6-46a9-b08f-acb0303a8802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755565491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1755565491
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3631476715
Short name T443
Test name
Test status
Simulation time 6407639735 ps
CPU time 284.97 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 02:01:40 PM PDT 24
Peak memory 1111916 kb
Host smart-eb83870e-d845-40f7-b50e-ca1a18f50c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631476715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3631476715
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1335407606
Short name T670
Test name
Test status
Simulation time 1878901747 ps
CPU time 18.98 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:57:13 PM PDT 24
Peak memory 205008 kb
Host smart-d76600cb-400e-494e-8e59-7954142598c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335407606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1335407606
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1294956283
Short name T380
Test name
Test status
Simulation time 2221911004 ps
CPU time 41.81 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:57:46 PM PDT 24
Peak memory 372816 kb
Host smart-3eef88fa-496c-40ad-b1d7-3c9ddcddd52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294956283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1294956283
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.739594029
Short name T1269
Test name
Test status
Simulation time 17830965 ps
CPU time 0.63 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:56:53 PM PDT 24
Peak memory 204700 kb
Host smart-2c25ea6c-d1f0-4bef-82c5-c607cfc6cc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739594029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.739594029
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3415836653
Short name T1013
Test name
Test status
Simulation time 3035374954 ps
CPU time 65.04 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 616404 kb
Host smart-c06c893f-d054-4abf-af6c-39d459d0b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415836653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3415836653
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2201356408
Short name T997
Test name
Test status
Simulation time 1920805183 ps
CPU time 31.39 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 375068 kb
Host smart-70cda93c-56dc-403c-907b-e549b2f245e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201356408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2201356408
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1449466138
Short name T990
Test name
Test status
Simulation time 8948806646 ps
CPU time 219.93 seconds
Started May 19 01:56:52 PM PDT 24
Finished May 19 02:00:36 PM PDT 24
Peak memory 378740 kb
Host smart-4ed0d0f7-6724-418b-9480-45c779b795ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449466138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1449466138
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2974199447
Short name T55
Test name
Test status
Simulation time 5217832249 ps
CPU time 13.91 seconds
Started May 19 01:56:42 PM PDT 24
Finished May 19 01:57:03 PM PDT 24
Peak memory 221132 kb
Host smart-543b70af-ed48-4d98-a3db-2316cc83140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974199447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2974199447
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.4142644064
Short name T1164
Test name
Test status
Simulation time 1342215547 ps
CPU time 3.5 seconds
Started May 19 01:56:58 PM PDT 24
Finished May 19 01:57:03 PM PDT 24
Peak memory 204968 kb
Host smart-63471fe0-5258-4310-a680-d511b9e889f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142644064 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.4142644064
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3582008943
Short name T820
Test name
Test status
Simulation time 10078724996 ps
CPU time 71.09 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 436740 kb
Host smart-3e2d34e2-1055-495a-a2b1-a0ff968ff984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582008943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3582008943
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.719850633
Short name T939
Test name
Test status
Simulation time 10267355849 ps
CPU time 16.17 seconds
Started May 19 01:56:52 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 286512 kb
Host smart-1d006b73-cbae-4307-8028-c55b03a11c06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719850633 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.719850633
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2107723730
Short name T620
Test name
Test status
Simulation time 961321157 ps
CPU time 2.72 seconds
Started May 19 01:56:53 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 205016 kb
Host smart-5da89e2f-0ad2-46d2-98a3-b63b16840595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107723730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2107723730
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2353985272
Short name T1145
Test name
Test status
Simulation time 13659705044 ps
CPU time 6.92 seconds
Started May 19 01:56:47 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 212144 kb
Host smart-0f0a6686-1976-4346-b3b2-9bde0099e5c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353985272 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2353985272
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.705280885
Short name T954
Test name
Test status
Simulation time 18726442196 ps
CPU time 276.89 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 02:01:29 PM PDT 24
Peak memory 2922436 kb
Host smart-3ab315c0-798b-496f-bc22-59fbe069e677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705280885 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.705280885
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3206104451
Short name T481
Test name
Test status
Simulation time 5365955441 ps
CPU time 22.34 seconds
Started May 19 01:56:41 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 205028 kb
Host smart-ab5aa450-4d32-4485-8b45-041bc133eb87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206104451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3206104451
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3964954722
Short name T386
Test name
Test status
Simulation time 2031615653 ps
CPU time 8.77 seconds
Started May 19 01:56:54 PM PDT 24
Finished May 19 01:57:05 PM PDT 24
Peak memory 204892 kb
Host smart-04d4f660-6b68-401e-b613-a5d553934d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964954722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3964954722
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2234908528
Short name T1175
Test name
Test status
Simulation time 11801916668 ps
CPU time 7.48 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 205252 kb
Host smart-d59c5865-5369-4e89-8227-ac26a7c65a02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234908528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2234908528
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1763871641
Short name T695
Test name
Test status
Simulation time 22875514048 ps
CPU time 1765.94 seconds
Started May 19 01:56:44 PM PDT 24
Finished May 19 02:26:18 PM PDT 24
Peak memory 5475792 kb
Host smart-f3c4744f-07ed-407d-bf51-fbf175d00e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763871641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1763871641
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1275789519
Short name T829
Test name
Test status
Simulation time 1246575274 ps
CPU time 6.77 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 213160 kb
Host smart-008e4af7-e037-4c6c-879b-9c5618e14796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275789519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1275789519
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1809083268
Short name T588
Test name
Test status
Simulation time 15288455 ps
CPU time 0.63 seconds
Started May 19 01:56:57 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 204632 kb
Host smart-3ddddf54-3073-4b97-be88-101c0e6b66fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809083268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1809083268
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.382258510
Short name T1226
Test name
Test status
Simulation time 121214092 ps
CPU time 3.28 seconds
Started May 19 01:56:54 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 213224 kb
Host smart-85c6064f-8acf-4ddb-bc62-1fa8488aa549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382258510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.382258510
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3514223526
Short name T986
Test name
Test status
Simulation time 354818606 ps
CPU time 8.41 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 01:57:16 PM PDT 24
Peak memory 276804 kb
Host smart-9abb1afb-919e-4b9d-8115-57fccbe7e977
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514223526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3514223526
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3735328502
Short name T527
Test name
Test status
Simulation time 1587823328 ps
CPU time 54.61 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 01:58:03 PM PDT 24
Peak memory 581392 kb
Host smart-d1a43c4c-5428-4a8a-9ee8-ba7716415645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735328502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3735328502
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2844353537
Short name T737
Test name
Test status
Simulation time 8256119449 ps
CPU time 211.29 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 02:00:34 PM PDT 24
Peak memory 818008 kb
Host smart-46d94173-c667-4c1f-910d-73c63093fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844353537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2844353537
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2918849402
Short name T231
Test name
Test status
Simulation time 138617781 ps
CPU time 1.26 seconds
Started May 19 01:56:59 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 204984 kb
Host smart-571aada5-5f2e-4f25-9f35-0cdce64430b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918849402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2918849402
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3547500179
Short name T1090
Test name
Test status
Simulation time 441383849 ps
CPU time 5.56 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 204820 kb
Host smart-bdfb67b3-6681-4097-baa7-f675792dba6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547500179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3547500179
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1888575286
Short name T610
Test name
Test status
Simulation time 4723723072 ps
CPU time 155.57 seconds
Started May 19 01:57:12 PM PDT 24
Finished May 19 01:59:48 PM PDT 24
Peak memory 1345056 kb
Host smart-dca33565-7e73-49a7-8c76-0a6cb3fbc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888575286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1888575286
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1007724305
Short name T692
Test name
Test status
Simulation time 934411957 ps
CPU time 4.19 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 205020 kb
Host smart-46d331ea-3656-4860-b97f-0508eb24d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007724305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1007724305
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3583047934
Short name T616
Test name
Test status
Simulation time 8283366199 ps
CPU time 31.82 seconds
Started May 19 01:56:59 PM PDT 24
Finished May 19 01:57:31 PM PDT 24
Peak memory 374484 kb
Host smart-50f5e76a-8946-4348-aa57-ba0ce29a9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583047934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3583047934
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.173682601
Short name T662
Test name
Test status
Simulation time 95767780 ps
CPU time 0.66 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 01:56:55 PM PDT 24
Peak memory 204680 kb
Host smart-34ad2148-dd8e-497e-84d7-9987ae1a15af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173682601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.173682601
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1929856356
Short name T601
Test name
Test status
Simulation time 26973866002 ps
CPU time 1911.37 seconds
Started May 19 01:56:54 PM PDT 24
Finished May 19 02:28:48 PM PDT 24
Peak memory 3967100 kb
Host smart-b9f5993c-5ca2-400f-b973-6090fe31d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929856356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1929856356
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1739023879
Short name T591
Test name
Test status
Simulation time 5491286453 ps
CPU time 22.85 seconds
Started May 19 01:56:54 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 339800 kb
Host smart-de3644e7-1520-47a8-9bf2-0d17bd33b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739023879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1739023879
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1761946159
Short name T1098
Test name
Test status
Simulation time 18627118986 ps
CPU time 2160.65 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 02:32:56 PM PDT 24
Peak memory 3043240 kb
Host smart-8c742ab1-a334-4ecf-b93a-d74ac67d623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761946159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1761946159
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1529772938
Short name T1127
Test name
Test status
Simulation time 719309058 ps
CPU time 11.52 seconds
Started May 19 01:56:46 PM PDT 24
Finished May 19 01:57:04 PM PDT 24
Peak memory 215132 kb
Host smart-8dd17e9f-1b10-4279-8967-8ef3cf7ee153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529772938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1529772938
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1170331355
Short name T1002
Test name
Test status
Simulation time 7800800847 ps
CPU time 4.02 seconds
Started May 19 01:56:58 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 205088 kb
Host smart-1755a509-debf-4d77-b8a9-b3e8bb801042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170331355 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1170331355
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3553276318
Short name T423
Test name
Test status
Simulation time 10034054907 ps
CPU time 51.95 seconds
Started May 19 01:57:08 PM PDT 24
Finished May 19 01:58:01 PM PDT 24
Peak memory 379520 kb
Host smart-da2b2dc3-ba24-4d02-947e-239dd8855a94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553276318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3553276318
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.123474674
Short name T251
Test name
Test status
Simulation time 10142634992 ps
CPU time 16.83 seconds
Started May 19 01:56:45 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 271152 kb
Host smart-e07c4ab6-0053-472d-88f0-20e75efb6641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123474674 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.123474674
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1344712906
Short name T275
Test name
Test status
Simulation time 390551591 ps
CPU time 2.47 seconds
Started May 19 01:57:03 PM PDT 24
Finished May 19 01:57:06 PM PDT 24
Peak memory 205092 kb
Host smart-1e3ac85f-a781-4594-9448-607d3d8a2084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344712906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1344712906
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.34558617
Short name T283
Test name
Test status
Simulation time 5379607612 ps
CPU time 5.13 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 205012 kb
Host smart-d72fdf22-aaff-44f4-a9b2-38217704f7e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34558617 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.34558617
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2474716373
Short name T1276
Test name
Test status
Simulation time 3576021601 ps
CPU time 6.41 seconds
Started May 19 01:56:49 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 205056 kb
Host smart-e6dc8ce8-0371-41b5-8833-60b33d31bdb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474716373 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2474716373
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2191229657
Short name T852
Test name
Test status
Simulation time 3324258479 ps
CPU time 11.76 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 205048 kb
Host smart-7b8a5734-93f4-45b1-a872-1efa3d7c4030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191229657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2191229657
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2537654708
Short name T395
Test name
Test status
Simulation time 1787513355 ps
CPU time 7.56 seconds
Started May 19 01:56:53 PM PDT 24
Finished May 19 01:57:04 PM PDT 24
Peak memory 208188 kb
Host smart-b0807a48-33f0-4392-85ac-59b9cda80e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537654708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2537654708
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1839843408
Short name T916
Test name
Test status
Simulation time 39288387061 ps
CPU time 200.32 seconds
Started May 19 01:57:09 PM PDT 24
Finished May 19 02:00:30 PM PDT 24
Peak memory 2416152 kb
Host smart-338756c4-04f8-4436-acd9-f4a1e51320c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839843408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1839843408
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1705922286
Short name T1239
Test name
Test status
Simulation time 27448432174 ps
CPU time 865.32 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 02:11:34 PM PDT 24
Peak memory 3765516 kb
Host smart-e8dfb87e-616b-450b-a006-0da5c6daccbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705922286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1705922286
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1043169776
Short name T806
Test name
Test status
Simulation time 1484141855 ps
CPU time 8.19 seconds
Started May 19 01:56:57 PM PDT 24
Finished May 19 01:57:06 PM PDT 24
Peak memory 221152 kb
Host smart-bc422d1c-d26a-4a44-93d3-704ac0b72b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043169776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1043169776
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3747669060
Short name T1172
Test name
Test status
Simulation time 31914755 ps
CPU time 0.63 seconds
Started May 19 01:57:11 PM PDT 24
Finished May 19 01:57:12 PM PDT 24
Peak memory 204620 kb
Host smart-5e2e17fb-b5d8-46b3-80a2-a2a82f0558f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747669060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3747669060
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1834908585
Short name T495
Test name
Test status
Simulation time 149026030 ps
CPU time 1.4 seconds
Started May 19 01:57:11 PM PDT 24
Finished May 19 01:57:13 PM PDT 24
Peak memory 213268 kb
Host smart-1bd88ed6-5f6d-4e86-bec5-6d8403cd65f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834908585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1834908585
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1651959025
Short name T1058
Test name
Test status
Simulation time 645353730 ps
CPU time 16.91 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 254420 kb
Host smart-d54d6268-1552-4a96-b4bc-cff744d4c891
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651959025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1651959025
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3988907921
Short name T792
Test name
Test status
Simulation time 4876963898 ps
CPU time 31.23 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:57:27 PM PDT 24
Peak memory 451340 kb
Host smart-443e3ca5-c86e-4e27-9082-a823a9a5a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988907921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3988907921
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2921593569
Short name T420
Test name
Test status
Simulation time 8957011704 ps
CPU time 57.94 seconds
Started May 19 01:56:52 PM PDT 24
Finished May 19 01:57:54 PM PDT 24
Peak memory 583640 kb
Host smart-f8b3e706-84ca-496e-b792-0421876c348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921593569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2921593569
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.4282331882
Short name T401
Test name
Test status
Simulation time 226547922 ps
CPU time 0.91 seconds
Started May 19 01:57:06 PM PDT 24
Finished May 19 01:57:08 PM PDT 24
Peak memory 204740 kb
Host smart-81faf747-645e-47ad-a108-6b6b3be771fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282331882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.4282331882
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2596463310
Short name T454
Test name
Test status
Simulation time 330827344 ps
CPU time 8.83 seconds
Started May 19 01:56:56 PM PDT 24
Finished May 19 01:57:06 PM PDT 24
Peak memory 204928 kb
Host smart-4712d746-6c3f-4586-9f00-c5505b6d4223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596463310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2596463310
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1399942014
Short name T419
Test name
Test status
Simulation time 18276290665 ps
CPU time 129.67 seconds
Started May 19 01:56:55 PM PDT 24
Finished May 19 01:59:06 PM PDT 24
Peak memory 1207632 kb
Host smart-3b526fa2-09f4-44cc-92a5-b42fa0604d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399942014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1399942014
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.424893346
Short name T1216
Test name
Test status
Simulation time 11380984954 ps
CPU time 24.19 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 01:57:27 PM PDT 24
Peak memory 205100 kb
Host smart-a1466247-6531-4bab-b8a4-1a04f955c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424893346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.424893346
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1742733521
Short name T416
Test name
Test status
Simulation time 35506930910 ps
CPU time 29.96 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 360056 kb
Host smart-35d0d7ca-0603-4683-b3b0-35e1125b431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742733521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1742733521
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2527704717
Short name T71
Test name
Test status
Simulation time 190314321 ps
CPU time 0.67 seconds
Started May 19 01:57:05 PM PDT 24
Finished May 19 01:57:07 PM PDT 24
Peak memory 204648 kb
Host smart-5c9525bd-a612-4900-8cbb-c30df9750cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527704717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2527704717
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2678465251
Short name T358
Test name
Test status
Simulation time 6578530200 ps
CPU time 18.94 seconds
Started May 19 01:57:01 PM PDT 24
Finished May 19 01:57:21 PM PDT 24
Peak memory 213856 kb
Host smart-504cf5f0-7033-4bab-a123-a5a33e14e001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678465251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2678465251
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3300060457
Short name T823
Test name
Test status
Simulation time 9964649617 ps
CPU time 35.97 seconds
Started May 19 01:56:52 PM PDT 24
Finished May 19 01:57:31 PM PDT 24
Peak memory 357136 kb
Host smart-3a4551c5-3dcb-472e-b321-e8ba0caffaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300060457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3300060457
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2838763063
Short name T123
Test name
Test status
Simulation time 28696016508 ps
CPU time 409.66 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 02:03:45 PM PDT 24
Peak memory 1506460 kb
Host smart-4bc78885-54b8-427e-871d-01c3ef058b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838763063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2838763063
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.542217526
Short name T1137
Test name
Test status
Simulation time 1552572190 ps
CPU time 36.38 seconds
Started May 19 01:56:59 PM PDT 24
Finished May 19 01:57:36 PM PDT 24
Peak memory 213428 kb
Host smart-6fc5887a-3854-4cbc-93b9-c1a5ac1f42ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542217526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.542217526
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.40706223
Short name T641
Test name
Test status
Simulation time 994262749 ps
CPU time 5.23 seconds
Started May 19 01:57:02 PM PDT 24
Finished May 19 01:57:08 PM PDT 24
Peak memory 213560 kb
Host smart-ed6d0b71-7191-4480-87e7-99177fd73477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40706223 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_bad_addr.40706223
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.824786427
Short name T575
Test name
Test status
Simulation time 10095610466 ps
CPU time 73.46 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 419440 kb
Host smart-796bc7d4-2a3c-4fa5-b185-85d478d0efc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824786427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.824786427
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1876557585
Short name T1035
Test name
Test status
Simulation time 10215299742 ps
CPU time 14.15 seconds
Started May 19 01:57:07 PM PDT 24
Finished May 19 01:57:22 PM PDT 24
Peak memory 279832 kb
Host smart-99fa7541-6be2-4fad-9be8-47e94ac1bf82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876557585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1876557585
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1953902190
Short name T707
Test name
Test status
Simulation time 1422605224 ps
CPU time 2.39 seconds
Started May 19 01:57:14 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 205284 kb
Host smart-f8a89962-c4f0-42a0-bdab-ac53de77a1b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953902190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1953902190
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.4240163450
Short name T30
Test name
Test status
Simulation time 1066846740 ps
CPU time 5.61 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 204972 kb
Host smart-3979cf99-4d6c-418e-a81f-18d8c2ed57bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240163450 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.4240163450
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3556502128
Short name T873
Test name
Test status
Simulation time 16826395098 ps
CPU time 32.27 seconds
Started May 19 01:56:52 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 851196 kb
Host smart-6dc6f34c-4f1a-40f3-a118-7665e0fa14c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556502128 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3556502128
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2007332339
Short name T7
Test name
Test status
Simulation time 1203838790 ps
CPU time 21.1 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 01:57:16 PM PDT 24
Peak memory 204940 kb
Host smart-29b4e8ae-09d1-4e34-b4bd-a03118a182a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007332339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2007332339
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.862650794
Short name T1166
Test name
Test status
Simulation time 19019858561 ps
CPU time 61.56 seconds
Started May 19 01:57:04 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 210476 kb
Host smart-5a96961d-f467-4e6c-9205-57126f5fcea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862650794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.862650794
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2869232574
Short name T1263
Test name
Test status
Simulation time 40929861417 ps
CPU time 209.13 seconds
Started May 19 01:56:50 PM PDT 24
Finished May 19 02:00:24 PM PDT 24
Peak memory 2573944 kb
Host smart-56399536-2088-4766-af41-af211d80fe5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869232574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2869232574
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.4092447872
Short name T1111
Test name
Test status
Simulation time 11995581395 ps
CPU time 70.48 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:58:06 PM PDT 24
Peak memory 773284 kb
Host smart-98358ad8-1f13-4b49-b5c2-7acf6ce303ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092447872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.4092447872
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2128653817
Short name T1215
Test name
Test status
Simulation time 1262600904 ps
CPU time 6.56 seconds
Started May 19 01:56:51 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 213216 kb
Host smart-a22e1c97-85ab-4bc7-90ca-4e0e6dcc9b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128653817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2128653817
Directory /workspace/9.i2c_target_timeout/latest
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