Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	9	51	85.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	9	51	85.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	979973	1			T1	2		T2	1		T3	2
all_values[1]	979973	1			T1	2		T2	1		T3	2
all_values[2]	979973	1			T1	2		T2	1		T3	2
all_values[3]	979973	1			T1	2		T2	1		T3	2
all_values[4]	979973	1			T1	2		T2	1		T3	2
all_values[5]	979973	1			T1	2		T2	1		T3	2
all_values[6]	979973	1			T1	2		T2	1		T3	2
all_values[7]	979973	1			T1	2		T2	1		T3	2
all_values[8]	979973	1			T1	2		T2	1		T3	2
all_values[9]	979973	1			T1	2		T2	1		T3	2
all_values[10]	979973	1			T1	2		T2	1		T3	2
all_values[11]	979973	1			T1	2		T2	1		T3	2
all_values[12]	979973	1			T1	2		T2	1		T3	2
all_values[13]	979973	1			T1	2		T2	1		T3	2
all_values[14]	979973	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12058366

1

T1

26

T2

15

T3

26

auto[1]

2641229

1

T1

4

T3

4

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12636531

1

T1

30

T2

15

T3

30

auto[1]

2063064

1

T80

79032

T37

160

T46

83593

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	9	51	85.00	9

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98770	1			T2	1		T6	1		T7	1
all_values[0]	auto[0]	auto[1]	21663	1			T80	3933		T46	45		T196	58
all_values[0]	auto[1]	auto[0]	740624	1			T1	2		T3	2		T4	2
all_values[0]	auto[1]	auto[1]	118916	1			T80	1333		T37	10		T46	5529
all_values[1]	auto[0]	auto[0]	839040	1			T1	2		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	140382	1			T80	5267		T37	7		T46	5570
all_values[1]	auto[1]	auto[0]	360	1			T52	2		T33	4		T209	2
all_values[1]	auto[1]	auto[1]	191	1			T80	3		T37	2		T46	2
all_values[2]	auto[0]	auto[0]	839381	1			T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	140393	1			T80	5264		T37	9		T46	5569
all_values[2]	auto[1]	auto[1]	199	1			T80	6		T37	3		T46	5
all_values[3]	auto[0]	auto[0]	839377	1			T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	140369	1			T80	5266		T37	10		T46	5571
all_values[3]	auto[1]	auto[1]	227	1			T80	3		T37	2		T196	4
all_values[4]	auto[0]	auto[0]	839626	1			T1	2		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	140124	1			T80	5265		T37	9		T46	5571
all_values[4]	auto[1]	auto[0]	25	1			T42	1		T210	1		T211	2
all_values[4]	auto[1]	auto[1]	198	1			T80	4		T37	1		T46	3
all_values[5]	auto[0]	auto[0]	875151	1			T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	104581	1			T80	5263		T37	6		T46	5569
all_values[5]	auto[1]	auto[1]	241	1			T80	7		T37	6		T46	1
all_values[6]	auto[0]	auto[0]	839419	1			T1	2		T2	1		T3	2
all_values[6]	auto[0]	auto[1]	140330	1			T80	5265		T37	9		T46	5570
all_values[6]	auto[1]	auto[1]	224	1			T80	4		T37	1		T46	4
all_values[7]	auto[0]	auto[0]	816541	1			T1	2		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	132407	1			T80	4940		T37	6		T46	5375
all_values[7]	auto[1]	auto[0]	27906	1			T7	1		T8	1		T47	387
all_values[7]	auto[1]	auto[1]	3119	1			T80	329		T37	3		T46	199
all_values[8]	auto[0]	auto[0]	842934	1			T1	2		T2	1		T3	2
all_values[8]	auto[0]	auto[1]	136831	1			T80	5263		T37	7		T46	5571
all_values[8]	auto[1]	auto[1]	208	1			T80	2		T37	4		T46	3
all_values[9]	auto[0]	auto[0]	171185	1			T1	2		T2	1		T3	2
all_values[9]	auto[0]	auto[1]	37633	1			T80	5264		T37	5		T46	430
all_values[9]	auto[1]	auto[0]	668491	1			T5	1		T7	1		T8	1
all_values[9]	auto[1]	auto[1]	102664	1			T80	5		T37	5		T46	5143
all_values[10]	auto[0]	auto[0]	839408	1			T1	2		T2	1		T3	2
all_values[10]	auto[0]	auto[1]	140374	1			T80	5267		T37	9		T46	5570
all_values[10]	auto[1]	auto[1]	191	1			T80	3		T37	3		T46	4
all_values[11]	auto[0]	auto[0]	2768	1			T2	1		T6	1		T7	1
all_values[11]	auto[0]	auto[1]	378	1			T80	2		T46	23		T196	13
all_values[11]	auto[1]	auto[0]	836639	1			T1	2		T3	2		T4	2
all_values[11]	auto[1]	auto[1]	140188	1			T80	5267		T37	12		T46	5548
all_values[12]	auto[0]	auto[0]	839659	1			T1	2		T2	1		T3	2
all_values[12]	auto[0]	auto[1]	140118	1			T80	5264		T37	7		T46	5570
all_values[12]	auto[1]	auto[1]	196	1			T80	6		T37	5		T46	2
all_values[13]	auto[0]	auto[0]	839797	1			T1	2		T2	1		T3	2
all_values[13]	auto[0]	auto[1]	139956	1			T80	5269		T37	9		T46	5573
all_values[13]	auto[1]	auto[1]	220	1			T80	1		T37	2		T46	1
all_values[14]	auto[0]	auto[0]	839430	1			T1	2		T2	1		T3	2
all_values[14]	auto[0]	auto[1]	140341	1			T80	5266		T37	5		T46	5571
all_values[14]	auto[1]	auto[1]	202	1			T80	1		T37	3		T46	1