Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	979973	1			T1	2		T2	1		T3	2
all_pins[1]	979973	1			T1	2		T2	1		T3	2
all_pins[2]	979973	1			T1	2		T2	1		T3	2
all_pins[3]	979973	1			T1	2		T2	1		T3	2
all_pins[4]	979973	1			T1	2		T2	1		T3	2
all_pins[5]	979973	1			T1	2		T2	1		T3	2
all_pins[6]	979973	1			T1	2		T2	1		T3	2
all_pins[7]	979973	1			T1	2		T2	1		T3	2
all_pins[8]	979973	1			T1	2		T2	1		T3	2
all_pins[9]	979973	1			T1	2		T2	1		T3	2
all_pins[10]	979973	1			T1	2		T2	1		T3	2
all_pins[11]	979973	1			T1	2		T2	1		T3	2
all_pins[12]	979973	1			T1	2		T2	1		T3	2
all_pins[13]	979973	1			T1	2		T2	1		T3	2
all_pins[14]	979973	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12063898	1			T1	26		T2	15		T3	26
values[0x1]	2635697	1			T1	4		T3	4		T4	4
transitions[0x0=>0x1]	2634929	1			T1	4		T3	4		T4	4
transitions[0x1=>0x0]	2633898	1			T1	3		T3	3		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	124003	1			T2	1		T6	1		T7	1
all_pins[0]	values[0x1]	855970	1			T1	2		T3	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	855582	1			T1	2		T3	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	141	1			T37	1		T46	1		T196	3
all_pins[1]	values[0x0]	979444	1			T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	529	1			T52	2		T33	4		T209	3
all_pins[1]	transitions[0x0=>0x1]	507	1			T52	2		T33	4		T209	3
all_pins[1]	transitions[0x1=>0x0]	75	1			T80	4		T37	2		T46	3
all_pins[2]	values[0x0]	979876	1			T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	97	1			T80	5		T37	2		T46	4
all_pins[2]	transitions[0x0=>0x1]	75	1			T80	4		T46	4		T196	1
all_pins[2]	transitions[0x1=>0x0]	91	1			T80	1		T196	1		T104	4
all_pins[3]	values[0x0]	979860	1			T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	113	1			T80	2		T37	2		T196	2
all_pins[3]	transitions[0x0=>0x1]	83	1			T80	1		T37	2		T196	2
all_pins[3]	transitions[0x1=>0x0]	102	1			T80	3		T42	1		T210	2
all_pins[4]	values[0x0]	979841	1			T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	132	1			T80	4		T42	1		T210	2
all_pins[4]	transitions[0x0=>0x1]	106	1			T80	2		T42	1		T210	2
all_pins[4]	transitions[0x1=>0x0]	94	1			T80	2		T37	4		T196	1
all_pins[5]	values[0x0]	979853	1			T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	120	1			T80	4		T37	4		T196	1
all_pins[5]	transitions[0x0=>0x1]	96	1			T80	3		T37	4		T104	2
all_pins[5]	transitions[0x1=>0x0]	84	1			T46	3		T196	2		T197	4
all_pins[6]	values[0x0]	979865	1			T1	2		T2	1		T3	2
all_pins[6]	values[0x1]	108	1			T80	1		T46	3		T196	3
all_pins[6]	transitions[0x0=>0x1]	75	1			T80	1		T46	1		T196	2
all_pins[6]	transitions[0x1=>0x0]	34069	1			T7	1		T8	1		T47	488
all_pins[7]	values[0x0]	945871	1			T1	2		T2	1		T3	2
all_pins[7]	values[0x1]	34102	1			T7	1		T8	1		T47	488
all_pins[7]	transitions[0x0=>0x1]	34083	1			T7	1		T8	1		T47	488
all_pins[7]	transitions[0x1=>0x0]	77	1			T104	1		T197	1		T243	1
all_pins[8]	values[0x0]	979877	1			T1	2		T2	1		T3	2
all_pins[8]	values[0x1]	96	1			T196	2		T104	1		T197	3
all_pins[8]	transitions[0x0=>0x1]	67	1			T196	2		T197	3		T243	1
all_pins[8]	transitions[0x1=>0x0]	771053	1			T5	1		T7	1		T8	1
all_pins[9]	values[0x0]	208891	1			T1	2		T2	1		T3	2
all_pins[9]	values[0x1]	771082	1			T5	1		T7	1		T8	1
all_pins[9]	transitions[0x0=>0x1]	771061	1			T5	1		T7	1		T8	1
all_pins[9]	transitions[0x1=>0x0]	86	1			T80	3		T46	3		T196	1
all_pins[10]	values[0x0]	979866	1			T1	2		T2	1		T3	2
all_pins[10]	values[0x1]	107	1			T80	3		T37	1		T46	3
all_pins[10]	transitions[0x0=>0x1]	81	1			T80	3		T46	2		T196	1
all_pins[10]	transitions[0x1=>0x0]	972887	1			T1	2		T3	2		T4	2
all_pins[11]	values[0x0]	7060	1			T2	1		T6	1		T7	1
all_pins[11]	values[0x1]	972913	1			T1	2		T3	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	972880	1			T1	2		T3	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	76	1			T80	3		T196	1		T104	3
all_pins[12]	values[0x0]	979864	1			T1	2		T2	1		T3	2
all_pins[12]	values[0x1]	109	1			T80	3		T196	1		T104	4
all_pins[12]	transitions[0x0=>0x1]	76	1			T80	3		T196	1		T104	4
all_pins[12]	transitions[0x1=>0x0]	88	1			T37	1		T46	1		T104	2
all_pins[13]	values[0x0]	979852	1			T1	2		T2	1		T3	2
all_pins[13]	values[0x1]	121	1			T37	1		T46	1		T104	2
all_pins[13]	transitions[0x0=>0x1]	97	1			T46	1		T104	2		T197	3
all_pins[13]	transitions[0x1=>0x0]	74	1			T80	1		T46	1		T104	1
all_pins[14]	values[0x0]	979875	1			T1	2		T2	1		T3	2
all_pins[14]	values[0x1]	98	1			T80	1		T37	1		T46	1
all_pins[14]	transitions[0x0=>0x1]	60	1			T46	1		T104	1		T137	1
all_pins[14]	transitions[0x1=>0x0]	854901	1			T1	1		T3	1		T4	1