Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	448	1			T80	7		T37	7		T46	7
all_values[1]	448	1			T80	7		T37	7		T46	7
all_values[2]	448	1			T80	7		T37	7		T46	7
all_values[3]	448	1			T80	7		T37	7		T46	7
all_values[4]	448	1			T80	7		T37	7		T46	7
all_values[5]	448	1			T80	7		T37	7		T46	7
all_values[6]	448	1			T80	7		T37	7		T46	7
all_values[7]	448	1			T80	7		T37	7		T46	7
all_values[8]	448	1			T80	7		T37	7		T46	7
all_values[9]	448	1			T80	7		T37	7		T46	7
all_values[10]	448	1			T80	7		T37	7		T46	7
all_values[11]	448	1			T80	7		T37	7		T46	7
all_values[12]	448	1			T80	7		T37	7		T46	7
all_values[13]	448	1			T80	7		T37	7		T46	7
all_values[14]	448	1			T80	7		T37	7		T46	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3488

1

T80

39

T37

55

T46

47

auto[1]

3232

1

T80

66

T37

50

T46

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T80

18

T37

20

T46

17

auto[1]

5671

1

T80

87

T37

85

T46

88

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3874

1

T80

55

T37

63

T46

60

auto[1]

2846

1

T80

50

T37

42

T46

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T80	1		T37	1		T196	2
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T80	2		T37	1		T46	2
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T80	3		T37	1		T244	3
all_values[0]	auto[0]	auto[1]	auto[1]	114	1			T37	1		T104	3		T197	5
all_values[0]	auto[1]	auto[0]	auto[1]	107	1			T80	1		T37	2		T46	4
all_values[0]	auto[1]	auto[1]	auto[1]	76	1			T37	1		T46	1		T196	1
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T37	2		T46	1		T243	2
all_values[1]	auto[0]	auto[0]	auto[1]	103	1			T80	2		T37	1		T46	3
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T37	1		T46	1		T162	1
all_values[1]	auto[0]	auto[1]	auto[1]	95	1			T80	2		T37	1		T196	2
all_values[1]	auto[1]	auto[0]	auto[1]	91	1			T80	1		T37	2		T46	1
all_values[1]	auto[1]	auto[1]	auto[1]	86	1			T80	2		T46	1		T196	3
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T243	1		T106	2		T107	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T37	2		T46	2		T196	2
all_values[2]	auto[0]	auto[1]	auto[0]	21	1			T104	1		T197	1		T243	1
all_values[2]	auto[0]	auto[1]	auto[1]	106	1			T80	1		T37	2		T196	1
all_values[2]	auto[1]	auto[0]	auto[1]	116	1			T80	1		T37	1		T46	1
all_values[2]	auto[1]	auto[1]	auto[1]	83	1			T80	5		T37	2		T46	4
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T80	1		T46	1		T106	1
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T80	1		T37	3		T196	1
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T46	2		T243	1		T162	1
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T80	3		T37	1		T46	3
all_values[3]	auto[1]	auto[0]	auto[1]	112	1			T80	1		T196	3		T104	1
all_values[3]	auto[1]	auto[1]	auto[1]	103	1			T80	1		T37	3		T46	1
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T196	1		T197	5		T244	3
all_values[4]	auto[0]	auto[0]	auto[1]	105	1			T37	4		T46	1		T196	3
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T80	1		T37	2		T137	1
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T80	2		T46	3		T104	2
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T37	1		T46	2		T196	3
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T80	4		T46	1		T104	2
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T46	2		T244	1		T203	1
all_values[5]	auto[0]	auto[0]	auto[1]	91	1			T80	2		T37	1		T196	1
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T46	2		T196	1		T137	1
all_values[5]	auto[0]	auto[1]	auto[1]	94	1			T80	1		T37	2		T46	1
all_values[5]	auto[1]	auto[0]	auto[1]	105	1			T80	1		T37	3		T46	2
all_values[5]	auto[1]	auto[1]	auto[1]	95	1			T80	3		T37	1		T196	2
all_values[6]	auto[0]	auto[0]	auto[0]	56	1			T80	1		T37	1		T104	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T80	3		T37	1		T196	2
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T37	1		T104	3		T243	2
all_values[6]	auto[0]	auto[1]	auto[1]	110	1			T80	1		T37	2		T46	4
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T80	1		T37	2		T46	1
all_values[6]	auto[1]	auto[1]	auto[1]	75	1			T80	1		T46	2		T196	4
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T243	1		T106	1		T245	1
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T80	1		T37	1		T196	2
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T80	1		T37	3		T243	1
all_values[7]	auto[0]	auto[1]	auto[1]	102	1			T80	1		T37	1		T46	2
all_values[7]	auto[1]	auto[0]	auto[1]	107	1			T80	1		T46	4		T196	1
all_values[7]	auto[1]	auto[1]	auto[1]	82	1			T80	3		T37	2		T46	1
all_values[8]	auto[0]	auto[0]	auto[0]	48	1			T80	3		T137	2		T162	1
all_values[8]	auto[0]	auto[0]	auto[1]	92	1			T80	1		T37	2		T46	2
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T80	2		T37	1		T137	2
all_values[8]	auto[0]	auto[1]	auto[1]	102	1			T37	1		T46	1		T196	2
all_values[8]	auto[1]	auto[0]	auto[1]	102	1			T37	3		T46	2		T196	1
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T80	1		T46	2		T196	2
all_values[9]	auto[0]	auto[0]	auto[0]	53	1			T46	1		T243	1		T105	1
all_values[9]	auto[0]	auto[0]	auto[1]	91	1			T37	1		T46	1		T196	1
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T80	1		T37	2		T196	1
all_values[9]	auto[0]	auto[1]	auto[1]	88	1			T80	2		T37	1		T46	3
all_values[9]	auto[1]	auto[0]	auto[1]	87	1			T80	1		T46	1		T196	2
all_values[9]	auto[1]	auto[1]	auto[1]	99	1			T80	3		T37	3		T46	1
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T196	1		T197	2		T162	1
all_values[10]	auto[0]	auto[0]	auto[1]	79	1			T80	1		T37	4		T196	4
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T245	1		T246	1		T247	3
all_values[10]	auto[0]	auto[1]	auto[1]	99	1			T80	3		T46	3		T197	4
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T37	1		T46	1		T196	2
all_values[10]	auto[1]	auto[1]	auto[1]	99	1			T80	3		T37	2		T46	3
all_values[11]	auto[0]	auto[0]	auto[0]	46	1			T80	1		T46	3		T243	1
all_values[11]	auto[0]	auto[0]	auto[1]	91	1			T80	1		T37	2		T46	3
all_values[11]	auto[0]	auto[1]	auto[0]	35	1			T243	1		T106	1		T107	1
all_values[11]	auto[0]	auto[1]	auto[1]	102	1			T37	3		T196	4		T197	3
all_values[11]	auto[1]	auto[0]	auto[1]	86	1			T80	2		T37	1		T196	2
all_values[11]	auto[1]	auto[1]	auto[1]	88	1			T80	3		T37	1		T46	1
all_values[12]	auto[0]	auto[0]	auto[0]	34	1			T46	1		T104	1		T179	2
all_values[12]	auto[0]	auto[0]	auto[1]	86	1			T37	2		T46	2		T196	1
all_values[12]	auto[0]	auto[1]	auto[0]	33	1			T46	1		T197	1		T137	1
all_values[12]	auto[0]	auto[1]	auto[1]	99	1			T80	1		T46	1		T196	3
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T80	4		T37	4		T46	1
all_values[12]	auto[1]	auto[1]	auto[1]	103	1			T80	2		T37	1		T46	1
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T105	4		T245	1		T108	2
all_values[13]	auto[0]	auto[0]	auto[1]	92	1			T196	2		T104	1		T197	7
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T37	1		T196	2		T197	1
all_values[13]	auto[0]	auto[1]	auto[1]	91	1			T80	4		T37	2		T46	3
all_values[13]	auto[1]	auto[0]	auto[1]	100	1			T80	1		T37	2		T46	1
all_values[13]	auto[1]	auto[1]	auto[1]	97	1			T80	2		T37	2		T46	3
all_values[14]	auto[0]	auto[0]	auto[0]	52	1			T80	2		T37	3		T46	1
all_values[14]	auto[0]	auto[0]	auto[1]	98	1			T80	1		T37	1		T196	2
all_values[14]	auto[0]	auto[1]	auto[0]	39	1			T80	1		T37	1		T46	1
all_values[14]	auto[0]	auto[1]	auto[1]	80	1			T80	1		T46	3		T104	2
all_values[14]	auto[1]	auto[0]	auto[1]	85	1			T196	1		T197	5		T243	2
all_values[14]	auto[1]	auto[1]	auto[1]	94	1			T80	2		T37	2		T46	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal