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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.90 96.53 89.89 97.67 69.64 93.48 98.44 90.63


Total test records in report: 1460
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T1297 /workspace/coverage/default/21.i2c_target_stress_wr.3491958801 May 21 02:50:14 PM PDT 24 May 21 02:50:38 PM PDT 24 12759273043 ps
T1298 /workspace/coverage/default/34.i2c_host_fifo_watermark.517269683 May 21 02:52:04 PM PDT 24 May 21 02:54:47 PM PDT 24 25103236777 ps
T1299 /workspace/coverage/default/27.i2c_target_smoke.680329779 May 21 02:51:01 PM PDT 24 May 21 02:51:24 PM PDT 24 1091914821 ps
T1300 /workspace/coverage/default/19.i2c_host_error_intr.1740737481 May 21 02:49:58 PM PDT 24 May 21 02:50:08 PM PDT 24 395289035 ps
T1301 /workspace/coverage/default/46.i2c_host_stress_all.861560444 May 21 02:53:45 PM PDT 24 May 21 03:26:44 PM PDT 24 90879746888 ps
T1302 /workspace/coverage/default/4.i2c_alert_test.2523868666 May 21 02:47:38 PM PDT 24 May 21 02:47:41 PM PDT 24 46559254 ps
T1303 /workspace/coverage/default/23.i2c_target_stretch.2383609503 May 21 02:50:35 PM PDT 24 May 21 02:51:54 PM PDT 24 13166104654 ps
T1304 /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2354847095 May 21 02:47:10 PM PDT 24 May 21 02:47:20 PM PDT 24 374498407 ps
T1305 /workspace/coverage/default/9.i2c_target_timeout.3868229383 May 21 02:48:19 PM PDT 24 May 21 02:48:27 PM PDT 24 5678537770 ps
T1306 /workspace/coverage/default/27.i2c_target_intr_smoke.4145560901 May 21 02:51:04 PM PDT 24 May 21 02:51:15 PM PDT 24 979180251 ps
T1307 /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1546956973 May 21 02:53:02 PM PDT 24 May 21 02:53:07 PM PDT 24 217596693 ps
T1308 /workspace/coverage/default/18.i2c_host_fifo_overflow.3248392153 May 21 02:49:50 PM PDT 24 May 21 02:51:04 PM PDT 24 4744797138 ps
T1309 /workspace/coverage/default/28.i2c_host_smoke.3538050681 May 21 02:51:11 PM PDT 24 May 21 02:51:45 PM PDT 24 8234769727 ps
T1310 /workspace/coverage/default/12.i2c_target_intr_smoke.3603286555 May 21 02:49:00 PM PDT 24 May 21 02:49:10 PM PDT 24 4059296887 ps
T1311 /workspace/coverage/default/36.i2c_host_smoke.2702283970 May 21 02:52:21 PM PDT 24 May 21 02:52:50 PM PDT 24 5496037467 ps
T109 /workspace/coverage/default/40.i2c_host_stress_all.1504102666 May 21 02:52:58 PM PDT 24 May 21 02:55:39 PM PDT 24 28727353622 ps
T1312 /workspace/coverage/default/28.i2c_host_fifo_watermark.4165681125 May 21 02:51:11 PM PDT 24 May 21 02:53:34 PM PDT 24 59858456701 ps
T1313 /workspace/coverage/default/46.i2c_target_fifo_reset_acq.377454344 May 21 02:53:47 PM PDT 24 May 21 02:54:00 PM PDT 24 10433885850 ps
T1314 /workspace/coverage/default/31.i2c_host_error_intr.2008449435 May 21 02:51:40 PM PDT 24 May 21 02:51:47 PM PDT 24 172470779 ps
T1315 /workspace/coverage/default/22.i2c_target_stress_wr.2906129261 May 21 02:50:20 PM PDT 24 May 21 02:59:08 PM PDT 24 55230917427 ps
T1316 /workspace/coverage/default/27.i2c_host_fifo_watermark.675030549 May 21 02:51:09 PM PDT 24 May 21 02:55:36 PM PDT 24 35013730879 ps
T1317 /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1962718880 May 21 02:51:38 PM PDT 24 May 21 02:51:49 PM PDT 24 169031439 ps
T1318 /workspace/coverage/default/44.i2c_target_hrst.902355645 May 21 02:53:35 PM PDT 24 May 21 02:53:41 PM PDT 24 612611756 ps
T1319 /workspace/coverage/default/27.i2c_host_perf.2576497924 May 21 02:51:09 PM PDT 24 May 21 02:52:42 PM PDT 24 6529057059 ps
T1320 /workspace/coverage/default/23.i2c_target_intr_stress_wr.2924387181 May 21 02:50:37 PM PDT 24 May 21 02:52:49 PM PDT 24 18645971018 ps
T1321 /workspace/coverage/default/31.i2c_host_stretch_timeout.1696667362 May 21 02:51:40 PM PDT 24 May 21 02:51:55 PM PDT 24 690475103 ps
T1322 /workspace/coverage/default/47.i2c_target_hrst.1036119548 May 21 02:53:57 PM PDT 24 May 21 02:54:02 PM PDT 24 306356705 ps
T1323 /workspace/coverage/default/23.i2c_target_bad_addr.2651092402 May 21 02:50:36 PM PDT 24 May 21 02:50:42 PM PDT 24 1745369274 ps
T1324 /workspace/coverage/default/30.i2c_target_stress_wr.2819901642 May 21 02:51:34 PM PDT 24 May 21 02:53:11 PM PDT 24 25636218420 ps
T1325 /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1402261316 May 21 02:48:32 PM PDT 24 May 21 02:48:39 PM PDT 24 745544706 ps
T1326 /workspace/coverage/default/38.i2c_host_mode_toggle.3583880590 May 21 02:52:45 PM PDT 24 May 21 02:53:24 PM PDT 24 21593951104 ps
T1327 /workspace/coverage/default/5.i2c_host_fifo_overflow.1239672349 May 21 02:47:38 PM PDT 24 May 21 02:51:11 PM PDT 24 36953073828 ps
T1328 /workspace/coverage/default/41.i2c_host_fifo_overflow.3483931416 May 21 02:53:01 PM PDT 24 May 21 02:55:14 PM PDT 24 1979186157 ps
T1329 /workspace/coverage/default/10.i2c_host_smoke.3819539568 May 21 02:48:33 PM PDT 24 May 21 02:48:56 PM PDT 24 7706929036 ps
T1330 /workspace/coverage/default/16.i2c_host_smoke.2554903337 May 21 02:49:29 PM PDT 24 May 21 02:51:27 PM PDT 24 4106341452 ps
T1331 /workspace/coverage/default/37.i2c_host_may_nack.2481280080 May 21 02:52:39 PM PDT 24 May 21 02:53:02 PM PDT 24 425942865 ps
T1332 /workspace/coverage/default/2.i2c_target_timeout.44890895 May 21 02:47:03 PM PDT 24 May 21 02:47:12 PM PDT 24 1592970303 ps
T1333 /workspace/coverage/default/22.i2c_host_fifo_full.3992180538 May 21 02:50:25 PM PDT 24 May 21 02:51:09 PM PDT 24 6884063446 ps
T1334 /workspace/coverage/default/34.i2c_host_may_nack.4160520681 May 21 02:52:09 PM PDT 24 May 21 02:52:20 PM PDT 24 526032806 ps
T1335 /workspace/coverage/default/48.i2c_target_bad_addr.202611196 May 21 02:54:11 PM PDT 24 May 21 02:54:18 PM PDT 24 782643569 ps
T1336 /workspace/coverage/default/5.i2c_host_perf.3700211914 May 21 02:47:39 PM PDT 24 May 21 02:49:11 PM PDT 24 13220431885 ps
T1337 /workspace/coverage/default/39.i2c_host_error_intr.3243867508 May 21 02:52:50 PM PDT 24 May 21 02:52:54 PM PDT 24 88931816 ps
T1338 /workspace/coverage/default/45.i2c_host_perf.4016534060 May 21 02:53:36 PM PDT 24 May 21 03:05:46 PM PDT 24 12089563480 ps
T1339 /workspace/coverage/default/44.i2c_host_stretch_timeout.4081436846 May 21 02:53:30 PM PDT 24 May 21 02:54:09 PM PDT 24 824042162 ps
T1340 /workspace/coverage/default/48.i2c_target_smoke.1651459047 May 21 02:54:10 PM PDT 24 May 21 02:54:35 PM PDT 24 1435245167 ps
T1341 /workspace/coverage/default/31.i2c_target_stress_wr.4232692951 May 21 02:51:46 PM PDT 24 May 21 02:55:06 PM PDT 24 52802795142 ps
T1342 /workspace/coverage/default/10.i2c_host_perf.3979092346 May 21 02:48:34 PM PDT 24 May 21 02:48:48 PM PDT 24 2688784398 ps
T1343 /workspace/coverage/default/43.i2c_target_intr_smoke.3213496547 May 21 02:53:27 PM PDT 24 May 21 02:53:37 PM PDT 24 8171513698 ps
T127 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2239187924 May 21 03:03:56 PM PDT 24 May 21 03:03:57 PM PDT 24 18333698 ps
T110 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2168145492 May 21 03:03:47 PM PDT 24 May 21 03:03:49 PM PDT 24 19844287 ps
T1344 /workspace/coverage/cover_reg_top/16.i2c_intr_test.829062081 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 22730783 ps
T1345 /workspace/coverage/cover_reg_top/24.i2c_intr_test.338940187 May 21 03:04:16 PM PDT 24 May 21 03:04:17 PM PDT 24 15388105 ps
T1346 /workspace/coverage/cover_reg_top/23.i2c_intr_test.865705636 May 21 03:04:20 PM PDT 24 May 21 03:04:21 PM PDT 24 16766061 ps
T90 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3076444813 May 21 03:03:53 PM PDT 24 May 21 03:03:55 PM PDT 24 39510231 ps
T1347 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1580634610 May 21 03:04:17 PM PDT 24 May 21 03:04:19 PM PDT 24 14565170 ps
T91 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3657963953 May 21 03:04:09 PM PDT 24 May 21 03:04:13 PM PDT 24 207240265 ps
T128 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3169272658 May 21 03:03:59 PM PDT 24 May 21 03:04:03 PM PDT 24 85916506 ps
T1348 /workspace/coverage/cover_reg_top/49.i2c_intr_test.602676068 May 21 03:04:29 PM PDT 24 May 21 03:04:31 PM PDT 24 80721917 ps
T154 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.421874410 May 21 03:04:10 PM PDT 24 May 21 03:04:14 PM PDT 24 132061957 ps
T1349 /workspace/coverage/cover_reg_top/11.i2c_intr_test.4000584465 May 21 03:03:57 PM PDT 24 May 21 03:04:00 PM PDT 24 44878519 ps
T167 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1105528970 May 21 03:04:02 PM PDT 24 May 21 03:04:06 PM PDT 24 67292572 ps
T92 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.951986870 May 21 03:03:59 PM PDT 24 May 21 03:04:02 PM PDT 24 198994122 ps
T168 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1064335145 May 21 03:04:10 PM PDT 24 May 21 03:04:14 PM PDT 24 610210043 ps
T93 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.941260493 May 21 03:03:59 PM PDT 24 May 21 03:04:04 PM PDT 24 102374525 ps
T94 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.106891969 May 21 03:04:16 PM PDT 24 May 21 03:04:17 PM PDT 24 42405420 ps
T95 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1355722774 May 21 03:03:48 PM PDT 24 May 21 03:03:50 PM PDT 24 180794890 ps
T1350 /workspace/coverage/cover_reg_top/10.i2c_intr_test.396852694 May 21 03:03:59 PM PDT 24 May 21 03:04:02 PM PDT 24 92915135 ps
T189 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.220986313 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 93097419 ps
T96 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1240000838 May 21 03:03:55 PM PDT 24 May 21 03:03:58 PM PDT 24 90036038 ps
T1351 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1595858275 May 21 03:03:52 PM PDT 24 May 21 03:03:54 PM PDT 24 46219352 ps
T208 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1282243454 May 21 03:03:36 PM PDT 24 May 21 03:03:37 PM PDT 24 17599717 ps
T180 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4118537956 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 120426726 ps
T97 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1747414589 May 21 03:03:47 PM PDT 24 May 21 03:03:50 PM PDT 24 105999968 ps
T98 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2719806548 May 21 03:04:00 PM PDT 24 May 21 03:04:03 PM PDT 24 88980847 ps
T169 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1996557465 May 21 03:04:03 PM PDT 24 May 21 03:04:07 PM PDT 24 32092419 ps
T190 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3358407644 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 183141553 ps
T99 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2159353309 May 21 03:03:36 PM PDT 24 May 21 03:03:38 PM PDT 24 42439824 ps
T1352 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.63938017 May 21 03:04:09 PM PDT 24 May 21 03:04:12 PM PDT 24 28815921 ps
T1353 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1828337335 May 21 03:03:48 PM PDT 24 May 21 03:03:50 PM PDT 24 16782526 ps
T191 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.739507073 May 21 03:03:59 PM PDT 24 May 21 03:04:02 PM PDT 24 163182182 ps
T226 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.221948730 May 21 03:03:52 PM PDT 24 May 21 03:03:55 PM PDT 24 66589641 ps
T1354 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3737293102 May 21 03:03:56 PM PDT 24 May 21 03:03:59 PM PDT 24 136321074 ps
T174 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.799258120 May 21 03:04:17 PM PDT 24 May 21 03:04:20 PM PDT 24 196542066 ps
T126 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2417421133 May 21 03:03:30 PM PDT 24 May 21 03:03:32 PM PDT 24 68398592 ps
T192 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1474304301 May 21 03:04:09 PM PDT 24 May 21 03:04:13 PM PDT 24 116225021 ps
T1355 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2095620904 May 21 03:04:02 PM PDT 24 May 21 03:04:04 PM PDT 24 103780930 ps
T1356 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.200423771 May 21 03:03:21 PM PDT 24 May 21 03:03:23 PM PDT 24 22529364 ps
T1357 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3675208505 May 21 03:03:29 PM PDT 24 May 21 03:03:31 PM PDT 24 62899796 ps
T181 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3782808579 May 21 03:03:40 PM PDT 24 May 21 03:03:42 PM PDT 24 47035418 ps
T193 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2722735032 May 21 03:03:53 PM PDT 24 May 21 03:03:55 PM PDT 24 24783640 ps
T1358 /workspace/coverage/cover_reg_top/22.i2c_intr_test.670806232 May 21 03:04:18 PM PDT 24 May 21 03:04:20 PM PDT 24 31907639 ps
T1359 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1782001146 May 21 03:03:18 PM PDT 24 May 21 03:03:21 PM PDT 24 23833579 ps
T1360 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3734691145 May 21 03:03:47 PM PDT 24 May 21 03:03:51 PM PDT 24 367630087 ps
T1361 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3468222060 May 21 03:03:44 PM PDT 24 May 21 03:03:46 PM PDT 24 136446534 ps
T194 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2977364785 May 21 03:04:21 PM PDT 24 May 21 03:04:23 PM PDT 24 80676365 ps
T1362 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1789895019 May 21 03:03:17 PM PDT 24 May 21 03:03:19 PM PDT 24 19610404 ps
T1363 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1270779637 May 21 03:04:21 PM PDT 24 May 21 03:04:24 PM PDT 24 28986545 ps
T195 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2414379088 May 21 03:04:13 PM PDT 24 May 21 03:04:14 PM PDT 24 181849272 ps
T1364 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2423283326 May 21 03:04:25 PM PDT 24 May 21 03:04:28 PM PDT 24 54254366 ps
T1365 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1444445244 May 21 03:04:21 PM PDT 24 May 21 03:04:23 PM PDT 24 19613218 ps
T1366 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1141995988 May 21 03:03:52 PM PDT 24 May 21 03:03:55 PM PDT 24 29343895 ps
T1367 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3499415454 May 21 03:03:30 PM PDT 24 May 21 03:03:32 PM PDT 24 23698779 ps
T182 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1341296126 May 21 03:04:09 PM PDT 24 May 21 03:04:12 PM PDT 24 44364894 ps
T1368 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2953328223 May 21 03:04:28 PM PDT 24 May 21 03:04:30 PM PDT 24 20232014 ps
T1369 /workspace/coverage/cover_reg_top/28.i2c_intr_test.401251593 May 21 03:04:21 PM PDT 24 May 21 03:04:23 PM PDT 24 26684292 ps
T1370 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2643521616 May 21 03:03:12 PM PDT 24 May 21 03:03:17 PM PDT 24 211800593 ps
T1371 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.4207934633 May 21 03:03:29 PM PDT 24 May 21 03:03:31 PM PDT 24 99973887 ps
T1372 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3977357649 May 21 03:04:18 PM PDT 24 May 21 03:04:20 PM PDT 24 16802246 ps
T1373 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2808441915 May 21 03:03:58 PM PDT 24 May 21 03:04:01 PM PDT 24 106106805 ps
T1374 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1385019875 May 21 03:03:57 PM PDT 24 May 21 03:03:59 PM PDT 24 77696818 ps
T1375 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1069315228 May 21 03:03:29 PM PDT 24 May 21 03:03:33 PM PDT 24 135419159 ps
T1376 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2064088758 May 21 03:03:37 PM PDT 24 May 21 03:03:38 PM PDT 24 27537164 ps
T1377 /workspace/coverage/cover_reg_top/48.i2c_intr_test.925189285 May 21 03:04:29 PM PDT 24 May 21 03:04:31 PM PDT 24 43449419 ps
T1378 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3467027572 May 21 03:04:17 PM PDT 24 May 21 03:04:20 PM PDT 24 45420481 ps
T1379 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2872040898 May 21 03:04:03 PM PDT 24 May 21 03:04:06 PM PDT 24 190481905 ps
T183 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2592041918 May 21 03:03:53 PM PDT 24 May 21 03:03:55 PM PDT 24 43841220 ps
T1380 /workspace/coverage/cover_reg_top/26.i2c_intr_test.811167635 May 21 03:04:25 PM PDT 24 May 21 03:04:27 PM PDT 24 81083119 ps
T1381 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1010445209 May 21 03:03:59 PM PDT 24 May 21 03:04:03 PM PDT 24 96068663 ps
T184 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1416612273 May 21 03:03:46 PM PDT 24 May 21 03:03:47 PM PDT 24 20106903 ps
T1382 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1431004254 May 21 03:03:59 PM PDT 24 May 21 03:04:04 PM PDT 24 205497570 ps
T1383 /workspace/coverage/cover_reg_top/41.i2c_intr_test.4266959669 May 21 03:04:31 PM PDT 24 May 21 03:04:32 PM PDT 24 15699004 ps
T1384 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1709357026 May 21 03:04:24 PM PDT 24 May 21 03:04:25 PM PDT 24 17138997 ps
T1385 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2022388329 May 21 03:03:18 PM PDT 24 May 21 03:03:21 PM PDT 24 54750512 ps
T1386 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.171050339 May 21 03:03:58 PM PDT 24 May 21 03:04:01 PM PDT 24 25823437 ps
T1387 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1083383204 May 21 03:03:45 PM PDT 24 May 21 03:03:47 PM PDT 24 59210432 ps
T1388 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2399121453 May 21 03:04:21 PM PDT 24 May 21 03:04:24 PM PDT 24 17454668 ps
T1389 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3156262322 May 21 03:04:21 PM PDT 24 May 21 03:04:24 PM PDT 24 18362319 ps
T1390 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3996010448 May 21 03:03:52 PM PDT 24 May 21 03:03:54 PM PDT 24 41757158 ps
T1391 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1971125824 May 21 03:03:58 PM PDT 24 May 21 03:04:01 PM PDT 24 41219772 ps
T1392 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3154821214 May 21 03:03:46 PM PDT 24 May 21 03:03:48 PM PDT 24 30799925 ps
T1393 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.269662701 May 21 03:03:30 PM PDT 24 May 21 03:03:37 PM PDT 24 1759396514 ps
T1394 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3433451423 May 21 03:04:23 PM PDT 24 May 21 03:04:25 PM PDT 24 80650817 ps
T1395 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.75901575 May 21 03:03:41 PM PDT 24 May 21 03:03:46 PM PDT 24 902258932 ps
T1396 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1382856490 May 21 03:04:30 PM PDT 24 May 21 03:04:32 PM PDT 24 22385799 ps
T1397 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2719907741 May 21 03:04:05 PM PDT 24 May 21 03:04:07 PM PDT 24 21188323 ps
T1398 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3487859074 May 21 03:03:37 PM PDT 24 May 21 03:03:39 PM PDT 24 113413487 ps
T1399 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3752483238 May 21 03:04:17 PM PDT 24 May 21 03:04:20 PM PDT 24 22009895 ps
T1400 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1264232007 May 21 03:03:47 PM PDT 24 May 21 03:03:50 PM PDT 24 172365464 ps
T1401 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2260032108 May 21 03:04:17 PM PDT 24 May 21 03:04:18 PM PDT 24 112087916 ps
T1402 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2711375857 May 21 03:03:53 PM PDT 24 May 21 03:03:55 PM PDT 24 71033369 ps
T1403 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1465906189 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 43419877 ps
T1404 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3567850907 May 21 03:04:24 PM PDT 24 May 21 03:04:26 PM PDT 24 17241660 ps
T1405 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2608184028 May 21 03:04:10 PM PDT 24 May 21 03:04:13 PM PDT 24 122093025 ps
T1406 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2197835177 May 21 03:03:33 PM PDT 24 May 21 03:03:36 PM PDT 24 47831580 ps
T1407 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.384342174 May 21 03:03:21 PM PDT 24 May 21 03:03:24 PM PDT 24 260231605 ps
T175 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3012312957 May 21 03:04:00 PM PDT 24 May 21 03:04:03 PM PDT 24 138886318 ps
T1408 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1734304947 May 21 03:04:08 PM PDT 24 May 21 03:04:10 PM PDT 24 62568243 ps
T1409 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2761787156 May 21 03:04:21 PM PDT 24 May 21 03:04:22 PM PDT 24 42839768 ps
T1410 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.547518787 May 21 03:03:39 PM PDT 24 May 21 03:03:42 PM PDT 24 41836359 ps
T1411 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3816182899 May 21 03:03:18 PM PDT 24 May 21 03:03:20 PM PDT 24 23975225 ps
T1412 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3172613288 May 21 03:03:45 PM PDT 24 May 21 03:03:47 PM PDT 24 50757218 ps
T1413 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1644397975 May 21 03:04:03 PM PDT 24 May 21 03:04:06 PM PDT 24 253246047 ps
T1414 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4202112120 May 21 03:03:18 PM PDT 24 May 21 03:03:23 PM PDT 24 158826991 ps
T1415 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1322776989 May 21 03:03:58 PM PDT 24 May 21 03:04:01 PM PDT 24 30079605 ps
T170 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1360857090 May 21 03:03:18 PM PDT 24 May 21 03:03:22 PM PDT 24 96984522 ps
T178 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3282901836 May 21 03:03:18 PM PDT 24 May 21 03:03:22 PM PDT 24 301563326 ps
T1416 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.913027603 May 21 03:03:57 PM PDT 24 May 21 03:03:59 PM PDT 24 40018211 ps
T1417 /workspace/coverage/cover_reg_top/18.i2c_intr_test.4214215548 May 21 03:04:09 PM PDT 24 May 21 03:04:12 PM PDT 24 38964899 ps
T1418 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4110191831 May 21 03:04:00 PM PDT 24 May 21 03:04:04 PM PDT 24 104547976 ps
T1419 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2792866276 May 21 03:04:00 PM PDT 24 May 21 03:04:02 PM PDT 24 24898795 ps
T1420 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1172825949 May 21 03:03:41 PM PDT 24 May 21 03:03:43 PM PDT 24 18848693 ps
T1421 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3680738482 May 21 03:03:57 PM PDT 24 May 21 03:04:00 PM PDT 24 81008823 ps
T1422 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2647123568 May 21 03:04:29 PM PDT 24 May 21 03:04:31 PM PDT 24 33753171 ps
T1423 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1842677817 May 21 03:03:19 PM PDT 24 May 21 03:03:21 PM PDT 24 16526018 ps
T1424 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1749062235 May 21 03:03:18 PM PDT 24 May 21 03:03:21 PM PDT 24 21435340 ps
T1425 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2052237736 May 21 03:04:11 PM PDT 24 May 21 03:04:14 PM PDT 24 114371314 ps
T1426 /workspace/coverage/cover_reg_top/17.i2c_intr_test.860520722 May 21 03:04:09 PM PDT 24 May 21 03:04:12 PM PDT 24 39470748 ps
T172 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4008410047 May 21 03:03:59 PM PDT 24 May 21 03:04:03 PM PDT 24 136322859 ps
T1427 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.712621205 May 21 03:03:23 PM PDT 24 May 21 03:03:25 PM PDT 24 90854036 ps
T1428 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3318909732 May 21 03:03:23 PM PDT 24 May 21 03:03:25 PM PDT 24 39253320 ps
T176 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4127135507 May 21 03:03:45 PM PDT 24 May 21 03:03:47 PM PDT 24 260063815 ps
T1429 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1908063645 May 21 03:03:23 PM PDT 24 May 21 03:03:25 PM PDT 24 62091157 ps
T1430 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2054456266 May 21 03:04:21 PM PDT 24 May 21 03:04:24 PM PDT 24 28986230 ps
T1431 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3327366060 May 21 03:04:26 PM PDT 24 May 21 03:04:28 PM PDT 24 14530091 ps
T1432 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.317767041 May 21 03:03:57 PM PDT 24 May 21 03:04:00 PM PDT 24 50901962 ps
T1433 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3680897838 May 21 03:03:59 PM PDT 24 May 21 03:04:02 PM PDT 24 111597358 ps
T1434 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1740247675 May 21 03:03:47 PM PDT 24 May 21 03:03:50 PM PDT 24 290805112 ps
T1435 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2161913499 May 21 03:03:51 PM PDT 24 May 21 03:03:52 PM PDT 24 114695391 ps
T1436 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1019410201 May 21 03:03:57 PM PDT 24 May 21 03:04:00 PM PDT 24 36817225 ps
T1437 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2499801956 May 21 03:04:03 PM PDT 24 May 21 03:04:06 PM PDT 24 35535714 ps
T1438 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3264382854 May 21 03:03:19 PM PDT 24 May 21 03:03:22 PM PDT 24 458680456 ps
T1439 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3464159880 May 21 03:04:22 PM PDT 24 May 21 03:04:24 PM PDT 24 21224604 ps
T1440 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1317167780 May 21 03:04:09 PM PDT 24 May 21 03:04:11 PM PDT 24 26636071 ps
T1441 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.549925130 May 21 03:03:49 PM PDT 24 May 21 03:03:52 PM PDT 24 22861388 ps
T185 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1462382976 May 21 03:03:17 PM PDT 24 May 21 03:03:18 PM PDT 24 27730996 ps
T1442 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1612105452 May 21 03:04:21 PM PDT 24 May 21 03:04:23 PM PDT 24 16710391 ps
T1443 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.781027311 May 21 03:04:12 PM PDT 24 May 21 03:04:14 PM PDT 24 124935698 ps
T1444 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1042578606 May 21 03:03:26 PM PDT 24 May 21 03:03:30 PM PDT 24 147454222 ps
T186 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1098747940 May 21 03:03:51 PM PDT 24 May 21 03:03:53 PM PDT 24 47183952 ps
T1445 /workspace/coverage/cover_reg_top/13.i2c_intr_test.640332491 May 21 03:03:57 PM PDT 24 May 21 03:04:00 PM PDT 24 19589435 ps
T1446 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3449582627 May 21 03:03:29 PM PDT 24 May 21 03:03:31 PM PDT 24 681239959 ps
T1447 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2877481427 May 21 03:03:42 PM PDT 24 May 21 03:03:44 PM PDT 24 26028851 ps
T1448 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3858641580 May 21 03:04:29 PM PDT 24 May 21 03:04:31 PM PDT 24 50315246 ps
T1449 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3989628940 May 21 03:04:21 PM PDT 24 May 21 03:04:23 PM PDT 24 20986435 ps
T1450 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2018692768 May 21 03:04:17 PM PDT 24 May 21 03:04:19 PM PDT 24 27214398 ps
T187 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2329628906 May 21 03:03:22 PM PDT 24 May 21 03:03:25 PM PDT 24 72790198 ps
T1451 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2780768879 May 21 03:03:42 PM PDT 24 May 21 03:03:46 PM PDT 24 420627038 ps
T1452 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.310247456 May 21 03:03:40 PM PDT 24 May 21 03:03:43 PM PDT 24 57870878 ps
T1453 /workspace/coverage/cover_reg_top/21.i2c_intr_test.76689073 May 21 03:04:17 PM PDT 24 May 21 03:04:19 PM PDT 24 14651137 ps
T1454 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1032042815 May 21 03:04:00 PM PDT 24 May 21 03:04:05 PM PDT 24 491850897 ps
T1455 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2488060134 May 21 03:04:08 PM PDT 24 May 21 03:04:11 PM PDT 24 92504792 ps
T1456 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3395789330 May 21 03:03:52 PM PDT 24 May 21 03:03:54 PM PDT 24 37129364 ps
T1457 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3222301549 May 21 03:03:42 PM PDT 24 May 21 03:03:46 PM PDT 24 811875150 ps
T173 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1434561353 May 21 03:04:07 PM PDT 24 May 21 03:04:10 PM PDT 24 971729744 ps
T1458 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1412606047 May 21 03:03:34 PM PDT 24 May 21 03:03:38 PM PDT 24 893505523 ps
T177 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2020550116 May 21 03:03:47 PM PDT 24 May 21 03:03:50 PM PDT 24 91413090 ps
T171 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3740475184 May 21 03:03:51 PM PDT 24 May 21 03:03:54 PM PDT 24 53993370 ps
T188 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3791072144 May 21 03:03:34 PM PDT 24 May 21 03:03:35 PM PDT 24 56708738 ps
T1459 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3591878493 May 21 03:04:25 PM PDT 24 May 21 03:04:27 PM PDT 24 48271074 ps
T1460 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1025312374 May 21 03:03:30 PM PDT 24 May 21 03:03:31 PM PDT 24 34691130 ps

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2090101456
Short name T7
Test name
Test status
Simulation time 12110602209 ps
CPU time 74.96 seconds
Started May 21 02:49:36 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 896536 kb
Host smart-0cf06d4e-740e-4d72-b2b7-d115590f918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090101456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2090101456
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2559253427
Short name T3
Test name
Test status
Simulation time 1462172945 ps
CPU time 7.83 seconds
Started May 21 02:54:06 PM PDT 24
Finished May 21 02:54:17 PM PDT 24
Peak memory 221448 kb
Host smart-4b523243-a7ad-420d-b99b-a0b1d9c0c468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559253427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2559253427
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3635192539
Short name T80
Test name
Test status
Simulation time 35258783854 ps
CPU time 945.25 seconds
Started May 21 02:51:28 PM PDT 24
Finished May 21 03:07:16 PM PDT 24
Peak memory 1685324 kb
Host smart-89760d66-8f01-458b-8b2b-052444aa17be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635192539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3635192539
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2910890254
Short name T15
Test name
Test status
Simulation time 2294152372 ps
CPU time 11.56 seconds
Started May 21 02:46:17 PM PDT 24
Finished May 21 02:46:30 PM PDT 24
Peak memory 213796 kb
Host smart-e55acdb0-ce5e-4a45-becf-727eaef3c472
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910890254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2910890254
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1355722774
Short name T95
Test name
Test status
Simulation time 180794890 ps
CPU time 0.82 seconds
Started May 21 03:03:48 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203820 kb
Host smart-04aa955b-364f-461f-ace9-5531af31df8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355722774 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1355722774
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1064295414
Short name T35
Test name
Test status
Simulation time 28410001943 ps
CPU time 1261.21 seconds
Started May 21 02:53:38 PM PDT 24
Finished May 21 03:14:43 PM PDT 24
Peak memory 1787108 kb
Host smart-0198ec12-300b-4d7d-bf98-ac1367d9222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064295414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1064295414
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_override.2449153206
Short name T2
Test name
Test status
Simulation time 49608412 ps
CPU time 0.63 seconds
Started May 21 02:49:50 PM PDT 24
Finished May 21 02:49:53 PM PDT 24
Peak memory 204740 kb
Host smart-ecf3dbea-f953-4a97-91f2-bf1cca1b3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449153206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2449153206
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2266352966
Short name T46
Test name
Test status
Simulation time 20367615219 ps
CPU time 1418.93 seconds
Started May 21 02:52:11 PM PDT 24
Finished May 21 03:15:53 PM PDT 24
Peak memory 4524448 kb
Host smart-fc651ea4-5cdc-45b6-84c3-b22fc18a974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266352966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2266352966
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3169272658
Short name T128
Test name
Test status
Simulation time 85916506 ps
CPU time 2.23 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:03 PM PDT 24
Peak memory 203592 kb
Host smart-42f0a5f3-2d37-4bc6-87fa-272e1d77563f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169272658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3169272658
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.2207511737
Short name T144
Test name
Test status
Simulation time 3055170552 ps
CPU time 9.25 seconds
Started May 21 02:48:08 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 205104 kb
Host smart-3ad5113e-7633-4ba0-85b5-0b4e3c8b9879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207511737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.2207511737
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1952472631
Short name T19
Test name
Test status
Simulation time 10087402201 ps
CPU time 24.19 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:51:45 PM PDT 24
Peak memory 339820 kb
Host smart-88126018-d8ad-466d-a771-e7eea83330fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952472631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1952472631
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1149059580
Short name T17
Test name
Test status
Simulation time 34886684438 ps
CPU time 49.07 seconds
Started May 21 02:48:34 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 954388 kb
Host smart-e13178a6-d3e6-4cde-b6bb-7026dbf30aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149059580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1149059580
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1953168955
Short name T368
Test name
Test status
Simulation time 25287773 ps
CPU time 0.62 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:40 PM PDT 24
Peak memory 204668 kb
Host smart-10953dab-f948-4cbf-a23a-437b5a3730fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953168955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1953168955
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2329628906
Short name T187
Test name
Test status
Simulation time 72790198 ps
CPU time 1.42 seconds
Started May 21 03:03:22 PM PDT 24
Finished May 21 03:03:25 PM PDT 24
Peak memory 203704 kb
Host smart-92b04134-0b1b-4483-b513-fe4ec0847662
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329628906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2329628906
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1589994815
Short name T243
Test name
Test status
Simulation time 75196227129 ps
CPU time 3451.49 seconds
Started May 21 02:47:52 PM PDT 24
Finished May 21 03:45:28 PM PDT 24
Peak memory 408492 kb
Host smart-42c2888f-c7f4-440c-8cf0-b22a447d7825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589994815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1589994815
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2769228061
Short name T159
Test name
Test status
Simulation time 213407630 ps
CPU time 0.88 seconds
Started May 21 02:46:50 PM PDT 24
Finished May 21 02:46:52 PM PDT 24
Peak memory 222980 kb
Host smart-f07b9c1b-f862-4715-9000-bd66473230a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769228061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2769228061
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2297531903
Short name T48
Test name
Test status
Simulation time 610381372 ps
CPU time 2.84 seconds
Started May 21 02:50:24 PM PDT 24
Finished May 21 02:50:28 PM PDT 24
Peak memory 222888 kb
Host smart-904c4c22-504d-4f32-bb42-2557b6bdea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297531903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2297531903
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.4121425646
Short name T1
Test name
Test status
Simulation time 1195292827 ps
CPU time 3.28 seconds
Started May 21 02:46:28 PM PDT 24
Finished May 21 02:46:35 PM PDT 24
Peak memory 204984 kb
Host smart-006e6ed4-700d-453b-aded-83b52ebdaa2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121425646 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.4121425646
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.941260493
Short name T93
Test name
Test status
Simulation time 102374525 ps
CPU time 2.15 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:04 PM PDT 24
Peak memory 203860 kb
Host smart-8ca0cc6b-7604-4ef6-b8f4-7d0df6ae8357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941260493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.941260493
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2672838701
Short name T54
Test name
Test status
Simulation time 1844975019 ps
CPU time 1.04 seconds
Started May 21 02:52:37 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 204812 kb
Host smart-a996a8e1-ca18-4906-8112-26e53887cbbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672838701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2672838701
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2068174424
Short name T63
Test name
Test status
Simulation time 3457992861 ps
CPU time 27.28 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:51:05 PM PDT 24
Peak memory 386548 kb
Host smart-6f32f226-3438-429f-8965-09f273001a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068174424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2068174424
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2581657458
Short name T77
Test name
Test status
Simulation time 10120028241 ps
CPU time 53.83 seconds
Started May 21 02:51:23 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 491556 kb
Host smart-a4967694-a989-4ba7-b57e-979da6a4ffdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581657458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2581657458
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.304359563
Short name T203
Test name
Test status
Simulation time 28059842115 ps
CPU time 598.87 seconds
Started May 21 02:46:58 PM PDT 24
Finished May 21 02:56:58 PM PDT 24
Peak memory 2412048 kb
Host smart-c46f3923-47e8-4dc3-8f7d-73d40b91d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304359563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.304359563
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2805265378
Short name T201
Test name
Test status
Simulation time 149919995 ps
CPU time 4.27 seconds
Started May 21 02:51:11 PM PDT 24
Finished May 21 02:51:19 PM PDT 24
Peak memory 230340 kb
Host smart-6cbfa902-aa1b-4ee7-ac6d-6eeac4f32433
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805265378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2805265378
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1474304301
Short name T192
Test name
Test status
Simulation time 116225021 ps
CPU time 1.3 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:13 PM PDT 24
Peak memory 203852 kb
Host smart-fe4dff36-4fd4-418e-a55f-36c3e4c1dec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474304301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1474304301
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3760234761
Short name T344
Test name
Test status
Simulation time 6662149213 ps
CPU time 75.28 seconds
Started May 21 02:48:41 PM PDT 24
Finished May 21 02:49:59 PM PDT 24
Peak memory 403872 kb
Host smart-f1aa3b56-363f-4e8b-a8f4-526738714825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760234761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3760234761
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1434561353
Short name T173
Test name
Test status
Simulation time 971729744 ps
CPU time 2.28 seconds
Started May 21 03:04:07 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203892 kb
Host smart-b26df7b3-e741-4893-b840-55734ca32140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434561353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1434561353
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3042283198
Short name T37
Test name
Test status
Simulation time 42855335145 ps
CPU time 1012.98 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 03:08:42 PM PDT 24
Peak memory 2190312 kb
Host smart-8d095266-d3d2-4c2b-ab40-18c1ad362445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042283198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3042283198
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3380090036
Short name T230
Test name
Test status
Simulation time 10041766204 ps
CPU time 62.23 seconds
Started May 21 02:53:42 PM PDT 24
Finished May 21 02:54:49 PM PDT 24
Peak memory 385328 kb
Host smart-98bd4080-947e-4cb7-86a3-12c022c36c9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380090036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3380090036
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.396852694
Short name T1350
Test name
Test status
Simulation time 92915135 ps
CPU time 0.65 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 203612 kb
Host smart-ee88636a-134a-4c14-a5c7-db92ac54877d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396852694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.396852694
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2820929914
Short name T207
Test name
Test status
Simulation time 581868497 ps
CPU time 1.05 seconds
Started May 21 02:49:05 PM PDT 24
Finished May 21 02:49:10 PM PDT 24
Peak memory 205008 kb
Host smart-a120ae77-30b0-4c55-8b5c-620036405e44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820929914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2820929914
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.768259585
Short name T936
Test name
Test status
Simulation time 574740817 ps
CPU time 4.31 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:50:06 PM PDT 24
Peak memory 205020 kb
Host smart-2defc109-fc47-4cd3-bba9-b68e5096fdf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768259585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.768259585
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2078758706
Short name T179
Test name
Test status
Simulation time 92661403755 ps
CPU time 2475.46 seconds
Started May 21 02:50:23 PM PDT 24
Finished May 21 03:31:40 PM PDT 24
Peak memory 3537080 kb
Host smart-c5183d6b-a770-41c3-a282-48876ec90b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078758706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2078758706
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2840454333
Short name T246
Test name
Test status
Simulation time 56944081305 ps
CPU time 1405.25 seconds
Started May 21 02:48:09 PM PDT 24
Finished May 21 03:11:37 PM PDT 24
Peak memory 2246232 kb
Host smart-5f508bc0-b36b-45f4-883c-2d947ad5d817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840454333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2840454333
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1413613074
Short name T76
Test name
Test status
Simulation time 118952783543 ps
CPU time 1538.34 seconds
Started May 21 02:49:14 PM PDT 24
Finished May 21 03:14:53 PM PDT 24
Peak memory 2194568 kb
Host smart-855cc9a6-8547-42d2-bdaf-ff68268e623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413613074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1413613074
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3473274864
Short name T70
Test name
Test status
Simulation time 5839243679 ps
CPU time 64.38 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:52:15 PM PDT 24
Peak memory 312516 kb
Host smart-9bdbb01b-c943-4dad-a9b3-4b1143e3be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473274864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3473274864
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3412096032
Short name T56
Test name
Test status
Simulation time 89216618823 ps
CPU time 1550.12 seconds
Started May 21 02:49:01 PM PDT 24
Finished May 21 03:14:56 PM PDT 24
Peak memory 3955784 kb
Host smart-bbb3a608-76b4-4bbd-8f8f-53224f1a3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412096032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3412096032
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3782808579
Short name T181
Test name
Test status
Simulation time 47035418 ps
CPU time 0.81 seconds
Started May 21 03:03:40 PM PDT 24
Finished May 21 03:03:42 PM PDT 24
Peak memory 203668 kb
Host smart-c70800c0-b9b5-455d-922b-de1edb839470
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782808579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3782808579
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1621077887
Short name T702
Test name
Test status
Simulation time 1627443610 ps
CPU time 2.36 seconds
Started May 21 02:48:36 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 205084 kb
Host smart-e79dd9b2-cc7d-4671-ac63-305d864f9b2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621077887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1621077887
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3046122825
Short name T239
Test name
Test status
Simulation time 3681074431 ps
CPU time 93.43 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:50:13 PM PDT 24
Peak memory 1067724 kb
Host smart-0e87c09b-b264-4ffb-ad09-c7ea1f419b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046122825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3046122825
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2350628136
Short name T219
Test name
Test status
Simulation time 2920795320 ps
CPU time 27.73 seconds
Started May 21 02:48:42 PM PDT 24
Finished May 21 02:49:13 PM PDT 24
Peak memory 224936 kb
Host smart-746ba9c6-ee81-4cbb-a3bd-9743c351a400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350628136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2350628136
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.4163090175
Short name T225
Test name
Test status
Simulation time 10598781027 ps
CPU time 37.73 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:50:05 PM PDT 24
Peak memory 317704 kb
Host smart-d62a8f0d-3439-4682-97cc-de47c99efdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163090175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.4163090175
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1523472454
Short name T55
Test name
Test status
Simulation time 144448878 ps
CPU time 1.02 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:49:40 PM PDT 24
Peak memory 204800 kb
Host smart-94c572b3-eed0-4657-a28f-1021a0d83afd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523472454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1523472454
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.260804769
Short name T235
Test name
Test status
Simulation time 44794699707 ps
CPU time 651.28 seconds
Started May 21 02:50:34 PM PDT 24
Finished May 21 03:01:27 PM PDT 24
Peak memory 2629732 kb
Host smart-f8a9da64-799d-47dc-a698-8435bd145a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260804769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.260804769
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2990538687
Short name T227
Test name
Test status
Simulation time 10080698958 ps
CPU time 79.69 seconds
Started May 21 02:52:10 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 528448 kb
Host smart-923fdbee-bf14-4c1b-b7cf-9cb26c058674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990538687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2990538687
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2643521616
Short name T1370
Test name
Test status
Simulation time 211800593 ps
CPU time 2.75 seconds
Started May 21 03:03:12 PM PDT 24
Finished May 21 03:03:17 PM PDT 24
Peak memory 203756 kb
Host smart-805c4ab8-af89-4de7-8503-f8ffe02b7318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643521616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2643521616
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2319563669
Short name T41
Test name
Test status
Simulation time 333775124 ps
CPU time 4.2 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:44 PM PDT 24
Peak memory 204980 kb
Host smart-367cc54f-de38-4a67-a0c4-fad039c51c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319563669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2319563669
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1360857090
Short name T170
Test name
Test status
Simulation time 96984522 ps
CPU time 2.3 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:22 PM PDT 24
Peak memory 203868 kb
Host smart-e8c160e3-a519-498b-9d3e-9160c9bc6305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360857090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1360857090
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4008410047
Short name T172
Test name
Test status
Simulation time 136322859 ps
CPU time 2.47 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:03 PM PDT 24
Peak memory 203904 kb
Host smart-dada77f7-e8bf-4b36-b3c5-1942a3f68a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008410047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4008410047
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2719806548
Short name T98
Test name
Test status
Simulation time 88980847 ps
CPU time 1.55 seconds
Started May 21 03:04:00 PM PDT 24
Finished May 21 03:04:03 PM PDT 24
Peak memory 203828 kb
Host smart-978ca478-6e71-4ba3-aa51-0d47d9c0d689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719806548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2719806548
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3012312957
Short name T175
Test name
Test status
Simulation time 138886318 ps
CPU time 1.58 seconds
Started May 21 03:04:00 PM PDT 24
Finished May 21 03:04:03 PM PDT 24
Peak memory 203880 kb
Host smart-46280cbf-4305-406e-b970-ef64cbda1269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012312957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3012312957
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2273689058
Short name T942
Test name
Test status
Simulation time 8212146643 ps
CPU time 44.35 seconds
Started May 21 02:49:01 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 461688 kb
Host smart-4b294f52-e8a3-42bb-8f8b-605fd82a41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273689058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2273689058
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3954932745
Short name T68
Test name
Test status
Simulation time 2686028070 ps
CPU time 24.48 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:53:48 PM PDT 24
Peak memory 410584 kb
Host smart-b109d823-b44e-4ba4-a0a7-ec895d5b1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954932745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3954932745
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1024294128
Short name T130
Test name
Test status
Simulation time 10320443697 ps
CPU time 12.04 seconds
Started May 21 02:53:20 PM PDT 24
Finished May 21 02:53:38 PM PDT 24
Peak memory 267636 kb
Host smart-f2ff9c90-0848-433d-adef-a7f93604161f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024294128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1024294128
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3264382854
Short name T1438
Test name
Test status
Simulation time 458680456 ps
CPU time 1.39 seconds
Started May 21 03:03:19 PM PDT 24
Finished May 21 03:03:22 PM PDT 24
Peak memory 203808 kb
Host smart-41a44a25-e33a-47be-9557-46a0f9f44691
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264382854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3264382854
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4202112120
Short name T1414
Test name
Test status
Simulation time 158826991 ps
CPU time 3 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:23 PM PDT 24
Peak memory 203836 kb
Host smart-e7837f1a-6333-44e8-8c51-711ef3e6788b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202112120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4202112120
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1749062235
Short name T1424
Test name
Test status
Simulation time 21435340 ps
CPU time 0.73 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:21 PM PDT 24
Peak memory 203720 kb
Host smart-3ea37c2d-698b-434d-b6c5-13b3de2338f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749062235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1749062235
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3816182899
Short name T1411
Test name
Test status
Simulation time 23975225 ps
CPU time 0.78 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:20 PM PDT 24
Peak memory 203836 kb
Host smart-91dac7b8-ffc5-4b4c-b7a2-5273a4f9216c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816182899 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3816182899
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1462382976
Short name T185
Test name
Test status
Simulation time 27730996 ps
CPU time 0.77 seconds
Started May 21 03:03:17 PM PDT 24
Finished May 21 03:03:18 PM PDT 24
Peak memory 203748 kb
Host smart-db84c07d-c8e1-4bc6-a6a9-7f7f9100b93f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462382976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1462382976
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1789895019
Short name T1362
Test name
Test status
Simulation time 19610404 ps
CPU time 0.68 seconds
Started May 21 03:03:17 PM PDT 24
Finished May 21 03:03:19 PM PDT 24
Peak memory 203628 kb
Host smart-c4e68e5d-9880-4caf-9306-2c05842a3e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789895019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1789895019
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2022388329
Short name T1385
Test name
Test status
Simulation time 54750512 ps
CPU time 1.18 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:21 PM PDT 24
Peak memory 203792 kb
Host smart-3c33d1ec-88e8-42ab-bc08-fa1979f88896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022388329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2022388329
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1042578606
Short name T1444
Test name
Test status
Simulation time 147454222 ps
CPU time 3.1 seconds
Started May 21 03:03:26 PM PDT 24
Finished May 21 03:03:30 PM PDT 24
Peak memory 203756 kb
Host smart-28d6e3e1-41bd-4715-8341-cec13bedaa92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042578606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1042578606
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.200423771
Short name T1356
Test name
Test status
Simulation time 22529364 ps
CPU time 0.7 seconds
Started May 21 03:03:21 PM PDT 24
Finished May 21 03:03:23 PM PDT 24
Peak memory 203612 kb
Host smart-70279878-40d4-4756-9077-339070ea76a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200423771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.200423771
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1908063645
Short name T1429
Test name
Test status
Simulation time 62091157 ps
CPU time 1.04 seconds
Started May 21 03:03:23 PM PDT 24
Finished May 21 03:03:25 PM PDT 24
Peak memory 203732 kb
Host smart-555e07f6-05c9-4ca7-84ef-315b39172120
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908063645 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1908063645
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1842677817
Short name T1423
Test name
Test status
Simulation time 16526018 ps
CPU time 0.74 seconds
Started May 21 03:03:19 PM PDT 24
Finished May 21 03:03:21 PM PDT 24
Peak memory 203688 kb
Host smart-a8ab1be6-f6b3-46c7-82cc-323045639bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842677817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1842677817
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1782001146
Short name T1359
Test name
Test status
Simulation time 23833579 ps
CPU time 0.62 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:21 PM PDT 24
Peak memory 203640 kb
Host smart-c8162b22-bb30-487d-abac-b25e2b088c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782001146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1782001146
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.712621205
Short name T1427
Test name
Test status
Simulation time 90854036 ps
CPU time 1.19 seconds
Started May 21 03:03:23 PM PDT 24
Finished May 21 03:03:25 PM PDT 24
Peak memory 203880 kb
Host smart-3a349e1f-0d42-4a68-8d78-77d92d023b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712621205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.712621205
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.384342174
Short name T1407
Test name
Test status
Simulation time 260231605 ps
CPU time 2.08 seconds
Started May 21 03:03:21 PM PDT 24
Finished May 21 03:03:24 PM PDT 24
Peak memory 203788 kb
Host smart-bffc5c8c-a98a-4aff-a989-92cbffc04788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384342174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.384342174
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3282901836
Short name T178
Test name
Test status
Simulation time 301563326 ps
CPU time 2.32 seconds
Started May 21 03:03:18 PM PDT 24
Finished May 21 03:03:22 PM PDT 24
Peak memory 203812 kb
Host smart-e4e7c899-c68a-49be-a956-d4c9bb7e78f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282901836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3282901836
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3737293102
Short name T1354
Test name
Test status
Simulation time 136321074 ps
CPU time 1.01 seconds
Started May 21 03:03:56 PM PDT 24
Finished May 21 03:03:59 PM PDT 24
Peak memory 203840 kb
Host smart-e380a272-9a37-4646-9556-feddc5dfda60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737293102 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3737293102
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1019410201
Short name T1436
Test name
Test status
Simulation time 36817225 ps
CPU time 0.69 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:04:00 PM PDT 24
Peak memory 203736 kb
Host smart-e7318b6d-52fd-4313-adf8-2115fbbe5d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019410201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1019410201
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.951986870
Short name T92
Test name
Test status
Simulation time 198994122 ps
CPU time 0.93 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 203644 kb
Host smart-ebe0a5a5-88a4-48c9-8fcc-2973484d18dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951986870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.951986870
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1431004254
Short name T1382
Test name
Test status
Simulation time 205497570 ps
CPU time 2.81 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:04 PM PDT 24
Peak memory 203804 kb
Host smart-a155dc5e-3504-44fd-80f6-59cfa209cdd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431004254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1431004254
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1971125824
Short name T1391
Test name
Test status
Simulation time 41219772 ps
CPU time 0.97 seconds
Started May 21 03:03:58 PM PDT 24
Finished May 21 03:04:01 PM PDT 24
Peak memory 203756 kb
Host smart-910176c3-b426-4410-a8c7-b1e249570ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971125824 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1971125824
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3680738482
Short name T1421
Test name
Test status
Simulation time 81008823 ps
CPU time 0.73 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:04:00 PM PDT 24
Peak memory 203640 kb
Host smart-8ad8ceee-71e0-4bc2-a61c-20f2cabe4f07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680738482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3680738482
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.4000584465
Short name T1349
Test name
Test status
Simulation time 44878519 ps
CPU time 0.67 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:04:00 PM PDT 24
Peak memory 203656 kb
Host smart-73df1c4b-51ae-4495-b7ee-2fa84b7ae55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000584465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.4000584465
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1322776989
Short name T1415
Test name
Test status
Simulation time 30079605 ps
CPU time 1.15 seconds
Started May 21 03:03:58 PM PDT 24
Finished May 21 03:04:01 PM PDT 24
Peak memory 203864 kb
Host smart-14e9fcdf-acbc-4f7b-9e42-348a3ed1be5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322776989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1322776989
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2095620904
Short name T1355
Test name
Test status
Simulation time 103780930 ps
CPU time 0.99 seconds
Started May 21 03:04:02 PM PDT 24
Finished May 21 03:04:04 PM PDT 24
Peak memory 203712 kb
Host smart-04c583af-212f-402e-80b8-6d87afada4e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095620904 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2095620904
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2239187924
Short name T127
Test name
Test status
Simulation time 18333698 ps
CPU time 0.7 seconds
Started May 21 03:03:56 PM PDT 24
Finished May 21 03:03:57 PM PDT 24
Peak memory 203680 kb
Host smart-a333d423-b8ab-49ed-8913-4d67ea769202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239187924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2239187924
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2792866276
Short name T1419
Test name
Test status
Simulation time 24898795 ps
CPU time 0.66 seconds
Started May 21 03:04:00 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 203664 kb
Host smart-610fbc72-c666-4a99-b13c-267ff38a8753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792866276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2792866276
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3680897838
Short name T1433
Test name
Test status
Simulation time 111597358 ps
CPU time 1.27 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 203532 kb
Host smart-82f010ac-c8a4-4004-8684-b8f570a2fdf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680897838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3680897838
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4110191831
Short name T1418
Test name
Test status
Simulation time 104547976 ps
CPU time 1.75 seconds
Started May 21 03:04:00 PM PDT 24
Finished May 21 03:04:04 PM PDT 24
Peak memory 203788 kb
Host smart-6f32f50c-91e3-4b76-8872-3aaf8fbf5260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110191831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4110191831
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1010445209
Short name T1381
Test name
Test status
Simulation time 96068663 ps
CPU time 1.18 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:03 PM PDT 24
Peak memory 203860 kb
Host smart-47c9572e-7d40-4f76-82d5-938223055097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010445209 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1010445209
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.913027603
Short name T1416
Test name
Test status
Simulation time 40018211 ps
CPU time 0.71 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:03:59 PM PDT 24
Peak memory 203692 kb
Host smart-51600f49-a61e-489b-b93b-adef3e707d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913027603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.913027603
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.640332491
Short name T1445
Test name
Test status
Simulation time 19589435 ps
CPU time 0.66 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:04:00 PM PDT 24
Peak memory 203648 kb
Host smart-057cb40e-73b1-434b-a51c-7ac8b485d8de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640332491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.640332491
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.739507073
Short name T191
Test name
Test status
Simulation time 163182182 ps
CPU time 0.86 seconds
Started May 21 03:03:59 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 203692 kb
Host smart-4dc756ad-ae19-46e0-9ae1-9bc387d03d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739507073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.739507073
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1032042815
Short name T1454
Test name
Test status
Simulation time 491850897 ps
CPU time 2.51 seconds
Started May 21 03:04:00 PM PDT 24
Finished May 21 03:04:05 PM PDT 24
Peak memory 203864 kb
Host smart-e99ebae0-753f-404c-94ff-3b2270804036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032042815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1032042815
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1996557465
Short name T169
Test name
Test status
Simulation time 32092419 ps
CPU time 1.39 seconds
Started May 21 03:04:03 PM PDT 24
Finished May 21 03:04:07 PM PDT 24
Peak memory 219344 kb
Host smart-e8cce7c2-8019-4445-8329-4202ae6a3124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996557465 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1996557465
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2872040898
Short name T1379
Test name
Test status
Simulation time 190481905 ps
CPU time 0.69 seconds
Started May 21 03:04:03 PM PDT 24
Finished May 21 03:04:06 PM PDT 24
Peak memory 203780 kb
Host smart-c8b54ea2-146c-4cff-884b-7cf16529c8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872040898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2872040898
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2719907741
Short name T1397
Test name
Test status
Simulation time 21188323 ps
CPU time 0.82 seconds
Started May 21 03:04:05 PM PDT 24
Finished May 21 03:04:07 PM PDT 24
Peak memory 203660 kb
Host smart-02c32562-5fd0-4f86-b82c-d738a097d5e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719907741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2719907741
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1644397975
Short name T1413
Test name
Test status
Simulation time 253246047 ps
CPU time 1.21 seconds
Started May 21 03:04:03 PM PDT 24
Finished May 21 03:04:06 PM PDT 24
Peak memory 203784 kb
Host smart-7658dd35-f51b-4ee7-85f8-2e2bb7588f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644397975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1644397975
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.317767041
Short name T1432
Test name
Test status
Simulation time 50901962 ps
CPU time 1.43 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:04:00 PM PDT 24
Peak memory 203820 kb
Host smart-173a9a30-31bf-4aaa-8a5b-7acadb98cad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317767041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.317767041
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.781027311
Short name T1443
Test name
Test status
Simulation time 124935698 ps
CPU time 0.98 seconds
Started May 21 03:04:12 PM PDT 24
Finished May 21 03:04:14 PM PDT 24
Peak memory 203828 kb
Host smart-7070952e-a5dc-4d68-bd43-d9ee560a2d24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781027311 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.781027311
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3358407644
Short name T190
Test name
Test status
Simulation time 183141553 ps
CPU time 0.73 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203728 kb
Host smart-82892bd3-d554-4cc5-a430-4efd3b2b6f30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358407644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3358407644
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2499801956
Short name T1437
Test name
Test status
Simulation time 35535714 ps
CPU time 0.7 seconds
Started May 21 03:04:03 PM PDT 24
Finished May 21 03:04:06 PM PDT 24
Peak memory 203660 kb
Host smart-218f0e56-95d6-4b3b-8fed-ce2e28d586b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499801956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2499801956
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1105528970
Short name T167
Test name
Test status
Simulation time 67292572 ps
CPU time 1.44 seconds
Started May 21 03:04:02 PM PDT 24
Finished May 21 03:04:06 PM PDT 24
Peak memory 203848 kb
Host smart-91d32ac9-4335-4b0c-8a21-88d7a25a3479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105528970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1105528970
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1734304947
Short name T1408
Test name
Test status
Simulation time 62568243 ps
CPU time 1.01 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203752 kb
Host smart-88cfe137-77ca-43ad-8b20-637ad5678fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734304947 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1734304947
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1341296126
Short name T182
Test name
Test status
Simulation time 44364894 ps
CPU time 0.71 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:12 PM PDT 24
Peak memory 203724 kb
Host smart-72a363d2-4def-4f42-954b-0ff775d8c32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341296126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1341296126
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.829062081
Short name T1344
Test name
Test status
Simulation time 22730783 ps
CPU time 0.65 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203684 kb
Host smart-c66bbad6-cd2a-4877-b314-130b9e18ed45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829062081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.829062081
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.220986313
Short name T189
Test name
Test status
Simulation time 93097419 ps
CPU time 0.84 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203748 kb
Host smart-54d32e51-947c-4bde-92f0-94eb283d8a33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220986313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.220986313
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2052237736
Short name T1425
Test name
Test status
Simulation time 114371314 ps
CPU time 2.18 seconds
Started May 21 03:04:11 PM PDT 24
Finished May 21 03:04:14 PM PDT 24
Peak memory 203856 kb
Host smart-276d5303-3d64-4c10-9cb5-80929a199c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052237736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2052237736
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1064335145
Short name T168
Test name
Test status
Simulation time 610210043 ps
CPU time 2.32 seconds
Started May 21 03:04:10 PM PDT 24
Finished May 21 03:04:14 PM PDT 24
Peak memory 203804 kb
Host smart-9b10ec6e-eb81-4a82-bd1c-6ced11675178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064335145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1064335145
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4118537956
Short name T180
Test name
Test status
Simulation time 120426726 ps
CPU time 1.63 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203952 kb
Host smart-491c75de-8703-49dd-b3c4-74fdae18ab0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118537956 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.4118537956
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1465906189
Short name T1403
Test name
Test status
Simulation time 43419877 ps
CPU time 0.68 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:10 PM PDT 24
Peak memory 203648 kb
Host smart-076487e3-b8f4-4148-8e1a-1771ec65baaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465906189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1465906189
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.860520722
Short name T1426
Test name
Test status
Simulation time 39470748 ps
CPU time 0.64 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:12 PM PDT 24
Peak memory 203660 kb
Host smart-1082082a-c3cf-48d3-87cc-58538baaf842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860520722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.860520722
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2414379088
Short name T195
Test name
Test status
Simulation time 181849272 ps
CPU time 0.84 seconds
Started May 21 03:04:13 PM PDT 24
Finished May 21 03:04:14 PM PDT 24
Peak memory 203692 kb
Host smart-9a32f16a-0fb6-46fa-ae42-4fa81cd978ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414379088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2414379088
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3657963953
Short name T91
Test name
Test status
Simulation time 207240265 ps
CPU time 1.27 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:13 PM PDT 24
Peak memory 203828 kb
Host smart-b4e1d111-2373-4177-8ea6-1ba3c9ab0d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657963953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3657963953
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.421874410
Short name T154
Test name
Test status
Simulation time 132061957 ps
CPU time 2.74 seconds
Started May 21 03:04:10 PM PDT 24
Finished May 21 03:04:14 PM PDT 24
Peak memory 203880 kb
Host smart-b82af7fa-688c-407c-95a1-49ca79941a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421874410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.421874410
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.106891969
Short name T94
Test name
Test status
Simulation time 42405420 ps
CPU time 0.83 seconds
Started May 21 03:04:16 PM PDT 24
Finished May 21 03:04:17 PM PDT 24
Peak memory 203696 kb
Host smart-5b3f6c81-81b9-4bf2-9418-13b3fe63b5af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106891969 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.106891969
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1317167780
Short name T1440
Test name
Test status
Simulation time 26636071 ps
CPU time 0.8 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:11 PM PDT 24
Peak memory 203736 kb
Host smart-8d933de7-d7ac-4376-b760-9a1d19f6851b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317167780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1317167780
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.4214215548
Short name T1417
Test name
Test status
Simulation time 38964899 ps
CPU time 0.65 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:12 PM PDT 24
Peak memory 203628 kb
Host smart-de94909b-ff37-41c8-8425-744c7cf6a5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214215548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.4214215548
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2488060134
Short name T1455
Test name
Test status
Simulation time 92504792 ps
CPU time 1.21 seconds
Started May 21 03:04:08 PM PDT 24
Finished May 21 03:04:11 PM PDT 24
Peak memory 203848 kb
Host smart-5bfb29fe-5796-41f2-b626-dfbb40672fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488060134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2488060134
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.63938017
Short name T1352
Test name
Test status
Simulation time 28815921 ps
CPU time 1.39 seconds
Started May 21 03:04:09 PM PDT 24
Finished May 21 03:04:12 PM PDT 24
Peak memory 203868 kb
Host smart-97756af5-2d13-4945-a69b-ecf3f6c876b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63938017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.63938017
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2608184028
Short name T1405
Test name
Test status
Simulation time 122093025 ps
CPU time 1.62 seconds
Started May 21 03:04:10 PM PDT 24
Finished May 21 03:04:13 PM PDT 24
Peak memory 203824 kb
Host smart-b7233858-f39c-4711-8cbd-854753cee34d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608184028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2608184028
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2260032108
Short name T1401
Test name
Test status
Simulation time 112087916 ps
CPU time 0.74 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:18 PM PDT 24
Peak memory 203836 kb
Host smart-be22539a-06b8-4f38-97fb-872bedee63a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260032108 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2260032108
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2018692768
Short name T1450
Test name
Test status
Simulation time 27214398 ps
CPU time 0.78 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:19 PM PDT 24
Peak memory 203608 kb
Host smart-c5356867-4f62-4c6f-9ea9-900330950ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018692768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2018692768
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3977357649
Short name T1372
Test name
Test status
Simulation time 16802246 ps
CPU time 0.67 seconds
Started May 21 03:04:18 PM PDT 24
Finished May 21 03:04:20 PM PDT 24
Peak memory 203600 kb
Host smart-38dc6113-4937-4343-aa9e-10455457c9d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977357649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3977357649
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2977364785
Short name T194
Test name
Test status
Simulation time 80676365 ps
CPU time 0.98 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:23 PM PDT 24
Peak memory 203712 kb
Host smart-5b0ad68b-3fec-4282-adab-531144836853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977364785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2977364785
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3467027572
Short name T1378
Test name
Test status
Simulation time 45420481 ps
CPU time 2.28 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:20 PM PDT 24
Peak memory 203800 kb
Host smart-eaceea58-ac3b-4f8a-b8dd-9f2a81cf4087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467027572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3467027572
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.799258120
Short name T174
Test name
Test status
Simulation time 196542066 ps
CPU time 1.45 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:20 PM PDT 24
Peak memory 203892 kb
Host smart-9c9b2320-dd46-4725-a543-7d66fa7d60ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799258120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.799258120
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3449582627
Short name T1446
Test name
Test status
Simulation time 681239959 ps
CPU time 2.26 seconds
Started May 21 03:03:29 PM PDT 24
Finished May 21 03:03:31 PM PDT 24
Peak memory 203792 kb
Host smart-3f44dac6-63ab-4a64-a8b6-4b3514a54477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449582627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3449582627
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.269662701
Short name T1393
Test name
Test status
Simulation time 1759396514 ps
CPU time 6.03 seconds
Started May 21 03:03:30 PM PDT 24
Finished May 21 03:03:37 PM PDT 24
Peak memory 203764 kb
Host smart-92128355-a721-47e1-b56e-202ecd7f0339
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269662701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.269662701
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3499415454
Short name T1367
Test name
Test status
Simulation time 23698779 ps
CPU time 0.72 seconds
Started May 21 03:03:30 PM PDT 24
Finished May 21 03:03:32 PM PDT 24
Peak memory 203772 kb
Host smart-1b639882-374d-45ff-8b70-295121ea4e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499415454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3499415454
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3675208505
Short name T1357
Test name
Test status
Simulation time 62899796 ps
CPU time 0.98 seconds
Started May 21 03:03:29 PM PDT 24
Finished May 21 03:03:31 PM PDT 24
Peak memory 203756 kb
Host smart-455ea5b7-1e54-486f-85c7-982677bc6450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675208505 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3675208505
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.4207934633
Short name T1371
Test name
Test status
Simulation time 99973887 ps
CPU time 0.81 seconds
Started May 21 03:03:29 PM PDT 24
Finished May 21 03:03:31 PM PDT 24
Peak memory 203720 kb
Host smart-1515e526-324e-407b-8386-0d07b95df7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207934633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.4207934633
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1025312374
Short name T1460
Test name
Test status
Simulation time 34691130 ps
CPU time 0.62 seconds
Started May 21 03:03:30 PM PDT 24
Finished May 21 03:03:31 PM PDT 24
Peak memory 202944 kb
Host smart-14b95819-f268-4924-b0e5-31419baaf118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025312374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1025312374
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2417421133
Short name T126
Test name
Test status
Simulation time 68398592 ps
CPU time 1.23 seconds
Started May 21 03:03:30 PM PDT 24
Finished May 21 03:03:32 PM PDT 24
Peak memory 203808 kb
Host smart-84da78bf-b6ce-47ed-bc01-be9e2c5c014f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417421133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2417421133
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3318909732
Short name T1428
Test name
Test status
Simulation time 39253320 ps
CPU time 1.08 seconds
Started May 21 03:03:23 PM PDT 24
Finished May 21 03:03:25 PM PDT 24
Peak memory 203832 kb
Host smart-44d107e5-9aba-431c-88a7-6ca94d302cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318909732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3318909732
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3752483238
Short name T1399
Test name
Test status
Simulation time 22009895 ps
CPU time 0.68 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:20 PM PDT 24
Peak memory 203516 kb
Host smart-db2dc199-5486-41d2-baf4-77d03a8c47c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752483238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3752483238
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.76689073
Short name T1453
Test name
Test status
Simulation time 14651137 ps
CPU time 0.66 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:19 PM PDT 24
Peak memory 203580 kb
Host smart-51bd6ad9-4db7-4205-9709-e20305a974df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76689073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.76689073
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.670806232
Short name T1358
Test name
Test status
Simulation time 31907639 ps
CPU time 0.67 seconds
Started May 21 03:04:18 PM PDT 24
Finished May 21 03:04:20 PM PDT 24
Peak memory 203656 kb
Host smart-a1069388-6b1b-43b3-b487-c514dc991f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670806232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.670806232
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.865705636
Short name T1346
Test name
Test status
Simulation time 16766061 ps
CPU time 0.7 seconds
Started May 21 03:04:20 PM PDT 24
Finished May 21 03:04:21 PM PDT 24
Peak memory 203656 kb
Host smart-1fa7b04b-c60c-400c-ad1d-6a7a200a9527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865705636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.865705636
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.338940187
Short name T1345
Test name
Test status
Simulation time 15388105 ps
CPU time 0.67 seconds
Started May 21 03:04:16 PM PDT 24
Finished May 21 03:04:17 PM PDT 24
Peak memory 203604 kb
Host smart-1d76b616-9e2a-4f28-9d23-9f170918d6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338940187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.338940187
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1580634610
Short name T1347
Test name
Test status
Simulation time 14565170 ps
CPU time 0.65 seconds
Started May 21 03:04:17 PM PDT 24
Finished May 21 03:04:19 PM PDT 24
Peak memory 203664 kb
Host smart-88427886-94a5-4dce-8328-eb4f8a0ef995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580634610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1580634610
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.811167635
Short name T1380
Test name
Test status
Simulation time 81083119 ps
CPU time 0.65 seconds
Started May 21 03:04:25 PM PDT 24
Finished May 21 03:04:27 PM PDT 24
Peak memory 203652 kb
Host smart-cebf12c6-c2ab-4b35-88a2-0178346df143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811167635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.811167635
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3989628940
Short name T1449
Test name
Test status
Simulation time 20986435 ps
CPU time 0.69 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:23 PM PDT 24
Peak memory 203624 kb
Host smart-bd06308f-3419-43cf-aad2-eb5774deccd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989628940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3989628940
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.401251593
Short name T1369
Test name
Test status
Simulation time 26684292 ps
CPU time 0.72 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:23 PM PDT 24
Peak memory 203644 kb
Host smart-dc13052b-b603-401b-8fd2-b7c145724fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401251593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.401251593
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2054456266
Short name T1430
Test name
Test status
Simulation time 28986230 ps
CPU time 0.64 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:24 PM PDT 24
Peak memory 203620 kb
Host smart-b1c3fda5-6366-464b-8fd7-c3c676d7a99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054456266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2054456266
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2197835177
Short name T1406
Test name
Test status
Simulation time 47831580 ps
CPU time 2.06 seconds
Started May 21 03:03:33 PM PDT 24
Finished May 21 03:03:36 PM PDT 24
Peak memory 203740 kb
Host smart-2f83207e-b5f4-4f1c-9943-6d4eed3abac4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197835177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2197835177
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1412606047
Short name T1458
Test name
Test status
Simulation time 893505523 ps
CPU time 3.36 seconds
Started May 21 03:03:34 PM PDT 24
Finished May 21 03:03:38 PM PDT 24
Peak memory 203752 kb
Host smart-2463c616-65ac-4101-a54e-87c26dd8857c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412606047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1412606047
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1282243454
Short name T208
Test name
Test status
Simulation time 17599717 ps
CPU time 0.69 seconds
Started May 21 03:03:36 PM PDT 24
Finished May 21 03:03:37 PM PDT 24
Peak memory 203616 kb
Host smart-60308623-8d6c-4dc3-8ee1-e95fdc8aeb69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282243454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1282243454
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2159353309
Short name T99
Test name
Test status
Simulation time 42439824 ps
CPU time 1.03 seconds
Started May 21 03:03:36 PM PDT 24
Finished May 21 03:03:38 PM PDT 24
Peak memory 203788 kb
Host smart-793e8121-528e-4033-a41e-11d4219546a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159353309 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2159353309
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3791072144
Short name T188
Test name
Test status
Simulation time 56708738 ps
CPU time 0.67 seconds
Started May 21 03:03:34 PM PDT 24
Finished May 21 03:03:35 PM PDT 24
Peak memory 203668 kb
Host smart-40afc8ba-da26-4bfa-8f5a-446969b6ae19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791072144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3791072144
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2064088758
Short name T1376
Test name
Test status
Simulation time 27537164 ps
CPU time 0.67 seconds
Started May 21 03:03:37 PM PDT 24
Finished May 21 03:03:38 PM PDT 24
Peak memory 203656 kb
Host smart-13e253ae-b17f-40b7-9749-1400d5d58951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064088758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2064088758
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3487859074
Short name T1398
Test name
Test status
Simulation time 113413487 ps
CPU time 1.29 seconds
Started May 21 03:03:37 PM PDT 24
Finished May 21 03:03:39 PM PDT 24
Peak memory 203860 kb
Host smart-a7fe8ae9-492a-4a61-aed8-1fb416c7530d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487859074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3487859074
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1069315228
Short name T1375
Test name
Test status
Simulation time 135419159 ps
CPU time 2.47 seconds
Started May 21 03:03:29 PM PDT 24
Finished May 21 03:03:33 PM PDT 24
Peak memory 203836 kb
Host smart-75c3fb09-5b1f-4731-9fc5-0b6d107c062b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069315228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1069315228
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2761787156
Short name T1409
Test name
Test status
Simulation time 42839768 ps
CPU time 0.68 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:22 PM PDT 24
Peak memory 203608 kb
Host smart-c927388d-49da-426e-a6f6-b8715c4e8a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761787156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2761787156
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2423283326
Short name T1364
Test name
Test status
Simulation time 54254366 ps
CPU time 0.67 seconds
Started May 21 03:04:25 PM PDT 24
Finished May 21 03:04:28 PM PDT 24
Peak memory 203656 kb
Host smart-119f04c9-be1b-4457-86b9-8a89efec16a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423283326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2423283326
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2399121453
Short name T1388
Test name
Test status
Simulation time 17454668 ps
CPU time 0.65 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:24 PM PDT 24
Peak memory 203664 kb
Host smart-5bb7c8dd-8c65-46ad-b0b7-f577ae93afdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399121453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2399121453
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3567850907
Short name T1404
Test name
Test status
Simulation time 17241660 ps
CPU time 0.7 seconds
Started May 21 03:04:24 PM PDT 24
Finished May 21 03:04:26 PM PDT 24
Peak memory 203656 kb
Host smart-409f16c2-d89b-40ca-a4cf-cfcf85152676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567850907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3567850907
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3464159880
Short name T1439
Test name
Test status
Simulation time 21224604 ps
CPU time 0.68 seconds
Started May 21 03:04:22 PM PDT 24
Finished May 21 03:04:24 PM PDT 24
Peak memory 203648 kb
Host smart-ac8296a4-ff08-4852-8f90-53386d0288ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464159880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3464159880
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3591878493
Short name T1459
Test name
Test status
Simulation time 48271074 ps
CPU time 0.64 seconds
Started May 21 03:04:25 PM PDT 24
Finished May 21 03:04:27 PM PDT 24
Peak memory 203656 kb
Host smart-daf03d8e-e3d7-491d-bf8a-5e640c4a2724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591878493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3591878493
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1709357026
Short name T1384
Test name
Test status
Simulation time 17138997 ps
CPU time 0.7 seconds
Started May 21 03:04:24 PM PDT 24
Finished May 21 03:04:25 PM PDT 24
Peak memory 203660 kb
Host smart-0cc23bb9-d41d-4947-82e0-fa458c183bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709357026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1709357026
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1270779637
Short name T1363
Test name
Test status
Simulation time 28986545 ps
CPU time 0.65 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:24 PM PDT 24
Peak memory 203632 kb
Host smart-d4d38ad5-174c-4a60-84ea-020e586c4b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270779637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1270779637
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3327366060
Short name T1431
Test name
Test status
Simulation time 14530091 ps
CPU time 0.7 seconds
Started May 21 03:04:26 PM PDT 24
Finished May 21 03:04:28 PM PDT 24
Peak memory 203656 kb
Host smart-b3058630-f5ff-468b-a60f-092ae5e38398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327366060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3327366060
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1612105452
Short name T1442
Test name
Test status
Simulation time 16710391 ps
CPU time 0.66 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:23 PM PDT 24
Peak memory 203684 kb
Host smart-a4fa2442-a5e3-4940-b4cc-5beab344f560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612105452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1612105452
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2780768879
Short name T1451
Test name
Test status
Simulation time 420627038 ps
CPU time 2.23 seconds
Started May 21 03:03:42 PM PDT 24
Finished May 21 03:03:46 PM PDT 24
Peak memory 203884 kb
Host smart-981abd14-8be3-4fec-87a4-890a56a8f2f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780768879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2780768879
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.75901575
Short name T1395
Test name
Test status
Simulation time 902258932 ps
CPU time 3.27 seconds
Started May 21 03:03:41 PM PDT 24
Finished May 21 03:03:46 PM PDT 24
Peak memory 203824 kb
Host smart-30db8c3f-dcba-4d91-ba78-69a021033c5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75901575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.75901575
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3154821214
Short name T1392
Test name
Test status
Simulation time 30799925 ps
CPU time 1.34 seconds
Started May 21 03:03:46 PM PDT 24
Finished May 21 03:03:48 PM PDT 24
Peak memory 203908 kb
Host smart-88b1ab5a-a509-4767-8f17-5ca09a8b69fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154821214 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3154821214
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2877481427
Short name T1447
Test name
Test status
Simulation time 26028851 ps
CPU time 0.73 seconds
Started May 21 03:03:42 PM PDT 24
Finished May 21 03:03:44 PM PDT 24
Peak memory 203720 kb
Host smart-97007122-d5cc-499c-abee-834a6434b8fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877481427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2877481427
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1172825949
Short name T1420
Test name
Test status
Simulation time 18848693 ps
CPU time 0.7 seconds
Started May 21 03:03:41 PM PDT 24
Finished May 21 03:03:43 PM PDT 24
Peak memory 203632 kb
Host smart-d9fa3473-759d-4df9-a548-cc8edd082507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172825949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1172825949
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.547518787
Short name T1410
Test name
Test status
Simulation time 41836359 ps
CPU time 0.94 seconds
Started May 21 03:03:39 PM PDT 24
Finished May 21 03:03:42 PM PDT 24
Peak memory 203664 kb
Host smart-4436e3ad-fdb9-46fc-ab15-d9f20ad70bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547518787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.547518787
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3222301549
Short name T1457
Test name
Test status
Simulation time 811875150 ps
CPU time 2.86 seconds
Started May 21 03:03:42 PM PDT 24
Finished May 21 03:03:46 PM PDT 24
Peak memory 203812 kb
Host smart-f54aa0e4-c6f6-456a-8339-6095b8ee836e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222301549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3222301549
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.310247456
Short name T1452
Test name
Test status
Simulation time 57870878 ps
CPU time 1.4 seconds
Started May 21 03:03:40 PM PDT 24
Finished May 21 03:03:43 PM PDT 24
Peak memory 203860 kb
Host smart-6e978433-613b-4e11-91c9-3abb49156972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310247456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.310247456
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3156262322
Short name T1389
Test name
Test status
Simulation time 18362319 ps
CPU time 0.67 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:24 PM PDT 24
Peak memory 203636 kb
Host smart-799e498e-d03a-44ff-b8f0-6ccaea54870a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156262322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3156262322
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.4266959669
Short name T1383
Test name
Test status
Simulation time 15699004 ps
CPU time 0.64 seconds
Started May 21 03:04:31 PM PDT 24
Finished May 21 03:04:32 PM PDT 24
Peak memory 203648 kb
Host smart-4875fb97-e261-4536-95bb-0a3d4b467a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266959669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.4266959669
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3433451423
Short name T1394
Test name
Test status
Simulation time 80650817 ps
CPU time 0.7 seconds
Started May 21 03:04:23 PM PDT 24
Finished May 21 03:04:25 PM PDT 24
Peak memory 203656 kb
Host smart-546d387e-5dab-40b7-adeb-9b54e05ca13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433451423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3433451423
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1444445244
Short name T1365
Test name
Test status
Simulation time 19613218 ps
CPU time 0.74 seconds
Started May 21 03:04:21 PM PDT 24
Finished May 21 03:04:23 PM PDT 24
Peak memory 203664 kb
Host smart-1f01ee31-41aa-4e3b-8689-09eac4a50187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444445244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1444445244
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2647123568
Short name T1422
Test name
Test status
Simulation time 33753171 ps
CPU time 0.73 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:31 PM PDT 24
Peak memory 203660 kb
Host smart-f126655d-be25-436e-8fd5-555251413dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647123568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2647123568
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2953328223
Short name T1368
Test name
Test status
Simulation time 20232014 ps
CPU time 0.69 seconds
Started May 21 03:04:28 PM PDT 24
Finished May 21 03:04:30 PM PDT 24
Peak memory 203700 kb
Host smart-0e4d5698-00de-48bf-988a-cc1803ecdf06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953328223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2953328223
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3858641580
Short name T1448
Test name
Test status
Simulation time 50315246 ps
CPU time 0.68 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:31 PM PDT 24
Peak memory 203668 kb
Host smart-95d60228-021e-461b-9619-623854fe0705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858641580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3858641580
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1382856490
Short name T1396
Test name
Test status
Simulation time 22385799 ps
CPU time 0.72 seconds
Started May 21 03:04:30 PM PDT 24
Finished May 21 03:04:32 PM PDT 24
Peak memory 203680 kb
Host smart-905db0df-75ec-428f-81da-383850e3ece2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382856490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1382856490
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.925189285
Short name T1377
Test name
Test status
Simulation time 43449419 ps
CPU time 0.67 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:31 PM PDT 24
Peak memory 203680 kb
Host smart-ea9a20aa-941a-4bde-b1b1-a426c9be5bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925189285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.925189285
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.602676068
Short name T1348
Test name
Test status
Simulation time 80721917 ps
CPU time 0.69 seconds
Started May 21 03:04:29 PM PDT 24
Finished May 21 03:04:31 PM PDT 24
Peak memory 203636 kb
Host smart-4d22ec6b-4032-4886-9708-61dc93e89e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602676068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.602676068
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.549925130
Short name T1441
Test name
Test status
Simulation time 22861388 ps
CPU time 1.06 seconds
Started May 21 03:03:49 PM PDT 24
Finished May 21 03:03:52 PM PDT 24
Peak memory 203800 kb
Host smart-61ff4fc7-392b-4ff7-931e-383178707e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549925130 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.549925130
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1083383204
Short name T1387
Test name
Test status
Simulation time 59210432 ps
CPU time 0.69 seconds
Started May 21 03:03:45 PM PDT 24
Finished May 21 03:03:47 PM PDT 24
Peak memory 203668 kb
Host smart-7bb4018a-8e95-4a47-95e6-584d0f081723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083383204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1083383204
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2168145492
Short name T110
Test name
Test status
Simulation time 19844287 ps
CPU time 0.65 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:49 PM PDT 24
Peak memory 203680 kb
Host smart-a494fb88-4ba4-4ad6-aaff-7d15ab27349b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168145492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2168145492
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3172613288
Short name T1412
Test name
Test status
Simulation time 50757218 ps
CPU time 1.21 seconds
Started May 21 03:03:45 PM PDT 24
Finished May 21 03:03:47 PM PDT 24
Peak memory 203768 kb
Host smart-900164d2-b2b8-4494-9929-0ddb3d7116d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172613288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3172613288
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3468222060
Short name T1361
Test name
Test status
Simulation time 136446534 ps
CPU time 1.71 seconds
Started May 21 03:03:44 PM PDT 24
Finished May 21 03:03:46 PM PDT 24
Peak memory 203844 kb
Host smart-95788913-1ae3-4a7b-a1c5-7cab0957c276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468222060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3468222060
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4127135507
Short name T176
Test name
Test status
Simulation time 260063815 ps
CPU time 1.52 seconds
Started May 21 03:03:45 PM PDT 24
Finished May 21 03:03:47 PM PDT 24
Peak memory 203844 kb
Host smart-df51bff0-a610-4de1-a7ea-6ccccb939a84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127135507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4127135507
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1416612273
Short name T184
Test name
Test status
Simulation time 20106903 ps
CPU time 0.79 seconds
Started May 21 03:03:46 PM PDT 24
Finished May 21 03:03:47 PM PDT 24
Peak memory 203768 kb
Host smart-84816322-f32b-4bb7-8b3e-573765047129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416612273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1416612273
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1828337335
Short name T1353
Test name
Test status
Simulation time 16782526 ps
CPU time 0.66 seconds
Started May 21 03:03:48 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203652 kb
Host smart-855392fa-8089-4867-9e2f-601f4f092963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828337335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1828337335
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1264232007
Short name T1400
Test name
Test status
Simulation time 172365464 ps
CPU time 0.89 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203696 kb
Host smart-477da5c1-6ea1-44e7-ae45-03e75f6b24db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264232007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1264232007
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3734691145
Short name T1360
Test name
Test status
Simulation time 367630087 ps
CPU time 2.22 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:51 PM PDT 24
Peak memory 203768 kb
Host smart-a90f5feb-da65-4b62-8b73-c8bb082581b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734691145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3734691145
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2020550116
Short name T177
Test name
Test status
Simulation time 91413090 ps
CPU time 2.27 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203824 kb
Host smart-ffa5d879-afe4-4b9d-988e-b4a2243c1e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020550116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2020550116
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2161913499
Short name T1435
Test name
Test status
Simulation time 114695391 ps
CPU time 0.81 seconds
Started May 21 03:03:51 PM PDT 24
Finished May 21 03:03:52 PM PDT 24
Peak memory 203864 kb
Host smart-cff13103-5758-4be0-826b-e16a26bd8fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161913499 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2161913499
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2592041918
Short name T183
Test name
Test status
Simulation time 43841220 ps
CPU time 0.7 seconds
Started May 21 03:03:53 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203656 kb
Host smart-96083b04-af7e-4a60-bbcc-1f3bc8b6d7a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592041918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2592041918
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1595858275
Short name T1351
Test name
Test status
Simulation time 46219352 ps
CPU time 0.7 seconds
Started May 21 03:03:52 PM PDT 24
Finished May 21 03:03:54 PM PDT 24
Peak memory 203656 kb
Host smart-a9e7317d-feb6-49fe-aafc-a70bddd027e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595858275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1595858275
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1141995988
Short name T1366
Test name
Test status
Simulation time 29343895 ps
CPU time 1.18 seconds
Started May 21 03:03:52 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203824 kb
Host smart-385422db-b1da-40ec-90b5-ca8065213fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141995988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1141995988
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1747414589
Short name T97
Test name
Test status
Simulation time 105999968 ps
CPU time 1.39 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203824 kb
Host smart-2e418565-fc6c-4021-821b-b9f153644e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747414589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1747414589
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1740247675
Short name T1434
Test name
Test status
Simulation time 290805112 ps
CPU time 1.52 seconds
Started May 21 03:03:47 PM PDT 24
Finished May 21 03:03:50 PM PDT 24
Peak memory 203876 kb
Host smart-44585dce-996e-428d-a82e-646db4130c26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740247675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1740247675
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.171050339
Short name T1386
Test name
Test status
Simulation time 25823437 ps
CPU time 1.19 seconds
Started May 21 03:03:58 PM PDT 24
Finished May 21 03:04:01 PM PDT 24
Peak memory 203768 kb
Host smart-c979a7b7-d537-4001-b375-f0d35b901af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171050339 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.171050339
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1098747940
Short name T186
Test name
Test status
Simulation time 47183952 ps
CPU time 0.71 seconds
Started May 21 03:03:51 PM PDT 24
Finished May 21 03:03:53 PM PDT 24
Peak memory 203736 kb
Host smart-1d5b807a-83fb-4ddf-a688-23bccef2ee4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098747940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1098747940
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3996010448
Short name T1390
Test name
Test status
Simulation time 41757158 ps
CPU time 0.66 seconds
Started May 21 03:03:52 PM PDT 24
Finished May 21 03:03:54 PM PDT 24
Peak memory 203652 kb
Host smart-654736da-00f2-4f31-bd62-72a812949fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996010448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3996010448
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3076444813
Short name T90
Test name
Test status
Simulation time 39510231 ps
CPU time 0.9 seconds
Started May 21 03:03:53 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203548 kb
Host smart-ca52250b-8bf1-4125-a5be-9992bd2b03dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076444813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3076444813
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1240000838
Short name T96
Test name
Test status
Simulation time 90036038 ps
CPU time 1.88 seconds
Started May 21 03:03:55 PM PDT 24
Finished May 21 03:03:58 PM PDT 24
Peak memory 203808 kb
Host smart-696059d8-38ac-4fb1-94b3-6a80f002afca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240000838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1240000838
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.221948730
Short name T226
Test name
Test status
Simulation time 66589641 ps
CPU time 1.45 seconds
Started May 21 03:03:52 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203812 kb
Host smart-c45909ae-68c8-4398-aa98-7f83592b059a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221948730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.221948730
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1385019875
Short name T1374
Test name
Test status
Simulation time 77696818 ps
CPU time 1.16 seconds
Started May 21 03:03:57 PM PDT 24
Finished May 21 03:03:59 PM PDT 24
Peak memory 203860 kb
Host smart-4c03d8c4-3e1f-4b11-955c-7cbddfd2f3ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385019875 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1385019875
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2722735032
Short name T193
Test name
Test status
Simulation time 24783640 ps
CPU time 0.77 seconds
Started May 21 03:03:53 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203560 kb
Host smart-5a76e3f8-e7ff-466b-8cd7-a61c57cf7fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722735032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2722735032
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3395789330
Short name T1456
Test name
Test status
Simulation time 37129364 ps
CPU time 0.71 seconds
Started May 21 03:03:52 PM PDT 24
Finished May 21 03:03:54 PM PDT 24
Peak memory 203660 kb
Host smart-9d57addb-3059-4103-aefb-0ea99f6b34d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395789330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3395789330
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2711375857
Short name T1402
Test name
Test status
Simulation time 71033369 ps
CPU time 1.29 seconds
Started May 21 03:03:53 PM PDT 24
Finished May 21 03:03:55 PM PDT 24
Peak memory 203804 kb
Host smart-ef38bbd0-29fb-43a0-8fd3-dc52fc20aa18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711375857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2711375857
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2808441915
Short name T1373
Test name
Test status
Simulation time 106106805 ps
CPU time 1.27 seconds
Started May 21 03:03:58 PM PDT 24
Finished May 21 03:04:01 PM PDT 24
Peak memory 203840 kb
Host smart-aed36f12-bf66-48aa-9cff-b0cb5c941b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808441915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2808441915
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3740475184
Short name T171
Test name
Test status
Simulation time 53993370 ps
CPU time 1.45 seconds
Started May 21 03:03:51 PM PDT 24
Finished May 21 03:03:54 PM PDT 24
Peak memory 203880 kb
Host smart-263c4b88-d0cf-4453-81f0-435812d62d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740475184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3740475184
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2534136679
Short name T979
Test name
Test status
Simulation time 78478451 ps
CPU time 0.63 seconds
Started May 21 02:46:28 PM PDT 24
Finished May 21 02:46:31 PM PDT 24
Peak memory 204684 kb
Host smart-e474f488-b9e6-4e1d-8345-7e5cee5cfb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534136679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2534136679
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2223691186
Short name T49
Test name
Test status
Simulation time 95641950 ps
CPU time 2.81 seconds
Started May 21 02:46:15 PM PDT 24
Finished May 21 02:46:20 PM PDT 24
Peak memory 213284 kb
Host smart-aa46f39d-dcf5-4b1d-bca5-a468be6c68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223691186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2223691186
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.546834602
Short name T460
Test name
Test status
Simulation time 347047269 ps
CPU time 4.94 seconds
Started May 21 02:46:09 PM PDT 24
Finished May 21 02:46:15 PM PDT 24
Peak memory 247316 kb
Host smart-619300c1-7ae2-4ca2-b504-619ed357b6a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546834602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.546834602
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3456522486
Short name T810
Test name
Test status
Simulation time 30666890260 ps
CPU time 64.31 seconds
Started May 21 02:46:13 PM PDT 24
Finished May 21 02:47:21 PM PDT 24
Peak memory 547068 kb
Host smart-75ef3279-0f3f-45c2-b50a-c88adbce5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456522486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3456522486
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2069238079
Short name T381
Test name
Test status
Simulation time 3492713938 ps
CPU time 61.81 seconds
Started May 21 02:46:09 PM PDT 24
Finished May 21 02:47:13 PM PDT 24
Peak memory 640744 kb
Host smart-b0f7b1cf-9d13-4076-9e72-d6ea4722542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069238079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2069238079
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.393937365
Short name T1248
Test name
Test status
Simulation time 170377594 ps
CPU time 1.27 seconds
Started May 21 02:46:09 PM PDT 24
Finished May 21 02:46:12 PM PDT 24
Peak memory 204980 kb
Host smart-d0954259-65b5-4711-b5ec-98cf9ba38d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393937365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.393937365
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2362621129
Short name T695
Test name
Test status
Simulation time 142602015 ps
CPU time 3.63 seconds
Started May 21 02:46:17 PM PDT 24
Finished May 21 02:46:22 PM PDT 24
Peak memory 228976 kb
Host smart-abb85ada-00e2-4147-909d-7a857907f420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362621129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2362621129
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3334055240
Short name T642
Test name
Test status
Simulation time 15855494954 ps
CPU time 99.72 seconds
Started May 21 02:46:10 PM PDT 24
Finished May 21 02:47:51 PM PDT 24
Peak memory 1173916 kb
Host smart-c7c37d6c-1574-404d-8215-fd08267a2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334055240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3334055240
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3714852397
Short name T922
Test name
Test status
Simulation time 869854876 ps
CPU time 16.66 seconds
Started May 21 02:46:28 PM PDT 24
Finished May 21 02:46:48 PM PDT 24
Peak memory 204976 kb
Host smart-686da0b3-8e85-4300-8abd-9269ae67b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714852397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3714852397
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2690985515
Short name T1024
Test name
Test status
Simulation time 8371244192 ps
CPU time 40.91 seconds
Started May 21 02:46:28 PM PDT 24
Finished May 21 02:47:13 PM PDT 24
Peak memory 447520 kb
Host smart-e750f1a1-4baf-4d83-9432-66200af96c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690985515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2690985515
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3971377260
Short name T467
Test name
Test status
Simulation time 20032813 ps
CPU time 0.64 seconds
Started May 21 02:46:09 PM PDT 24
Finished May 21 02:46:11 PM PDT 24
Peak memory 204700 kb
Host smart-b44a22b5-d487-4b26-b3d7-5f72fe867f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971377260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3971377260
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.370531427
Short name T914
Test name
Test status
Simulation time 7004568741 ps
CPU time 97.26 seconds
Started May 21 02:46:15 PM PDT 24
Finished May 21 02:47:55 PM PDT 24
Peak memory 644440 kb
Host smart-f1621f1d-cc97-4ea2-bd9f-d3450261d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370531427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.370531427
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3892314813
Short name T768
Test name
Test status
Simulation time 1252449796 ps
CPU time 21.15 seconds
Started May 21 02:46:09 PM PDT 24
Finished May 21 02:46:32 PM PDT 24
Peak memory 375092 kb
Host smart-3e543c6b-d02f-4d45-b2a1-1a7580b517ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892314813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3892314813
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1990723164
Short name T1250
Test name
Test status
Simulation time 32717281804 ps
CPU time 322.44 seconds
Started May 21 02:46:15 PM PDT 24
Finished May 21 02:51:40 PM PDT 24
Peak memory 1273236 kb
Host smart-2413de0b-1579-4196-a2c1-34704cca2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990723164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1990723164
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2731912362
Short name T209
Test name
Test status
Simulation time 1269962060 ps
CPU time 8.56 seconds
Started May 21 02:46:14 PM PDT 24
Finished May 21 02:46:26 PM PDT 24
Peak memory 213432 kb
Host smart-ebe1df1d-9e34-4ba4-a638-d3abbd43fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731912362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2731912362
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.157216719
Short name T156
Test name
Test status
Simulation time 117842083 ps
CPU time 0.81 seconds
Started May 21 02:46:26 PM PDT 24
Finished May 21 02:46:29 PM PDT 24
Peak memory 222348 kb
Host smart-0ef41e09-1968-48f1-af43-b76aabf803ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157216719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.157216719
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2437479591
Short name T598
Test name
Test status
Simulation time 10349095144 ps
CPU time 40.2 seconds
Started May 21 02:46:23 PM PDT 24
Finished May 21 02:47:04 PM PDT 24
Peak memory 344996 kb
Host smart-86622a07-de35-4a08-9656-f524ba5ef77b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437479591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2437479591
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3012364664
Short name T378
Test name
Test status
Simulation time 10041092264 ps
CPU time 63.89 seconds
Started May 21 02:46:27 PM PDT 24
Finished May 21 02:47:33 PM PDT 24
Peak memory 432660 kb
Host smart-84da1c12-77fe-46b8-b599-6bfa25be5bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012364664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3012364664
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1934656463
Short name T21
Test name
Test status
Simulation time 1508992414 ps
CPU time 2.41 seconds
Started May 21 02:46:26 PM PDT 24
Finished May 21 02:46:31 PM PDT 24
Peak memory 205092 kb
Host smart-d0cb08b9-b02c-48b5-9769-60580d2c9679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934656463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1934656463
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2254105308
Short name T581
Test name
Test status
Simulation time 893179351 ps
CPU time 4.29 seconds
Started May 21 02:46:20 PM PDT 24
Finished May 21 02:46:25 PM PDT 24
Peak memory 206888 kb
Host smart-fb3b2d19-f5e4-423b-8703-807bdc178ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254105308 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2254105308
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1336876426
Short name T412
Test name
Test status
Simulation time 23307852726 ps
CPU time 453.83 seconds
Started May 21 02:46:21 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 4000204 kb
Host smart-c1427a62-99da-4e78-ac40-9623c345bb42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336876426 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1336876426
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2749530733
Short name T420
Test name
Test status
Simulation time 4251877596 ps
CPU time 20.09 seconds
Started May 21 02:46:15 PM PDT 24
Finished May 21 02:46:38 PM PDT 24
Peak memory 205140 kb
Host smart-4b32e5bd-48f3-40fd-8ce9-d0e17553ab79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749530733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2749530733
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.930029413
Short name T1215
Test name
Test status
Simulation time 87905423342 ps
CPU time 148.94 seconds
Started May 21 02:46:28 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 1547356 kb
Host smart-df9b1e0f-4f4c-40a5-8de7-b08d91d161e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930029413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.930029413
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2493153368
Short name T451
Test name
Test status
Simulation time 4276254915 ps
CPU time 47.65 seconds
Started May 21 02:46:20 PM PDT 24
Finished May 21 02:47:09 PM PDT 24
Peak memory 207316 kb
Host smart-f498d814-2b8c-4249-96b2-3beb5ffd3ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493153368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2493153368
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1723966410
Short name T407
Test name
Test status
Simulation time 39272887837 ps
CPU time 63.67 seconds
Started May 21 02:46:14 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 1183744 kb
Host smart-bc1e4d08-5967-43aa-9bae-54bbe6dbcd5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723966410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1723966410
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3573023288
Short name T1056
Test name
Test status
Simulation time 11274601868 ps
CPU time 832.99 seconds
Started May 21 02:46:22 PM PDT 24
Finished May 21 03:00:16 PM PDT 24
Peak memory 2152208 kb
Host smart-a2455c0a-8d46-4b14-8ddf-451dbb12fcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573023288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3573023288
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.266715861
Short name T583
Test name
Test status
Simulation time 32642357108 ps
CPU time 7.43 seconds
Started May 21 02:46:19 PM PDT 24
Finished May 21 02:46:27 PM PDT 24
Peak memory 213892 kb
Host smart-63c34c59-a067-490e-a0f9-a2beaf3d4154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266715861 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.266715861
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.377656377
Short name T1116
Test name
Test status
Simulation time 15414076 ps
CPU time 0.63 seconds
Started May 21 02:46:51 PM PDT 24
Finished May 21 02:46:54 PM PDT 24
Peak memory 204652 kb
Host smart-b3d11956-f24e-43a7-ba03-2423d353ccbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377656377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.377656377
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3683064988
Short name T1255
Test name
Test status
Simulation time 188055295 ps
CPU time 2.58 seconds
Started May 21 02:46:33 PM PDT 24
Finished May 21 02:46:39 PM PDT 24
Peak memory 213244 kb
Host smart-10baca6e-d979-4051-abf3-d81626f86b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683064988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3683064988
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1916805984
Short name T643
Test name
Test status
Simulation time 1292622105 ps
CPU time 7.32 seconds
Started May 21 02:46:33 PM PDT 24
Finished May 21 02:46:44 PM PDT 24
Peak memory 272692 kb
Host smart-a78ca895-e084-4610-b2e4-00701748b248
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916805984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1916805984
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1005585394
Short name T517
Test name
Test status
Simulation time 5441813244 ps
CPU time 237.24 seconds
Started May 21 02:46:34 PM PDT 24
Finished May 21 02:50:34 PM PDT 24
Peak memory 908852 kb
Host smart-8f83f599-6435-4dcc-8454-975445add91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005585394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1005585394
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2668137192
Short name T927
Test name
Test status
Simulation time 1835715340 ps
CPU time 45.61 seconds
Started May 21 02:46:32 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 563092 kb
Host smart-7749f610-f5b5-40bb-b8c1-164e35994ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668137192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2668137192
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.4249498997
Short name T734
Test name
Test status
Simulation time 125559298 ps
CPU time 0.98 seconds
Started May 21 02:46:37 PM PDT 24
Finished May 21 02:46:42 PM PDT 24
Peak memory 204796 kb
Host smart-1c2774e5-6bdb-4a52-8954-0ba5e6ad978d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249498997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.4249498997
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1654780471
Short name T1121
Test name
Test status
Simulation time 698437629 ps
CPU time 3.51 seconds
Started May 21 02:46:35 PM PDT 24
Finished May 21 02:46:41 PM PDT 24
Peak memory 204900 kb
Host smart-f5823aaa-9627-40e9-ae6d-b0fe4c6e2c87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654780471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1654780471
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3801606552
Short name T715
Test name
Test status
Simulation time 28100960240 ps
CPU time 329.55 seconds
Started May 21 02:46:35 PM PDT 24
Finished May 21 02:52:08 PM PDT 24
Peak memory 1157528 kb
Host smart-98d6f751-4a64-409c-8e9f-2326f665d67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801606552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3801606552
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.539166577
Short name T1032
Test name
Test status
Simulation time 2462521400 ps
CPU time 9.86 seconds
Started May 21 02:46:50 PM PDT 24
Finished May 21 02:47:02 PM PDT 24
Peak memory 205164 kb
Host smart-ac5a27b6-2e13-4a16-93f2-b594cb836d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539166577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.539166577
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1460451635
Short name T903
Test name
Test status
Simulation time 6845271044 ps
CPU time 84.49 seconds
Started May 21 02:46:47 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 324616 kb
Host smart-e95aaeb5-e4b1-4b16-85ec-6064c6d41b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460451635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1460451635
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3760361772
Short name T337
Test name
Test status
Simulation time 80691535 ps
CPU time 0.64 seconds
Started May 21 02:46:35 PM PDT 24
Finished May 21 02:46:39 PM PDT 24
Peak memory 204692 kb
Host smart-4ebdf048-e541-41c7-a93d-031cb7d31e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760361772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3760361772
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.298834814
Short name T943
Test name
Test status
Simulation time 5441701749 ps
CPU time 48.93 seconds
Started May 21 02:46:35 PM PDT 24
Finished May 21 02:47:27 PM PDT 24
Peak memory 226264 kb
Host smart-e4f0a46d-58f0-453b-b270-849c8c3bf235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298834814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.298834814
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.695437675
Short name T291
Test name
Test status
Simulation time 7034378410 ps
CPU time 32.79 seconds
Started May 21 02:46:33 PM PDT 24
Finished May 21 02:47:09 PM PDT 24
Peak memory 343804 kb
Host smart-e1bc163d-246a-4e11-8b75-3558b414ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695437675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.695437675
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.159283788
Short name T244
Test name
Test status
Simulation time 7812434806 ps
CPU time 462.16 seconds
Started May 21 02:46:34 PM PDT 24
Finished May 21 02:54:20 PM PDT 24
Peak memory 1685968 kb
Host smart-0945fb78-684f-41c9-aa18-e57909f136fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159283788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.159283788
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1654343972
Short name T685
Test name
Test status
Simulation time 2157244690 ps
CPU time 10.37 seconds
Started May 21 02:46:33 PM PDT 24
Finished May 21 02:46:46 PM PDT 24
Peak memory 213344 kb
Host smart-813c479b-491b-45c2-a4ae-67c87f89552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654343972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1654343972
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.105458937
Short name T1085
Test name
Test status
Simulation time 926443467 ps
CPU time 2.47 seconds
Started May 21 02:46:45 PM PDT 24
Finished May 21 02:46:49 PM PDT 24
Peak memory 205040 kb
Host smart-f1a0fac9-c35a-4fc8-9c3c-e5c18009cf7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105458937 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.105458937
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1946669246
Short name T1120
Test name
Test status
Simulation time 10577652190 ps
CPU time 8.67 seconds
Started May 21 02:46:45 PM PDT 24
Finished May 21 02:46:55 PM PDT 24
Peak memory 244776 kb
Host smart-0a10cd4e-37df-446a-ad31-7091f22af8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946669246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1946669246
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2032393947
Short name T550
Test name
Test status
Simulation time 10185728749 ps
CPU time 34.99 seconds
Started May 21 02:46:46 PM PDT 24
Finished May 21 02:47:23 PM PDT 24
Peak memory 376008 kb
Host smart-a2b881b2-95f4-40be-857b-d9ac48f255f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032393947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2032393947
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3188502726
Short name T16
Test name
Test status
Simulation time 2072597681 ps
CPU time 10.33 seconds
Started May 21 02:46:34 PM PDT 24
Finished May 21 02:46:47 PM PDT 24
Peak memory 213632 kb
Host smart-5642eb3a-88aa-42b5-a248-b2b4c29a8188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188502726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3188502726
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.222098100
Short name T1058
Test name
Test status
Simulation time 517600660 ps
CPU time 3.04 seconds
Started May 21 02:46:45 PM PDT 24
Finished May 21 02:46:50 PM PDT 24
Peak memory 205060 kb
Host smart-77f152b0-fd98-489c-9844-0bba91241f88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222098100 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.222098100
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1898010898
Short name T384
Test name
Test status
Simulation time 2630460258 ps
CPU time 4.02 seconds
Started May 21 02:46:39 PM PDT 24
Finished May 21 02:46:47 PM PDT 24
Peak memory 205140 kb
Host smart-f703d7b3-4aa7-4231-b729-fbdae45f8abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898010898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1898010898
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3705143838
Short name T1226
Test name
Test status
Simulation time 2936724401 ps
CPU time 10.92 seconds
Started May 21 02:46:39 PM PDT 24
Finished May 21 02:46:53 PM PDT 24
Peak memory 544844 kb
Host smart-536e4d26-3366-4953-81bb-ce8cbbcd6c95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705143838 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3705143838
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.214882740
Short name T1091
Test name
Test status
Simulation time 1298522100 ps
CPU time 23.16 seconds
Started May 21 02:46:35 PM PDT 24
Finished May 21 02:47:02 PM PDT 24
Peak memory 205016 kb
Host smart-388aedcd-de70-4907-882d-b6655a2e7026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214882740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.214882740
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1236956855
Short name T781
Test name
Test status
Simulation time 6626311792 ps
CPU time 42.93 seconds
Started May 21 02:46:39 PM PDT 24
Finished May 21 02:47:26 PM PDT 24
Peak memory 205136 kb
Host smart-bcda9a80-15e1-47fe-a440-47642e3c66c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236956855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1236956855
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3121769131
Short name T691
Test name
Test status
Simulation time 38787380027 ps
CPU time 135.86 seconds
Started May 21 02:46:38 PM PDT 24
Finished May 21 02:48:57 PM PDT 24
Peak memory 2040060 kb
Host smart-f721810d-86f3-47b6-97f5-134ff39a1ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121769131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3121769131
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1606114915
Short name T1176
Test name
Test status
Simulation time 14579358982 ps
CPU time 561.02 seconds
Started May 21 02:46:39 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 1553616 kb
Host smart-3834bec3-42a7-461e-a4e4-688f7ca822c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606114915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1606114915
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2419985619
Short name T1052
Test name
Test status
Simulation time 1391169129 ps
CPU time 7.13 seconds
Started May 21 02:46:44 PM PDT 24
Finished May 21 02:46:52 PM PDT 24
Peak memory 213236 kb
Host smart-3a41eb39-b169-4132-9bbc-04c30db7947f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419985619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2419985619
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2685471630
Short name T377
Test name
Test status
Simulation time 222009301 ps
CPU time 1.59 seconds
Started May 21 02:48:30 PM PDT 24
Finished May 21 02:48:33 PM PDT 24
Peak memory 213264 kb
Host smart-e2caf247-c84d-4e27-8712-d59b85aa65e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685471630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2685471630
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2542857016
Short name T673
Test name
Test status
Simulation time 1552128595 ps
CPU time 25.31 seconds
Started May 21 02:48:34 PM PDT 24
Finished May 21 02:49:02 PM PDT 24
Peak memory 297992 kb
Host smart-f00c47e9-1495-4254-92cd-e7dcf88c45ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542857016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2542857016
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2966476604
Short name T1184
Test name
Test status
Simulation time 18904857899 ps
CPU time 211.41 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:52:05 PM PDT 24
Peak memory 863572 kb
Host smart-9dcb8973-b2d0-4f11-b60e-99ecae0aadce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966476604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2966476604
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1238615953
Short name T540
Test name
Test status
Simulation time 6941780579 ps
CPU time 56.22 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 620696 kb
Host smart-8291cf68-e9a7-497e-8255-8c936b0e6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238615953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1238615953
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1980774968
Short name T485
Test name
Test status
Simulation time 94386102 ps
CPU time 0.88 seconds
Started May 21 02:48:32 PM PDT 24
Finished May 21 02:48:36 PM PDT 24
Peak memory 204784 kb
Host smart-6db9d88f-dff2-486d-a2bd-8623f58972e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980774968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1980774968
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1402261316
Short name T1325
Test name
Test status
Simulation time 745544706 ps
CPU time 4.87 seconds
Started May 21 02:48:32 PM PDT 24
Finished May 21 02:48:39 PM PDT 24
Peak memory 205012 kb
Host smart-a79daa63-54f0-4ed6-9dc1-b0dbeac35033
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402261316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1402261316
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2933823191
Short name T236
Test name
Test status
Simulation time 4274692701 ps
CPU time 134.22 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:50:48 PM PDT 24
Peak memory 1200352 kb
Host smart-b4080d20-d7ac-4457-8645-d4d839873581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933823191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2933823191
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_override.1059617079
Short name T118
Test name
Test status
Simulation time 138533103 ps
CPU time 0.65 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:48:34 PM PDT 24
Peak memory 204716 kb
Host smart-567f1ab8-52b3-4144-98d7-91a2dab1daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059617079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1059617079
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3979092346
Short name T1342
Test name
Test status
Simulation time 2688784398 ps
CPU time 11.45 seconds
Started May 21 02:48:34 PM PDT 24
Finished May 21 02:48:48 PM PDT 24
Peak memory 299364 kb
Host smart-3d8522a5-7511-4896-8246-36539c76c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979092346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3979092346
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3819539568
Short name T1329
Test name
Test status
Simulation time 7706929036 ps
CPU time 20.04 seconds
Started May 21 02:48:33 PM PDT 24
Finished May 21 02:48:56 PM PDT 24
Peak memory 302668 kb
Host smart-91675c41-bb65-436c-8857-aadc09134d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819539568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3819539568
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.868287853
Short name T893
Test name
Test status
Simulation time 97051205774 ps
CPU time 479.52 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:56:33 PM PDT 24
Peak memory 2118476 kb
Host smart-f607b855-e3a0-41ca-b218-c41a990fdd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868287853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.868287853
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2854695361
Short name T697
Test name
Test status
Simulation time 632483656 ps
CPU time 12.52 seconds
Started May 21 02:48:32 PM PDT 24
Finished May 21 02:48:47 PM PDT 24
Peak memory 214488 kb
Host smart-be4da394-11df-4c44-8be6-0f3638979fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854695361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2854695361
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1875808155
Short name T458
Test name
Test status
Simulation time 2190194923 ps
CPU time 5.32 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:45 PM PDT 24
Peak memory 213300 kb
Host smart-c44ed224-dd7d-4f7e-9f4e-803be73354e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875808155 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1875808155
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3934517850
Short name T1211
Test name
Test status
Simulation time 10183874319 ps
CPU time 15.38 seconds
Started May 21 02:48:41 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 263616 kb
Host smart-ff8f79eb-14ef-4dfd-a354-bdc6bdb1ef7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934517850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3934517850
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2465320629
Short name T541
Test name
Test status
Simulation time 10277348993 ps
CPU time 11.3 seconds
Started May 21 02:48:36 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 251684 kb
Host smart-4cfdfce7-5868-4a79-9e05-f704903a0f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465320629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2465320629
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1342138681
Short name T566
Test name
Test status
Simulation time 4091165694 ps
CPU time 4.49 seconds
Started May 21 02:48:30 PM PDT 24
Finished May 21 02:48:35 PM PDT 24
Peak memory 209020 kb
Host smart-c1a6441e-fcbd-4051-8e95-faff9190b314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342138681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1342138681
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3136144735
Short name T795
Test name
Test status
Simulation time 9017793090 ps
CPU time 11.62 seconds
Started May 21 02:48:36 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 253764 kb
Host smart-707d7751-9257-425a-a9d5-908e636a7330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136144735 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3136144735
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.260757852
Short name T646
Test name
Test status
Simulation time 5274135169 ps
CPU time 10.79 seconds
Started May 21 02:48:29 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 205112 kb
Host smart-0a3de2ee-8b58-4ace-83a8-8c082e920275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260757852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.260757852
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1901611275
Short name T1194
Test name
Test status
Simulation time 5370664141 ps
CPU time 20.36 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:48:52 PM PDT 24
Peak memory 237344 kb
Host smart-12ccc09b-a027-43e6-b1bf-dfae6b168722
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901611275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1901611275
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1812955435
Short name T222
Test name
Test status
Simulation time 11773658526 ps
CPU time 1352.27 seconds
Started May 21 02:48:30 PM PDT 24
Finished May 21 03:11:03 PM PDT 24
Peak memory 2785676 kb
Host smart-dda848ea-b396-48ca-804f-7d9e97ea6f5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812955435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1812955435
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3723994317
Short name T391
Test name
Test status
Simulation time 3264437302 ps
CPU time 5.83 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:45 PM PDT 24
Peak memory 205076 kb
Host smart-6aab2ad2-653a-43d2-aae0-619c8edf0f48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723994317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3723994317
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.639962806
Short name T1138
Test name
Test status
Simulation time 16519046 ps
CPU time 0.68 seconds
Started May 21 02:48:48 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 204672 kb
Host smart-b8c11ede-b311-4c57-9244-f3003ed3c69d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639962806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.639962806
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.4102769320
Short name T684
Test name
Test status
Simulation time 238143705 ps
CPU time 2.22 seconds
Started May 21 02:48:40 PM PDT 24
Finished May 21 02:48:45 PM PDT 24
Peak memory 213272 kb
Host smart-d0bf1ed4-0fa8-46e4-8a5b-f5d7e0ad3bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102769320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.4102769320
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.4053006163
Short name T310
Test name
Test status
Simulation time 1883990084 ps
CPU time 21.47 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:49:01 PM PDT 24
Peak memory 292916 kb
Host smart-540d2cbc-08c9-4dc1-9dd3-4b6755c70525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053006163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.4053006163
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1504119560
Short name T441
Test name
Test status
Simulation time 2005944902 ps
CPU time 61.6 seconds
Started May 21 02:48:43 PM PDT 24
Finished May 21 02:49:47 PM PDT 24
Peak memory 686112 kb
Host smart-05ca2d73-30e1-41b2-9714-fefff472e4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504119560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1504119560
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2373973270
Short name T270
Test name
Test status
Simulation time 1620214425 ps
CPU time 116.61 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:50:37 PM PDT 24
Peak memory 588860 kb
Host smart-7f99bb98-7069-4b1d-9f5e-df3cdc2f330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373973270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2373973270
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2932022983
Short name T1192
Test name
Test status
Simulation time 126642630 ps
CPU time 1.02 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 204796 kb
Host smart-d5d7265d-91e4-46eb-926f-d9c1c0084e8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932022983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2932022983
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1781284864
Short name T1005
Test name
Test status
Simulation time 370669577 ps
CPU time 3.86 seconds
Started May 21 02:48:37 PM PDT 24
Finished May 21 02:48:44 PM PDT 24
Peak memory 205044 kb
Host smart-cd38713f-4101-476b-ad3d-68ecdc0f6be4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781284864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1781284864
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.4108918490
Short name T233
Test name
Test status
Simulation time 2556640948 ps
CPU time 8.97 seconds
Started May 21 02:48:48 PM PDT 24
Finished May 21 02:48:58 PM PDT 24
Peak memory 205116 kb
Host smart-64fc6342-b4b9-426d-a2e3-28af8345cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108918490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.4108918490
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1653768662
Short name T413
Test name
Test status
Simulation time 13380642530 ps
CPU time 118.11 seconds
Started May 21 02:48:48 PM PDT 24
Finished May 21 02:50:47 PM PDT 24
Peak memory 390892 kb
Host smart-6f38a8dc-3279-481b-9bc2-dae9fcb3ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653768662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1653768662
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2702709485
Short name T385
Test name
Test status
Simulation time 41799019 ps
CPU time 0.71 seconds
Started May 21 02:48:38 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 204700 kb
Host smart-22798eec-f349-4cc1-97e7-cd0353a0185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702709485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2702709485
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1597419602
Short name T613
Test name
Test status
Simulation time 19940956834 ps
CPU time 67.36 seconds
Started May 21 02:48:36 PM PDT 24
Finished May 21 02:49:46 PM PDT 24
Peak memory 298280 kb
Host smart-c9291c63-beed-4a06-9115-86b827462107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597419602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1597419602
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1326704489
Short name T245
Test name
Test status
Simulation time 16030080624 ps
CPU time 917.56 seconds
Started May 21 02:48:41 PM PDT 24
Finished May 21 03:04:02 PM PDT 24
Peak memory 3308736 kb
Host smart-78d5b241-614e-41d5-b40c-c96f0a8ccd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326704489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1326704489
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1574194450
Short name T999
Test name
Test status
Simulation time 730820135 ps
CPU time 11.16 seconds
Started May 21 02:48:41 PM PDT 24
Finished May 21 02:48:55 PM PDT 24
Peak memory 221396 kb
Host smart-aecb89ea-25b6-4c59-b9d4-fab8da619846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574194450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1574194450
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3536250541
Short name T1185
Test name
Test status
Simulation time 5593291558 ps
CPU time 3.45 seconds
Started May 21 02:48:47 PM PDT 24
Finished May 21 02:48:51 PM PDT 24
Peak memory 205060 kb
Host smart-5030f0c3-c48f-4ab6-ba9d-413fc9155e23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536250541 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3536250541
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.4178746963
Short name T131
Test name
Test status
Simulation time 10226202378 ps
CPU time 13.08 seconds
Started May 21 02:48:44 PM PDT 24
Finished May 21 02:48:59 PM PDT 24
Peak memory 248240 kb
Host smart-f2d2f990-c146-4d7c-8e2a-794cd3427545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178746963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.4178746963
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.661890470
Short name T1247
Test name
Test status
Simulation time 10086933039 ps
CPU time 67.59 seconds
Started May 21 02:48:48 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 430204 kb
Host smart-a147fbe5-5e57-41f9-adda-65898f07ab99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661890470 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.661890470
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.656920198
Short name T665
Test name
Test status
Simulation time 4461364059 ps
CPU time 2.23 seconds
Started May 21 02:48:49 PM PDT 24
Finished May 21 02:48:53 PM PDT 24
Peak memory 205220 kb
Host smart-44123455-4c30-45ff-88d5-3c3918bbe1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656920198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.656920198
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.324792490
Short name T920
Test name
Test status
Simulation time 5328167626 ps
CPU time 6.95 seconds
Started May 21 02:48:44 PM PDT 24
Finished May 21 02:48:53 PM PDT 24
Peak memory 221124 kb
Host smart-97358c18-0ae0-4ccf-a86f-99f45877bf92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324792490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.324792490
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3935277792
Short name T937
Test name
Test status
Simulation time 16627419701 ps
CPU time 116 seconds
Started May 21 02:48:42 PM PDT 24
Finished May 21 02:50:41 PM PDT 24
Peak memory 1981984 kb
Host smart-374b24d2-34fc-4d79-9216-172cc9243a96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935277792 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3935277792
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2658758908
Short name T603
Test name
Test status
Simulation time 3926450133 ps
CPU time 15.08 seconds
Started May 21 02:48:43 PM PDT 24
Finished May 21 02:49:01 PM PDT 24
Peak memory 205084 kb
Host smart-f756f480-d9f1-45ba-9090-695cb307a2eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658758908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2658758908
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3689460519
Short name T1086
Test name
Test status
Simulation time 18782628720 ps
CPU time 38.93 seconds
Started May 21 02:48:44 PM PDT 24
Finished May 21 02:49:25 PM PDT 24
Peak memory 205024 kb
Host smart-cfbddfdb-1ee8-48ec-8d01-6be40a2337cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689460519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3689460519
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1594572456
Short name T1230
Test name
Test status
Simulation time 14403522592 ps
CPU time 1855.86 seconds
Started May 21 02:48:42 PM PDT 24
Finished May 21 03:19:41 PM PDT 24
Peak memory 3336460 kb
Host smart-fd212ca0-5d49-4381-a9e7-65612330de7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594572456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1594572456
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2978891252
Short name T582
Test name
Test status
Simulation time 2640120054 ps
CPU time 6.32 seconds
Started May 21 02:48:42 PM PDT 24
Finished May 21 02:48:51 PM PDT 24
Peak memory 219024 kb
Host smart-d122b8c1-3d53-4cfa-9630-876e03688a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978891252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2978891252
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3104969707
Short name T329
Test name
Test status
Simulation time 29891183 ps
CPU time 0.57 seconds
Started May 21 02:48:56 PM PDT 24
Finished May 21 02:49:01 PM PDT 24
Peak memory 204648 kb
Host smart-2ff384f3-3892-49c3-ab50-208d67a720ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104969707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3104969707
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.4265664772
Short name T520
Test name
Test status
Simulation time 98507737 ps
CPU time 1.58 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:08 PM PDT 24
Peak memory 213228 kb
Host smart-efcb5dec-2482-4969-93dd-5e08866e81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265664772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.4265664772
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3924598739
Short name T89
Test name
Test status
Simulation time 4711995224 ps
CPU time 24.02 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:49:16 PM PDT 24
Peak memory 300968 kb
Host smart-8c76e18e-f885-4352-b654-72ad8d6b7b8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924598739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3924598739
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2164381095
Short name T1135
Test name
Test status
Simulation time 10340845353 ps
CPU time 94.05 seconds
Started May 21 02:48:51 PM PDT 24
Finished May 21 02:50:28 PM PDT 24
Peak memory 825580 kb
Host smart-504d1888-93ae-4438-bc91-964aaf9d7f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164381095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2164381095
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.5176608
Short name T1183
Test name
Test status
Simulation time 1419314565 ps
CPU time 37.52 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:49:30 PM PDT 24
Peak memory 544320 kb
Host smart-c781626b-b71d-4266-a34f-6038b27e03de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5176608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.5176608
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3236054319
Short name T728
Test name
Test status
Simulation time 391619224 ps
CPU time 0.99 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:48:53 PM PDT 24
Peak memory 204940 kb
Host smart-7a492cb8-6a93-42ce-88fd-bdec700e7cbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236054319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3236054319
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1175388849
Short name T462
Test name
Test status
Simulation time 169632108 ps
CPU time 4.13 seconds
Started May 21 02:48:51 PM PDT 24
Finished May 21 02:48:57 PM PDT 24
Peak memory 234236 kb
Host smart-0849cabe-dde8-432b-84aa-4ded5450dedf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175388849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1175388849
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2502699684
Short name T1267
Test name
Test status
Simulation time 22319659446 ps
CPU time 165.21 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:51:38 PM PDT 24
Peak memory 1538224 kb
Host smart-8378e289-617f-4647-a6b1-4c20624b93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502699684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2502699684
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1153226317
Short name T825
Test name
Test status
Simulation time 2698021097 ps
CPU time 6.58 seconds
Started May 21 02:48:57 PM PDT 24
Finished May 21 02:49:08 PM PDT 24
Peak memory 205096 kb
Host smart-c564804c-b869-4521-82da-a1028caa89e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153226317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1153226317
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.1984405116
Short name T67
Test name
Test status
Simulation time 48835286 ps
CPU time 0.66 seconds
Started May 21 02:48:51 PM PDT 24
Finished May 21 02:48:54 PM PDT 24
Peak memory 204720 kb
Host smart-c85a3185-69cf-44fc-aa2d-99a5a6264dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984405116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1984405116
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3305770735
Short name T908
Test name
Test status
Simulation time 72641121142 ps
CPU time 1662.5 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 03:16:35 PM PDT 24
Peak memory 1532640 kb
Host smart-78dedf2e-20dc-4b9d-81c9-6bb98a73684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305770735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3305770735
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.469227041
Short name T823
Test name
Test status
Simulation time 6020992881 ps
CPU time 26.05 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:49:18 PM PDT 24
Peak memory 343156 kb
Host smart-4c665b59-7f3a-484c-9ebc-68aa5d666e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469227041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.469227041
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.86743845
Short name T1004
Test name
Test status
Simulation time 41292916563 ps
CPU time 971.14 seconds
Started May 21 02:48:56 PM PDT 24
Finished May 21 03:05:11 PM PDT 24
Peak memory 1553676 kb
Host smart-f91d69b4-b6d4-4100-a5a0-f42444f9ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86743845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.86743845
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2322080946
Short name T442
Test name
Test status
Simulation time 769254346 ps
CPU time 36.29 seconds
Started May 21 02:48:50 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 213240 kb
Host smart-7edc72aa-9381-4e7f-9dd8-f882b2e361b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322080946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2322080946
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3260513544
Short name T554
Test name
Test status
Simulation time 1031965759 ps
CPU time 3.23 seconds
Started May 21 02:48:57 PM PDT 24
Finished May 21 02:49:05 PM PDT 24
Peak memory 213184 kb
Host smart-31edab2c-effe-4de8-95cd-1fae16ad56ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260513544 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3260513544
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.504386458
Short name T694
Test name
Test status
Simulation time 10053156697 ps
CPU time 62.31 seconds
Started May 21 02:48:54 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 477420 kb
Host smart-3365e473-87c5-4f1d-9545-e6711f20dae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504386458 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.504386458
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.887574469
Short name T1043
Test name
Test status
Simulation time 10584160159 ps
CPU time 4.32 seconds
Started May 21 02:49:01 PM PDT 24
Finished May 21 02:49:10 PM PDT 24
Peak memory 225564 kb
Host smart-dcf6d45e-3aaa-43fd-b2cd-97990e6c6b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887574469 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.887574469
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1253947731
Short name T294
Test name
Test status
Simulation time 1447848701 ps
CPU time 2.36 seconds
Started May 21 02:48:57 PM PDT 24
Finished May 21 02:49:04 PM PDT 24
Peak memory 205032 kb
Host smart-132d8454-4707-4b69-aa96-a1dbba611bd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253947731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1253947731
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3603286555
Short name T1310
Test name
Test status
Simulation time 4059296887 ps
CPU time 4.84 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:10 PM PDT 24
Peak memory 213224 kb
Host smart-f71579a2-62c9-4293-b0af-91be75f4567a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603286555 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3603286555
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.664231149
Short name T729
Test name
Test status
Simulation time 21537959768 ps
CPU time 61.28 seconds
Started May 21 02:48:58 PM PDT 24
Finished May 21 02:50:04 PM PDT 24
Peak memory 866876 kb
Host smart-8ab9c76e-e47f-42bf-9486-d948f20313d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664231149 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.664231149
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.771700549
Short name T1260
Test name
Test status
Simulation time 4779889229 ps
CPU time 12.12 seconds
Started May 21 02:48:55 PM PDT 24
Finished May 21 02:49:10 PM PDT 24
Peak memory 205108 kb
Host smart-02489152-b738-4491-bc27-d26170731b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771700549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.771700549
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2754794972
Short name T1161
Test name
Test status
Simulation time 275630231 ps
CPU time 11.78 seconds
Started May 21 02:48:54 PM PDT 24
Finished May 21 02:49:09 PM PDT 24
Peak memory 205000 kb
Host smart-0e357c2c-e64a-456c-bc9d-5e5f18c353a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754794972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2754794972
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3888375175
Short name T1075
Test name
Test status
Simulation time 22238771845 ps
CPU time 24.12 seconds
Started May 21 02:48:54 PM PDT 24
Finished May 21 02:49:19 PM PDT 24
Peak memory 341508 kb
Host smart-b9a6ee96-8974-4df2-bed5-5b71a1a2947e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888375175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3888375175
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2528686027
Short name T606
Test name
Test status
Simulation time 3931170013 ps
CPU time 96.43 seconds
Started May 21 02:48:58 PM PDT 24
Finished May 21 02:50:40 PM PDT 24
Peak memory 1034204 kb
Host smart-1b3ac9f2-76b5-49a5-a791-4a47484e7408
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528686027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2528686027
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3131732624
Short name T290
Test name
Test status
Simulation time 7006761322 ps
CPU time 6.49 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:13 PM PDT 24
Peak memory 205108 kb
Host smart-21eb80f7-a037-4fef-aff2-5a7f554557bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131732624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3131732624
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3757001600
Short name T1128
Test name
Test status
Simulation time 16623149 ps
CPU time 0.63 seconds
Started May 21 02:49:05 PM PDT 24
Finished May 21 02:49:10 PM PDT 24
Peak memory 204668 kb
Host smart-445c5ada-1f57-4ce6-83c6-176c802709e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757001600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3757001600
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1443337472
Short name T1131
Test name
Test status
Simulation time 175147233 ps
CPU time 2.86 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:08 PM PDT 24
Peak memory 219668 kb
Host smart-a45415ec-40a2-421b-83aa-615ebee64a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443337472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1443337472
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2136001795
Short name T500
Test name
Test status
Simulation time 752484302 ps
CPU time 8.24 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 280868 kb
Host smart-62ca5089-8eec-4b84-86fd-c0f980d02fac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136001795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2136001795
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.229330412
Short name T775
Test name
Test status
Simulation time 3730408509 ps
CPU time 45 seconds
Started May 21 02:48:59 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 445752 kb
Host smart-f10f3d0e-8d69-484f-8cb8-f3c137acd3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229330412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.229330412
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.683176025
Short name T969
Test name
Test status
Simulation time 9044365371 ps
CPU time 69.54 seconds
Started May 21 02:49:01 PM PDT 24
Finished May 21 02:50:16 PM PDT 24
Peak memory 745008 kb
Host smart-0cc0a2aa-bde1-4419-9600-ff4fe572980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683176025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.683176025
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3876668194
Short name T506
Test name
Test status
Simulation time 337057543 ps
CPU time 1.22 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:07 PM PDT 24
Peak memory 205040 kb
Host smart-0e8f38c4-2fe9-4054-9cf2-f93d307f9dff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876668194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3876668194
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.970426107
Short name T1108
Test name
Test status
Simulation time 807076846 ps
CPU time 4.41 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:09 PM PDT 24
Peak memory 204988 kb
Host smart-197c5904-33a5-4623-a695-eb83e5a730d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970426107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
970426107
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.93916700
Short name T967
Test name
Test status
Simulation time 3454599871 ps
CPU time 262.35 seconds
Started May 21 02:48:57 PM PDT 24
Finished May 21 02:53:24 PM PDT 24
Peak memory 1007512 kb
Host smart-2b5b07fd-9549-4e30-86d0-f417d19d2c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93916700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.93916700
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1931693765
Short name T490
Test name
Test status
Simulation time 1774789592 ps
CPU time 6.9 seconds
Started May 21 02:49:07 PM PDT 24
Finished May 21 02:49:18 PM PDT 24
Peak memory 205012 kb
Host smart-78a5c4c7-9f74-45b6-9d76-5a8eda7f5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931693765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1931693765
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3150119495
Short name T512
Test name
Test status
Simulation time 8607274968 ps
CPU time 97.61 seconds
Started May 21 02:49:05 PM PDT 24
Finished May 21 02:50:47 PM PDT 24
Peak memory 370696 kb
Host smart-fb2c5275-7995-4106-a160-8e5b5c035805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150119495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3150119495
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3366158222
Short name T553
Test name
Test status
Simulation time 31378468 ps
CPU time 0.66 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:07 PM PDT 24
Peak memory 204688 kb
Host smart-1e8a7419-1900-4b64-8b49-9d0bbee58152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366158222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3366158222
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1839922417
Short name T484
Test name
Test status
Simulation time 3788617479 ps
CPU time 57.23 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:50:04 PM PDT 24
Peak memory 560048 kb
Host smart-3d337a77-fb18-46b1-bee2-8ec38837ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839922417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1839922417
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1959621011
Short name T669
Test name
Test status
Simulation time 1025134158 ps
CPU time 20.88 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:28 PM PDT 24
Peak memory 326860 kb
Host smart-ecb84c7e-583a-4898-ab13-c96360e7ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959621011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1959621011
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2269746170
Short name T1242
Test name
Test status
Simulation time 9869483500 ps
CPU time 16.02 seconds
Started May 21 02:49:01 PM PDT 24
Finished May 21 02:49:22 PM PDT 24
Peak memory 229652 kb
Host smart-d32f5f12-79f4-497e-80fa-30bb1aa4e99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269746170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2269746170
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.4271674368
Short name T275
Test name
Test status
Simulation time 5959015074 ps
CPU time 3.59 seconds
Started May 21 02:49:06 PM PDT 24
Finished May 21 02:49:14 PM PDT 24
Peak memory 213464 kb
Host smart-38fa3a93-4499-4e32-aa94-3e050b509e6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271674368 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.4271674368
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1713385173
Short name T1246
Test name
Test status
Simulation time 10152596829 ps
CPU time 70.38 seconds
Started May 21 02:49:06 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 555448 kb
Host smart-c12acf80-aa96-44b5-81a5-880dd3e9f986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713385173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1713385173
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.734989992
Short name T353
Test name
Test status
Simulation time 10302853072 ps
CPU time 7.9 seconds
Started May 21 02:49:06 PM PDT 24
Finished May 21 02:49:18 PM PDT 24
Peak memory 260732 kb
Host smart-918a1784-679b-4926-aeb8-6ab19fbe260e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734989992 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.734989992
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2739294759
Short name T88
Test name
Test status
Simulation time 1370475487 ps
CPU time 2.27 seconds
Started May 21 02:49:07 PM PDT 24
Finished May 21 02:49:13 PM PDT 24
Peak memory 205088 kb
Host smart-0543616d-077e-453c-92c7-4eed4f1d0041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739294759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2739294759
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2743410680
Short name T389
Test name
Test status
Simulation time 4593557167 ps
CPU time 6.25 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:11 PM PDT 24
Peak memory 205048 kb
Host smart-a32c0d64-cb01-4fd1-a46a-68c2ce20db3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743410680 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2743410680
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2224565450
Short name T322
Test name
Test status
Simulation time 17285304448 ps
CPU time 346.72 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:54:54 PM PDT 24
Peak memory 4144448 kb
Host smart-4899d979-bab6-45cc-b42d-8acb6673aaac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224565450 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2224565450
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3009024315
Short name T562
Test name
Test status
Simulation time 2767602572 ps
CPU time 10.71 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:16 PM PDT 24
Peak memory 205072 kb
Host smart-741968e7-b23a-4c7c-b222-364a19354aae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009024315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3009024315
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3024063481
Short name T565
Test name
Test status
Simulation time 3416769306 ps
CPU time 15.12 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:22 PM PDT 24
Peak memory 214168 kb
Host smart-0467ce08-3787-4f36-a7e3-14df7239a9a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024063481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3024063481
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.4103497409
Short name T803
Test name
Test status
Simulation time 20330213603 ps
CPU time 37.83 seconds
Started May 21 02:49:02 PM PDT 24
Finished May 21 02:49:44 PM PDT 24
Peak memory 205032 kb
Host smart-91efedb1-f7a0-4a66-8ba9-8a24762fc66d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103497409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.4103497409
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2520618956
Short name T371
Test name
Test status
Simulation time 34062766116 ps
CPU time 2229.68 seconds
Started May 21 02:48:59 PM PDT 24
Finished May 21 03:26:15 PM PDT 24
Peak memory 3901512 kb
Host smart-d0054267-d0c2-442e-b898-39f22bbf4eec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520618956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2520618956
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3677784883
Short name T491
Test name
Test status
Simulation time 1438972091 ps
CPU time 7.1 seconds
Started May 21 02:49:00 PM PDT 24
Finished May 21 02:49:12 PM PDT 24
Peak memory 213216 kb
Host smart-69e75914-4c3d-4012-b851-ded6405e61d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677784883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3677784883
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2469210462
Short name T772
Test name
Test status
Simulation time 85362366 ps
CPU time 0.61 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:20 PM PDT 24
Peak memory 204672 kb
Host smart-a24581ae-27da-4e80-84f8-bd6a179da897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469210462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2469210462
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2415597861
Short name T626
Test name
Test status
Simulation time 95945523 ps
CPU time 1.28 seconds
Started May 21 02:49:12 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 213336 kb
Host smart-ef9e9f3f-ebff-4d59-8a88-11c1ebe1b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415597861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2415597861
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.4068940476
Short name T251
Test name
Test status
Simulation time 5104418415 ps
CPU time 6.55 seconds
Started May 21 02:49:05 PM PDT 24
Finished May 21 02:49:17 PM PDT 24
Peak memory 274296 kb
Host smart-ca271388-dcdd-4b1a-a141-a5744d783c73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068940476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.4068940476
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3086607702
Short name T599
Test name
Test status
Simulation time 8889227730 ps
CPU time 53.66 seconds
Started May 21 02:49:12 PM PDT 24
Finished May 21 02:50:07 PM PDT 24
Peak memory 370208 kb
Host smart-51aa6cf0-b9ca-45df-8d66-8ed6221149eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086607702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3086607702
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3207252819
Short name T72
Test name
Test status
Simulation time 2245227816 ps
CPU time 81.18 seconds
Started May 21 02:49:07 PM PDT 24
Finished May 21 02:50:32 PM PDT 24
Peak memory 744632 kb
Host smart-85256970-1c16-4ec2-a7d5-9d3d16642462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207252819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3207252819
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2685262203
Short name T134
Test name
Test status
Simulation time 249702866 ps
CPU time 6.67 seconds
Started May 21 02:49:07 PM PDT 24
Finished May 21 02:49:18 PM PDT 24
Peak memory 250944 kb
Host smart-43d917f7-c3ed-43e8-aac9-4e1966d41c03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685262203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2685262203
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3509100881
Short name T64
Test name
Test status
Simulation time 10040586706 ps
CPU time 166.49 seconds
Started May 21 02:49:06 PM PDT 24
Finished May 21 02:51:57 PM PDT 24
Peak memory 1459792 kb
Host smart-66d772aa-8590-4a28-be62-d4afa7c28332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509100881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3509100881
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3171896496
Short name T700
Test name
Test status
Simulation time 366077940 ps
CPU time 15.41 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:36 PM PDT 24
Peak memory 204956 kb
Host smart-7cbb0c13-f176-49b0-914b-258c3df09946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171896496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3171896496
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3450304664
Short name T1201
Test name
Test status
Simulation time 3418061878 ps
CPU time 30.11 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 295724 kb
Host smart-81448fab-9042-4464-8351-8727b419cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450304664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3450304664
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.758884192
Short name T1222
Test name
Test status
Simulation time 15889688 ps
CPU time 0.64 seconds
Started May 21 02:49:07 PM PDT 24
Finished May 21 02:49:12 PM PDT 24
Peak memory 204696 kb
Host smart-cd484a42-f5c1-4368-9130-35dbc20a552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758884192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.758884192
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.964229180
Short name T1266
Test name
Test status
Simulation time 1409638201 ps
CPU time 2.91 seconds
Started May 21 02:49:16 PM PDT 24
Finished May 21 02:49:20 PM PDT 24
Peak memory 204992 kb
Host smart-b798f5ec-3e57-4655-8dac-bf1701513960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964229180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.964229180
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3241695450
Short name T443
Test name
Test status
Simulation time 7606426432 ps
CPU time 84.35 seconds
Started May 21 02:49:06 PM PDT 24
Finished May 21 02:50:35 PM PDT 24
Peak memory 414484 kb
Host smart-ebf05276-706b-48ba-a388-f803d3497e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241695450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3241695450
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.303283816
Short name T633
Test name
Test status
Simulation time 661362412 ps
CPU time 29.66 seconds
Started May 21 02:49:12 PM PDT 24
Finished May 21 02:49:43 PM PDT 24
Peak memory 213196 kb
Host smart-2537b375-0c55-4caa-b10c-f0412a194fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303283816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.303283816
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.440975214
Short name T1236
Test name
Test status
Simulation time 1649294804 ps
CPU time 2.52 seconds
Started May 21 02:49:17 PM PDT 24
Finished May 21 02:49:21 PM PDT 24
Peak memory 205016 kb
Host smart-1af1d989-7842-4059-8291-5b036b97b433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440975214 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.440975214
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3606925792
Short name T997
Test name
Test status
Simulation time 10336655434 ps
CPU time 5.49 seconds
Started May 21 02:49:16 PM PDT 24
Finished May 21 02:49:23 PM PDT 24
Peak memory 220208 kb
Host smart-2dc81f5e-adb2-4711-9e63-a766b83564f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606925792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3606925792
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.4293006363
Short name T597
Test name
Test status
Simulation time 10242832393 ps
CPU time 14.24 seconds
Started May 21 02:49:14 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 260044 kb
Host smart-36160b9e-eaa6-47c1-9b55-6a2c43cc0f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293006363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.4293006363
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1562269833
Short name T1035
Test name
Test status
Simulation time 746267440 ps
CPU time 2.58 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:23 PM PDT 24
Peak memory 205024 kb
Host smart-6f1f55c3-41cc-40c3-8ac6-80b02c4c095b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562269833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1562269833
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2826772000
Short name T519
Test name
Test status
Simulation time 3845122089 ps
CPU time 5.32 seconds
Started May 21 02:49:16 PM PDT 24
Finished May 21 02:49:23 PM PDT 24
Peak memory 218752 kb
Host smart-2effe7cc-3a22-4b67-866c-f6a39294254a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826772000 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2826772000
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1990019665
Short name T1187
Test name
Test status
Simulation time 7580352197 ps
CPU time 95.79 seconds
Started May 21 02:49:14 PM PDT 24
Finished May 21 02:50:51 PM PDT 24
Peak memory 1967572 kb
Host smart-096b5a08-3ebd-491a-af88-9380355e8d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990019665 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1990019665
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3878136741
Short name T769
Test name
Test status
Simulation time 5766430645 ps
CPU time 25.5 seconds
Started May 21 02:49:12 PM PDT 24
Finished May 21 02:49:39 PM PDT 24
Peak memory 205144 kb
Host smart-e23c0a98-cf91-419e-84c7-1c2421e303a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878136741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3878136741
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.732710313
Short name T656
Test name
Test status
Simulation time 6352239526 ps
CPU time 30.57 seconds
Started May 21 02:49:11 PM PDT 24
Finished May 21 02:49:43 PM PDT 24
Peak memory 223864 kb
Host smart-361be168-adf7-40f2-8c1c-befad37b47b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732710313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.732710313
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3546741890
Short name T938
Test name
Test status
Simulation time 75803666795 ps
CPU time 321 seconds
Started May 21 02:49:13 PM PDT 24
Finished May 21 02:54:35 PM PDT 24
Peak memory 2850700 kb
Host smart-047c828a-a627-491a-94ba-da668861c42a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546741890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3546741890
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3888910345
Short name T983
Test name
Test status
Simulation time 25086681580 ps
CPU time 666.82 seconds
Started May 21 02:49:12 PM PDT 24
Finished May 21 03:00:20 PM PDT 24
Peak memory 3072884 kb
Host smart-c2152ce2-dc7b-4184-b1aa-ec38e39aa097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888910345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3888910345
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4114517013
Short name T71
Test name
Test status
Simulation time 3850807169 ps
CPU time 6.89 seconds
Started May 21 02:49:10 PM PDT 24
Finished May 21 02:49:19 PM PDT 24
Peak memory 213448 kb
Host smart-d4c4ec48-e468-433b-8580-e54fe27add0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114517013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4114517013
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2843031865
Short name T522
Test name
Test status
Simulation time 18644029 ps
CPU time 0.62 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:27 PM PDT 24
Peak memory 204652 kb
Host smart-ce685be4-cbce-412d-a3a3-7ad505d5a179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843031865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2843031865
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1842299448
Short name T705
Test name
Test status
Simulation time 419547004 ps
CPU time 3.38 seconds
Started May 21 02:49:21 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 216320 kb
Host smart-004d3eb4-6d11-4062-bff2-8e269289bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842299448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1842299448
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1279919376
Short name T1265
Test name
Test status
Simulation time 1643952412 ps
CPU time 21.26 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 280740 kb
Host smart-e5b5ecfc-8322-41d0-bf38-b930772f0778
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279919376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1279919376
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1574822231
Short name T569
Test name
Test status
Simulation time 4526013622 ps
CPU time 68.23 seconds
Started May 21 02:49:17 PM PDT 24
Finished May 21 02:50:27 PM PDT 24
Peak memory 677640 kb
Host smart-4c6440fd-9f2a-49dc-95d5-6b525de7408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574822231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1574822231
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.569363136
Short name T1271
Test name
Test status
Simulation time 19239177888 ps
CPU time 37.44 seconds
Started May 21 02:49:19 PM PDT 24
Finished May 21 02:49:59 PM PDT 24
Peak memory 493812 kb
Host smart-5e3048fd-641b-4035-9363-1808d9e541c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569363136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.569363136
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3565698726
Short name T206
Test name
Test status
Simulation time 569808382 ps
CPU time 1.08 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:22 PM PDT 24
Peak memory 205032 kb
Host smart-b2a66888-1315-4cf9-9162-69df4261f68c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565698726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3565698726
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.4209513972
Short name T859
Test name
Test status
Simulation time 501721914 ps
CPU time 6.32 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 204984 kb
Host smart-ce121329-7719-411c-abdf-c758fc91531a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209513972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.4209513972
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1280809480
Short name T1177
Test name
Test status
Simulation time 5895512301 ps
CPU time 196.63 seconds
Started May 21 02:49:17 PM PDT 24
Finished May 21 02:52:35 PM PDT 24
Peak memory 897064 kb
Host smart-62516f8c-0bd4-447c-be04-d5def29d2211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280809480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1280809480
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.912059245
Short name T320
Test name
Test status
Simulation time 473948586 ps
CPU time 7.94 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:36 PM PDT 24
Peak memory 204900 kb
Host smart-69167fb3-b118-4599-b545-6d687ab68c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912059245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.912059245
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.2496883200
Short name T584
Test name
Test status
Simulation time 48092506 ps
CPU time 0.68 seconds
Started May 21 02:49:20 PM PDT 24
Finished May 21 02:49:23 PM PDT 24
Peak memory 204752 kb
Host smart-dbb20f5e-2b42-477f-854e-ecba9105dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496883200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2496883200
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1731231159
Short name T1115
Test name
Test status
Simulation time 7623068078 ps
CPU time 53.11 seconds
Started May 21 02:49:19 PM PDT 24
Finished May 21 02:50:14 PM PDT 24
Peak memory 213300 kb
Host smart-c481b092-0487-4faa-bdae-f737bda9fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731231159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1731231159
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3691476010
Short name T688
Test name
Test status
Simulation time 4841345266 ps
CPU time 20.71 seconds
Started May 21 02:49:19 PM PDT 24
Finished May 21 02:49:42 PM PDT 24
Peak memory 347280 kb
Host smart-3aadf6da-5d8e-4e7b-b5bf-1bb74b85ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691476010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3691476010
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.867740767
Short name T1067
Test name
Test status
Simulation time 23566045965 ps
CPU time 412.3 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:56:12 PM PDT 24
Peak memory 970404 kb
Host smart-affd591b-b4e1-4d16-ae27-daaac78fffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867740767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.867740767
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2535720431
Short name T802
Test name
Test status
Simulation time 1098849879 ps
CPU time 8.81 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 213192 kb
Host smart-c047f99a-3aff-46b7-aebe-9dfe5e6d4c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535720431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2535720431
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.504670372
Short name T682
Test name
Test status
Simulation time 1218686032 ps
CPU time 5.74 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:33 PM PDT 24
Peak memory 216736 kb
Host smart-330041e6-b7d6-4733-ab60-25641d7fbf4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504670372 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.504670372
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.21463900
Short name T975
Test name
Test status
Simulation time 10100648920 ps
CPU time 70.43 seconds
Started May 21 02:49:25 PM PDT 24
Finished May 21 02:50:38 PM PDT 24
Peak memory 460296 kb
Host smart-3e874a2d-2f66-4b1f-9df9-0f09ad0448e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21463900 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_acq.21463900
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.389372100
Short name T662
Test name
Test status
Simulation time 11310627945 ps
CPU time 5.48 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:33 PM PDT 24
Peak memory 238216 kb
Host smart-8273a8cb-2d3e-4044-ad7e-84a4469bf5d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389372100 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.389372100
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1746387384
Short name T806
Test name
Test status
Simulation time 740131798 ps
CPU time 2.36 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:30 PM PDT 24
Peak memory 205116 kb
Host smart-9f8207f2-2e46-4741-8df6-0857f275679c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746387384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1746387384
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2970172120
Short name T111
Test name
Test status
Simulation time 10779523787 ps
CPU time 5.75 seconds
Started May 21 02:49:23 PM PDT 24
Finished May 21 02:49:32 PM PDT 24
Peak memory 205040 kb
Host smart-b1f3785b-1bfb-4ebf-bec2-b9f5d648a903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970172120 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2970172120
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2261467303
Short name T1213
Test name
Test status
Simulation time 16680616462 ps
CPU time 90.04 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:50:57 PM PDT 24
Peak memory 1860452 kb
Host smart-3a10b4e0-cbc6-410e-916f-ad98f2127f61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261467303 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2261467303
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2058088441
Short name T713
Test name
Test status
Simulation time 2785311554 ps
CPU time 27.77 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 02:49:48 PM PDT 24
Peak memory 205080 kb
Host smart-b83b390d-753b-4b93-b123-8bb1c8cbdfee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058088441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2058088441
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3821418835
Short name T1275
Test name
Test status
Simulation time 3533553191 ps
CPU time 15 seconds
Started May 21 02:49:20 PM PDT 24
Finished May 21 02:49:37 PM PDT 24
Peak memory 211156 kb
Host smart-1fea27d8-867b-4806-a17c-02d48e4e8332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821418835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3821418835
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1639554938
Short name T299
Test name
Test status
Simulation time 49852164076 ps
CPU time 1401.64 seconds
Started May 21 02:49:18 PM PDT 24
Finished May 21 03:12:42 PM PDT 24
Peak memory 7380776 kb
Host smart-44a6b5ba-12a6-4444-a5c8-e2960c8d153a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639554938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1639554938
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.826010906
Short name T771
Test name
Test status
Simulation time 19642580103 ps
CPU time 74.94 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:50:42 PM PDT 24
Peak memory 745776 kb
Host smart-e33d371d-3cfc-4afc-819e-3bc3fd588cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826010906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.826010906
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2540498186
Short name T325
Test name
Test status
Simulation time 3358038600 ps
CPU time 7.83 seconds
Started May 21 02:49:24 PM PDT 24
Finished May 21 02:49:35 PM PDT 24
Peak memory 221388 kb
Host smart-84950242-bb50-4848-9f48-75afb8b5b08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540498186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2540498186
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1593149671
Short name T980
Test name
Test status
Simulation time 76484958 ps
CPU time 0.64 seconds
Started May 21 02:49:36 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 204684 kb
Host smart-aa8f3972-d284-4a75-a0db-bfa1730a9786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593149671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1593149671
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3212289522
Short name T10
Test name
Test status
Simulation time 195899195 ps
CPU time 2.89 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:49:37 PM PDT 24
Peak memory 232664 kb
Host smart-75a1ee12-3872-4491-ab2f-0ff5e859de88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212289522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3212289522
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.842370420
Short name T793
Test name
Test status
Simulation time 1255179721 ps
CPU time 18.44 seconds
Started May 21 02:49:34 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 281704 kb
Host smart-8d21a183-686c-497b-9031-874181e5eb04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842370420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.842370420
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.164433588
Short name T1126
Test name
Test status
Simulation time 2053590825 ps
CPU time 71.66 seconds
Started May 21 02:49:31 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 695296 kb
Host smart-b1bd5861-6d82-4e23-a88b-840187c34844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164433588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.164433588
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1472671839
Short name T805
Test name
Test status
Simulation time 1691493590 ps
CPU time 47.96 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:50:27 PM PDT 24
Peak memory 608912 kb
Host smart-30fff152-e50d-4f7d-8563-4a88389f225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472671839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1472671839
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.412898374
Short name T1269
Test name
Test status
Simulation time 314938628 ps
CPU time 3.6 seconds
Started May 21 02:49:31 PM PDT 24
Finished May 21 02:49:38 PM PDT 24
Peak memory 204968 kb
Host smart-9ee2f39b-5111-47b1-9fa3-ac11171cf369
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412898374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
412898374
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.776270973
Short name T483
Test name
Test status
Simulation time 25426554406 ps
CPU time 113 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:51:26 PM PDT 24
Peak memory 1257252 kb
Host smart-bd8b9988-256b-4009-974b-facd768da78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776270973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.776270973
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1629563818
Short name T1133
Test name
Test status
Simulation time 2474517686 ps
CPU time 7.78 seconds
Started May 21 02:49:39 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 205248 kb
Host smart-01691b97-23ce-4a01-bfbe-c97adafd191e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629563818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1629563818
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3850712809
Short name T69
Test name
Test status
Simulation time 1461246110 ps
CPU time 74.12 seconds
Started May 21 02:49:38 PM PDT 24
Finished May 21 02:50:56 PM PDT 24
Peak memory 364796 kb
Host smart-e5d6f928-96e7-4b9b-bce4-24a24cb4be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850712809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3850712809
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1307816391
Short name T269
Test name
Test status
Simulation time 48557652 ps
CPU time 0.64 seconds
Started May 21 02:49:26 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 204720 kb
Host smart-11f633dc-8153-44e3-bded-4444363f8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307816391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1307816391
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.4247811701
Short name T1221
Test name
Test status
Simulation time 7548612164 ps
CPU time 53.6 seconds
Started May 21 02:49:34 PM PDT 24
Finished May 21 02:50:32 PM PDT 24
Peak memory 229756 kb
Host smart-71bd24b7-2c1a-4646-973e-56f0385a8bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247811701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.4247811701
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2554903337
Short name T1330
Test name
Test status
Simulation time 4106341452 ps
CPU time 115.24 seconds
Started May 21 02:49:29 PM PDT 24
Finished May 21 02:51:27 PM PDT 24
Peak memory 461312 kb
Host smart-ac4722ea-085d-4f5d-9c7c-2a4806cba2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554903337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2554903337
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.553197673
Short name T305
Test name
Test status
Simulation time 377869434 ps
CPU time 17.83 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:49:51 PM PDT 24
Peak memory 213188 kb
Host smart-5f12fcdf-c7ae-44d8-ad37-f5eacc95ed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553197673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.553197673
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.4050358826
Short name T1050
Test name
Test status
Simulation time 1800719088 ps
CPU time 4.33 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:49:43 PM PDT 24
Peak memory 213240 kb
Host smart-f5c2f552-c7a0-4113-aece-6f19ba9dcf18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050358826 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.4050358826
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1254659653
Short name T1026
Test name
Test status
Simulation time 10122006103 ps
CPU time 82.37 seconds
Started May 21 02:49:34 PM PDT 24
Finished May 21 02:51:00 PM PDT 24
Peak memory 478356 kb
Host smart-07d68d44-1aa5-43f7-b3f0-f0daba54fd01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254659653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1254659653
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2893157699
Short name T696
Test name
Test status
Simulation time 10145814477 ps
CPU time 34.24 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 397800 kb
Host smart-5b64db84-e5ef-4ed5-8afc-e6b2525744c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893157699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2893157699
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3783910592
Short name T523
Test name
Test status
Simulation time 378758697 ps
CPU time 2.44 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:49:42 PM PDT 24
Peak memory 205100 kb
Host smart-1e71d505-8afa-40d0-a7cf-a2826365cabb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783910592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3783910592
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3852999156
Short name T868
Test name
Test status
Simulation time 1237044833 ps
CPU time 4.37 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:49:38 PM PDT 24
Peak memory 207960 kb
Host smart-2e4ff257-dec5-48b0-830a-a6e971f7977e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852999156 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3852999156
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1282481697
Short name T223
Test name
Test status
Simulation time 21704517682 ps
CPU time 168.48 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:52:21 PM PDT 24
Peak memory 1848432 kb
Host smart-dbb960e5-c246-4309-9bff-e773d554873b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282481697 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1282481697
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2258415345
Short name T1074
Test name
Test status
Simulation time 4546509049 ps
CPU time 46.19 seconds
Started May 21 02:49:29 PM PDT 24
Finished May 21 02:50:18 PM PDT 24
Peak memory 205060 kb
Host smart-e1f59b6a-c7b4-4e17-b361-5223e8fdc1ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258415345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2258415345
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.4100963878
Short name T610
Test name
Test status
Simulation time 1897785383 ps
CPU time 77.12 seconds
Started May 21 02:49:29 PM PDT 24
Finished May 21 02:50:49 PM PDT 24
Peak memory 207656 kb
Host smart-39f59c52-a009-437e-8295-9cdb5838cef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100963878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.4100963878
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2345376678
Short name T411
Test name
Test status
Simulation time 49632965517 ps
CPU time 1165.83 seconds
Started May 21 02:49:33 PM PDT 24
Finished May 21 03:09:03 PM PDT 24
Peak memory 7467208 kb
Host smart-e93ba6d6-44d7-45d0-bf2e-1f39a6c772c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345376678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2345376678
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1555282134
Short name T748
Test name
Test status
Simulation time 12946248313 ps
CPU time 1401.06 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 03:13:00 PM PDT 24
Peak memory 2821948 kb
Host smart-1b5f7770-4d71-486d-afca-85325af914d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555282134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1555282134
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.839747378
Short name T495
Test name
Test status
Simulation time 6279833308 ps
CPU time 8.44 seconds
Started May 21 02:49:30 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 221392 kb
Host smart-c5fdedc8-9286-4a2d-97c5-79d1d84df24f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839747378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.839747378
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1435806114
Short name T153
Test name
Test status
Simulation time 55626591 ps
CPU time 0.62 seconds
Started May 21 02:49:46 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 204656 kb
Host smart-8af89933-d17e-4087-a20e-73c1ba1255cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435806114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1435806114
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2067495354
Short name T1083
Test name
Test status
Simulation time 3853666071 ps
CPU time 7.92 seconds
Started May 21 02:49:42 PM PDT 24
Finished May 21 02:49:53 PM PDT 24
Peak memory 213368 kb
Host smart-ca30627b-5ee7-4d53-81f0-855e84908260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067495354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2067495354
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1453196714
Short name T1000
Test name
Test status
Simulation time 7265716768 ps
CPU time 8.65 seconds
Started May 21 02:49:33 PM PDT 24
Finished May 21 02:49:46 PM PDT 24
Peak memory 300872 kb
Host smart-7ac0fc58-cd38-408f-9f4a-fd763e1d7124
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453196714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1453196714
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1582417396
Short name T899
Test name
Test status
Simulation time 2349769364 ps
CPU time 78.36 seconds
Started May 21 02:49:36 PM PDT 24
Finished May 21 02:50:59 PM PDT 24
Peak memory 730028 kb
Host smart-353d99e2-d33a-46ac-9ebf-49fa16e9ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582417396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1582417396
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.396120033
Short name T392
Test name
Test status
Simulation time 27127909997 ps
CPU time 88.74 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:51:08 PM PDT 24
Peak memory 883796 kb
Host smart-a6bada9c-c703-4979-aa28-3de62c92baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396120033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.396120033
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.346172145
Short name T727
Test name
Test status
Simulation time 137336880 ps
CPU time 0.87 seconds
Started May 21 02:49:35 PM PDT 24
Finished May 21 02:49:40 PM PDT 24
Peak memory 204796 kb
Host smart-f5b89030-393a-4a96-9832-5e4d90bd1199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346172145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.346172145
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2433968223
Short name T165
Test name
Test status
Simulation time 167654008 ps
CPU time 3.94 seconds
Started May 21 02:49:36 PM PDT 24
Finished May 21 02:49:44 PM PDT 24
Peak memory 204976 kb
Host smart-38f5b859-aacd-483c-a0ec-0fea2cb01632
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433968223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2433968223
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3678921009
Short name T39
Test name
Test status
Simulation time 1190371433 ps
CPU time 12.24 seconds
Started May 21 02:49:49 PM PDT 24
Finished May 21 02:50:03 PM PDT 24
Peak memory 205052 kb
Host smart-6e4aa1d7-abc4-43dc-a8c3-bea6118655c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678921009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3678921009
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3168919836
Short name T1064
Test name
Test status
Simulation time 2297550237 ps
CPU time 105.12 seconds
Started May 21 02:49:45 PM PDT 24
Finished May 21 02:51:32 PM PDT 24
Peak memory 380392 kb
Host smart-d55deda6-c203-4573-8c26-6ffcb84e86ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168919836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3168919836
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.169423715
Short name T1106
Test name
Test status
Simulation time 22586268 ps
CPU time 0.67 seconds
Started May 21 02:49:36 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 204700 kb
Host smart-c57b37cb-77c8-469c-ab9f-dff07ea870f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169423715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.169423715
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1645507235
Short name T862
Test name
Test status
Simulation time 4168833762 ps
CPU time 12.41 seconds
Started May 21 02:49:37 PM PDT 24
Finished May 21 02:49:54 PM PDT 24
Peak memory 205064 kb
Host smart-674ac9d4-c3be-40ce-99ba-ee38b9f3c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645507235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1645507235
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2022409210
Short name T1107
Test name
Test status
Simulation time 5869986802 ps
CPU time 16.64 seconds
Started May 21 02:49:34 PM PDT 24
Finished May 21 02:49:55 PM PDT 24
Peak memory 261920 kb
Host smart-6583b6f8-242b-4f00-a3bc-de23cb1f6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022409210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2022409210
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2979819824
Short name T107
Test name
Test status
Simulation time 70243428867 ps
CPU time 830.55 seconds
Started May 21 02:49:40 PM PDT 24
Finished May 21 03:03:35 PM PDT 24
Peak memory 2975632 kb
Host smart-ed7a166d-2400-45f0-8b2a-02612f747aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979819824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2979819824
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2835830233
Short name T1065
Test name
Test status
Simulation time 1287627489 ps
CPU time 29.99 seconds
Started May 21 02:49:37 PM PDT 24
Finished May 21 02:50:12 PM PDT 24
Peak memory 213228 kb
Host smart-842038e5-4204-4b78-86d9-648748e56041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835830233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2835830233
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3677831614
Short name T281
Test name
Test status
Simulation time 1365717744 ps
CPU time 4.64 seconds
Started May 21 02:49:41 PM PDT 24
Finished May 21 02:49:49 PM PDT 24
Peak memory 213236 kb
Host smart-98b3bf0b-219f-4f74-8cc6-fdb724caf7b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677831614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3677831614
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2466181959
Short name T292
Test name
Test status
Simulation time 11767827244 ps
CPU time 5.86 seconds
Started May 21 02:49:41 PM PDT 24
Finished May 21 02:49:51 PM PDT 24
Peak memory 229416 kb
Host smart-dd749dbb-a31d-47e1-8bf6-e71b2a998859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466181959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2466181959
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2331158123
Short name T1144
Test name
Test status
Simulation time 10092235817 ps
CPU time 69.02 seconds
Started May 21 02:49:43 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 544836 kb
Host smart-6b63785f-1e11-404a-8f9e-f213a0cf1509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331158123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2331158123
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2595671338
Short name T981
Test name
Test status
Simulation time 376266502 ps
CPU time 2.3 seconds
Started May 21 02:49:42 PM PDT 24
Finished May 21 02:49:48 PM PDT 24
Peak memory 205076 kb
Host smart-cb5749a2-7cc7-444a-88e4-699c4ba25b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595671338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2595671338
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1695261935
Short name T634
Test name
Test status
Simulation time 4248671867 ps
CPU time 4.94 seconds
Started May 21 02:49:40 PM PDT 24
Finished May 21 02:49:49 PM PDT 24
Peak memory 205060 kb
Host smart-ad12a72a-99d7-4a67-a79f-52d64124fe74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695261935 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1695261935
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2726835651
Short name T515
Test name
Test status
Simulation time 9578582694 ps
CPU time 17.57 seconds
Started May 21 02:49:42 PM PDT 24
Finished May 21 02:50:03 PM PDT 24
Peak memory 662820 kb
Host smart-8f65c5e6-bb51-4bf9-b528-75ba2a2520df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726835651 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2726835651
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.656389019
Short name T147
Test name
Test status
Simulation time 871320451 ps
CPU time 15.25 seconds
Started May 21 02:49:44 PM PDT 24
Finished May 21 02:50:01 PM PDT 24
Peak memory 204896 kb
Host smart-c97c35fb-d9f2-4e7d-93a4-faf3e15cd6ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656389019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_tar
get_smoke.656389019
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.385498441
Short name T667
Test name
Test status
Simulation time 5264274119 ps
CPU time 23.9 seconds
Started May 21 02:49:40 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 218764 kb
Host smart-71520eb0-1350-4778-8aca-e57916ad066b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385498441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.385498441
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.785116618
Short name T1101
Test name
Test status
Simulation time 24737208333 ps
CPU time 17.43 seconds
Started May 21 02:49:42 PM PDT 24
Finished May 21 02:50:03 PM PDT 24
Peak memory 368380 kb
Host smart-269e6c2c-f7fa-4d93-8407-a20f3a5079af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785116618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.785116618
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2083573056
Short name T365
Test name
Test status
Simulation time 7734513811 ps
CPU time 688.62 seconds
Started May 21 02:49:42 PM PDT 24
Finished May 21 03:01:14 PM PDT 24
Peak memory 1985404 kb
Host smart-be7d9742-c41e-44a3-b903-44499cac50d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083573056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2083573056
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.4096176627
Short name T880
Test name
Test status
Simulation time 2910515463 ps
CPU time 7.4 seconds
Started May 21 02:49:40 PM PDT 24
Finished May 21 02:49:51 PM PDT 24
Peak memory 213296 kb
Host smart-de3ef744-ddf6-4278-9d27-f0407da38894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096176627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.4096176627
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.290287467
Short name T419
Test name
Test status
Simulation time 22792298 ps
CPU time 0.62 seconds
Started May 21 02:49:52 PM PDT 24
Finished May 21 02:49:55 PM PDT 24
Peak memory 204680 kb
Host smart-f02f5a45-26e6-444f-878a-63bbd0753db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290287467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.290287467
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3744927129
Short name T858
Test name
Test status
Simulation time 331087863 ps
CPU time 3.71 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 02:49:54 PM PDT 24
Peak memory 218164 kb
Host smart-2908d179-7861-481f-8343-505faf7afdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744927129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3744927129
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1612645370
Short name T1134
Test name
Test status
Simulation time 2224983700 ps
CPU time 8.81 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 02:49:58 PM PDT 24
Peak memory 301296 kb
Host smart-a0e40eaf-27b3-4b12-96d6-f392a9e1ab39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612645370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1612645370
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.900209668
Short name T435
Test name
Test status
Simulation time 3034941825 ps
CPU time 57.84 seconds
Started May 21 02:49:46 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 562748 kb
Host smart-4e573b16-d969-480e-99ee-4d0de619137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900209668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.900209668
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3248392153
Short name T1308
Test name
Test status
Simulation time 4744797138 ps
CPU time 72.36 seconds
Started May 21 02:49:50 PM PDT 24
Finished May 21 02:51:04 PM PDT 24
Peak memory 770880 kb
Host smart-f751e8ab-1ba5-428e-8562-a0ea7c3016b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248392153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3248392153
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.277929789
Short name T332
Test name
Test status
Simulation time 123935130 ps
CPU time 0.79 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 204792 kb
Host smart-7f1ecbe9-f9fa-4bc1-b719-f6d527c8b218
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277929789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.277929789
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.4134157351
Short name T514
Test name
Test status
Simulation time 3954503254 ps
CPU time 5.21 seconds
Started May 21 02:49:46 PM PDT 24
Finished May 21 02:49:53 PM PDT 24
Peak memory 205092 kb
Host smart-d3914c7b-7872-46e7-a13b-a6a65b27a6cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134157351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.4134157351
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2091199221
Short name T753
Test name
Test status
Simulation time 38004688147 ps
CPU time 179.7 seconds
Started May 21 02:49:50 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 1518128 kb
Host smart-caa4116f-59e5-42ad-8518-234d63698922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091199221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2091199221
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.42760721
Short name T444
Test name
Test status
Simulation time 810979085 ps
CPU time 6.16 seconds
Started May 21 02:49:54 PM PDT 24
Finished May 21 02:50:03 PM PDT 24
Peak memory 205036 kb
Host smart-4fd1c094-6940-44bb-9e41-e4b98b66fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42760721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.42760721
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.378826822
Short name T33
Test name
Test status
Simulation time 5955925732 ps
CPU time 26.46 seconds
Started May 21 02:49:54 PM PDT 24
Finished May 21 02:50:22 PM PDT 24
Peak memory 351308 kb
Host smart-ec722956-3a03-49dd-a54e-4ad6abdea0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378826822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.378826822
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.75004613
Short name T123
Test name
Test status
Simulation time 21157383 ps
CPU time 0.67 seconds
Started May 21 02:49:45 PM PDT 24
Finished May 21 02:49:48 PM PDT 24
Peak memory 204696 kb
Host smart-480dc48d-1e51-41c4-8b8e-570f6d632b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75004613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.75004613
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3662244860
Short name T814
Test name
Test status
Simulation time 72275020747 ps
CPU time 739.11 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 03:02:08 PM PDT 24
Peak memory 213336 kb
Host smart-b62f5793-0324-47c1-b4ab-6c9c1f0873e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662244860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3662244860
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2513067083
Short name T52
Test name
Test status
Simulation time 14506440939 ps
CPU time 26.38 seconds
Started May 21 02:49:48 PM PDT 24
Finished May 21 02:50:17 PM PDT 24
Peak memory 334320 kb
Host smart-989f5fc7-9777-4875-bede-cd9d12c43b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513067083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2513067083
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.4210794621
Short name T247
Test name
Test status
Simulation time 51245127117 ps
CPU time 874.48 seconds
Started May 21 02:49:49 PM PDT 24
Finished May 21 03:04:26 PM PDT 24
Peak memory 1040824 kb
Host smart-eb78c8c5-a40e-4c27-a6e7-47dd90c6b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210794621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.4210794621
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.2888428827
Short name T238
Test name
Test status
Simulation time 3528645770 ps
CPU time 26.09 seconds
Started May 21 02:49:46 PM PDT 24
Finished May 21 02:50:15 PM PDT 24
Peak memory 213276 kb
Host smart-e8d73ac6-93cc-4857-be1f-2a8c49bf33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888428827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.2888428827
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3933612444
Short name T464
Test name
Test status
Simulation time 528923355 ps
CPU time 2.93 seconds
Started May 21 02:49:53 PM PDT 24
Finished May 21 02:49:58 PM PDT 24
Peak memory 205028 kb
Host smart-577e641d-811c-4695-b9a9-c03699172753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933612444 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3933612444
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1862438374
Short name T1033
Test name
Test status
Simulation time 10556179844 ps
CPU time 4.02 seconds
Started May 21 02:49:51 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 213700 kb
Host smart-d5ac7f06-f876-4048-8085-d7bdf8fdf252
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862438374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1862438374
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3833313677
Short name T592
Test name
Test status
Simulation time 10117739010 ps
CPU time 19.33 seconds
Started May 21 02:49:52 PM PDT 24
Finished May 21 02:50:13 PM PDT 24
Peak memory 314344 kb
Host smart-b9e1442b-1513-44b7-b9d7-2cccb68f0332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833313677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3833313677
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2103560052
Short name T877
Test name
Test status
Simulation time 794183273 ps
CPU time 1.78 seconds
Started May 21 02:49:53 PM PDT 24
Finished May 21 02:49:57 PM PDT 24
Peak memory 205060 kb
Host smart-c0207465-4cc2-4daa-b870-5b547de8ec14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103560052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2103560052
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2707772361
Short name T742
Test name
Test status
Simulation time 2940011828 ps
CPU time 6.5 seconds
Started May 21 02:49:45 PM PDT 24
Finished May 21 02:49:53 PM PDT 24
Peak memory 205116 kb
Host smart-d70d61f8-e551-4c7e-9617-9375e4d8509b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707772361 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2707772361
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1852588024
Short name T956
Test name
Test status
Simulation time 21906116740 ps
CPU time 525.13 seconds
Started May 21 02:49:45 PM PDT 24
Finished May 21 02:58:33 PM PDT 24
Peak memory 5364896 kb
Host smart-83a1846e-0b87-4ccf-b5fb-25ea951146be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852588024 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1852588024
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1942962861
Short name T811
Test name
Test status
Simulation time 5213105705 ps
CPU time 13.16 seconds
Started May 21 02:49:46 PM PDT 24
Finished May 21 02:50:01 PM PDT 24
Peak memory 205092 kb
Host smart-17a9d724-852b-4e57-86b6-0b8dd86c0733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942962861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1942962861
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.1420686982
Short name T750
Test name
Test status
Simulation time 1033689276 ps
CPU time 6.74 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 02:49:56 PM PDT 24
Peak memory 206604 kb
Host smart-ff547bf8-4eb8-4c61-b2af-239207e50f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420686982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.1420686982
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.35474049
Short name T138
Test name
Test status
Simulation time 26522038082 ps
CPU time 49 seconds
Started May 21 02:49:48 PM PDT 24
Finished May 21 02:50:39 PM PDT 24
Peak memory 905628 kb
Host smart-3f3a5a5f-1848-4f65-81c4-8e3fc995c890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35474049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_wr.35474049
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1300345686
Short name T1102
Test name
Test status
Simulation time 36968111853 ps
CPU time 178.82 seconds
Started May 21 02:49:48 PM PDT 24
Finished May 21 02:52:49 PM PDT 24
Peak memory 1523860 kb
Host smart-308f739e-8364-47a7-88f8-ae84f019eb57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300345686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1300345686
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2054473372
Short name T1200
Test name
Test status
Simulation time 1295666508 ps
CPU time 7.2 seconds
Started May 21 02:49:47 PM PDT 24
Finished May 21 02:49:56 PM PDT 24
Peak memory 221240 kb
Host smart-60e4b22d-a0c1-4257-956d-544ddf1cd51a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054473372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2054473372
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1673167235
Short name T529
Test name
Test status
Simulation time 43260722 ps
CPU time 0.58 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:09 PM PDT 24
Peak memory 204656 kb
Host smart-85963b7a-e6ba-4c95-8088-c851ba24648f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673167235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1673167235
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1740737481
Short name T1300
Test name
Test status
Simulation time 395289035 ps
CPU time 6.28 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 234512 kb
Host smart-ecc54614-478b-487f-b1d0-7ffa4e622c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740737481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1740737481
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3438307453
Short name T815
Test name
Test status
Simulation time 1239730422 ps
CPU time 7.78 seconds
Started May 21 02:49:54 PM PDT 24
Finished May 21 02:50:04 PM PDT 24
Peak memory 266008 kb
Host smart-e033b01d-ace8-4dbc-92c4-f4ead2f977ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438307453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3438307453
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1596573471
Short name T1029
Test name
Test status
Simulation time 15543352008 ps
CPU time 81.94 seconds
Started May 21 02:49:52 PM PDT 24
Finished May 21 02:51:16 PM PDT 24
Peak memory 749420 kb
Host smart-14338e97-718b-476c-8be3-ae98f6d97bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596573471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1596573471
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2254838731
Short name T1249
Test name
Test status
Simulation time 10124465789 ps
CPU time 82.43 seconds
Started May 21 02:49:54 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 806016 kb
Host smart-c09df6ce-496d-4877-a0fe-a04dd70974c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254838731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2254838731
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4181668227
Short name T428
Test name
Test status
Simulation time 331139607 ps
CPU time 0.97 seconds
Started May 21 02:49:52 PM PDT 24
Finished May 21 02:49:56 PM PDT 24
Peak memory 204716 kb
Host smart-0116076b-7f0b-4090-9f5b-c3275909d71e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181668227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4181668227
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.190468089
Short name T861
Test name
Test status
Simulation time 480912830 ps
CPU time 6.9 seconds
Started May 21 02:49:51 PM PDT 24
Finished May 21 02:50:00 PM PDT 24
Peak memory 223012 kb
Host smart-fdcd7a81-f0dd-4e14-b07b-b4f9d6e2c2dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190468089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
190468089
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3827623519
Short name T478
Test name
Test status
Simulation time 17435991554 ps
CPU time 143.52 seconds
Started May 21 02:49:54 PM PDT 24
Finished May 21 02:52:20 PM PDT 24
Peak memory 1289324 kb
Host smart-7f0644cd-0414-467c-b0f2-5a2a6c827229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827623519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3827623519
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1806012362
Short name T534
Test name
Test status
Simulation time 302931494 ps
CPU time 4.22 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:11 PM PDT 24
Peak memory 205032 kb
Host smart-ad1f47b8-557e-463f-ac7e-8372b746843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806012362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1806012362
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3807132072
Short name T400
Test name
Test status
Simulation time 24815427628 ps
CPU time 66.17 seconds
Started May 21 02:49:59 PM PDT 24
Finished May 21 02:51:08 PM PDT 24
Peak memory 314464 kb
Host smart-daf94c74-f5aa-40ad-a7ba-3e5afe82e7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807132072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3807132072
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_perf.891849955
Short name T542
Test name
Test status
Simulation time 28991845565 ps
CPU time 2463.68 seconds
Started May 21 02:49:52 PM PDT 24
Finished May 21 03:30:59 PM PDT 24
Peak memory 3137372 kb
Host smart-9816b5ea-7939-484d-9b5d-171ae7e2e8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891849955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.891849955
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.572554323
Short name T744
Test name
Test status
Simulation time 5250061478 ps
CPU time 46.91 seconds
Started May 21 02:49:53 PM PDT 24
Finished May 21 02:50:42 PM PDT 24
Peak memory 327296 kb
Host smart-c40012fb-8b66-41eb-98c4-7d463613b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572554323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.572554323
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1061379597
Short name T720
Test name
Test status
Simulation time 196810556037 ps
CPU time 2131.54 seconds
Started May 21 02:49:57 PM PDT 24
Finished May 21 03:25:32 PM PDT 24
Peak memory 2870360 kb
Host smart-e7fb6821-88ff-4f50-a2de-8a11568d4a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061379597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1061379597
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3055085042
Short name T164
Test name
Test status
Simulation time 598833776 ps
CPU time 11.01 seconds
Started May 21 02:50:01 PM PDT 24
Finished May 21 02:50:14 PM PDT 24
Peak memory 215212 kb
Host smart-1554e57a-d83c-4caf-ae41-a9df3b08a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055085042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3055085042
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2351270776
Short name T263
Test name
Test status
Simulation time 3515616657 ps
CPU time 3.8 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:50:05 PM PDT 24
Peak memory 205036 kb
Host smart-f83510c2-3ec1-4692-ad15-550ef30ffc7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351270776 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2351270776
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3130555130
Short name T79
Test name
Test status
Simulation time 10107789797 ps
CPU time 78.85 seconds
Started May 21 02:49:59 PM PDT 24
Finished May 21 02:51:21 PM PDT 24
Peak memory 515608 kb
Host smart-f0fb852f-77cd-4ffc-ae10-6b0df6f74bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130555130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3130555130
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1266281623
Short name T701
Test name
Test status
Simulation time 10100424959 ps
CPU time 80.96 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:51:22 PM PDT 24
Peak memory 493736 kb
Host smart-61239b0e-48c4-4d5d-b4a4-b72d4300f6c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266281623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1266281623
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1362456773
Short name T898
Test name
Test status
Simulation time 1778355124 ps
CPU time 3.31 seconds
Started May 21 02:50:00 PM PDT 24
Finished May 21 02:50:06 PM PDT 24
Peak memory 205080 kb
Host smart-f7fca581-665e-4792-b7eb-39dd9a39d06c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362456773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1362456773
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2383110735
Short name T828
Test name
Test status
Simulation time 10563291585 ps
CPU time 158.15 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 2609732 kb
Host smart-119f9695-70c2-42ff-b261-a4b7c9b57d75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383110735 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2383110735
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2791450122
Short name T885
Test name
Test status
Simulation time 986793990 ps
CPU time 13.47 seconds
Started May 21 02:50:01 PM PDT 24
Finished May 21 02:50:16 PM PDT 24
Peak memory 204992 kb
Host smart-60a485d6-2187-42bf-a2c3-29983c90c25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791450122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2791450122
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2830214935
Short name T544
Test name
Test status
Simulation time 2699434540 ps
CPU time 68.78 seconds
Started May 21 02:50:00 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 209244 kb
Host smart-ca831bc5-e09e-468c-9fc2-48505de50ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830214935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2830214935
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1206140810
Short name T253
Test name
Test status
Simulation time 10788989134 ps
CPU time 2.68 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:50:04 PM PDT 24
Peak memory 205116 kb
Host smart-e2ee5f5e-0764-4d27-a6f6-4d1942260b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206140810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1206140810
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2249486822
Short name T255
Test name
Test status
Simulation time 4464415190 ps
CPU time 120.01 seconds
Started May 21 02:50:11 PM PDT 24
Finished May 21 02:52:13 PM PDT 24
Peak memory 1203096 kb
Host smart-d00ef499-1241-4415-a165-865f2ac23aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249486822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2249486822
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.4253369185
Short name T1047
Test name
Test status
Simulation time 4862992807 ps
CPU time 7.53 seconds
Started May 21 02:49:58 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 213360 kb
Host smart-3ab9760d-5220-463b-ad70-cbc887ca041e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253369185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.4253369185
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.581091232
Short name T636
Test name
Test status
Simulation time 18882296 ps
CPU time 0.62 seconds
Started May 21 02:47:06 PM PDT 24
Finished May 21 02:47:08 PM PDT 24
Peak memory 204656 kb
Host smart-afcb49d3-9ee7-4133-ac19-1174c71c7631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581091232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.581091232
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2656346497
Short name T971
Test name
Test status
Simulation time 105849291 ps
CPU time 1.79 seconds
Started May 21 02:46:58 PM PDT 24
Finished May 21 02:47:01 PM PDT 24
Peak memory 213300 kb
Host smart-1cd99a9f-af9d-403b-82ee-15dfc36f7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656346497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2656346497
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.4242789409
Short name T1154
Test name
Test status
Simulation time 401191844 ps
CPU time 3.89 seconds
Started May 21 02:46:57 PM PDT 24
Finished May 21 02:47:02 PM PDT 24
Peak memory 240156 kb
Host smart-b67d9f2a-4e0d-4eb8-ac1f-d68c4ab5df98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242789409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.4242789409
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.843874537
Short name T1042
Test name
Test status
Simulation time 1699627155 ps
CPU time 50.75 seconds
Started May 21 02:47:03 PM PDT 24
Finished May 21 02:47:55 PM PDT 24
Peak memory 610800 kb
Host smart-d9689f71-adb3-415e-80b5-f96e855d1b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843874537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.843874537
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.4064266377
Short name T336
Test name
Test status
Simulation time 4103066887 ps
CPU time 164.97 seconds
Started May 21 02:46:56 PM PDT 24
Finished May 21 02:49:42 PM PDT 24
Peak memory 714040 kb
Host smart-7da19803-6ed9-4ff7-91f5-27e3af0f65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064266377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.4064266377
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2380053116
Short name T374
Test name
Test status
Simulation time 260801207 ps
CPU time 1.11 seconds
Started May 21 02:46:58 PM PDT 24
Finished May 21 02:47:00 PM PDT 24
Peak memory 204776 kb
Host smart-255a0f7c-7e90-4e14-8678-200c8034232b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380053116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2380053116
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.555334935
Short name T960
Test name
Test status
Simulation time 616111420 ps
CPU time 8.26 seconds
Started May 21 02:47:02 PM PDT 24
Finished May 21 02:47:12 PM PDT 24
Peak memory 205020 kb
Host smart-622a337c-d498-4030-a9b8-c9e44ac41137
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555334935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.555334935
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3413441557
Short name T1111
Test name
Test status
Simulation time 2993065337 ps
CPU time 70.77 seconds
Started May 21 02:46:52 PM PDT 24
Finished May 21 02:48:04 PM PDT 24
Peak memory 873148 kb
Host smart-bdb47ed6-b8be-4870-b7fd-a2b942c4cb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413441557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3413441557
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1797292723
Short name T1030
Test name
Test status
Simulation time 2232744764 ps
CPU time 8.44 seconds
Started May 21 02:47:02 PM PDT 24
Finished May 21 02:47:12 PM PDT 24
Peak memory 205124 kb
Host smart-540566fb-8d44-4c38-80dd-3c2305187d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797292723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1797292723
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3822681400
Short name T759
Test name
Test status
Simulation time 18269441779 ps
CPU time 29.5 seconds
Started May 21 02:47:01 PM PDT 24
Finished May 21 02:47:32 PM PDT 24
Peak memory 368484 kb
Host smart-fa84554a-a6c9-4a95-bbde-c7355f4a6459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822681400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3822681400
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1050113447
Short name T297
Test name
Test status
Simulation time 49672792 ps
CPU time 0.68 seconds
Started May 21 02:46:51 PM PDT 24
Finished May 21 02:46:54 PM PDT 24
Peak memory 204708 kb
Host smart-5c2945eb-d9af-4ac6-96d1-37f8d084b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050113447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1050113447
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.245149250
Short name T1124
Test name
Test status
Simulation time 6337835226 ps
CPU time 24.81 seconds
Started May 21 02:46:56 PM PDT 24
Finished May 21 02:47:22 PM PDT 24
Peak memory 219684 kb
Host smart-b8a6d153-f380-4048-88b5-f1d934dd015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245149250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.245149250
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1625071024
Short name T459
Test name
Test status
Simulation time 2223652651 ps
CPU time 50.02 seconds
Started May 21 02:46:52 PM PDT 24
Finished May 21 02:47:43 PM PDT 24
Peak memory 471484 kb
Host smart-5a218755-1136-45ba-b1cf-b4bdb0d09225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625071024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1625071024
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3257610234
Short name T288
Test name
Test status
Simulation time 494748779 ps
CPU time 9.1 seconds
Started May 21 02:46:57 PM PDT 24
Finished May 21 02:47:07 PM PDT 24
Peak memory 213236 kb
Host smart-c118e733-2b9b-4446-ae98-bbe8db731256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257610234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3257610234
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2650016400
Short name T155
Test name
Test status
Simulation time 1185648871 ps
CPU time 1.01 seconds
Started May 21 02:47:05 PM PDT 24
Finished May 21 02:47:07 PM PDT 24
Peak memory 223204 kb
Host smart-89e3d5d2-7469-45f0-b037-ce792d0de910
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650016400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2650016400
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.4127254794
Short name T421
Test name
Test status
Simulation time 597925000 ps
CPU time 2.96 seconds
Started May 21 02:47:02 PM PDT 24
Finished May 21 02:47:06 PM PDT 24
Peak memory 205000 kb
Host smart-35d6a666-279d-405e-b444-93b53d95f055
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127254794 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.4127254794
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3848231494
Short name T81
Test name
Test status
Simulation time 10047700990 ps
CPU time 76.37 seconds
Started May 21 02:47:01 PM PDT 24
Finished May 21 02:48:19 PM PDT 24
Peak memory 436064 kb
Host smart-56a4a189-fe95-46c5-b59f-afb963595469
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848231494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3848231494
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3641903400
Short name T596
Test name
Test status
Simulation time 10183654526 ps
CPU time 62.22 seconds
Started May 21 02:47:06 PM PDT 24
Finished May 21 02:48:10 PM PDT 24
Peak memory 451056 kb
Host smart-54cd1554-24e2-4e9f-b226-a05f2fa181f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641903400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3641903400
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3578395184
Short name T12
Test name
Test status
Simulation time 290935585 ps
CPU time 2.25 seconds
Started May 21 02:47:02 PM PDT 24
Finished May 21 02:47:06 PM PDT 24
Peak memory 205240 kb
Host smart-8ff31edc-3cc9-4e79-bbdb-3e930a18c0b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578395184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3578395184
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2083045746
Short name T1193
Test name
Test status
Simulation time 856976664 ps
CPU time 2.72 seconds
Started May 21 02:46:56 PM PDT 24
Finished May 21 02:46:59 PM PDT 24
Peak memory 204956 kb
Host smart-f0f61286-aa6c-4c3a-b1fb-cfb3ae0d9674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083045746 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2083045746
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.933297370
Short name T395
Test name
Test status
Simulation time 15954143995 ps
CPU time 30.35 seconds
Started May 21 02:47:06 PM PDT 24
Finished May 21 02:47:38 PM PDT 24
Peak memory 777308 kb
Host smart-56660a1c-34d1-4dc7-a258-76a2602589e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933297370 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.933297370
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1745747835
Short name T845
Test name
Test status
Simulation time 924469127 ps
CPU time 15.77 seconds
Started May 21 02:46:57 PM PDT 24
Finished May 21 02:47:14 PM PDT 24
Peak memory 204964 kb
Host smart-34917314-0c20-433d-b5eb-86869d887a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745747835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1745747835
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.54967364
Short name T492
Test name
Test status
Simulation time 2311991065 ps
CPU time 20.86 seconds
Started May 21 02:46:58 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 216420 kb
Host smart-cb810184-ea6a-4818-86c1-785b167a1563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54967364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stress_rd.54967364
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3515009916
Short name T735
Test name
Test status
Simulation time 50072972039 ps
CPU time 1148.45 seconds
Started May 21 02:46:58 PM PDT 24
Finished May 21 03:06:08 PM PDT 24
Peak memory 7714720 kb
Host smart-a1af6962-620e-4811-8a6c-02a33f35dda3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515009916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3515009916
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2580337257
Short name T221
Test name
Test status
Simulation time 34639195686 ps
CPU time 343.47 seconds
Started May 21 02:46:57 PM PDT 24
Finished May 21 02:52:42 PM PDT 24
Peak memory 1107380 kb
Host smart-d7773358-5ec5-48d9-94e3-94dcef53cfcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580337257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2580337257
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.44890895
Short name T1332
Test name
Test status
Simulation time 1592970303 ps
CPU time 8.11 seconds
Started May 21 02:47:03 PM PDT 24
Finished May 21 02:47:12 PM PDT 24
Peak memory 213188 kb
Host smart-8962434e-ff23-4969-a06b-b716ff51934c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44890895 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_timeout.44890895
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.931723308
Short name T558
Test name
Test status
Simulation time 40605192 ps
CPU time 0.59 seconds
Started May 21 02:50:12 PM PDT 24
Finished May 21 02:50:14 PM PDT 24
Peak memory 204644 kb
Host smart-ec591be8-1bec-44f3-aa62-ae33083d0854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931723308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.931723308
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.60933142
Short name T51
Test name
Test status
Simulation time 188596028 ps
CPU time 4.35 seconds
Started May 21 02:50:07 PM PDT 24
Finished May 21 02:50:14 PM PDT 24
Peak memory 252108 kb
Host smart-f848372a-d42a-4148-816b-8442fa4495c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60933142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.60933142
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3829641558
Short name T285
Test name
Test status
Simulation time 438432016 ps
CPU time 10.34 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:18 PM PDT 24
Peak memory 301472 kb
Host smart-b8722da9-47d8-4c35-bc65-3768f7c116b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829641558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3829641558
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4207659558
Short name T475
Test name
Test status
Simulation time 1397633678 ps
CPU time 28.39 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:35 PM PDT 24
Peak memory 221240 kb
Host smart-6bd83e5c-e452-4908-bf00-0fce626e3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207659558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4207659558
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3306475756
Short name T692
Test name
Test status
Simulation time 9066598097 ps
CPU time 179.44 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:53:06 PM PDT 24
Peak memory 770828 kb
Host smart-31246f2a-645e-4da7-b2e0-78070f7ae41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306475756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3306475756
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1920790234
Short name T431
Test name
Test status
Simulation time 105043582 ps
CPU time 1.09 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 204936 kb
Host smart-8d030df9-1566-4552-8903-713dd84b5c05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920790234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1920790234
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1806921716
Short name T1151
Test name
Test status
Simulation time 254953468 ps
CPU time 3.85 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:12 PM PDT 24
Peak memory 226592 kb
Host smart-cc484a6a-ddd0-4deb-8c0c-7a8d17375985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806921716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1806921716
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2728327841
Short name T242
Test name
Test status
Simulation time 22497481704 ps
CPU time 129.84 seconds
Started May 21 02:50:06 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 1401008 kb
Host smart-239248c2-4e68-41e4-9024-babbd3658c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728327841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2728327841
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3333305345
Short name T652
Test name
Test status
Simulation time 2782096703 ps
CPU time 28.94 seconds
Started May 21 02:50:10 PM PDT 24
Finished May 21 02:50:40 PM PDT 24
Peak memory 205160 kb
Host smart-5dc0213a-8ca4-4a8d-a6d9-14256c342140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333305345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3333305345
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2884258836
Short name T1119
Test name
Test status
Simulation time 4344714520 ps
CPU time 73.22 seconds
Started May 21 02:50:09 PM PDT 24
Finished May 21 02:51:24 PM PDT 24
Peak memory 308360 kb
Host smart-862a7f1a-5118-4ee7-8a65-b4d0b3cbc388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884258836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2884258836
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.4024659354
Short name T1015
Test name
Test status
Simulation time 45623337 ps
CPU time 0.65 seconds
Started May 21 02:50:06 PM PDT 24
Finished May 21 02:50:10 PM PDT 24
Peak memory 204728 kb
Host smart-4c50cf57-0e65-4c73-bc3b-11980e3d15e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024659354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.4024659354
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.4178663492
Short name T973
Test name
Test status
Simulation time 4908928134 ps
CPU time 6.43 seconds
Started May 21 02:50:06 PM PDT 24
Finished May 21 02:50:15 PM PDT 24
Peak memory 237552 kb
Host smart-18204cbd-9d5e-4e7f-b9dd-79080d1493d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178663492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4178663492
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2087903875
Short name T995
Test name
Test status
Simulation time 2479896655 ps
CPU time 26.4 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:34 PM PDT 24
Peak memory 343716 kb
Host smart-93077f77-b9a7-4f5f-9a49-53f3f92b443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087903875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2087903875
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1725214794
Short name T43
Test name
Test status
Simulation time 15895542497 ps
CPU time 371.23 seconds
Started May 21 02:50:06 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 1239640 kb
Host smart-94776ce0-f7f4-4443-943a-bcfa8c458024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725214794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1725214794
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1186436112
Short name T427
Test name
Test status
Simulation time 3773587308 ps
CPU time 15.29 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 221348 kb
Host smart-b2b2266f-f664-422b-b315-f0ff5cc5001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186436112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1186436112
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1458352785
Short name T788
Test name
Test status
Simulation time 3073888383 ps
CPU time 4.88 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:13 PM PDT 24
Peak memory 205176 kb
Host smart-df793ca8-ae79-48ea-b0b3-6270634938db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458352785 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1458352785
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2024856884
Short name T758
Test name
Test status
Simulation time 10151055228 ps
CPU time 14.67 seconds
Started May 21 02:50:06 PM PDT 24
Finished May 21 02:50:24 PM PDT 24
Peak memory 261156 kb
Host smart-24630411-a66e-4edd-ba02-a016bb8dcab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024856884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2024856884
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3016047043
Short name T712
Test name
Test status
Simulation time 10191109787 ps
CPU time 31.43 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:39 PM PDT 24
Peak memory 384060 kb
Host smart-7fbc4734-d632-41c3-8a8a-f0e620ec7353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016047043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3016047043
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.402652366
Short name T1220
Test name
Test status
Simulation time 807104900 ps
CPU time 2.82 seconds
Started May 21 02:50:12 PM PDT 24
Finished May 21 02:50:16 PM PDT 24
Peak memory 205028 kb
Host smart-221a56c3-35ef-4c9e-8c5b-edad612bf421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402652366 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.402652366
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3256745870
Short name T309
Test name
Test status
Simulation time 2042386811 ps
CPU time 7.1 seconds
Started May 21 02:50:03 PM PDT 24
Finished May 21 02:50:12 PM PDT 24
Peak memory 213180 kb
Host smart-fbe34c2b-2ec4-49fc-89b2-420e5836ac0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256745870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3256745870
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.70244594
Short name T657
Test name
Test status
Simulation time 19267803346 ps
CPU time 391.88 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:56:37 PM PDT 24
Peak memory 4627288 kb
Host smart-0faa77f5-ff10-4af9-8e83-df58d7a843b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70244594 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.70244594
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3244500002
Short name T308
Test name
Test status
Simulation time 2412739492 ps
CPU time 20.85 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:29 PM PDT 24
Peak memory 205064 kb
Host smart-833c3e52-c61c-49f0-953e-595323de62d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244500002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3244500002
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1844173203
Short name T432
Test name
Test status
Simulation time 1667575555 ps
CPU time 31.16 seconds
Started May 21 02:50:04 PM PDT 24
Finished May 21 02:50:38 PM PDT 24
Peak memory 227796 kb
Host smart-fca93dbc-94f8-414d-bf35-c87faa3d03a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844173203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1844173203
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2296848864
Short name T1218
Test name
Test status
Simulation time 35050116216 ps
CPU time 142.53 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:52:30 PM PDT 24
Peak memory 1900360 kb
Host smart-888271b5-20c7-4d54-9a39-fae2fc9c6ed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296848864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2296848864
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2216457372
Short name T763
Test name
Test status
Simulation time 10022644248 ps
CPU time 512.24 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:58:41 PM PDT 24
Peak memory 1674908 kb
Host smart-094f2287-9fc9-4e83-a48f-81a58656d7e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216457372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2216457372
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.359628749
Short name T30
Test name
Test status
Simulation time 9761009718 ps
CPU time 7.93 seconds
Started May 21 02:50:05 PM PDT 24
Finished May 21 02:50:16 PM PDT 24
Peak memory 221348 kb
Host smart-67383c3e-7f93-495c-913c-c44310b8adcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359628749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.359628749
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2800979790
Short name T1066
Test name
Test status
Simulation time 68653183 ps
CPU time 0.64 seconds
Started May 21 02:50:18 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 204580 kb
Host smart-b6073b06-36c6-4a81-b5e0-1c792300fd07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800979790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2800979790
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2741961976
Short name T754
Test name
Test status
Simulation time 115379666 ps
CPU time 3.71 seconds
Started May 21 02:50:11 PM PDT 24
Finished May 21 02:50:16 PM PDT 24
Peak memory 213304 kb
Host smart-a0743b29-51c9-4d73-87bc-9949f5bebe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741961976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2741961976
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1005959286
Short name T1039
Test name
Test status
Simulation time 374908825 ps
CPU time 6.74 seconds
Started May 21 02:50:10 PM PDT 24
Finished May 21 02:50:19 PM PDT 24
Peak memory 283244 kb
Host smart-2f78e983-4359-477e-95b1-ea1cd0c6faf1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005959286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1005959286
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.4107216111
Short name T774
Test name
Test status
Simulation time 2841473175 ps
CPU time 71.55 seconds
Started May 21 02:50:10 PM PDT 24
Finished May 21 02:51:24 PM PDT 24
Peak memory 691480 kb
Host smart-d7f31901-9458-4fdf-9113-6e8e68d21eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107216111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.4107216111
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2787517509
Short name T532
Test name
Test status
Simulation time 2841261751 ps
CPU time 38.63 seconds
Started May 21 02:50:11 PM PDT 24
Finished May 21 02:50:52 PM PDT 24
Peak memory 544668 kb
Host smart-fdd5e295-1008-4912-96f7-4433a8c2be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787517509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2787517509
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1240752533
Short name T1214
Test name
Test status
Simulation time 593346043 ps
CPU time 1.04 seconds
Started May 21 02:50:11 PM PDT 24
Finished May 21 02:50:13 PM PDT 24
Peak memory 204800 kb
Host smart-7d3b0dfe-1c71-465c-99e9-368189e9ca28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240752533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1240752533
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3813874322
Short name T731
Test name
Test status
Simulation time 158495133 ps
CPU time 8.98 seconds
Started May 21 02:50:09 PM PDT 24
Finished May 21 02:50:20 PM PDT 24
Peak memory 232720 kb
Host smart-3b52d792-cdd6-43d8-94d9-c4d00692905d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813874322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3813874322
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3552703871
Short name T1113
Test name
Test status
Simulation time 20678494573 ps
CPU time 124.82 seconds
Started May 21 02:50:12 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 1302784 kb
Host smart-b0235ce8-8ed5-4b96-b9c9-55aecb689fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552703871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3552703871
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.66874152
Short name T931
Test name
Test status
Simulation time 2435003426 ps
CPU time 3.9 seconds
Started May 21 02:50:15 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 205084 kb
Host smart-3e86fd7c-bb8a-4f9b-9bb0-5614f02ba95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66874152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.66874152
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3294595528
Short name T1203
Test name
Test status
Simulation time 12057135808 ps
CPU time 88.32 seconds
Started May 21 02:50:20 PM PDT 24
Finished May 21 02:51:50 PM PDT 24
Peak memory 357460 kb
Host smart-0331c8f1-b2fa-45cd-b979-96f76890d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294595528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3294595528
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2570120132
Short name T124
Test name
Test status
Simulation time 88744636 ps
CPU time 0.64 seconds
Started May 21 02:50:10 PM PDT 24
Finished May 21 02:50:12 PM PDT 24
Peak memory 204716 kb
Host smart-ad35590f-1661-4e35-aaa2-05ba058b11d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570120132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2570120132
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2518148877
Short name T526
Test name
Test status
Simulation time 13247132945 ps
CPU time 230.26 seconds
Started May 21 02:50:14 PM PDT 24
Finished May 21 02:54:06 PM PDT 24
Peak memory 942524 kb
Host smart-37ce020d-c8ab-452b-88b7-6f9a7657d76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518148877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2518148877
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.28054037
Short name T989
Test name
Test status
Simulation time 17453566857 ps
CPU time 22.08 seconds
Started May 21 02:50:10 PM PDT 24
Finished May 21 02:50:33 PM PDT 24
Peak memory 315008 kb
Host smart-2c0d0a4a-8f74-40fb-a8b2-18a77e5be313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28054037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.28054037
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1836187107
Short name T137
Test name
Test status
Simulation time 58447547814 ps
CPU time 924.29 seconds
Started May 21 02:50:11 PM PDT 24
Finished May 21 03:05:38 PM PDT 24
Peak memory 3013560 kb
Host smart-ab1c4749-5ab9-44b8-831c-c0115462f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836187107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1836187107
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1224213698
Short name T535
Test name
Test status
Simulation time 1260813791 ps
CPU time 7.48 seconds
Started May 21 02:50:12 PM PDT 24
Finished May 21 02:50:22 PM PDT 24
Peak memory 213164 kb
Host smart-16b5decd-96cf-4afc-a667-ec949576f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224213698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1224213698
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.552906360
Short name T20
Test name
Test status
Simulation time 474600923 ps
CPU time 2.52 seconds
Started May 21 02:50:17 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 205016 kb
Host smart-dcc6844c-e7ef-463e-9cea-1cfe5bc915c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552906360 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.552906360
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3137626892
Short name T836
Test name
Test status
Simulation time 10118444789 ps
CPU time 62.79 seconds
Started May 21 02:50:19 PM PDT 24
Finished May 21 02:51:23 PM PDT 24
Peak memory 467860 kb
Host smart-5d50e826-77cb-4bf3-bdce-58433261b559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137626892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3137626892
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3924938424
Short name T1253
Test name
Test status
Simulation time 10449039650 ps
CPU time 15.33 seconds
Started May 21 02:50:18 PM PDT 24
Finished May 21 02:50:35 PM PDT 24
Peak memory 284556 kb
Host smart-f280e830-d3aa-46fa-9722-0249d2442f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924938424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3924938424
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.4120851054
Short name T1072
Test name
Test status
Simulation time 1822577928 ps
CPU time 2.69 seconds
Started May 21 02:50:17 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 205068 kb
Host smart-18260350-3108-46c4-b824-0dba442927a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120851054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.4120851054
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2909988278
Short name T574
Test name
Test status
Simulation time 742775290 ps
CPU time 4.02 seconds
Started May 21 02:50:15 PM PDT 24
Finished May 21 02:50:21 PM PDT 24
Peak memory 204988 kb
Host smart-2a0315d6-6d9a-4897-9f13-ebedf0a78c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909988278 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2909988278
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2889132788
Short name T1204
Test name
Test status
Simulation time 5672383854 ps
CPU time 4.23 seconds
Started May 21 02:50:16 PM PDT 24
Finished May 21 02:50:22 PM PDT 24
Peak memory 205100 kb
Host smart-b4d46d3a-ca39-42cb-8628-9a3da63a0be5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889132788 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2889132788
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.2518623176
Short name T480
Test name
Test status
Simulation time 1311261710 ps
CPU time 46.47 seconds
Started May 21 02:50:18 PM PDT 24
Finished May 21 02:51:06 PM PDT 24
Peak memory 204968 kb
Host smart-4e21e62f-6650-41db-a15b-9526cbaf63f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518623176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.2518623176
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2139635106
Short name T661
Test name
Test status
Simulation time 6445352194 ps
CPU time 63.31 seconds
Started May 21 02:50:20 PM PDT 24
Finished May 21 02:51:25 PM PDT 24
Peak memory 207664 kb
Host smart-9981b54f-3dc5-424e-9721-ba58bdedf3b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139635106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2139635106
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3491958801
Short name T1297
Test name
Test status
Simulation time 12759273043 ps
CPU time 22.38 seconds
Started May 21 02:50:14 PM PDT 24
Finished May 21 02:50:38 PM PDT 24
Peak memory 205080 kb
Host smart-6d69da81-bcc8-4155-9709-156ddbcf8de1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491958801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3491958801
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1346655013
Short name T959
Test name
Test status
Simulation time 30520660075 ps
CPU time 596.59 seconds
Started May 21 02:50:16 PM PDT 24
Finished May 21 03:00:14 PM PDT 24
Peak memory 1725864 kb
Host smart-27cc0cf3-13b6-4c19-9500-b260764d43cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346655013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1346655013
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1579317145
Short name T1198
Test name
Test status
Simulation time 2775022295 ps
CPU time 7.53 seconds
Started May 21 02:50:17 PM PDT 24
Finished May 21 02:50:27 PM PDT 24
Peak memory 221412 kb
Host smart-8cfaa976-3eb3-48f9-adce-2de9da4cf9e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579317145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1579317145
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.107702994
Short name T436
Test name
Test status
Simulation time 15881076 ps
CPU time 0.63 seconds
Started May 21 02:50:30 PM PDT 24
Finished May 21 02:50:32 PM PDT 24
Peak memory 204648 kb
Host smart-65789f62-6bd8-4ccc-b0d9-803dbf85fe93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107702994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.107702994
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1840448247
Short name T1034
Test name
Test status
Simulation time 418276950 ps
CPU time 21.53 seconds
Started May 21 02:50:24 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 293152 kb
Host smart-b0c62c24-98eb-4fe4-8f99-acd84550b6e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840448247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1840448247
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3992180538
Short name T1333
Test name
Test status
Simulation time 6884063446 ps
CPU time 42.83 seconds
Started May 21 02:50:25 PM PDT 24
Finished May 21 02:51:09 PM PDT 24
Peak memory 470556 kb
Host smart-73b38285-e24e-4941-abbb-987a2def936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992180538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3992180538
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.4230573822
Short name T872
Test name
Test status
Simulation time 8226187578 ps
CPU time 60.86 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:51:24 PM PDT 24
Peak memory 639216 kb
Host smart-e8059d60-5f30-490c-a5a6-4d8d180c0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230573822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.4230573822
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.101306791
Short name T1129
Test name
Test status
Simulation time 73503361 ps
CPU time 0.82 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:50:25 PM PDT 24
Peak memory 204728 kb
Host smart-e4f2957a-f288-4640-959f-f58cdab4b400
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101306791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.101306791
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1392377215
Short name T1157
Test name
Test status
Simulation time 312165512 ps
CPU time 4.11 seconds
Started May 21 02:50:23 PM PDT 24
Finished May 21 02:50:28 PM PDT 24
Peak memory 234920 kb
Host smart-36c79e97-b325-4a61-9887-adb050012421
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392377215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1392377215
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4230237534
Short name T359
Test name
Test status
Simulation time 7012357879 ps
CPU time 103.36 seconds
Started May 21 02:50:26 PM PDT 24
Finished May 21 02:52:10 PM PDT 24
Peak memory 1043348 kb
Host smart-1bb6bc50-483c-4739-9dd5-48bb1690236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230237534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4230237534
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3212482989
Short name T1272
Test name
Test status
Simulation time 721571461 ps
CPU time 2.77 seconds
Started May 21 02:50:30 PM PDT 24
Finished May 21 02:50:33 PM PDT 24
Peak memory 204964 kb
Host smart-fb1f3903-44e6-45a7-9e34-88902e3f4dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212482989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3212482989
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.661676803
Short name T851
Test name
Test status
Simulation time 2545782180 ps
CPU time 38.83 seconds
Started May 21 02:50:27 PM PDT 24
Finished May 21 02:51:07 PM PDT 24
Peak memory 402188 kb
Host smart-0af4ffa1-375f-4b20-8859-e8c5bbbda694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661676803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.661676803
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1522223053
Short name T1099
Test name
Test status
Simulation time 26507183 ps
CPU time 0.71 seconds
Started May 21 02:50:17 PM PDT 24
Finished May 21 02:50:20 PM PDT 24
Peak memory 204696 kb
Host smart-3ef56a17-14a9-40c8-b3dc-22e914d20bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522223053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1522223053
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1399847295
Short name T1209
Test name
Test status
Simulation time 26624353550 ps
CPU time 1528.07 seconds
Started May 21 02:50:23 PM PDT 24
Finished May 21 03:15:53 PM PDT 24
Peak memory 923600 kb
Host smart-51e31468-4527-4f02-9ebe-34a7ab280d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399847295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1399847295
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.733011740
Short name T403
Test name
Test status
Simulation time 1981775027 ps
CPU time 105.76 seconds
Started May 21 02:50:19 PM PDT 24
Finished May 21 02:52:06 PM PDT 24
Peak memory 486980 kb
Host smart-db79431a-70a7-4665-ab64-55636ff164da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733011740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.733011740
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2660987660
Short name T1166
Test name
Test status
Simulation time 782887081 ps
CPU time 12.03 seconds
Started May 21 02:50:23 PM PDT 24
Finished May 21 02:50:37 PM PDT 24
Peak memory 221380 kb
Host smart-a66fc0cb-4dec-4156-ad19-e2eca5bfda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660987660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2660987660
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3178153971
Short name T502
Test name
Test status
Simulation time 530328899 ps
CPU time 2.48 seconds
Started May 21 02:50:27 PM PDT 24
Finished May 21 02:50:31 PM PDT 24
Peak memory 205016 kb
Host smart-847f9c1b-557e-4844-b102-c4896b4cb558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178153971 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3178153971
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1218358795
Short name T406
Test name
Test status
Simulation time 10163367764 ps
CPU time 13.85 seconds
Started May 21 02:50:21 PM PDT 24
Finished May 21 02:50:36 PM PDT 24
Peak memory 263908 kb
Host smart-faab2b75-3f2b-4f2d-a2cf-a85f32530cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218358795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1218358795
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.462733256
Short name T1059
Test name
Test status
Simulation time 10155252742 ps
CPU time 80.06 seconds
Started May 21 02:50:30 PM PDT 24
Finished May 21 02:51:51 PM PDT 24
Peak memory 639404 kb
Host smart-5b432e19-51c0-464b-816e-c697d16fa146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462733256 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.462733256
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.4213174983
Short name T747
Test name
Test status
Simulation time 1529396922 ps
CPU time 2.73 seconds
Started May 21 02:50:27 PM PDT 24
Finished May 21 02:50:32 PM PDT 24
Peak memory 205072 kb
Host smart-3adf0dc4-841d-485e-b74e-781ae3545f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213174983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.4213174983
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1984972734
Short name T277
Test name
Test status
Simulation time 704027133 ps
CPU time 4.02 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:50:28 PM PDT 24
Peak memory 204992 kb
Host smart-ec4a5b6e-7f01-40f4-898b-7839f470dfd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984972734 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1984972734
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.15357480
Short name T354
Test name
Test status
Simulation time 16444539994 ps
CPU time 6.91 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:50:31 PM PDT 24
Peak memory 308036 kb
Host smart-f05dc283-306e-4ac3-9bc9-1d97378443be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357480 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.15357480
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.287059674
Short name T994
Test name
Test status
Simulation time 3693289695 ps
CPU time 36.24 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:51:00 PM PDT 24
Peak memory 205088 kb
Host smart-6490bc8f-fbc9-4140-b73d-12f31616f3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287059674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.287059674
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.472467233
Short name T31
Test name
Test status
Simulation time 5014275979 ps
CPU time 49.59 seconds
Started May 21 02:50:26 PM PDT 24
Finished May 21 02:51:16 PM PDT 24
Peak memory 206996 kb
Host smart-36a04e62-d52a-495d-ae59-7e8a7109b711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472467233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.472467233
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2906129261
Short name T1315
Test name
Test status
Simulation time 55230917427 ps
CPU time 525.61 seconds
Started May 21 02:50:20 PM PDT 24
Finished May 21 02:59:08 PM PDT 24
Peak memory 4497968 kb
Host smart-4c5f9ce5-0262-4565-82b7-cfe33cee5f08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906129261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2906129261
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3063866330
Short name T671
Test name
Test status
Simulation time 20136379618 ps
CPU time 346.67 seconds
Started May 21 02:50:26 PM PDT 24
Finished May 21 02:56:13 PM PDT 24
Peak memory 2122504 kb
Host smart-e9930c60-96d9-4811-be8b-4ba166af6574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063866330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3063866330
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.502535998
Short name T1003
Test name
Test status
Simulation time 1178958873 ps
CPU time 6.85 seconds
Started May 21 02:50:22 PM PDT 24
Finished May 21 02:50:31 PM PDT 24
Peak memory 218428 kb
Host smart-9ad7d7fc-0906-432b-9065-c877530cf571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502535998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.502535998
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.441360417
Short name T430
Test name
Test status
Simulation time 78426459 ps
CPU time 0.61 seconds
Started May 21 02:50:37 PM PDT 24
Finished May 21 02:50:39 PM PDT 24
Peak memory 204660 kb
Host smart-384c4c93-c12d-4984-a665-ba7b4caa675d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441360417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.441360417
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3097221609
Short name T976
Test name
Test status
Simulation time 201061374 ps
CPU time 6.89 seconds
Started May 21 02:50:38 PM PDT 24
Finished May 21 02:50:47 PM PDT 24
Peak memory 221448 kb
Host smart-5a85f4aa-2d3c-40d5-b33e-c8daa89e4930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097221609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3097221609
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.4112220418
Short name T1294
Test name
Test status
Simulation time 287615662 ps
CPU time 15.06 seconds
Started May 21 02:50:27 PM PDT 24
Finished May 21 02:50:44 PM PDT 24
Peak memory 259432 kb
Host smart-fc795c10-f29e-4349-adba-c2d8861309ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112220418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.4112220418
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.4100654153
Short name T907
Test name
Test status
Simulation time 7565070072 ps
CPU time 58.97 seconds
Started May 21 02:50:38 PM PDT 24
Finished May 21 02:51:39 PM PDT 24
Peak memory 656576 kb
Host smart-766dad5c-f6ed-4c65-acc7-44295ddd9553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100654153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.4100654153
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2365821676
Short name T587
Test name
Test status
Simulation time 11152245422 ps
CPU time 93.23 seconds
Started May 21 02:50:27 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 869300 kb
Host smart-81094b74-5553-4f4b-8580-1765cd49e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365821676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2365821676
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2518362248
Short name T510
Test name
Test status
Simulation time 226800297 ps
CPU time 0.93 seconds
Started May 21 02:50:29 PM PDT 24
Finished May 21 02:50:31 PM PDT 24
Peak memory 204776 kb
Host smart-4d0a800c-7824-4097-b24b-3f4bdf95d9da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518362248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2518362248
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2447973977
Short name T1031
Test name
Test status
Simulation time 784224705 ps
CPU time 10.2 seconds
Started May 21 02:50:30 PM PDT 24
Finished May 21 02:50:41 PM PDT 24
Peak memory 204948 kb
Host smart-d8f9a156-33ab-46c4-9993-3af5af7b3a97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447973977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2447973977
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.695362795
Short name T100
Test name
Test status
Simulation time 36943643247 ps
CPU time 120.19 seconds
Started May 21 02:50:30 PM PDT 24
Finished May 21 02:52:31 PM PDT 24
Peak memory 1310276 kb
Host smart-c8ba8394-cd4d-4cfc-9c21-0b751ae4b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695362795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.695362795
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.3509455078
Short name T1025
Test name
Test status
Simulation time 824221274 ps
CPU time 6.11 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:50:44 PM PDT 24
Peak memory 204984 kb
Host smart-e0f53c3e-ad6b-45fd-9aab-d33aec3274b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509455078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3509455078
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.1973236022
Short name T125
Test name
Test status
Simulation time 27440398 ps
CPU time 0.65 seconds
Started May 21 02:50:28 PM PDT 24
Finished May 21 02:50:30 PM PDT 24
Peak memory 204716 kb
Host smart-24cf8e07-a4a3-4423-b9d2-361e88f9ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973236022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1973236022
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.319387795
Short name T362
Test name
Test status
Simulation time 6607892702 ps
CPU time 197.89 seconds
Started May 21 02:50:34 PM PDT 24
Finished May 21 02:53:54 PM PDT 24
Peak memory 1118712 kb
Host smart-c9780fbf-c236-45f1-852e-835351d1481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319387795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.319387795
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2335828665
Short name T545
Test name
Test status
Simulation time 4559214403 ps
CPU time 64.6 seconds
Started May 21 02:50:29 PM PDT 24
Finished May 21 02:51:34 PM PDT 24
Peak memory 324116 kb
Host smart-ed57a8f7-984f-46ae-a257-bfbc7795fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335828665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2335828665
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3711625159
Short name T760
Test name
Test status
Simulation time 3032254185 ps
CPU time 11.86 seconds
Started May 21 02:50:38 PM PDT 24
Finished May 21 02:50:52 PM PDT 24
Peak memory 218292 kb
Host smart-49efb9bc-f942-4ce5-b80e-44a0d1589f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711625159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3711625159
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2651092402
Short name T1323
Test name
Test status
Simulation time 1745369274 ps
CPU time 4.32 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:50:42 PM PDT 24
Peak memory 213244 kb
Host smart-8d62bbb3-5d33-4da6-bea5-49531180bccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651092402 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2651092402
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.205870080
Short name T1293
Test name
Test status
Simulation time 10030550185 ps
CPU time 71.66 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:51:50 PM PDT 24
Peak memory 446928 kb
Host smart-f8cee95d-0f06-48ad-a13f-3aea2ca92692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205870080 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.205870080
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3687515436
Short name T647
Test name
Test status
Simulation time 10097080276 ps
CPU time 73.69 seconds
Started May 21 02:50:35 PM PDT 24
Finished May 21 02:51:51 PM PDT 24
Peak memory 573192 kb
Host smart-fa7dca97-7358-4587-a01e-863e163435cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687515436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3687515436
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.492711452
Short name T23
Test name
Test status
Simulation time 721507118 ps
CPU time 2.35 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:50:40 PM PDT 24
Peak memory 205108 kb
Host smart-2323ff2c-6fb1-41ba-9aa5-68e2ba151a07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492711452 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.492711452
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.454124118
Short name T361
Test name
Test status
Simulation time 4888113063 ps
CPU time 6.12 seconds
Started May 21 02:50:37 PM PDT 24
Finished May 21 02:50:45 PM PDT 24
Peak memory 213316 kb
Host smart-3ade847b-a61f-4e7b-9a46-2eb3cd868411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454124118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.454124118
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2924387181
Short name T1320
Test name
Test status
Simulation time 18645971018 ps
CPU time 129.36 seconds
Started May 21 02:50:37 PM PDT 24
Finished May 21 02:52:49 PM PDT 24
Peak memory 2325368 kb
Host smart-5253cfd0-5b8f-4574-90e3-0cea9fc96573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924387181 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2924387181
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1989721388
Short name T1132
Test name
Test status
Simulation time 4496321898 ps
CPU time 30.26 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 02:51:08 PM PDT 24
Peak memory 205092 kb
Host smart-30c8daf5-27a2-4dc6-a3cc-435b9d1be1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989721388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1989721388
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1642851900
Short name T799
Test name
Test status
Simulation time 1025350634 ps
CPU time 15.63 seconds
Started May 21 02:50:35 PM PDT 24
Finished May 21 02:50:52 PM PDT 24
Peak memory 213312 kb
Host smart-7ea0c0ad-ea35-41cf-af68-4eb385d04566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642851900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1642851900
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1638949893
Short name T449
Test name
Test status
Simulation time 48219688820 ps
CPU time 1154.56 seconds
Started May 21 02:50:36 PM PDT 24
Finished May 21 03:09:52 PM PDT 24
Peak memory 6814636 kb
Host smart-e2d874d9-5eac-499f-ab87-a9f1e05b3109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638949893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1638949893
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2383609503
Short name T1303
Test name
Test status
Simulation time 13166104654 ps
CPU time 76.15 seconds
Started May 21 02:50:35 PM PDT 24
Finished May 21 02:51:54 PM PDT 24
Peak memory 851008 kb
Host smart-c0e07c20-fd14-4664-b978-08fe22982fe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383609503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2383609503
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3330301907
Short name T1007
Test name
Test status
Simulation time 18601866030 ps
CPU time 6.91 seconds
Started May 21 02:50:38 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 215984 kb
Host smart-560a4a18-3831-4c23-bb63-f99bfa814c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330301907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3330301907
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3486956697
Short name T905
Test name
Test status
Simulation time 125163415 ps
CPU time 0.6 seconds
Started May 21 02:50:47 PM PDT 24
Finished May 21 02:50:54 PM PDT 24
Peak memory 204588 kb
Host smart-dace57f5-fd01-40df-8118-2da2797901e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486956697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3486956697
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.4086028884
Short name T968
Test name
Test status
Simulation time 1241275655 ps
CPU time 4.66 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:50:51 PM PDT 24
Peak memory 262668 kb
Host smart-6bb7c5d5-fff3-45b4-91c8-eef4b366a1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086028884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.4086028884
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.82728179
Short name T330
Test name
Test status
Simulation time 604167084 ps
CPU time 4.65 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:50:52 PM PDT 24
Peak memory 252296 kb
Host smart-98953916-582b-4143-a924-7e02348d072c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82728179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty
.82728179
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2965712070
Short name T897
Test name
Test status
Simulation time 3869771161 ps
CPU time 55.89 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:51:41 PM PDT 24
Peak memory 649268 kb
Host smart-2ed5e90f-44df-4a7e-9f63-4168d03e74ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965712070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2965712070
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2310232459
Short name T350
Test name
Test status
Simulation time 8181530237 ps
CPU time 79.74 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:52:06 PM PDT 24
Peak memory 736896 kb
Host smart-d36dbb64-5040-40ba-aab7-011eab793f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310232459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2310232459
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.186340509
Short name T870
Test name
Test status
Simulation time 98633247 ps
CPU time 0.9 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 204788 kb
Host smart-6aa5cb38-8256-449a-a95c-47505e2991da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186340509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.186340509
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.228765535
Short name T714
Test name
Test status
Simulation time 722489923 ps
CPU time 5 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:50:51 PM PDT 24
Peak memory 240620 kb
Host smart-3e377d16-1662-4a4a-8ef7-6d711caf6b44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228765535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
228765535
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.987057554
Short name T1186
Test name
Test status
Simulation time 4105294141 ps
CPU time 142.77 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:53:07 PM PDT 24
Peak memory 1224272 kb
Host smart-b40ff85e-4994-4ae4-955a-fe133907df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987057554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.987057554
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1623014454
Short name T726
Test name
Test status
Simulation time 2261459959 ps
CPU time 5.66 seconds
Started May 21 02:50:49 PM PDT 24
Finished May 21 02:51:01 PM PDT 24
Peak memory 205132 kb
Host smart-43f72ced-63e8-4854-9bf7-074a71dedad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623014454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1623014454
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3372184554
Short name T434
Test name
Test status
Simulation time 7838082766 ps
CPU time 27.79 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 334696 kb
Host smart-83ce2141-9401-4642-b388-7340e06d9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372184554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3372184554
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1594419467
Short name T1190
Test name
Test status
Simulation time 49174831 ps
CPU time 0.65 seconds
Started May 21 02:50:44 PM PDT 24
Finished May 21 02:50:49 PM PDT 24
Peak memory 204736 kb
Host smart-d45a71e6-d6d2-4a64-9f03-b88a72e4a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594419467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1594419467
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3664650481
Short name T794
Test name
Test status
Simulation time 3499783710 ps
CPU time 9.56 seconds
Started May 21 02:50:43 PM PDT 24
Finished May 21 02:50:58 PM PDT 24
Peak memory 205152 kb
Host smart-ece52261-13c5-4a9f-bae5-e701726fb150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664650481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3664650481
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.407717076
Short name T1169
Test name
Test status
Simulation time 9689599445 ps
CPU time 35.22 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:51:22 PM PDT 24
Peak memory 428956 kb
Host smart-a61c6b8a-aeb2-4c1c-8766-362750956910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407717076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.407717076
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1391755659
Short name T106
Test name
Test status
Simulation time 13026918707 ps
CPU time 565.18 seconds
Started May 21 02:50:40 PM PDT 24
Finished May 21 03:00:09 PM PDT 24
Peak memory 2111256 kb
Host smart-08336f4d-6d08-41c5-92fe-d111b035e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391755659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1391755659
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2170517357
Short name T873
Test name
Test status
Simulation time 1864747771 ps
CPU time 17.76 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:51:04 PM PDT 24
Peak memory 213332 kb
Host smart-e242a158-110f-4bb1-8c1a-c80923e3f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170517357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2170517357
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.689726896
Short name T707
Test name
Test status
Simulation time 517473676 ps
CPU time 3 seconds
Started May 21 02:50:44 PM PDT 24
Finished May 21 02:50:53 PM PDT 24
Peak memory 205032 kb
Host smart-bd0dc9e9-29a4-40ff-88a8-10dddb81a8c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689726896 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.689726896
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3269246016
Short name T1053
Test name
Test status
Simulation time 10080768503 ps
CPU time 10.53 seconds
Started May 21 02:50:43 PM PDT 24
Finished May 21 02:50:59 PM PDT 24
Peak memory 229924 kb
Host smart-9a500ff1-a552-4b08-8b61-867746b5713a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269246016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3269246016
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2129659743
Short name T1152
Test name
Test status
Simulation time 10076277392 ps
CPU time 82.82 seconds
Started May 21 02:50:43 PM PDT 24
Finished May 21 02:52:11 PM PDT 24
Peak memory 446512 kb
Host smart-b492596f-9c6c-4c10-93f2-49cdd54f0950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129659743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2129659743
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2591427044
Short name T681
Test name
Test status
Simulation time 777605695 ps
CPU time 2.11 seconds
Started May 21 02:50:48 PM PDT 24
Finished May 21 02:50:56 PM PDT 24
Peak memory 205108 kb
Host smart-a3053ff7-9de9-4724-af3e-7e5efcbb43b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591427044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2591427044
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1989505982
Short name T864
Test name
Test status
Simulation time 4297419047 ps
CPU time 5.85 seconds
Started May 21 02:50:44 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 208892 kb
Host smart-5da9d3bc-0547-4558-9b2f-aad0e46f9331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989505982 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1989505982
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2900116215
Short name T841
Test name
Test status
Simulation time 17119375919 ps
CPU time 37.83 seconds
Started May 21 02:50:43 PM PDT 24
Finished May 21 02:51:26 PM PDT 24
Peak memory 645040 kb
Host smart-1ec7d955-f838-4e05-be5c-95bcd25e8dd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900116215 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2900116215
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.690032587
Short name T345
Test name
Test status
Simulation time 1103934710 ps
CPU time 44.71 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:51:31 PM PDT 24
Peak memory 204960 kb
Host smart-b95375b1-fead-4e60-b9ea-a0c10b1ce1c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690032587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.690032587
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1640738907
Short name T1295
Test name
Test status
Simulation time 8579319070 ps
CPU time 56.14 seconds
Started May 21 02:50:41 PM PDT 24
Finished May 21 02:51:42 PM PDT 24
Peak memory 207972 kb
Host smart-69841c2f-e837-4eee-84c5-d8bd6de520d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640738907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1640738907
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3362520616
Short name T710
Test name
Test status
Simulation time 61710925101 ps
CPU time 239.19 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:54:46 PM PDT 24
Peak memory 2695856 kb
Host smart-3f7ef402-02c9-4097-aec6-02e8d0cef903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362520616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3362520616
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2380449215
Short name T349
Test name
Test status
Simulation time 9634040635 ps
CPU time 143.63 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:53:11 PM PDT 24
Peak memory 656524 kb
Host smart-e01f634e-8704-4b9f-a65b-2217b170486d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380449215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2380449215
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1779814862
Short name T518
Test name
Test status
Simulation time 1255963266 ps
CPU time 7.04 seconds
Started May 21 02:50:42 PM PDT 24
Finished May 21 02:50:54 PM PDT 24
Peak memory 220544 kb
Host smart-2bec1d92-309d-4530-9923-e35a76913b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779814862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1779814862
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1540857065
Short name T1168
Test name
Test status
Simulation time 36384928 ps
CPU time 0.62 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:51:02 PM PDT 24
Peak memory 204636 kb
Host smart-3bd0b8f0-5d67-4f92-9f0f-3604c8810d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540857065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1540857065
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2609549785
Short name T538
Test name
Test status
Simulation time 709887272 ps
CPU time 3.02 seconds
Started May 21 02:50:48 PM PDT 24
Finished May 21 02:50:57 PM PDT 24
Peak memory 227328 kb
Host smart-e1dcdee5-bda1-4ec0-9987-e552c3a10595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609549785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2609549785
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.75287075
Short name T300
Test name
Test status
Simulation time 648816175 ps
CPU time 9.15 seconds
Started May 21 02:50:47 PM PDT 24
Finished May 21 02:51:02 PM PDT 24
Peak memory 239164 kb
Host smart-004ebd94-c30d-4f7e-be13-e3c24f1875a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75287075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty
.75287075
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2979019529
Short name T340
Test name
Test status
Simulation time 3579902227 ps
CPU time 60.59 seconds
Started May 21 02:50:49 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 640816 kb
Host smart-31431cfd-0802-490d-9fdf-438281b62924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979019529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2979019529
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1300978024
Short name T302
Test name
Test status
Simulation time 11479146302 ps
CPU time 151.06 seconds
Started May 21 02:50:49 PM PDT 24
Finished May 21 02:53:26 PM PDT 24
Peak memory 692800 kb
Host smart-0cec72f1-5532-4f93-9f3a-edf3d4262fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300978024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1300978024
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2014755035
Short name T653
Test name
Test status
Simulation time 708103485 ps
CPU time 1.18 seconds
Started May 21 02:50:48 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 204964 kb
Host smart-14610d45-bc01-4785-911a-5433553a9aa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014755035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2014755035
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3467698655
Short name T933
Test name
Test status
Simulation time 571636884 ps
CPU time 7.55 seconds
Started May 21 02:50:47 PM PDT 24
Finished May 21 02:51:01 PM PDT 24
Peak memory 205140 kb
Host smart-2756ff61-5736-49b5-9bf1-ee34cbd240b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467698655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3467698655
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.4090938135
Short name T511
Test name
Test status
Simulation time 11568433902 ps
CPU time 185.96 seconds
Started May 21 02:50:50 PM PDT 24
Finished May 21 02:54:03 PM PDT 24
Peak memory 861436 kb
Host smart-799c3bf1-7cb2-4203-a15c-e13421d194b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090938135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.4090938135
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2158073047
Short name T1057
Test name
Test status
Simulation time 861410851 ps
CPU time 7.11 seconds
Started May 21 02:50:55 PM PDT 24
Finished May 21 02:51:09 PM PDT 24
Peak memory 205048 kb
Host smart-3781d23b-c540-4492-bf50-6f8ccdd1d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158073047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2158073047
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3418462601
Short name T1223
Test name
Test status
Simulation time 2078823205 ps
CPU time 38.17 seconds
Started May 21 02:50:58 PM PDT 24
Finished May 21 02:51:43 PM PDT 24
Peak memory 353240 kb
Host smart-357df15c-904d-4073-91da-89d0c3ffaa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418462601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3418462601
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.4286141599
Short name T1018
Test name
Test status
Simulation time 20618589 ps
CPU time 0.65 seconds
Started May 21 02:50:48 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 204708 kb
Host smart-2b87a356-3afa-4bba-b9c3-2be5c17d21e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286141599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.4286141599
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2235484443
Short name T1142
Test name
Test status
Simulation time 48043482515 ps
CPU time 2206.27 seconds
Started May 21 02:50:50 PM PDT 24
Finished May 21 03:27:43 PM PDT 24
Peak memory 4000144 kb
Host smart-73924014-b5db-466d-874e-aa1818697959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235484443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2235484443
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3162078453
Short name T659
Test name
Test status
Simulation time 1914383904 ps
CPU time 31.53 seconds
Started May 21 02:50:49 PM PDT 24
Finished May 21 02:51:27 PM PDT 24
Peak memory 353016 kb
Host smart-da1f2475-b2ee-44ec-939b-40339b2bf8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162078453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3162078453
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1362187196
Short name T202
Test name
Test status
Simulation time 26647651800 ps
CPU time 545.7 seconds
Started May 21 02:50:50 PM PDT 24
Finished May 21 03:00:03 PM PDT 24
Peak memory 1097272 kb
Host smart-319b56cf-5e50-4b33-8876-4e4b6d71c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362187196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1362187196
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.301478791
Short name T536
Test name
Test status
Simulation time 1824779601 ps
CPU time 8.68 seconds
Started May 21 02:50:49 PM PDT 24
Finished May 21 02:51:04 PM PDT 24
Peak memory 213084 kb
Host smart-1314c28d-f376-45ef-91fa-9f80bf6495bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301478791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.301478791
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1318759033
Short name T751
Test name
Test status
Simulation time 629962932 ps
CPU time 3.38 seconds
Started May 21 02:50:53 PM PDT 24
Finished May 21 02:51:04 PM PDT 24
Peak memory 205012 kb
Host smart-fca183f5-3916-4738-a145-47fcc6cf04c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318759033 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1318759033
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1848181064
Short name T670
Test name
Test status
Simulation time 10089562354 ps
CPU time 61.91 seconds
Started May 21 02:50:59 PM PDT 24
Finished May 21 02:52:07 PM PDT 24
Peak memory 421604 kb
Host smart-48e9cc81-e865-4c0f-9320-0c436abfb313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848181064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1848181064
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2840055005
Short name T767
Test name
Test status
Simulation time 10069998317 ps
CPU time 14.11 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:51:16 PM PDT 24
Peak memory 270828 kb
Host smart-1e05e989-e2b0-4069-bf6a-31a012c4c211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840055005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2840055005
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3666147966
Short name T217
Test name
Test status
Simulation time 935216181 ps
CPU time 2.41 seconds
Started May 21 02:50:53 PM PDT 24
Finished May 21 02:51:03 PM PDT 24
Peak memory 205060 kb
Host smart-8f4e2c68-ea8f-44a8-9493-4697fdf5fd1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666147966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3666147966
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3498172667
Short name T252
Test name
Test status
Simulation time 3066232178 ps
CPU time 7.39 seconds
Started May 21 02:50:57 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 213328 kb
Host smart-dcc1a66f-f967-45b0-93ce-c737d5b25c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498172667 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3498172667
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1422272575
Short name T398
Test name
Test status
Simulation time 21825674512 ps
CPU time 159.58 seconds
Started May 21 02:50:52 PM PDT 24
Finished May 21 02:53:38 PM PDT 24
Peak memory 2519380 kb
Host smart-1616ca00-d87e-4fa1-9107-b2db93f12c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422272575 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1422272575
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.916938286
Short name T560
Test name
Test status
Simulation time 6422270510 ps
CPU time 63.16 seconds
Started May 21 02:50:50 PM PDT 24
Finished May 21 02:52:00 PM PDT 24
Peak memory 205128 kb
Host smart-4d05aec4-83aa-416b-9804-3608aa81a19b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916938286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.916938286
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1560785021
Short name T260
Test name
Test status
Simulation time 7195250528 ps
CPU time 27.32 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 205108 kb
Host smart-96216fdd-4f46-4007-9135-065a474b262e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560785021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1560785021
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2526288331
Short name T333
Test name
Test status
Simulation time 24097895031 ps
CPU time 14.59 seconds
Started May 21 02:50:53 PM PDT 24
Finished May 21 02:51:14 PM PDT 24
Peak memory 307936 kb
Host smart-a890a90d-245d-421c-b7b2-37c238883b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526288331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2526288331
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3233691072
Short name T321
Test name
Test status
Simulation time 21869844381 ps
CPU time 281.74 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 1020620 kb
Host smart-5b34b79c-ddb4-4e3c-80e9-576e9134421a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233691072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3233691072
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.264405373
Short name T1219
Test name
Test status
Simulation time 7684909568 ps
CPU time 6.55 seconds
Started May 21 02:50:53 PM PDT 24
Finished May 21 02:51:06 PM PDT 24
Peak memory 221392 kb
Host smart-1699640d-11c9-421f-8d1a-ef39f019f59b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264405373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.264405373
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3968112227
Short name T1002
Test name
Test status
Simulation time 19197149 ps
CPU time 0.64 seconds
Started May 21 02:51:05 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 204644 kb
Host smart-08acd48a-778b-49e7-abef-5f7df29132ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968112227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3968112227
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.929764462
Short name T1061
Test name
Test status
Simulation time 317973454 ps
CPU time 1.56 seconds
Started May 21 02:50:58 PM PDT 24
Finished May 21 02:51:06 PM PDT 24
Peak memory 205052 kb
Host smart-4d136462-a0d7-44d4-8637-774837955a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929764462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.929764462
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2386936918
Short name T1189
Test name
Test status
Simulation time 1424328520 ps
CPU time 4.92 seconds
Started May 21 02:50:57 PM PDT 24
Finished May 21 02:51:08 PM PDT 24
Peak memory 257676 kb
Host smart-9c035702-920b-4f58-b8ef-b580a358f936
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386936918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2386936918
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2270778245
Short name T867
Test name
Test status
Simulation time 2695988545 ps
CPU time 102.8 seconds
Started May 21 02:50:59 PM PDT 24
Finished May 21 02:52:47 PM PDT 24
Peak memory 868188 kb
Host smart-6ad7bb8d-f12f-447d-a368-af34a1dfe9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270778245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2270778245
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1829007777
Short name T1011
Test name
Test status
Simulation time 4250274460 ps
CPU time 66.45 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 663840 kb
Host smart-ee08cf95-6204-4434-a50d-0fa73791f456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829007777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1829007777
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2341921283
Short name T486
Test name
Test status
Simulation time 120978733 ps
CPU time 0.97 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:10 PM PDT 24
Peak memory 204764 kb
Host smart-fbefae33-b16c-4504-9339-e259e4bf5939
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341921283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2341921283
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1421213412
Short name T706
Test name
Test status
Simulation time 672819046 ps
CPU time 8.22 seconds
Started May 21 02:50:57 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 204980 kb
Host smart-8edcdcf4-2c83-490c-9a12-dc05f355805a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421213412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1421213412
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.4068759912
Short name T666
Test name
Test status
Simulation time 2838097995 ps
CPU time 77.01 seconds
Started May 21 02:51:00 PM PDT 24
Finished May 21 02:52:23 PM PDT 24
Peak memory 864600 kb
Host smart-4d004ccc-7bfd-4670-b88f-8171edcb2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068759912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.4068759912
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.4032214662
Short name T988
Test name
Test status
Simulation time 474547769 ps
CPU time 19.55 seconds
Started May 21 02:51:02 PM PDT 24
Finished May 21 02:51:28 PM PDT 24
Peak memory 205052 kb
Host smart-7c62600f-4583-4bbc-9c39-85f6bf36f8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032214662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.4032214662
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.1858840812
Short name T1141
Test name
Test status
Simulation time 88464747 ps
CPU time 0.65 seconds
Started May 21 02:50:54 PM PDT 24
Finished May 21 02:51:01 PM PDT 24
Peak memory 204720 kb
Host smart-01c58b23-63e7-4df7-8f56-8ecb450142d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858840812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1858840812
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.916074015
Short name T36
Test name
Test status
Simulation time 47760856575 ps
CPU time 254.79 seconds
Started May 21 02:51:00 PM PDT 24
Finished May 21 02:55:21 PM PDT 24
Peak memory 1279644 kb
Host smart-dee91c67-ab75-4ddf-a640-96e174bf7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916074015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.916074015
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1933149969
Short name T414
Test name
Test status
Simulation time 6391487985 ps
CPU time 21.46 seconds
Started May 21 02:50:53 PM PDT 24
Finished May 21 02:51:22 PM PDT 24
Peak memory 293024 kb
Host smart-cb7da4b9-5a20-4fc3-8393-9bb1e6442cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933149969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1933149969
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.4289918847
Short name T1196
Test name
Test status
Simulation time 13632219449 ps
CPU time 698.23 seconds
Started May 21 02:50:58 PM PDT 24
Finished May 21 03:02:43 PM PDT 24
Peak memory 3182840 kb
Host smart-748e5a55-72fc-4550-857c-1b9610d8bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289918847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4289918847
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.134334681
Short name T1197
Test name
Test status
Simulation time 803224776 ps
CPU time 23.41 seconds
Started May 21 02:51:00 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 213188 kb
Host smart-87f11a43-980d-4690-a4c8-56abc4b0078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134334681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.134334681
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2335943009
Short name T1285
Test name
Test status
Simulation time 1834270541 ps
CPU time 2.56 seconds
Started May 21 02:50:59 PM PDT 24
Finished May 21 02:51:07 PM PDT 24
Peak memory 205024 kb
Host smart-fa9d3db0-0e84-4a54-890f-d889e8851d14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335943009 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2335943009
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3708043539
Short name T199
Test name
Test status
Simulation time 10141004861 ps
CPU time 81.97 seconds
Started May 21 02:51:01 PM PDT 24
Finished May 21 02:52:29 PM PDT 24
Peak memory 536320 kb
Host smart-bb0e2cdf-3a85-4bcf-b5fc-95af4a49afe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708043539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3708043539
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.749159304
Short name T1274
Test name
Test status
Simulation time 10136273665 ps
CPU time 46.53 seconds
Started May 21 02:51:00 PM PDT 24
Finished May 21 02:51:53 PM PDT 24
Peak memory 473948 kb
Host smart-0f745f90-8014-4446-b73e-f42852dc301f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749159304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.749159304
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1712564534
Short name T984
Test name
Test status
Simulation time 1074847925 ps
CPU time 2.15 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 205072 kb
Host smart-d1886148-3763-4300-bbe3-a72b1b73bef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712564534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1712564534
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3985500608
Short name T923
Test name
Test status
Simulation time 3649270266 ps
CPU time 5.34 seconds
Started May 21 02:50:59 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 213264 kb
Host smart-0b3277a5-7077-4f5a-b513-1951be2c33bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985500608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3985500608
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4164503725
Short name T1090
Test name
Test status
Simulation time 7428587101 ps
CPU time 9 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 205036 kb
Host smart-465301c3-3b4c-4781-9f69-c810be513a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164503725 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4164503725
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3631096381
Short name T791
Test name
Test status
Simulation time 12959567473 ps
CPU time 45.04 seconds
Started May 21 02:50:58 PM PDT 24
Finished May 21 02:51:49 PM PDT 24
Peak memory 205156 kb
Host smart-27467a51-3707-40e6-b5a2-f2e4f2e21548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631096381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3631096381
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3502441105
Short name T417
Test name
Test status
Simulation time 928719610 ps
CPU time 10.72 seconds
Started May 21 02:50:57 PM PDT 24
Finished May 21 02:51:14 PM PDT 24
Peak memory 205032 kb
Host smart-dbb43859-df8d-479c-909c-229d0d691360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502441105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3502441105
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.258047775
Short name T926
Test name
Test status
Simulation time 23595586861 ps
CPU time 71.11 seconds
Started May 21 02:51:01 PM PDT 24
Finished May 21 02:52:18 PM PDT 24
Peak memory 921416 kb
Host smart-3b6f2d39-f552-4723-a06b-5bf8c9feabdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258047775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.258047775
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1069954393
Short name T575
Test name
Test status
Simulation time 1262201949 ps
CPU time 6.71 seconds
Started May 21 02:50:58 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 213200 kb
Host smart-2a701b6c-a13a-47a9-8d5f-4d240862521f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069954393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1069954393
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.4173100497
Short name T455
Test name
Test status
Simulation time 15780581 ps
CPU time 0.61 seconds
Started May 21 02:51:12 PM PDT 24
Finished May 21 02:51:16 PM PDT 24
Peak memory 204672 kb
Host smart-0259e221-4759-457d-a4e8-bbecae1a5379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173100497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4173100497
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2392976280
Short name T1150
Test name
Test status
Simulation time 215908968 ps
CPU time 2.54 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:12 PM PDT 24
Peak memory 213288 kb
Host smart-ecb004ff-e234-480e-8672-11bdb4516073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392976280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2392976280
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.464300730
Short name T324
Test name
Test status
Simulation time 809139886 ps
CPU time 9.19 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 294764 kb
Host smart-4553aeec-a1f6-494c-958c-76765e30c3e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464300730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.464300730
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2696280030
Short name T135
Test name
Test status
Simulation time 22078288845 ps
CPU time 105.53 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:52:55 PM PDT 24
Peak memory 589376 kb
Host smart-cfeb3188-0c7f-4476-96b0-6b5fe54ef69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696280030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2696280030
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2757388482
Short name T259
Test name
Test status
Simulation time 10889434679 ps
CPU time 90.17 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 885456 kb
Host smart-191ab540-8c5a-4621-b620-53f533221f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757388482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2757388482
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2845351294
Short name T316
Test name
Test status
Simulation time 101007559 ps
CPU time 0.94 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:51:10 PM PDT 24
Peak memory 204756 kb
Host smart-7e3c0893-2501-4ab7-8939-47afa6153360
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845351294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2845351294
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.675030549
Short name T1316
Test name
Test status
Simulation time 35013730879 ps
CPU time 262.29 seconds
Started May 21 02:51:09 PM PDT 24
Finished May 21 02:55:36 PM PDT 24
Peak memory 1035340 kb
Host smart-f653949c-1ab8-4af9-a020-df76dda58fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675030549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.675030549
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1573919696
Short name T663
Test name
Test status
Simulation time 358205858 ps
CPU time 5.41 seconds
Started May 21 02:51:11 PM PDT 24
Finished May 21 02:51:20 PM PDT 24
Peak memory 205024 kb
Host smart-64cbc1f0-8409-4055-9ff3-62f83fa2dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573919696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1573919696
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2152704754
Short name T605
Test name
Test status
Simulation time 6376866649 ps
CPU time 76.21 seconds
Started May 21 02:51:10 PM PDT 24
Finished May 21 02:52:31 PM PDT 24
Peak memory 400644 kb
Host smart-3090fca2-99ea-4b7b-a0ef-fae523f889a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152704754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2152704754
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2084762359
Short name T1048
Test name
Test status
Simulation time 29897454 ps
CPU time 0.7 seconds
Started May 21 02:51:05 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 204648 kb
Host smart-bfa7656e-97e7-44d3-97df-0fb5b68438e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084762359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2084762359
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2576497924
Short name T1319
Test name
Test status
Simulation time 6529057059 ps
CPU time 88.53 seconds
Started May 21 02:51:09 PM PDT 24
Finished May 21 02:52:42 PM PDT 24
Peak memory 865440 kb
Host smart-6752474a-4526-4a64-8abb-c48985848874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576497924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2576497924
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1686066793
Short name T1110
Test name
Test status
Simulation time 2250158681 ps
CPU time 40.76 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:50 PM PDT 24
Peak memory 332456 kb
Host smart-93e28681-5408-40f0-993c-03453a6d66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686066793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1686066793
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1193621159
Short name T504
Test name
Test status
Simulation time 9101806578 ps
CPU time 963.9 seconds
Started May 21 02:51:08 PM PDT 24
Finished May 21 03:07:17 PM PDT 24
Peak memory 1844740 kb
Host smart-606c71dd-44f4-4610-a1f1-3a1baf8c1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193621159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1193621159
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3169159614
Short name T1174
Test name
Test status
Simulation time 907241780 ps
CPU time 17.45 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:26 PM PDT 24
Peak memory 216700 kb
Host smart-8f287d59-a617-482c-afdd-a75a4f5420a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169159614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3169159614
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3748556796
Short name T916
Test name
Test status
Simulation time 663483242 ps
CPU time 3.47 seconds
Started May 21 02:51:09 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 213228 kb
Host smart-caaf48a7-152d-47d2-8272-4bb7f740f59d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748556796 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3748556796
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.683028052
Short name T1268
Test name
Test status
Simulation time 10073084259 ps
CPU time 29.41 seconds
Started May 21 02:51:13 PM PDT 24
Finished May 21 02:51:45 PM PDT 24
Peak memory 330888 kb
Host smart-cf5ffc44-f454-4b9f-b6c9-7a5cf908b72a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683028052 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.683028052
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.4074192415
Short name T465
Test name
Test status
Simulation time 10996003041 ps
CPU time 8.15 seconds
Started May 21 02:51:12 PM PDT 24
Finished May 21 02:51:24 PM PDT 24
Peak memory 250504 kb
Host smart-45fa3a4f-915a-41d2-811e-e9708ca871ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074192415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.4074192415
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2781274601
Short name T559
Test name
Test status
Simulation time 744200164 ps
CPU time 2.64 seconds
Started May 21 02:51:10 PM PDT 24
Finished May 21 02:51:17 PM PDT 24
Peak memory 205084 kb
Host smart-d6915a28-7855-4f0a-b29f-7b26eb473aec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781274601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2781274601
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4145560901
Short name T1306
Test name
Test status
Simulation time 979180251 ps
CPU time 5.47 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:51:15 PM PDT 24
Peak memory 215448 kb
Host smart-e321a7da-f5ee-41cc-aaab-8366fbd463a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145560901 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4145560901
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3002578102
Short name T635
Test name
Test status
Simulation time 4500004598 ps
CPU time 9.53 seconds
Started May 21 02:51:02 PM PDT 24
Finished May 21 02:51:17 PM PDT 24
Peak memory 205140 kb
Host smart-3b87f4be-5738-46cc-b3b5-b897f732f00b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002578102 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3002578102
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.680329779
Short name T1299
Test name
Test status
Simulation time 1091914821 ps
CPU time 17.28 seconds
Started May 21 02:51:01 PM PDT 24
Finished May 21 02:51:24 PM PDT 24
Peak memory 204956 kb
Host smart-0288acb8-b93e-4a40-9755-b4a38e60bf0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680329779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.680329779
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3616618595
Short name T580
Test name
Test status
Simulation time 4647880590 ps
CPU time 16.49 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:51:25 PM PDT 24
Peak memory 212996 kb
Host smart-a2286aaa-1aec-4d1a-8c3f-6ea7fbe721ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616618595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3616618595
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1895255366
Short name T819
Test name
Test status
Simulation time 29966695899 ps
CPU time 76.44 seconds
Started May 21 02:51:03 PM PDT 24
Finished May 21 02:52:25 PM PDT 24
Peak memory 1269100 kb
Host smart-af453731-91ab-4942-8ab6-1e959e265dfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895255366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1895255366
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.154384078
Short name T607
Test name
Test status
Simulation time 30790118373 ps
CPU time 1837.84 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 03:21:48 PM PDT 24
Peak memory 7195216 kb
Host smart-2c22dfd2-bb0e-4d82-bf37-3cdf55677599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154384078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.154384078
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.233092181
Short name T1079
Test name
Test status
Simulation time 3738117842 ps
CPU time 8.04 seconds
Started May 21 02:51:04 PM PDT 24
Finished May 21 02:51:18 PM PDT 24
Peak memory 213328 kb
Host smart-5ccb4efb-4481-4443-9a6e-fb859505b505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233092181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.233092181
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3259437327
Short name T1096
Test name
Test status
Simulation time 23185874 ps
CPU time 0.62 seconds
Started May 21 02:51:24 PM PDT 24
Finished May 21 02:51:28 PM PDT 24
Peak memory 204664 kb
Host smart-6ae5dfb8-cc80-4f43-9f54-85158951d2f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259437327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3259437327
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.529711776
Short name T161
Test name
Test status
Simulation time 260907497 ps
CPU time 3.82 seconds
Started May 21 02:51:22 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 231000 kb
Host smart-a329b822-f1ca-4d17-b48c-2aafc83d3eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529711776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.529711776
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2538600931
Short name T985
Test name
Test status
Simulation time 1124649288 ps
CPU time 13.9 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:51:35 PM PDT 24
Peak memory 335712 kb
Host smart-acb19ea1-1ad7-46d8-ac3e-da5da6b80021
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538600931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2538600931
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3397227207
Short name T1095
Test name
Test status
Simulation time 11625078367 ps
CPU time 100.14 seconds
Started May 21 02:51:22 PM PDT 24
Finished May 21 02:53:05 PM PDT 24
Peak memory 929192 kb
Host smart-a07b80da-3969-4631-920f-b19f1d2a9807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397227207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3397227207
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4185484513
Short name T487
Test name
Test status
Simulation time 4381850700 ps
CPU time 67.75 seconds
Started May 21 02:51:13 PM PDT 24
Finished May 21 02:52:24 PM PDT 24
Peak memory 739124 kb
Host smart-2ae6066a-8a6d-4e64-89b4-7407b4287b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185484513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4185484513
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1948039821
Short name T594
Test name
Test status
Simulation time 138770581 ps
CPU time 1.21 seconds
Started May 21 02:51:13 PM PDT 24
Finished May 21 02:51:17 PM PDT 24
Peak memory 205020 kb
Host smart-0187568a-3462-4ec1-b5d3-c27db26aee9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948039821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1948039821
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1979624130
Short name T631
Test name
Test status
Simulation time 202379290 ps
CPU time 6.62 seconds
Started May 21 02:51:18 PM PDT 24
Finished May 21 02:51:28 PM PDT 24
Peak memory 205000 kb
Host smart-d8b3a388-130c-462d-ac56-b315881b88c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979624130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1979624130
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4165681125
Short name T1312
Test name
Test status
Simulation time 59858456701 ps
CPU time 139.24 seconds
Started May 21 02:51:11 PM PDT 24
Finished May 21 02:53:34 PM PDT 24
Peak memory 1366880 kb
Host smart-cb794824-9cd9-44f8-8e35-101a4713e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165681125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4165681125
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1749502257
Short name T42
Test name
Test status
Simulation time 655057572 ps
CPU time 5.21 seconds
Started May 21 02:51:22 PM PDT 24
Finished May 21 02:51:30 PM PDT 24
Peak memory 204968 kb
Host smart-bf2ded53-9097-476a-8396-7889080633db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749502257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1749502257
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2522023121
Short name T214
Test name
Test status
Simulation time 5309514310 ps
CPU time 27.19 seconds
Started May 21 02:51:27 PM PDT 24
Finished May 21 02:51:58 PM PDT 24
Peak memory 363988 kb
Host smart-ff9d0606-e0f0-4761-8617-517205a282ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522023121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2522023121
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.7111858
Short name T86
Test name
Test status
Simulation time 29746960 ps
CPU time 0.65 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:51:21 PM PDT 24
Peak memory 204672 kb
Host smart-97db43aa-ba17-4036-92db-dbf19a7afe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7111858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.7111858
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.359523250
Short name T875
Test name
Test status
Simulation time 7374655130 ps
CPU time 37.16 seconds
Started May 21 02:51:16 PM PDT 24
Finished May 21 02:51:56 PM PDT 24
Peak memory 205192 kb
Host smart-b47a0e01-fe05-4d29-8336-e2e84cff8838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359523250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.359523250
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3538050681
Short name T1309
Test name
Test status
Simulation time 8234769727 ps
CPU time 30.3 seconds
Started May 21 02:51:11 PM PDT 24
Finished May 21 02:51:45 PM PDT 24
Peak memory 363468 kb
Host smart-09adf680-b8d9-4693-8859-6ec3fecfc346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538050681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3538050681
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.504006373
Short name T1020
Test name
Test status
Simulation time 28871254122 ps
CPU time 669.57 seconds
Started May 21 02:51:16 PM PDT 24
Finished May 21 03:02:28 PM PDT 24
Peak memory 754864 kb
Host smart-0418c90b-57bb-4664-9830-1393568eab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504006373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.504006373
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1603466717
Short name T1191
Test name
Test status
Simulation time 806975178 ps
CPU time 12.52 seconds
Started May 21 02:51:19 PM PDT 24
Finished May 21 02:51:35 PM PDT 24
Peak memory 214728 kb
Host smart-f22047c7-2409-475c-acea-098d9819d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603466717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1603466717
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.378627179
Short name T919
Test name
Test status
Simulation time 855394635 ps
CPU time 4.19 seconds
Started May 21 02:51:22 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 205012 kb
Host smart-3369da50-1ffc-4e83-a82b-19d6fb8dd460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378627179 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.378627179
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3858236885
Short name T503
Test name
Test status
Simulation time 338915444 ps
CPU time 2.3 seconds
Started May 21 02:51:15 PM PDT 24
Finished May 21 02:51:20 PM PDT 24
Peak memory 205124 kb
Host smart-eacdc9bf-3493-4b33-b89d-327c91e0f0cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858236885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3858236885
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.80960375
Short name T557
Test name
Test status
Simulation time 628531047 ps
CPU time 3.6 seconds
Started May 21 02:51:18 PM PDT 24
Finished May 21 02:51:25 PM PDT 24
Peak memory 205040 kb
Host smart-5b0bc3c3-1c5a-4ffb-b279-0c40b7141c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80960375 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.80960375
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2796162806
Short name T974
Test name
Test status
Simulation time 22590674817 ps
CPU time 469.91 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:59:09 PM PDT 24
Peak memory 3936908 kb
Host smart-43c3a322-85a5-45bb-a8c6-58a1c0a115ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796162806 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2796162806
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2589303242
Short name T1159
Test name
Test status
Simulation time 12606461334 ps
CPU time 22.3 seconds
Started May 21 02:51:15 PM PDT 24
Finished May 21 02:51:40 PM PDT 24
Peak memory 205032 kb
Host smart-5ac3d6a7-e4c7-426b-ab59-26ec69107486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589303242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2589303242
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.4128068489
Short name T439
Test name
Test status
Simulation time 688614470 ps
CPU time 5.59 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:51:25 PM PDT 24
Peak memory 205112 kb
Host smart-62e9fd82-fbbd-4c44-8576-9df1407fd409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128068489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.4128068489
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2209432378
Short name T649
Test name
Test status
Simulation time 60152454330 ps
CPU time 251.33 seconds
Started May 21 02:51:19 PM PDT 24
Finished May 21 02:55:34 PM PDT 24
Peak memory 2467976 kb
Host smart-eb9166ff-4b62-4463-9df5-dc77357d88ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209432378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2209432378
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2922996433
Short name T555
Test name
Test status
Simulation time 24947840297 ps
CPU time 1556.11 seconds
Started May 21 02:51:16 PM PDT 24
Finished May 21 03:17:15 PM PDT 24
Peak memory 5918860 kb
Host smart-3a28261a-81fa-4221-a387-c5ac16e93d6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922996433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2922996433
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.929439811
Short name T884
Test name
Test status
Simulation time 1437151329 ps
CPU time 6.92 seconds
Started May 21 02:51:17 PM PDT 24
Finished May 21 02:51:26 PM PDT 24
Peak memory 218576 kb
Host smart-4cdaa82e-4d0e-4d3f-8ef9-7eb407ae4c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929439811 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.929439811
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3153793767
Short name T1001
Test name
Test status
Simulation time 135573097 ps
CPU time 0.6 seconds
Started May 21 02:51:27 PM PDT 24
Finished May 21 02:51:31 PM PDT 24
Peak memory 204660 kb
Host smart-57fb3148-9dd2-432d-ae3d-3c8f6f025dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153793767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3153793767
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2395961573
Short name T58
Test name
Test status
Simulation time 153396945 ps
CPU time 5.62 seconds
Started May 21 02:51:23 PM PDT 24
Finished May 21 02:51:32 PM PDT 24
Peak memory 214420 kb
Host smart-0626b1ae-738a-4375-aeac-54c4ea0f4a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395961573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2395961573
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1115229309
Short name T757
Test name
Test status
Simulation time 491037943 ps
CPU time 5.84 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:51:37 PM PDT 24
Peak memory 253484 kb
Host smart-1f2f3548-fda2-4ae0-bd8c-2f5e7ea7280f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115229309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1115229309
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2456177074
Short name T1291
Test name
Test status
Simulation time 12597371576 ps
CPU time 143.18 seconds
Started May 21 02:51:26 PM PDT 24
Finished May 21 02:53:52 PM PDT 24
Peak memory 706184 kb
Host smart-f8152cbe-1fc9-437b-adaf-b0a29addced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456177074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2456177074
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.497805009
Short name T323
Test name
Test status
Simulation time 2333913087 ps
CPU time 41.99 seconds
Started May 21 02:51:24 PM PDT 24
Finished May 21 02:52:09 PM PDT 24
Peak memory 511280 kb
Host smart-f58db7f7-625e-46ee-a2f4-0f453d55e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497805009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.497805009
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3074568352
Short name T531
Test name
Test status
Simulation time 137199427 ps
CPU time 1.02 seconds
Started May 21 02:51:24 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 204776 kb
Host smart-031b643c-2021-4fe6-9e7d-28d0c00a6bfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074568352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3074568352
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.345828696
Short name T552
Test name
Test status
Simulation time 197646638 ps
CPU time 4.55 seconds
Started May 21 02:51:28 PM PDT 24
Finished May 21 02:51:36 PM PDT 24
Peak memory 238912 kb
Host smart-da009aa0-82af-4c80-9cf4-27dd4c2ba092
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345828696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
345828696
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.83814520
Short name T896
Test name
Test status
Simulation time 20027126331 ps
CPU time 138.73 seconds
Started May 21 02:51:30 PM PDT 24
Finished May 21 02:53:51 PM PDT 24
Peak memory 1251220 kb
Host smart-547156a8-a8b8-4812-8f08-b9bdaa68d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83814520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.83814520
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1089539550
Short name T210
Test name
Test status
Simulation time 846997442 ps
CPU time 5.84 seconds
Started May 21 02:51:27 PM PDT 24
Finished May 21 02:51:36 PM PDT 24
Peak memory 204992 kb
Host smart-054e74c1-dd92-473e-952e-37a8b431c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089539550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1089539550
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3252320380
Short name T1235
Test name
Test status
Simulation time 8852938566 ps
CPU time 32.83 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:52:05 PM PDT 24
Peak memory 350228 kb
Host smart-26f8340f-20d8-456e-882c-4c3bc70ee6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252320380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3252320380
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3280989839
Short name T393
Test name
Test status
Simulation time 25225569 ps
CPU time 0.66 seconds
Started May 21 02:51:24 PM PDT 24
Finished May 21 02:51:28 PM PDT 24
Peak memory 204640 kb
Host smart-791f3792-90ea-4914-bcfe-a45ec6e0b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280989839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3280989839
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3780848117
Short name T1012
Test name
Test status
Simulation time 1416239155 ps
CPU time 72.07 seconds
Started May 21 02:51:28 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 350420 kb
Host smart-b17a514d-2a6c-4035-8a52-7adf4da243e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780848117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3780848117
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1712474244
Short name T853
Test name
Test status
Simulation time 713403880 ps
CPU time 11.64 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:51:43 PM PDT 24
Peak memory 229452 kb
Host smart-b238f1ae-8a7a-4f31-9eb4-69229bcc4d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712474244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1712474244
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1551832726
Short name T963
Test name
Test status
Simulation time 6116676204 ps
CPU time 3.3 seconds
Started May 21 02:51:31 PM PDT 24
Finished May 21 02:51:36 PM PDT 24
Peak memory 205140 kb
Host smart-ddf832e9-ba25-4b2c-a951-71576b991b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551832726 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1551832726
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.153624473
Short name T655
Test name
Test status
Simulation time 10140192253 ps
CPU time 12.31 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:51:44 PM PDT 24
Peak memory 262088 kb
Host smart-070d4959-c037-4014-bff9-50c3ba5ffd18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153624473 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.153624473
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.4220535457
Short name T966
Test name
Test status
Simulation time 10162094380 ps
CPU time 18.92 seconds
Started May 21 02:51:27 PM PDT 24
Finished May 21 02:51:49 PM PDT 24
Peak memory 280084 kb
Host smart-e74d2b4d-ca7b-48e5-91f3-e84c820b5790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220535457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.4220535457
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.4095232413
Short name T375
Test name
Test status
Simulation time 356769950 ps
CPU time 2.5 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:51:34 PM PDT 24
Peak memory 205104 kb
Host smart-4fdf8c4f-9186-49b2-a777-c75e1f7fdbf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095232413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.4095232413
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.305535294
Short name T807
Test name
Test status
Simulation time 1366479378 ps
CPU time 6.57 seconds
Started May 21 02:51:23 PM PDT 24
Finished May 21 02:51:33 PM PDT 24
Peak memory 221120 kb
Host smart-0ac41f8a-ca0d-4002-ab4d-b97daa338cfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305535294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.305535294
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.421143701
Short name T379
Test name
Test status
Simulation time 15317893818 ps
CPU time 91.02 seconds
Started May 21 02:51:30 PM PDT 24
Finished May 21 02:53:04 PM PDT 24
Peak memory 1700304 kb
Host smart-996dab00-4a0f-4270-a372-54ead3476a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421143701 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.421143701
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2131376917
Short name T282
Test name
Test status
Simulation time 853850010 ps
CPU time 34.18 seconds
Started May 21 02:51:23 PM PDT 24
Finished May 21 02:52:00 PM PDT 24
Peak memory 205000 kb
Host smart-07d0b059-70b3-4af0-a271-590afd51df6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131376917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2131376917
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1258549815
Short name T593
Test name
Test status
Simulation time 826339197 ps
CPU time 7.5 seconds
Started May 21 02:51:24 PM PDT 24
Finished May 21 02:51:35 PM PDT 24
Peak memory 204992 kb
Host smart-7cb49de0-b231-45e2-a1ab-731f0df90213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258549815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1258549815
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2391863974
Short name T1179
Test name
Test status
Simulation time 65968979482 ps
CPU time 2235.76 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 03:28:48 PM PDT 24
Peak memory 11632520 kb
Host smart-e154d711-ef09-40d3-80f5-602a4536639f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391863974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2391863974
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1918791815
Short name T469
Test name
Test status
Simulation time 5227444457 ps
CPU time 57.58 seconds
Started May 21 02:51:25 PM PDT 24
Finished May 21 02:52:26 PM PDT 24
Peak memory 452004 kb
Host smart-4fefcfc1-d00c-4836-8a97-8ea133078907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918791815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1918791815
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.624114337
Short name T617
Test name
Test status
Simulation time 6358434577 ps
CPU time 7.66 seconds
Started May 21 02:51:31 PM PDT 24
Finished May 21 02:51:40 PM PDT 24
Peak memory 213496 kb
Host smart-3fe22e7b-723c-4812-9ef7-d657e90c8a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624114337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.624114337
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.495469952
Short name T1287
Test name
Test status
Simulation time 29226823 ps
CPU time 0.63 seconds
Started May 21 02:47:19 PM PDT 24
Finished May 21 02:47:21 PM PDT 24
Peak memory 204660 kb
Host smart-0a108014-6d7a-4695-b20d-fb0eae894563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495469952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.495469952
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1933165805
Short name T1164
Test name
Test status
Simulation time 179421780 ps
CPU time 6.32 seconds
Started May 21 02:47:17 PM PDT 24
Finished May 21 02:47:25 PM PDT 24
Peak memory 231456 kb
Host smart-21752983-4ecc-40f5-94ea-7c8b4b07b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933165805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1933165805
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2354847095
Short name T1304
Test name
Test status
Simulation time 374498407 ps
CPU time 8.68 seconds
Started May 21 02:47:10 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 285432 kb
Host smart-00dd6857-8d58-470a-b060-4cd1d52e3f3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354847095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2354847095
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3033119743
Short name T849
Test name
Test status
Simulation time 2260395732 ps
CPU time 166.96 seconds
Started May 21 02:47:07 PM PDT 24
Finished May 21 02:49:56 PM PDT 24
Peak memory 716108 kb
Host smart-8ad33dde-fcfa-4f99-8b0e-7f510053cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033119743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3033119743
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2126703892
Short name T140
Test name
Test status
Simulation time 2439763039 ps
CPU time 77.54 seconds
Started May 21 02:47:10 PM PDT 24
Finished May 21 02:48:29 PM PDT 24
Peak memory 786468 kb
Host smart-e59d88b0-53d9-4684-b16a-33f9b406742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126703892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2126703892
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3895332270
Short name T1013
Test name
Test status
Simulation time 116414471 ps
CPU time 1 seconds
Started May 21 02:47:10 PM PDT 24
Finished May 21 02:47:13 PM PDT 24
Peak memory 204976 kb
Host smart-e46750e9-bb6e-4597-b417-d364e10f1f51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895332270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3895332270
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.4017962096
Short name T9
Test name
Test status
Simulation time 3321280548 ps
CPU time 4.4 seconds
Started May 21 02:47:09 PM PDT 24
Finished May 21 02:47:15 PM PDT 24
Peak memory 205064 kb
Host smart-604924c1-7bed-4ac3-9ef7-ab481e9124d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017962096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
4017962096
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1225975611
Short name T917
Test name
Test status
Simulation time 10634406090 ps
CPU time 72.57 seconds
Started May 21 02:47:09 PM PDT 24
Finished May 21 02:48:24 PM PDT 24
Peak memory 867416 kb
Host smart-208a55c0-9201-4bba-9906-282c4d61ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225975611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1225975611
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2525624804
Short name T1123
Test name
Test status
Simulation time 718763380 ps
CPU time 14.63 seconds
Started May 21 02:47:18 PM PDT 24
Finished May 21 02:47:35 PM PDT 24
Peak memory 205004 kb
Host smart-9e4dff35-4260-4056-8a49-cbd475a6a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525624804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2525624804
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3978137881
Short name T992
Test name
Test status
Simulation time 5736976109 ps
CPU time 31.56 seconds
Started May 21 02:47:21 PM PDT 24
Finished May 21 02:47:54 PM PDT 24
Peak memory 398744 kb
Host smart-941d8cb7-4003-4c26-b381-c8a9ae4ef483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978137881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3978137881
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.4264865904
Short name T556
Test name
Test status
Simulation time 26182026 ps
CPU time 0.68 seconds
Started May 21 02:47:08 PM PDT 24
Finished May 21 02:47:11 PM PDT 24
Peak memory 204708 kb
Host smart-3888ef19-90c8-425a-9652-6c6bd73a217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264865904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.4264865904
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1141951892
Short name T1173
Test name
Test status
Simulation time 642385127 ps
CPU time 2.75 seconds
Started May 21 02:47:09 PM PDT 24
Finished May 21 02:47:14 PM PDT 24
Peak memory 214340 kb
Host smart-0c619074-bcf9-468d-916d-11e229a95972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141951892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1141951892
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3435934021
Short name T468
Test name
Test status
Simulation time 3263574762 ps
CPU time 77.45 seconds
Started May 21 02:47:07 PM PDT 24
Finished May 21 02:48:26 PM PDT 24
Peak memory 326660 kb
Host smart-9ed78f63-f5b0-4ba5-a094-00a7d9ecaced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435934021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3435934021
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3989044998
Short name T740
Test name
Test status
Simulation time 38860791071 ps
CPU time 1128.43 seconds
Started May 21 02:47:14 PM PDT 24
Finished May 21 03:06:04 PM PDT 24
Peak memory 1597568 kb
Host smart-4564218c-46a5-40a0-b284-9943b1a26621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989044998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3989044998
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4115062122
Short name T798
Test name
Test status
Simulation time 1646201778 ps
CPU time 37.62 seconds
Started May 21 02:47:09 PM PDT 24
Finished May 21 02:47:49 PM PDT 24
Peak memory 220988 kb
Host smart-eb2d168d-f2e1-4355-bb61-34f5eaef0aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115062122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4115062122
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.610290429
Short name T158
Test name
Test status
Simulation time 64546393 ps
CPU time 0.94 seconds
Started May 21 02:47:19 PM PDT 24
Finished May 21 02:47:21 PM PDT 24
Peak memory 223152 kb
Host smart-8b8eb1a8-afa2-4b05-b79d-25b94c08519d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610290429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.610290429
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1159586809
Short name T856
Test name
Test status
Simulation time 2261927042 ps
CPU time 3.01 seconds
Started May 21 02:47:20 PM PDT 24
Finished May 21 02:47:26 PM PDT 24
Peak memory 205120 kb
Host smart-564be415-a12d-4cf6-8a76-e76b925e07bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159586809 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1159586809
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.4208210493
Short name T778
Test name
Test status
Simulation time 10057823462 ps
CPU time 76.88 seconds
Started May 21 02:47:16 PM PDT 24
Finished May 21 02:48:35 PM PDT 24
Peak memory 507980 kb
Host smart-a0539e2f-8f59-4056-a349-ce6845226e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208210493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.4208210493
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1337340760
Short name T461
Test name
Test status
Simulation time 10050611686 ps
CPU time 77.4 seconds
Started May 21 02:47:14 PM PDT 24
Finished May 21 02:48:33 PM PDT 24
Peak memory 486784 kb
Host smart-cc9d308b-f97b-4a89-b36c-c9bd6078e8f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337340760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1337340760
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2835109569
Short name T630
Test name
Test status
Simulation time 376125932 ps
CPU time 2.45 seconds
Started May 21 02:47:21 PM PDT 24
Finished May 21 02:47:25 PM PDT 24
Peak memory 205076 kb
Host smart-50af1e62-6402-419c-929d-22e15ba66c0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835109569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2835109569
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.598480243
Short name T387
Test name
Test status
Simulation time 4885673127 ps
CPU time 3.38 seconds
Started May 21 02:47:15 PM PDT 24
Finished May 21 02:47:20 PM PDT 24
Peak memory 205132 kb
Host smart-52837ae5-c526-4d78-b5d1-c5ddbd624cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598480243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.598480243
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2287934978
Short name T1071
Test name
Test status
Simulation time 3558513868 ps
CPU time 6.14 seconds
Started May 21 02:47:14 PM PDT 24
Finished May 21 02:47:22 PM PDT 24
Peak memory 350016 kb
Host smart-9e058d80-a28d-4545-86d0-71aa8e3ed5b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287934978 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2287934978
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3438753941
Short name T777
Test name
Test status
Simulation time 3056080724 ps
CPU time 9.44 seconds
Started May 21 02:47:16 PM PDT 24
Finished May 21 02:47:27 PM PDT 24
Peak memory 205068 kb
Host smart-fcaf4cee-7e2b-4159-ad56-0891ff0db94c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438753941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3438753941
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.624569617
Short name T882
Test name
Test status
Simulation time 3648396296 ps
CPU time 17.58 seconds
Started May 21 02:47:16 PM PDT 24
Finished May 21 02:47:35 PM PDT 24
Peak memory 217344 kb
Host smart-6f71015c-e13b-41d8-9b44-65ee50621bd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624569617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.624569617
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.774454823
Short name T949
Test name
Test status
Simulation time 20488828544 ps
CPU time 42.26 seconds
Started May 21 02:47:16 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 310684 kb
Host smart-296f6616-fb64-4d1b-a849-52a277cd74e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774454823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.774454823
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2491223147
Short name T264
Test name
Test status
Simulation time 16690682374 ps
CPU time 271.63 seconds
Started May 21 02:47:14 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 1024304 kb
Host smart-281cc047-a027-4145-b0be-a88dcba25ed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491223147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2491223147
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1873000372
Short name T546
Test name
Test status
Simulation time 1652197826 ps
CPU time 6.48 seconds
Started May 21 02:47:15 PM PDT 24
Finished May 21 02:47:23 PM PDT 24
Peak memory 219520 kb
Host smart-d9036a65-e6f9-4780-a731-c52e9dbfcb07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873000372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1873000372
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.4143510228
Short name T341
Test name
Test status
Simulation time 18467993 ps
CPU time 0.66 seconds
Started May 21 02:51:39 PM PDT 24
Finished May 21 02:51:42 PM PDT 24
Peak memory 204624 kb
Host smart-164831b6-c563-4e2c-9ffb-449cdb3b0694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143510228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4143510228
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2138328982
Short name T577
Test name
Test status
Simulation time 221232548 ps
CPU time 3.22 seconds
Started May 21 02:51:36 PM PDT 24
Finished May 21 02:51:41 PM PDT 24
Peak memory 213308 kb
Host smart-7093a356-8a22-4d6c-8b47-5ed5cd9776ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138328982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2138328982
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1288321416
Short name T785
Test name
Test status
Simulation time 3125769039 ps
CPU time 7.09 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:51:45 PM PDT 24
Peak memory 272680 kb
Host smart-fc9701c6-399f-4f02-91da-d6dc1f822499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288321416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1288321416
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2404352751
Short name T948
Test name
Test status
Simulation time 1801354934 ps
CPU time 122.14 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:53:38 PM PDT 24
Peak memory 557240 kb
Host smart-02d99169-7d3b-45e6-9536-f689a1216f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404352751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2404352751
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2448831091
Short name T139
Test name
Test status
Simulation time 3640875584 ps
CPU time 136.73 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:53:55 PM PDT 24
Peak memory 649656 kb
Host smart-0c81ddd0-b781-432c-8d8f-09a7cf243bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448831091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2448831091
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.236443584
Short name T1104
Test name
Test status
Simulation time 91518437 ps
CPU time 1.02 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:51:38 PM PDT 24
Peak memory 204968 kb
Host smart-d109b86a-4384-4be2-8ff8-cc453c950798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236443584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.236443584
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.550717961
Short name T1028
Test name
Test status
Simulation time 217229570 ps
CPU time 11.75 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:51:50 PM PDT 24
Peak memory 243864 kb
Host smart-1887bdab-9de0-4868-8df7-f020ec6252da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550717961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
550717961
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2551904805
Short name T102
Test name
Test status
Simulation time 14032485193 ps
CPU time 76.84 seconds
Started May 21 02:51:32 PM PDT 24
Finished May 21 02:52:50 PM PDT 24
Peak memory 975176 kb
Host smart-ca89a8a1-5d7b-4f4a-9803-3b657e84233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551904805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2551904805
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2918015698
Short name T508
Test name
Test status
Simulation time 713226027 ps
CPU time 3.5 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:51:46 PM PDT 24
Peak memory 205000 kb
Host smart-b3f67177-1ebc-410d-820e-27e652d96eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918015698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2918015698
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1376756323
Short name T1006
Test name
Test status
Simulation time 38063254037 ps
CPU time 33.36 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 386724 kb
Host smart-c74c4a7e-0bbf-4cbb-b014-846976adfd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376756323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1376756323
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.683933590
Short name T415
Test name
Test status
Simulation time 28086494 ps
CPU time 0.68 seconds
Started May 21 02:51:30 PM PDT 24
Finished May 21 02:51:33 PM PDT 24
Peak memory 204700 kb
Host smart-32b184e2-fca0-4ee4-90dc-be869eea094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683933590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.683933590
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2676759636
Short name T1145
Test name
Test status
Simulation time 19338999464 ps
CPU time 212.16 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 250404 kb
Host smart-5c1c3791-15a2-4453-9c42-2a2bbe71d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676759636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2676759636
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3547091589
Short name T472
Test name
Test status
Simulation time 2023978370 ps
CPU time 23.31 seconds
Started May 21 02:51:29 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 319916 kb
Host smart-0253afd2-5c00-402b-bf5b-23f17cc87532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547091589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3547091589
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3379139790
Short name T240
Test name
Test status
Simulation time 59417855384 ps
CPU time 581.46 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 03:01:17 PM PDT 24
Peak memory 761308 kb
Host smart-c552e8b1-8d39-4ddc-89d9-7ab14b6af4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379139790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3379139790
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.463563840
Short name T755
Test name
Test status
Simulation time 653270248 ps
CPU time 9.95 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 218960 kb
Host smart-746f89d7-35b4-4e2f-b8f9-dc4dd6dd1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463563840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.463563840
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2939493557
Short name T738
Test name
Test status
Simulation time 807197212 ps
CPU time 3.92 seconds
Started May 21 02:51:38 PM PDT 24
Finished May 21 02:51:44 PM PDT 24
Peak memory 213188 kb
Host smart-c9210739-fc08-4b31-9dff-53eea3b38c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939493557 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2939493557
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.4249673991
Short name T756
Test name
Test status
Simulation time 10043832937 ps
CPU time 74.06 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 425276 kb
Host smart-abbd4017-f50d-4e6e-9b8d-98d83d948811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249673991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.4249673991
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3974681373
Short name T527
Test name
Test status
Simulation time 10067578015 ps
CPU time 70.17 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:52:48 PM PDT 24
Peak memory 449940 kb
Host smart-29a93d37-7c5f-4ae2-9762-dbd926dac2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974681373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3974681373
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.113345001
Short name T14
Test name
Test status
Simulation time 1477707171 ps
CPU time 2.29 seconds
Started May 21 02:51:39 PM PDT 24
Finished May 21 02:51:43 PM PDT 24
Peak memory 204992 kb
Host smart-95a5b195-531e-4311-94d2-1f860776168d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113345001 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.113345001
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.961647613
Short name T261
Test name
Test status
Simulation time 754901057 ps
CPU time 4.55 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:51:41 PM PDT 24
Peak memory 204924 kb
Host smart-b577967f-301e-4177-9bfb-9a8c7b773f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961647613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.961647613
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3034336352
Short name T915
Test name
Test status
Simulation time 13885504345 ps
CPU time 264.04 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:56:02 PM PDT 24
Peak memory 3383676 kb
Host smart-d907478e-9869-4651-9c1e-0b497d46358f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034336352 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3034336352
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2888551950
Short name T447
Test name
Test status
Simulation time 876217182 ps
CPU time 12.69 seconds
Started May 21 02:51:33 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 205000 kb
Host smart-c9515446-7214-4645-97a8-1383a828910c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888551950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2888551950
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2642273515
Short name T808
Test name
Test status
Simulation time 837581643 ps
CPU time 33.83 seconds
Started May 21 02:51:35 PM PDT 24
Finished May 21 02:52:12 PM PDT 24
Peak memory 204964 kb
Host smart-c1057a83-ade6-41ae-a704-56aa01183b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642273515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2642273515
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2819901642
Short name T1324
Test name
Test status
Simulation time 25636218420 ps
CPU time 95 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:53:11 PM PDT 24
Peak memory 1371464 kb
Host smart-aa42ad83-6239-4a8f-bc6d-95628f52a28e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819901642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2819901642
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2365651076
Short name T29
Test name
Test status
Simulation time 25308802881 ps
CPU time 1474.06 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 03:16:10 PM PDT 24
Peak memory 6137388 kb
Host smart-c8e44423-4995-493a-bf93-be8a902f0806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365651076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2365651076
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.100819078
Short name T1019
Test name
Test status
Simulation time 8161344465 ps
CPU time 7.2 seconds
Started May 21 02:51:34 PM PDT 24
Finished May 21 02:51:44 PM PDT 24
Peak memory 221064 kb
Host smart-0144a8fd-23b1-4d65-aac2-da0f8c485aff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100819078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.100819078
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1831046251
Short name T151
Test name
Test status
Simulation time 61345847 ps
CPU time 0.63 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 02:51:50 PM PDT 24
Peak memory 204648 kb
Host smart-199db69e-94ad-42c0-a8ac-2ff507f949ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831046251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1831046251
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2008449435
Short name T1314
Test name
Test status
Simulation time 172470779 ps
CPU time 5.07 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 213252 kb
Host smart-aebd5a99-add8-4fee-b6f8-9368363b89f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008449435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2008449435
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3231593753
Short name T1087
Test name
Test status
Simulation time 627121676 ps
CPU time 16.43 seconds
Started May 21 02:51:39 PM PDT 24
Finished May 21 02:51:58 PM PDT 24
Peak memory 271904 kb
Host smart-6a893330-1a71-4bb3-9fc7-7ea1bc787acd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231593753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3231593753
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1615668929
Short name T85
Test name
Test status
Simulation time 7358082716 ps
CPU time 57.97 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:52:41 PM PDT 24
Peak memory 545256 kb
Host smart-7aa5e2d4-1a74-49c1-af80-d9c00c92dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615668929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1615668929
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3485438362
Short name T315
Test name
Test status
Simulation time 2191975826 ps
CPU time 80.2 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:53:03 PM PDT 24
Peak memory 748336 kb
Host smart-d22c3e0d-4e8a-4d65-b158-1da230f44434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485438362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3485438362
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3875274082
Short name T1256
Test name
Test status
Simulation time 294965483 ps
CPU time 0.87 seconds
Started May 21 02:51:42 PM PDT 24
Finished May 21 02:51:45 PM PDT 24
Peak memory 204780 kb
Host smart-48f7a276-4c9d-411f-ae24-c9159a8fc0fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875274082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3875274082
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1962718880
Short name T1317
Test name
Test status
Simulation time 169031439 ps
CPU time 9.2 seconds
Started May 21 02:51:38 PM PDT 24
Finished May 21 02:51:49 PM PDT 24
Peak memory 233472 kb
Host smart-c1174f95-c280-47ea-8299-2cd1690e92ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962718880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1962718880
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3506053527
Short name T241
Test name
Test status
Simulation time 5151685996 ps
CPU time 422.1 seconds
Started May 21 02:51:42 PM PDT 24
Finished May 21 02:58:47 PM PDT 24
Peak memory 1451536 kb
Host smart-0c392eea-f357-43a2-b98d-25b7e97f9885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506053527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3506053527
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3533136947
Short name T1147
Test name
Test status
Simulation time 317600785 ps
CPU time 4.14 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 02:51:53 PM PDT 24
Peak memory 205016 kb
Host smart-edcaec64-f9c9-4d24-a88a-af338fd88338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533136947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3533136947
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2417518662
Short name T857
Test name
Test status
Simulation time 3387993987 ps
CPU time 78.22 seconds
Started May 21 02:51:47 PM PDT 24
Finished May 21 02:53:08 PM PDT 24
Peak memory 310476 kb
Host smart-9cdcb819-8933-48f6-b4e1-94e56a08c88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417518662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2417518662
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1389281713
Short name T258
Test name
Test status
Simulation time 54439891 ps
CPU time 0.65 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:51:44 PM PDT 24
Peak memory 204696 kb
Host smart-95a3168b-0229-4cb7-a7bb-c14f0593dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389281713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1389281713
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.4220585815
Short name T1093
Test name
Test status
Simulation time 6146188658 ps
CPU time 218.19 seconds
Started May 21 02:51:38 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 931988 kb
Host smart-89693a57-eea9-49ef-b719-492b9c22615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220585815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.4220585815
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3493832817
Short name T586
Test name
Test status
Simulation time 1821243369 ps
CPU time 83.48 seconds
Started May 21 02:51:39 PM PDT 24
Finished May 21 02:53:04 PM PDT 24
Peak memory 318548 kb
Host smart-dc1ad4e3-3f2c-4b22-bb5a-2c5fcb4adf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493832817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3493832817
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1696667362
Short name T1321
Test name
Test status
Simulation time 690475103 ps
CPU time 12.24 seconds
Started May 21 02:51:40 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 215292 kb
Host smart-7181423a-d65e-425d-8529-7fba2ed94c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696667362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1696667362
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2668380941
Short name T474
Test name
Test status
Simulation time 2114337095 ps
CPU time 5.51 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 213164 kb
Host smart-c4fcb136-b01a-4c90-b034-37c936f5b6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668380941 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2668380941
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1700013187
Short name T513
Test name
Test status
Simulation time 10162169457 ps
CPU time 14.75 seconds
Started May 21 02:51:44 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 275776 kb
Host smart-0a80adac-b43e-4449-a7f1-f5d878228cc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700013187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1700013187
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2277823099
Short name T143
Test name
Test status
Simulation time 10077742562 ps
CPU time 68.15 seconds
Started May 21 02:51:47 PM PDT 24
Finished May 21 02:52:58 PM PDT 24
Peak memory 453500 kb
Host smart-fa57621b-626c-456d-93d2-e303a41f38c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277823099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2277823099
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.870833615
Short name T265
Test name
Test status
Simulation time 354244022 ps
CPU time 2.51 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 02:51:52 PM PDT 24
Peak memory 205044 kb
Host smart-fbc4429d-c671-4874-b467-5982cc6a49e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870833615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.870833615
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3960625043
Short name T231
Test name
Test status
Simulation time 2642694508 ps
CPU time 3.83 seconds
Started May 21 02:51:45 PM PDT 24
Finished May 21 02:51:52 PM PDT 24
Peak memory 205112 kb
Host smart-c608c6e0-222f-492c-bf33-614d3d8169b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960625043 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3960625043
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1497742534
Short name T965
Test name
Test status
Simulation time 17521305593 ps
CPU time 237.34 seconds
Started May 21 02:51:47 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 2615344 kb
Host smart-8a6aed33-41c0-46ab-9631-47f525884c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497742534 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1497742534
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.721763711
Short name T145
Test name
Test status
Simulation time 1239038345 ps
CPU time 20.05 seconds
Started May 21 02:51:48 PM PDT 24
Finished May 21 02:52:10 PM PDT 24
Peak memory 205008 kb
Host smart-cf6f77da-f6d5-4a5f-a77a-a66380121dcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721763711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.721763711
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.541893117
Short name T257
Test name
Test status
Simulation time 846058938 ps
CPU time 7.01 seconds
Started May 21 02:51:47 PM PDT 24
Finished May 21 02:51:56 PM PDT 24
Peak memory 205900 kb
Host smart-bd96a7c8-3712-41ca-9c45-56e75682876a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541893117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.541893117
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.4232692951
Short name T1341
Test name
Test status
Simulation time 52802795142 ps
CPU time 196.71 seconds
Started May 21 02:51:46 PM PDT 24
Finished May 21 02:55:06 PM PDT 24
Peak memory 2150312 kb
Host smart-7ae291d2-7aff-4559-9d73-439540a81ff3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232692951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.4232692951
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1314278088
Short name T1117
Test name
Test status
Simulation time 11616437693 ps
CPU time 938.84 seconds
Started May 21 02:51:44 PM PDT 24
Finished May 21 03:07:26 PM PDT 24
Peak memory 2147324 kb
Host smart-a215247a-3bbb-4c15-aa02-b2537352d6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314278088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1314278088
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.740142662
Short name T429
Test name
Test status
Simulation time 5506664574 ps
CPU time 6.99 seconds
Started May 21 02:51:49 PM PDT 24
Finished May 21 02:51:58 PM PDT 24
Peak memory 221452 kb
Host smart-4274a920-bee1-4f9d-b469-9c4c8d745423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740142662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.740142662
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1473219048
Short name T1182
Test name
Test status
Simulation time 27405813 ps
CPU time 0.62 seconds
Started May 21 02:51:56 PM PDT 24
Finished May 21 02:51:58 PM PDT 24
Peak memory 204588 kb
Host smart-26939441-d181-49bc-bd05-493a467cc60d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473219048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1473219048
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1366514508
Short name T579
Test name
Test status
Simulation time 187212754 ps
CPU time 6.25 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 213232 kb
Host smart-f0f40eb0-12d3-4720-b809-282b750d32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366514508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1366514508
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1925320790
Short name T404
Test name
Test status
Simulation time 1582395889 ps
CPU time 20.29 seconds
Started May 21 02:51:53 PM PDT 24
Finished May 21 02:52:15 PM PDT 24
Peak memory 291380 kb
Host smart-135e2fde-f92d-4b22-8664-555dda220add
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925320790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1925320790
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1746643170
Short name T351
Test name
Test status
Simulation time 28003804169 ps
CPU time 151.24 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 692732 kb
Host smart-4b96ae89-644c-481d-a275-5aa569a18f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746643170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1746643170
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.494013593
Short name T1240
Test name
Test status
Simulation time 4154159890 ps
CPU time 73.28 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:53:06 PM PDT 24
Peak memory 710688 kb
Host smart-9ed83c0d-fea3-47b7-aa8c-5145fed9f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494013593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.494013593
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.219687340
Short name T752
Test name
Test status
Simulation time 112730690 ps
CPU time 0.92 seconds
Started May 21 02:51:53 PM PDT 24
Finished May 21 02:51:56 PM PDT 24
Peak memory 204760 kb
Host smart-536884a6-49cb-4aa9-9227-7aa30ffb65e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219687340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.219687340
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.49237474
Short name T200
Test name
Test status
Simulation time 159196344 ps
CPU time 9.17 seconds
Started May 21 02:51:53 PM PDT 24
Finished May 21 02:52:04 PM PDT 24
Peak memory 234020 kb
Host smart-6edcbcf9-590b-4012-b41c-8c8aa17a36db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49237474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.49237474
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1832717530
Short name T837
Test name
Test status
Simulation time 4205049455 ps
CPU time 315.39 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:57:10 PM PDT 24
Peak memory 1207884 kb
Host smart-8b5fd185-4315-490a-89da-16864cc0d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832717530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1832717530
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.542927239
Short name T676
Test name
Test status
Simulation time 2817319815 ps
CPU time 7.46 seconds
Started May 21 02:51:58 PM PDT 24
Finished May 21 02:52:07 PM PDT 24
Peak memory 205124 kb
Host smart-af601095-35a9-412f-855d-14cd7a850021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542927239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.542927239
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2168055057
Short name T816
Test name
Test status
Simulation time 1374627956 ps
CPU time 64.24 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:53:03 PM PDT 24
Peak memory 365432 kb
Host smart-5621491b-3d97-4407-bb4b-a2470ff589e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168055057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2168055057
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3820199828
Short name T293
Test name
Test status
Simulation time 146730646 ps
CPU time 0.66 seconds
Started May 21 02:51:44 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 204712 kb
Host smart-e706857e-c8bb-432b-a946-3ad62c8e75d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820199828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3820199828
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3677763891
Short name T1049
Test name
Test status
Simulation time 12838888672 ps
CPU time 122.14 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 213312 kb
Host smart-da89575e-11e3-42b3-b385-229707dbafa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677763891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3677763891
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3128666945
Short name T590
Test name
Test status
Simulation time 5709245108 ps
CPU time 58.49 seconds
Started May 21 02:51:44 PM PDT 24
Finished May 21 02:52:45 PM PDT 24
Peak memory 269888 kb
Host smart-f82c66f5-ac47-451a-ae85-2b389d830696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128666945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3128666945
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.321508349
Short name T530
Test name
Test status
Simulation time 7919854450 ps
CPU time 769.24 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 03:04:44 PM PDT 24
Peak memory 1518504 kb
Host smart-a47c983e-3dbf-4276-b712-8be00130a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321508349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.321508349
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3217457881
Short name T1244
Test name
Test status
Simulation time 444752737 ps
CPU time 15.71 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:52:10 PM PDT 24
Peak memory 213216 kb
Host smart-d11d9e21-d426-4849-a9f5-35fd8e813be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217457881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3217457881
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2820907270
Short name T405
Test name
Test status
Simulation time 923054207 ps
CPU time 4.83 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:04 PM PDT 24
Peak memory 213228 kb
Host smart-a9fcf06b-d3a3-4600-bb52-638b38e3bc68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820907270 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2820907270
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1885365196
Short name T1257
Test name
Test status
Simulation time 10102426390 ps
CPU time 69.48 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:53:04 PM PDT 24
Peak memory 488852 kb
Host smart-8fbee2ef-3653-499b-8f07-d513f2d3d9ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885365196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1885365196
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2046335774
Short name T719
Test name
Test status
Simulation time 10212342076 ps
CPU time 15.02 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:52:07 PM PDT 24
Peak memory 288968 kb
Host smart-c129c4a1-090e-4316-a2ef-fc795376fffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046335774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2046335774
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3820284544
Short name T160
Test name
Test status
Simulation time 1523662409 ps
CPU time 2.55 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:02 PM PDT 24
Peak memory 205064 kb
Host smart-e2258a6c-9804-4556-b5e4-71fece45c537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820284544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3820284544
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2262206139
Short name T608
Test name
Test status
Simulation time 3611611903 ps
CPU time 6.36 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:52:00 PM PDT 24
Peak memory 213292 kb
Host smart-6f5f0af1-2836-4e5a-ae8d-bcb27d866169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262206139 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2262206139
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2462393064
Short name T383
Test name
Test status
Simulation time 6207679174 ps
CPU time 4.98 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:51:58 PM PDT 24
Peak memory 205136 kb
Host smart-bed5b5c4-a69d-4119-b32c-e281511670b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462393064 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2462393064
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3909098580
Short name T268
Test name
Test status
Simulation time 2389889240 ps
CPU time 8.27 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:52:00 PM PDT 24
Peak memory 205120 kb
Host smart-0b6b67ed-54b5-454f-b7f5-1e4a8003aec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909098580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3909098580
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3128047967
Short name T372
Test name
Test status
Simulation time 1124953168 ps
CPU time 10.52 seconds
Started May 21 02:51:53 PM PDT 24
Finished May 21 02:52:06 PM PDT 24
Peak memory 206576 kb
Host smart-feb91eab-c32e-4010-a24a-2f90032ebe7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128047967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3128047967
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1635276714
Short name T493
Test name
Test status
Simulation time 56130614523 ps
CPU time 508.82 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 03:00:24 PM PDT 24
Peak memory 4446472 kb
Host smart-56a8e977-627d-4fb2-b62f-7bb7d6904d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635276714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1635276714
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.289725813
Short name T848
Test name
Test status
Simulation time 9060713185 ps
CPU time 62.61 seconds
Started May 21 02:51:51 PM PDT 24
Finished May 21 02:52:56 PM PDT 24
Peak memory 472052 kb
Host smart-c45974a6-6851-444c-94ef-59301889456c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289725813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.289725813
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2549259332
Short name T654
Test name
Test status
Simulation time 4162952405 ps
CPU time 6.32 seconds
Started May 21 02:51:52 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 220524 kb
Host smart-80947ad1-0203-4100-9944-e00ee93c6234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549259332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2549259332
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.646826390
Short name T457
Test name
Test status
Simulation time 20141538 ps
CPU time 0.63 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:52:07 PM PDT 24
Peak memory 204676 kb
Host smart-9f13d31f-5958-46d4-8fbd-44ea333a62c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646826390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.646826390
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1320797782
Short name T499
Test name
Test status
Simulation time 142975005 ps
CPU time 4.03 seconds
Started May 21 02:51:58 PM PDT 24
Finished May 21 02:52:04 PM PDT 24
Peak memory 213312 kb
Host smart-179e929b-0164-4596-a0fd-96fb63ce0500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320797782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1320797782
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1316931124
Short name T1036
Test name
Test status
Simulation time 246021144 ps
CPU time 11.8 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:11 PM PDT 24
Peak memory 233204 kb
Host smart-ea19bb70-457b-4796-9415-1f3dbedd7d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316931124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1316931124
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.116543297
Short name T489
Test name
Test status
Simulation time 2343381379 ps
CPU time 81.2 seconds
Started May 21 02:51:58 PM PDT 24
Finished May 21 02:53:21 PM PDT 24
Peak memory 753756 kb
Host smart-f8c44598-6353-4c31-a5f2-339cda24df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116543297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.116543297
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1187437919
Short name T790
Test name
Test status
Simulation time 1958260055 ps
CPU time 57.56 seconds
Started May 21 02:52:00 PM PDT 24
Finished May 21 02:52:59 PM PDT 24
Peak memory 691772 kb
Host smart-386de74c-8230-406d-aab0-6442bb61a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187437919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1187437919
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.845830155
Short name T1217
Test name
Test status
Simulation time 113464057 ps
CPU time 0.97 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:00 PM PDT 24
Peak memory 204780 kb
Host smart-0d2e7835-72ca-4461-a4fa-6fcc3e931d5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845830155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.845830155
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.4192761218
Short name T482
Test name
Test status
Simulation time 127651658 ps
CPU time 2.67 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:02 PM PDT 24
Peak memory 205064 kb
Host smart-366c525b-ee5f-4144-b36e-3af15b3465db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192761218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.4192761218
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3141397328
Short name T1041
Test name
Test status
Simulation time 16531591549 ps
CPU time 247.29 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:56:07 PM PDT 24
Peak memory 1081812 kb
Host smart-192b65d1-fb01-49bb-ba7f-8b4c2018eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141397328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3141397328
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2979840948
Short name T784
Test name
Test status
Simulation time 238649513 ps
CPU time 9.05 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:52:15 PM PDT 24
Peak memory 205016 kb
Host smart-dbc3e623-25e4-405f-b6ab-d71ae4adf3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979840948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2979840948
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1214342691
Short name T1224
Test name
Test status
Simulation time 1927784644 ps
CPU time 93.36 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:53:40 PM PDT 24
Peak memory 309996 kb
Host smart-18f01bf8-524f-41dc-9619-068ecfb037cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214342691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1214342691
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3300273797
Short name T847
Test name
Test status
Simulation time 15996226 ps
CPU time 0.7 seconds
Started May 21 02:51:58 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 204712 kb
Host smart-b9cb2b04-e0f0-4ea0-b16d-f7588517a597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300273797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3300273797
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1889004008
Short name T881
Test name
Test status
Simulation time 3145083010 ps
CPU time 126.99 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:54:06 PM PDT 24
Peak memory 213344 kb
Host smart-2e62664c-3f5b-4260-ab15-ab9dfb2647aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889004008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1889004008
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.529395401
Short name T163
Test name
Test status
Simulation time 3854759342 ps
CPU time 96.61 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:53:35 PM PDT 24
Peak memory 405608 kb
Host smart-aa00f428-5695-47d3-8ba0-ad89c85e40e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529395401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.529395401
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1813523620
Short name T1237
Test name
Test status
Simulation time 17649533945 ps
CPU time 2861.69 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 03:39:41 PM PDT 24
Peak memory 4099524 kb
Host smart-e92578a0-c2e9-4fc0-ab6a-eeccdc53697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813523620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1813523620
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.3511650894
Short name T352
Test name
Test status
Simulation time 10119289550 ps
CPU time 16.87 seconds
Started May 21 02:51:57 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 229588 kb
Host smart-e6831653-60a3-48db-9744-2503f73d943e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511650894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3511650894
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2478173034
Short name T1155
Test name
Test status
Simulation time 836680337 ps
CPU time 2.59 seconds
Started May 21 02:52:07 PM PDT 24
Finished May 21 02:52:11 PM PDT 24
Peak memory 205024 kb
Host smart-011dcb1b-8bfe-4108-9283-5a84840c3632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478173034 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2478173034
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.4190976231
Short name T1103
Test name
Test status
Simulation time 10103864745 ps
CPU time 15.27 seconds
Started May 21 02:52:03 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 260288 kb
Host smart-5c3423e5-18c0-42d0-8eae-130ff98b4962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190976231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.4190976231
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1354198244
Short name T78
Test name
Test status
Simulation time 10386954368 ps
CPU time 13.72 seconds
Started May 21 02:52:02 PM PDT 24
Finished May 21 02:52:17 PM PDT 24
Peak memory 282020 kb
Host smart-56e296aa-7147-4106-8d8f-7d408e59bc83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354198244 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1354198244
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3865729475
Short name T737
Test name
Test status
Simulation time 8472924004 ps
CPU time 3.16 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:52:09 PM PDT 24
Peak memory 205164 kb
Host smart-fe192f99-18e9-47a5-a66c-ed435a7321df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865729475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3865729475
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3516674923
Short name T970
Test name
Test status
Simulation time 3784533457 ps
CPU time 4.7 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:52:11 PM PDT 24
Peak memory 205116 kb
Host smart-eaf070dd-6350-47c8-98f5-9a66440d522c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516674923 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3516674923
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2377701754
Short name T677
Test name
Test status
Simulation time 26649057165 ps
CPU time 83.91 seconds
Started May 21 02:52:06 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 1575964 kb
Host smart-84859f2f-f78f-4259-b484-f6e3a74e50de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377701754 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2377701754
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3848727647
Short name T1112
Test name
Test status
Simulation time 2961523789 ps
CPU time 36.27 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 205144 kb
Host smart-ce60c80a-6e9f-4bd5-b928-2cf6fd4c28e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848727647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3848727647
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2908119595
Short name T273
Test name
Test status
Simulation time 1363452124 ps
CPU time 59.4 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:53:06 PM PDT 24
Peak memory 207008 kb
Host smart-76e226af-d2bf-4cfb-aa77-d9573a0f7f7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908119595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2908119595
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1012651277
Short name T326
Test name
Test status
Simulation time 22900602956 ps
CPU time 14.14 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:52:21 PM PDT 24
Peak memory 227444 kb
Host smart-2ad35360-4b9f-4edd-9037-5337c2f136de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012651277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1012651277
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2444505382
Short name T911
Test name
Test status
Simulation time 15305622737 ps
CPU time 56.02 seconds
Started May 21 02:52:03 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 719172 kb
Host smart-341f1aba-87ff-47ca-8091-fdc29b4ddede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444505382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2444505382
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3048319161
Short name T941
Test name
Test status
Simulation time 2253886571 ps
CPU time 6.3 seconds
Started May 21 02:52:06 PM PDT 24
Finished May 21 02:52:14 PM PDT 24
Peak memory 213364 kb
Host smart-aa98cf17-68a6-4a54-b69f-f45d8ace397a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048319161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3048319161
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1166025506
Short name T335
Test name
Test status
Simulation time 36448276 ps
CPU time 0.61 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:52:17 PM PDT 24
Peak memory 204588 kb
Host smart-c8201307-9dc0-43c7-80e5-9b7a290246b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166025506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1166025506
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.676049345
Short name T425
Test name
Test status
Simulation time 128242434 ps
CPU time 1.87 seconds
Started May 21 02:52:11 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 213284 kb
Host smart-1b937706-f65e-423a-a7ff-d9ec976b294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676049345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.676049345
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.4114411395
Short name T65
Test name
Test status
Simulation time 1328208364 ps
CPU time 18.69 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:52:26 PM PDT 24
Peak memory 273848 kb
Host smart-8e9fe3d3-b7e9-4a05-9d2d-401084cea363
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114411395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.4114411395
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1329584403
Short name T972
Test name
Test status
Simulation time 2160654951 ps
CPU time 43.2 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:52:49 PM PDT 24
Peak memory 570628 kb
Host smart-53716672-431e-4653-92e6-79ae36cedd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329584403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1329584403
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1553197579
Short name T602
Test name
Test status
Simulation time 1849609788 ps
CPU time 51.77 seconds
Started May 21 02:52:08 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 616560 kb
Host smart-2e91d450-5b1a-4750-b968-318a71a6d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553197579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1553197579
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3967521718
Short name T894
Test name
Test status
Simulation time 151502479 ps
CPU time 0.87 seconds
Started May 21 02:52:03 PM PDT 24
Finished May 21 02:52:06 PM PDT 24
Peak memory 204780 kb
Host smart-b2b7c567-a27b-4d22-89cf-8f9c15fe6f00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967521718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3967521718
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.4080433477
Short name T1137
Test name
Test status
Simulation time 125513751 ps
CPU time 2.84 seconds
Started May 21 02:52:05 PM PDT 24
Finished May 21 02:52:09 PM PDT 24
Peak memory 205016 kb
Host smart-b95dc55c-f70e-4bee-8f84-9f060fe2537b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080433477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.4080433477
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.517269683
Short name T1298
Test name
Test status
Simulation time 25103236777 ps
CPU time 161.47 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:54:47 PM PDT 24
Peak memory 1394264 kb
Host smart-eaaeca70-9e90-4e31-bfc5-8e87b9266af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517269683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.517269683
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.4160520681
Short name T1334
Test name
Test status
Simulation time 526032806 ps
CPU time 8.27 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:52:20 PM PDT 24
Peak memory 205000 kb
Host smart-7e749a17-d46e-4a17-89e2-1624e7d1ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160520681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.4160520681
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4125860164
Short name T1228
Test name
Test status
Simulation time 1586845246 ps
CPU time 35.09 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:52:46 PM PDT 24
Peak memory 375648 kb
Host smart-30f7e969-df02-40d3-bb2b-7e25d53d87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125860164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4125860164
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.675049301
Short name T122
Test name
Test status
Simulation time 49339574 ps
CPU time 0.75 seconds
Started May 21 02:52:04 PM PDT 24
Finished May 21 02:52:07 PM PDT 24
Peak memory 204652 kb
Host smart-78914ad5-88b8-4671-a50b-12a87f5a6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675049301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.675049301
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3523115396
Short name T448
Test name
Test status
Simulation time 2797582837 ps
CPU time 35.37 seconds
Started May 21 02:52:03 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 229620 kb
Host smart-a0c4af00-85f7-48ea-ac19-b7db075e4167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523115396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3523115396
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.4090795048
Short name T986
Test name
Test status
Simulation time 1610548076 ps
CPU time 31.14 seconds
Started May 21 02:52:03 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 349068 kb
Host smart-4ab4e9c4-ff83-4f59-80cb-bec4f5f7b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090795048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.4090795048
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1799665632
Short name T773
Test name
Test status
Simulation time 1040721169 ps
CPU time 23.72 seconds
Started May 21 02:52:06 PM PDT 24
Finished May 21 02:52:31 PM PDT 24
Peak memory 213176 kb
Host smart-fd2b44f2-9ecf-4a1c-b6b8-dee247f5277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799665632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1799665632
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.758411445
Short name T267
Test name
Test status
Simulation time 2767115581 ps
CPU time 3.62 seconds
Started May 21 02:52:10 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 205172 kb
Host smart-ab756d39-39dd-465a-910a-e8164b71d6a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758411445 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.758411445
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.974446122
Short name T1175
Test name
Test status
Simulation time 10119204485 ps
CPU time 47.87 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 460628 kb
Host smart-40a82fbf-ad8a-44b6-9297-fd581d83c76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974446122 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.974446122
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.833894328
Short name T528
Test name
Test status
Simulation time 490519773 ps
CPU time 2.99 seconds
Started May 21 02:52:10 PM PDT 24
Finished May 21 02:52:16 PM PDT 24
Peak memory 205088 kb
Host smart-18fa27b5-8c00-4c4d-8bfa-07a7f7decd88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833894328 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.833894328
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1076547254
Short name T228
Test name
Test status
Simulation time 664911874 ps
CPU time 3.85 seconds
Started May 21 02:52:08 PM PDT 24
Finished May 21 02:52:13 PM PDT 24
Peak memory 204920 kb
Host smart-dc41dfbc-a910-46d2-ad14-cf300f0cadcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076547254 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1076547254
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.274833098
Short name T996
Test name
Test status
Simulation time 6124877871 ps
CPU time 4.64 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:52:15 PM PDT 24
Peak memory 205056 kb
Host smart-43d1add1-cf88-47be-8697-4c48d36348f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274833098 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.274833098
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.342914213
Short name T644
Test name
Test status
Simulation time 819202991 ps
CPU time 11.54 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:52:24 PM PDT 24
Peak memory 204968 kb
Host smart-a23b1651-5164-453a-8ab5-8efb9b1339eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342914213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.342914213
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.331208573
Short name T366
Test name
Test status
Simulation time 4006889467 ps
CPU time 39.57 seconds
Started May 21 02:52:10 PM PDT 24
Finished May 21 02:52:52 PM PDT 24
Peak memory 205144 kb
Host smart-b3be3526-b347-4410-bf67-1c15c29952f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331208573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.331208573
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.575956493
Short name T978
Test name
Test status
Simulation time 36512437662 ps
CPU time 57.78 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 02:53:09 PM PDT 24
Peak memory 1042712 kb
Host smart-1f0de18f-ea72-407f-b2f0-647e57210f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575956493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.575956493
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3221213469
Short name T327
Test name
Test status
Simulation time 29010841164 ps
CPU time 503.97 seconds
Started May 21 02:52:09 PM PDT 24
Finished May 21 03:00:36 PM PDT 24
Peak memory 3334792 kb
Host smart-ba84409c-63ea-42de-a6b2-18a27f4ffbdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221213469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3221213469
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.336761605
Short name T386
Test name
Test status
Simulation time 11039552582 ps
CPU time 7.81 seconds
Started May 21 02:52:10 PM PDT 24
Finished May 21 02:52:21 PM PDT 24
Peak memory 221496 kb
Host smart-604cff24-2ea1-493d-9b60-daf6d7fa9e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336761605 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.336761605
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2704093719
Short name T625
Test name
Test status
Simulation time 40388841 ps
CPU time 0.59 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:24 PM PDT 24
Peak memory 204624 kb
Host smart-b4c65915-5290-40f1-a105-af2c192b3e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704093719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2704093719
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1434725122
Short name T45
Test name
Test status
Simulation time 1292165754 ps
CPU time 5.23 seconds
Started May 21 02:52:16 PM PDT 24
Finished May 21 02:52:23 PM PDT 24
Peak memory 213328 kb
Host smart-44aad362-5a3a-4c3f-a79c-6581d547a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434725122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1434725122
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.4037524922
Short name T954
Test name
Test status
Simulation time 1996371095 ps
CPU time 19.6 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 279620 kb
Host smart-09229515-9bce-4380-9900-c5974ffd4fcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037524922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.4037524922
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1869177891
Short name T471
Test name
Test status
Simulation time 17314078647 ps
CPU time 57.99 seconds
Started May 21 02:52:17 PM PDT 24
Finished May 21 02:53:16 PM PDT 24
Peak memory 249756 kb
Host smart-90a733e4-d928-429e-bf41-5bde678414df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869177891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1869177891
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1859546610
Short name T765
Test name
Test status
Simulation time 4450037065 ps
CPU time 68.11 seconds
Started May 21 02:52:26 PM PDT 24
Finished May 21 02:53:37 PM PDT 24
Peak memory 757940 kb
Host smart-059bc214-075d-43b3-a0f3-a396b2aa0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859546610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1859546610
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1601673799
Short name T53
Test name
Test status
Simulation time 2297578504 ps
CPU time 1.04 seconds
Started May 21 02:52:18 PM PDT 24
Finished May 21 02:52:20 PM PDT 24
Peak memory 204896 kb
Host smart-9c8d4311-aa36-4522-93fb-2647e54030d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601673799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.1601673799
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.307458227
Short name T1125
Test name
Test status
Simulation time 134094660 ps
CPU time 3.36 seconds
Started May 21 02:52:16 PM PDT 24
Finished May 21 02:52:21 PM PDT 24
Peak memory 205048 kb
Host smart-ec9d4c20-8307-431a-886d-661c5ab99b9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307458227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.
307458227
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1676156647
Short name T133
Test name
Test status
Simulation time 4719334737 ps
CPU time 390.09 seconds
Started May 21 02:52:14 PM PDT 24
Finished May 21 02:58:45 PM PDT 24
Peak memory 1296360 kb
Host smart-59f7e072-9523-469e-b852-d14bd60d64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676156647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1676156647
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1620854884
Short name T211
Test name
Test status
Simulation time 938550366 ps
CPU time 19.83 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 02:52:44 PM PDT 24
Peak memory 205048 kb
Host smart-716350e1-a9fb-4f7c-a7f8-2bf61d3a5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620854884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1620854884
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2483739516
Short name T32
Test name
Test status
Simulation time 1354477864 ps
CPU time 50.6 seconds
Started May 21 02:52:19 PM PDT 24
Finished May 21 02:53:11 PM PDT 24
Peak memory 268348 kb
Host smart-fba728e2-03aa-44a4-8d09-2f139f7becd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483739516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2483739516
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.4282514760
Short name T1088
Test name
Test status
Simulation time 20853158 ps
CPU time 0.67 seconds
Started May 21 02:52:18 PM PDT 24
Finished May 21 02:52:20 PM PDT 24
Peak memory 204360 kb
Host smart-8b81da2c-b338-4db6-90e1-be20a9458675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282514760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.4282514760
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.70920101
Short name T516
Test name
Test status
Simulation time 17747864564 ps
CPU time 218.41 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:55:54 PM PDT 24
Peak memory 902348 kb
Host smart-03f14079-5237-48e0-8441-8f961fad544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70920101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.70920101
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.4043853327
Short name T1234
Test name
Test status
Simulation time 32647296080 ps
CPU time 93.53 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:53:50 PM PDT 24
Peak memory 405348 kb
Host smart-69518f84-b107-4112-81ed-97944e0def94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043853327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4043853327
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.159771464
Short name T50
Test name
Test status
Simulation time 41390154975 ps
CPU time 1131.71 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 03:11:09 PM PDT 24
Peak memory 3834032 kb
Host smart-45da622c-040f-4d11-9950-b30698e28a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159771464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.159771464
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.4092765392
Short name T576
Test name
Test status
Simulation time 1258230369 ps
CPU time 27.07 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 213156 kb
Host smart-b5bdc348-bf94-4daf-8fdd-4d897822164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092765392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4092765392
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3224264876
Short name T879
Test name
Test status
Simulation time 773097218 ps
CPU time 3.94 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:31 PM PDT 24
Peak memory 204980 kb
Host smart-b42400d5-13da-460c-957d-33b4201d4011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224264876 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3224264876
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3869186913
Short name T548
Test name
Test status
Simulation time 10627156748 ps
CPU time 14.62 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:42 PM PDT 24
Peak memory 290516 kb
Host smart-f256be84-08f6-446d-ae61-6454187e3740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869186913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3869186913
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.180582529
Short name T11
Test name
Test status
Simulation time 11050333451 ps
CPU time 4.89 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:27 PM PDT 24
Peak memory 228940 kb
Host smart-c2e5d188-8148-44aa-ae69-7c8c8136dc30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180582529 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.180582529
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3116239518
Short name T224
Test name
Test status
Simulation time 431820310 ps
CPU time 2.57 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:25 PM PDT 24
Peak memory 205084 kb
Host smart-76e4f00c-3eb4-49f4-8f20-6690a46955aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116239518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3116239518
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2017392971
Short name T87
Test name
Test status
Simulation time 3683525659 ps
CPU time 3.74 seconds
Started May 21 02:52:14 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 205096 kb
Host smart-a5d4704f-eebb-4c77-92cb-aa0e43c566b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017392971 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2017392971
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2120109172
Short name T496
Test name
Test status
Simulation time 8807595686 ps
CPU time 15.71 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 604404 kb
Host smart-b85a961d-97ad-4eed-bcec-db4a3ae8ba83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120109172 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2120109172
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1942537725
Short name T148
Test name
Test status
Simulation time 446092162 ps
CPU time 16.07 seconds
Started May 21 02:52:16 PM PDT 24
Finished May 21 02:52:33 PM PDT 24
Peak memory 204956 kb
Host smart-575cb9d4-0498-4530-b134-bcb5842185f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942537725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1942537725
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3658620627
Short name T218
Test name
Test status
Simulation time 1853079949 ps
CPU time 31.46 seconds
Started May 21 02:52:15 PM PDT 24
Finished May 21 02:52:48 PM PDT 24
Peak memory 221996 kb
Host smart-2476b925-f84a-4d60-b568-09475befcc14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658620627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3658620627
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2776079250
Short name T296
Test name
Test status
Simulation time 41894360382 ps
CPU time 88.99 seconds
Started May 21 02:52:18 PM PDT 24
Finished May 21 02:53:48 PM PDT 24
Peak memory 1337712 kb
Host smart-2f143c1d-dbfe-4b9c-b696-da17df560dfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776079250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2776079250
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.886604806
Short name T346
Test name
Test status
Simulation time 12766023597 ps
CPU time 35.81 seconds
Started May 21 02:52:17 PM PDT 24
Finished May 21 02:52:54 PM PDT 24
Peak memory 502904 kb
Host smart-ebc3a640-bfd8-4eca-b309-35fc0875db70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886604806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.886604806
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3650889915
Short name T910
Test name
Test status
Simulation time 4257707653 ps
CPU time 7.19 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 02:52:32 PM PDT 24
Peak memory 213324 kb
Host smart-9bb031ec-8b60-4854-a08c-d937736ba3e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650889915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3650889915
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2090854461
Short name T152
Test name
Test status
Simulation time 23521234 ps
CPU time 0.62 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:28 PM PDT 24
Peak memory 204652 kb
Host smart-45bfae18-973f-4482-a6d7-b967cc724308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090854461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2090854461
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2310559585
Short name T1288
Test name
Test status
Simulation time 236247832 ps
CPU time 1.57 seconds
Started May 21 02:52:19 PM PDT 24
Finished May 21 02:52:22 PM PDT 24
Peak memory 213292 kb
Host smart-3061094b-984a-424f-8b07-83a2ab7efbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310559585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2310559585
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.966500566
Short name T679
Test name
Test status
Simulation time 449883108 ps
CPU time 9.81 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 02:52:34 PM PDT 24
Peak memory 293884 kb
Host smart-41956464-5409-4df7-bb7d-a5290a26c1fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966500566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.966500566
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.10734118
Short name T982
Test name
Test status
Simulation time 11564654233 ps
CPU time 86.24 seconds
Started May 21 02:52:23 PM PDT 24
Finished May 21 02:53:52 PM PDT 24
Peak memory 608384 kb
Host smart-260dcb97-a035-446e-bdb5-2e8d36e4b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10734118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.10734118
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.621565134
Short name T890
Test name
Test status
Simulation time 9679923093 ps
CPU time 70.87 seconds
Started May 21 02:52:23 PM PDT 24
Finished May 21 02:53:36 PM PDT 24
Peak memory 783424 kb
Host smart-cf476d3c-3075-46d4-bd8e-4f31b782007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621565134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.621565134
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3451992102
Short name T306
Test name
Test status
Simulation time 699943401 ps
CPU time 1.02 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:24 PM PDT 24
Peak memory 204812 kb
Host smart-8e663f65-e629-4541-90f2-f6f958cc7835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451992102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3451992102
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2762900340
Short name T812
Test name
Test status
Simulation time 141396389 ps
CPU time 7.57 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 204996 kb
Host smart-48fcab4f-5a06-463a-9753-c4906bbcfe20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762900340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2762900340
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2169593781
Short name T477
Test name
Test status
Simulation time 38599486308 ps
CPU time 145.17 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:54:47 PM PDT 24
Peak memory 1440464 kb
Host smart-38c97eef-aca8-46e7-8f86-191107cf4fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169593781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2169593781
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1749244823
Short name T1181
Test name
Test status
Simulation time 4908250890 ps
CPU time 24.62 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:52:55 PM PDT 24
Peak memory 205028 kb
Host smart-a1b85b08-0937-4ef2-b666-e857c9485ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749244823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1749244823
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2014934976
Short name T951
Test name
Test status
Simulation time 1735292807 ps
CPU time 75.59 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 310632 kb
Host smart-006d2216-8020-42e4-8f2f-4cd8a90db02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014934976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2014934976
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2171195873
Short name T672
Test name
Test status
Simulation time 50708397 ps
CPU time 0.64 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:24 PM PDT 24
Peak memory 204708 kb
Host smart-04a7857f-838b-435b-b050-c7cc53b7465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171195873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2171195873
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3708116375
Short name T892
Test name
Test status
Simulation time 51513037447 ps
CPU time 1995.09 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 03:25:40 PM PDT 24
Peak memory 582176 kb
Host smart-ea94539d-62c9-47f7-bb3b-b07d1e6c80a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708116375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3708116375
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2702283970
Short name T1311
Test name
Test status
Simulation time 5496037467 ps
CPU time 25.96 seconds
Started May 21 02:52:21 PM PDT 24
Finished May 21 02:52:50 PM PDT 24
Peak memory 301276 kb
Host smart-31a10a89-bfc3-468d-a58a-b5e26f17a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702283970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2702283970
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2721877483
Short name T47
Test name
Test status
Simulation time 228452004343 ps
CPU time 1321.4 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 03:14:26 PM PDT 24
Peak memory 3430676 kb
Host smart-1952d9ab-bb26-4bf3-bb6a-40a0aca42ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721877483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2721877483
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1779989982
Short name T866
Test name
Test status
Simulation time 881602676 ps
CPU time 13.75 seconds
Started May 21 02:52:20 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 221324 kb
Host smart-878422fa-4409-454a-8c90-e638be6a7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779989982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1779989982
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1863386549
Short name T262
Test name
Test status
Simulation time 4639331032 ps
CPU time 4.57 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:33 PM PDT 24
Peak memory 205116 kb
Host smart-1635cda6-2d5c-4e27-a2c7-677c02dad389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863386549 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1863386549
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1664796980
Short name T456
Test name
Test status
Simulation time 10335600158 ps
CPU time 12.9 seconds
Started May 21 02:52:29 PM PDT 24
Finished May 21 02:52:45 PM PDT 24
Peak memory 257552 kb
Host smart-03901255-c994-4723-8b0b-f12411b3d835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664796980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1664796980
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2133231395
Short name T761
Test name
Test status
Simulation time 10034408630 ps
CPU time 88.86 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:53:59 PM PDT 24
Peak memory 558092 kb
Host smart-06567151-063d-4167-be30-cb5d835a47dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133231395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2133231395
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2528947154
Short name T1153
Test name
Test status
Simulation time 411054858 ps
CPU time 2.64 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:52:33 PM PDT 24
Peak memory 205080 kb
Host smart-50faf88e-86b0-49c9-9c8a-e208cf158207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528947154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2528947154
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2339931283
Short name T615
Test name
Test status
Simulation time 1963799393 ps
CPU time 5.48 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 213260 kb
Host smart-511a4cde-3fed-405c-86f1-1725a0bac372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339931283 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2339931283
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3377680311
Short name T623
Test name
Test status
Simulation time 20463439204 ps
CPU time 162.18 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:55:10 PM PDT 24
Peak memory 1819652 kb
Host smart-7ef1ce8f-7c3b-4aa6-9810-c2be85687aa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377680311 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3377680311
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1865449012
Short name T1231
Test name
Test status
Simulation time 3491006680 ps
CPU time 35.4 seconds
Started May 21 02:52:22 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 205136 kb
Host smart-2d0bf297-255d-41dd-8e74-98bb1c206ca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865449012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1865449012
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3830553592
Short name T678
Test name
Test status
Simulation time 4311541900 ps
CPU time 62.02 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 208252 kb
Host smart-e675f586-3b75-4da6-9d53-81cc08e4588b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830553592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3830553592
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.573203622
Short name T27
Test name
Test status
Simulation time 52777580691 ps
CPU time 181 seconds
Started May 21 02:52:28 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 2157452 kb
Host smart-048fab29-1765-4c1c-ae33-3437af6d63d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573203622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.573203622
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3898079185
Short name T28
Test name
Test status
Simulation time 26862560466 ps
CPU time 1537.22 seconds
Started May 21 02:52:28 PM PDT 24
Finished May 21 03:18:09 PM PDT 24
Peak memory 5696900 kb
Host smart-b8170eed-e7f4-41d5-ae2c-a18846f532d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898079185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3898079185
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2755367341
Short name T284
Test name
Test status
Simulation time 1179052434 ps
CPU time 5.96 seconds
Started May 21 02:52:27 PM PDT 24
Finished May 21 02:52:37 PM PDT 24
Peak memory 213248 kb
Host smart-5e176bc2-a8dc-413a-85d9-6d96ece41d4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755367341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2755367341
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.129663396
Short name T843
Test name
Test status
Simulation time 16974476 ps
CPU time 0.66 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:52:44 PM PDT 24
Peak memory 204676 kb
Host smart-d1d1073b-2709-4425-9467-c95a0abf74ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129663396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.129663396
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.227610525
Short name T835
Test name
Test status
Simulation time 595565589 ps
CPU time 2.86 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 226804 kb
Host smart-736f49fd-5184-4eaf-a41b-51c10e91f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227610525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.227610525
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.4084178217
Short name T254
Test name
Test status
Simulation time 1368529540 ps
CPU time 17.44 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:52:54 PM PDT 24
Peak memory 268368 kb
Host smart-e37218cd-bf13-432e-8e51-16b6d2d48ea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084178217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.4084178217
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1133110742
Short name T129
Test name
Test status
Simulation time 1780322360 ps
CPU time 104.62 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:54:22 PM PDT 24
Peak memory 428060 kb
Host smart-ca93261b-a8ae-4369-ab75-b1e40a98c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133110742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1133110742
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3171674584
Short name T962
Test name
Test status
Simulation time 6066864952 ps
CPU time 39.19 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:53:15 PM PDT 24
Peak memory 508536 kb
Host smart-77864be8-1b7c-44c2-8719-1e520dc3eb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171674584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3171674584
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3069129640
Short name T578
Test name
Test status
Simulation time 128822395 ps
CPU time 0.97 seconds
Started May 21 02:52:31 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 204780 kb
Host smart-e13bcdd6-5516-4d5d-a662-6f4868b9773b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069129640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3069129640
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.853133864
Short name T925
Test name
Test status
Simulation time 168389421 ps
CPU time 9.73 seconds
Started May 21 02:52:34 PM PDT 24
Finished May 21 02:52:49 PM PDT 24
Peak memory 234320 kb
Host smart-4606ea97-5950-4125-b455-fd528ed01897
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853133864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
853133864
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2671636478
Short name T8
Test name
Test status
Simulation time 16073262620 ps
CPU time 121.82 seconds
Started May 21 02:52:31 PM PDT 24
Finished May 21 02:54:36 PM PDT 24
Peak memory 1166344 kb
Host smart-0ab31113-99a1-4d21-9a51-58625112b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671636478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2671636478
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2481280080
Short name T1331
Test name
Test status
Simulation time 425942865 ps
CPU time 17.74 seconds
Started May 21 02:52:39 PM PDT 24
Finished May 21 02:53:02 PM PDT 24
Peak memory 205012 kb
Host smart-127bd129-7c5d-4ccc-ac9c-6fddd3d8bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481280080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2481280080
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1237578614
Short name T1122
Test name
Test status
Simulation time 8913013729 ps
CPU time 58.89 seconds
Started May 21 02:52:36 PM PDT 24
Finished May 21 02:53:40 PM PDT 24
Peak memory 523740 kb
Host smart-b59ce892-1783-4f05-ae98-a4d1fd1ab1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237578614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1237578614
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2142513721
Short name T1188
Test name
Test status
Simulation time 21300451 ps
CPU time 0.69 seconds
Started May 21 02:52:26 PM PDT 24
Finished May 21 02:52:30 PM PDT 24
Peak memory 204704 kb
Host smart-a5a83f35-8a46-4a9e-84df-41a05877b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142513721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2142513721
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2302454345
Short name T1055
Test name
Test status
Simulation time 50786974702 ps
CPU time 176.09 seconds
Started May 21 02:52:30 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 265768 kb
Host smart-49597698-be6b-45fc-8f26-d7062f4088b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302454345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2302454345
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2672150066
Short name T1195
Test name
Test status
Simulation time 952637488 ps
CPU time 12.13 seconds
Started May 21 02:52:25 PM PDT 24
Finished May 21 02:52:40 PM PDT 24
Peak memory 245632 kb
Host smart-b1ce5756-e7da-4b9f-9b00-74c9c4941dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672150066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2672150066
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3912690405
Short name T234
Test name
Test status
Simulation time 1776179100 ps
CPU time 22.96 seconds
Started May 21 02:52:31 PM PDT 24
Finished May 21 02:52:59 PM PDT 24
Peak memory 213212 kb
Host smart-f79426e3-affa-42a0-8065-c18e41e5db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912690405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3912690405
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3916453743
Short name T632
Test name
Test status
Simulation time 456273591 ps
CPU time 2.67 seconds
Started May 21 02:52:39 PM PDT 24
Finished May 21 02:52:47 PM PDT 24
Peak memory 204960 kb
Host smart-528d9f46-fa52-4006-a704-65e12c7cc912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916453743 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3916453743
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.395261520
Short name T84
Test name
Test status
Simulation time 10510110496 ps
CPU time 14.13 seconds
Started May 21 02:52:34 PM PDT 24
Finished May 21 02:52:53 PM PDT 24
Peak memory 256284 kb
Host smart-4f87cf11-27fe-4df5-ba5a-cacb9659898d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395261520 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.395261520
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3230280345
Short name T947
Test name
Test status
Simulation time 10219782718 ps
CPU time 6.99 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:52:44 PM PDT 24
Peak memory 247040 kb
Host smart-4608cfa1-3734-4f63-91d8-2e70a2fe1a26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230280345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3230280345
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3232559020
Short name T854
Test name
Test status
Simulation time 397525259 ps
CPU time 2.58 seconds
Started May 21 02:52:36 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 204996 kb
Host smart-14510b80-7b11-443c-9225-b82f6d40e268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232559020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3232559020
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.687429021
Short name T568
Test name
Test status
Simulation time 4570030987 ps
CPU time 5.92 seconds
Started May 21 02:52:31 PM PDT 24
Finished May 21 02:52:41 PM PDT 24
Peak memory 214004 kb
Host smart-f396751c-f327-46e0-926a-e863abfb5dc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687429021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.687429021
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.802518714
Short name T498
Test name
Test status
Simulation time 14994628356 ps
CPU time 29.23 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:53:06 PM PDT 24
Peak memory 850804 kb
Host smart-0c3d9f13-5de6-4f7d-af22-440281aaf3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802518714 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.802518714
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3667162811
Short name T913
Test name
Test status
Simulation time 1441175021 ps
CPU time 24.82 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 204996 kb
Host smart-e9f3a981-01f7-44aa-ad94-b954774fb0cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667162811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3667162811
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.475819218
Short name T842
Test name
Test status
Simulation time 4090803867 ps
CPU time 45.19 seconds
Started May 21 02:52:32 PM PDT 24
Finished May 21 02:53:22 PM PDT 24
Peak memory 205076 kb
Host smart-cd3963e4-b4a0-4551-96ca-45b6d81dcb9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475819218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.475819218
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1767247783
Short name T888
Test name
Test status
Simulation time 30216669582 ps
CPU time 17.67 seconds
Started May 21 02:52:33 PM PDT 24
Finished May 21 02:52:56 PM PDT 24
Peak memory 471844 kb
Host smart-02d51e53-f386-41b5-9436-ca49731e3c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767247783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1767247783
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2529909885
Short name T298
Test name
Test status
Simulation time 2173339740 ps
CPU time 5.87 seconds
Started May 21 02:52:39 PM PDT 24
Finished May 21 02:52:50 PM PDT 24
Peak memory 213340 kb
Host smart-90344b72-fa39-48a7-9826-38842d1c676c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529909885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2529909885
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.491235748
Short name T609
Test name
Test status
Simulation time 19049298 ps
CPU time 0.63 seconds
Started May 21 02:52:48 PM PDT 24
Finished May 21 02:52:50 PM PDT 24
Peak memory 204632 kb
Host smart-4047baf7-eb3e-498f-bce3-338fee22b3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491235748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.491235748
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2009844626
Short name T827
Test name
Test status
Simulation time 775115050 ps
CPU time 8.55 seconds
Started May 21 02:52:37 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 234184 kb
Host smart-47d056cd-b318-480b-8052-68ca95e5f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009844626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2009844626
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.534620088
Short name T1070
Test name
Test status
Simulation time 324250441 ps
CPU time 16.32 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:52:59 PM PDT 24
Peak memory 245912 kb
Host smart-78791263-006f-463c-b2fe-1bc291fdd2a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534620088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.534620088
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2530833999
Short name T549
Test name
Test status
Simulation time 2828380326 ps
CPU time 95.59 seconds
Started May 21 02:52:37 PM PDT 24
Finished May 21 02:54:17 PM PDT 24
Peak memory 872664 kb
Host smart-e8e7dce7-44ea-4038-b764-5273bb1579e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530833999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2530833999
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1103240367
Short name T1162
Test name
Test status
Simulation time 5518947923 ps
CPU time 101.66 seconds
Started May 21 02:52:37 PM PDT 24
Finished May 21 02:54:24 PM PDT 24
Peak memory 834152 kb
Host smart-e7e4333f-f268-4e07-a73c-df9196839f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103240367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1103240367
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2985447135
Short name T62
Test name
Test status
Simulation time 445584258 ps
CPU time 3.2 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:52:46 PM PDT 24
Peak memory 204980 kb
Host smart-d4e04089-e164-4869-96dd-d4397e3ca20f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985447135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2985447135
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3397706034
Short name T248
Test name
Test status
Simulation time 43096554662 ps
CPU time 391.37 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:59:14 PM PDT 24
Peak memory 1384448 kb
Host smart-18eaddb7-e0ff-4685-88f6-8c3782538e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397706034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3397706034
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2403268827
Short name T215
Test name
Test status
Simulation time 452033599 ps
CPU time 6.16 seconds
Started May 21 02:52:41 PM PDT 24
Finished May 21 02:52:52 PM PDT 24
Peak memory 205008 kb
Host smart-33a99989-ee17-4d06-b252-2c765b4e2c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403268827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2403268827
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.3583880590
Short name T1326
Test name
Test status
Simulation time 21593951104 ps
CPU time 36.2 seconds
Started May 21 02:52:45 PM PDT 24
Finished May 21 02:53:24 PM PDT 24
Peak memory 415556 kb
Host smart-9a4e200a-5ed4-46fe-9eaa-cbf5ff975223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583880590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.3583880590
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3365371862
Short name T1060
Test name
Test status
Simulation time 25867236 ps
CPU time 0.66 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:52:44 PM PDT 24
Peak memory 204724 kb
Host smart-77d6c9ae-6289-4b10-ab95-448f8f68a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365371862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3365371862
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2426410810
Short name T446
Test name
Test status
Simulation time 29110027425 ps
CPU time 1241.94 seconds
Started May 21 02:52:37 PM PDT 24
Finished May 21 03:13:24 PM PDT 24
Peak memory 237176 kb
Host smart-0509ba3d-5547-42b1-859a-7f1ceca02f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426410810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2426410810
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3715249137
Short name T716
Test name
Test status
Simulation time 3911943632 ps
CPU time 15.88 seconds
Started May 21 02:52:39 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 286720 kb
Host smart-8f2583f4-8ce1-4b23-a24e-0a07cbc71d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715249137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3715249137
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1302530742
Short name T494
Test name
Test status
Simulation time 3671155143 ps
CPU time 17.49 seconds
Started May 21 02:52:36 PM PDT 24
Finished May 21 02:52:59 PM PDT 24
Peak memory 220296 kb
Host smart-0397e42e-8b74-4ee0-95aa-5602668ac83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302530742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1302530742
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3831597508
Short name T112
Test name
Test status
Simulation time 1131382226 ps
CPU time 5.49 seconds
Started May 21 02:52:52 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 214528 kb
Host smart-fc169616-d6a8-45db-9212-8a32718c567f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831597508 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3831597508
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3299994280
Short name T317
Test name
Test status
Simulation time 10078539787 ps
CPU time 72.95 seconds
Started May 21 02:52:52 PM PDT 24
Finished May 21 02:54:08 PM PDT 24
Peak memory 450252 kb
Host smart-c2bdc49f-f1b4-428c-8c7a-6d0faa643011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299994280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3299994280
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1922870447
Short name T935
Test name
Test status
Simulation time 10376554787 ps
CPU time 15.01 seconds
Started May 21 02:52:43 PM PDT 24
Finished May 21 02:53:02 PM PDT 24
Peak memory 281616 kb
Host smart-96a6e352-b8e2-47bb-96db-f4f5c937da69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922870447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1922870447
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.4178449691
Short name T1210
Test name
Test status
Simulation time 3351057324 ps
CPU time 2.89 seconds
Started May 21 02:52:52 PM PDT 24
Finished May 21 02:52:57 PM PDT 24
Peak memory 205104 kb
Host smart-8b7c5695-ab1a-403c-b242-a4a0b99babda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178449691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.4178449691
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.496058484
Short name T730
Test name
Test status
Simulation time 2143824727 ps
CPU time 5.74 seconds
Started May 21 02:52:42 PM PDT 24
Finished May 21 02:52:52 PM PDT 24
Peak memory 213204 kb
Host smart-375f0486-f81c-4eb7-82e2-0a0e9cfb8720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496058484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.496058484
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2196036871
Short name T1270
Test name
Test status
Simulation time 12066133829 ps
CPU time 84.76 seconds
Started May 21 02:52:43 PM PDT 24
Finished May 21 02:54:12 PM PDT 24
Peak memory 1384260 kb
Host smart-9b4f23f7-5c6b-4465-ab8c-ca9c30e02c1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196036871 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2196036871
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.542985151
Short name T675
Test name
Test status
Simulation time 2106332166 ps
CPU time 21.26 seconds
Started May 21 02:52:39 PM PDT 24
Finished May 21 02:53:05 PM PDT 24
Peak memory 204948 kb
Host smart-1554fd29-4cdc-4ba1-8791-ba5689f0736e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542985151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.542985151
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2760457631
Short name T278
Test name
Test status
Simulation time 3831551030 ps
CPU time 10.15 seconds
Started May 21 02:52:43 PM PDT 24
Finished May 21 02:52:57 PM PDT 24
Peak memory 213156 kb
Host smart-dc005943-3a72-46e4-ad7d-b336aa101d1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760457631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2760457631
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2483011102
Short name T918
Test name
Test status
Simulation time 54738763225 ps
CPU time 186.61 seconds
Started May 21 02:52:38 PM PDT 24
Finished May 21 02:55:50 PM PDT 24
Peak memory 2143204 kb
Host smart-f7ecef56-0c70-4ca9-a31c-b5e40b93ace3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483011102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2483011102
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.272046980
Short name T611
Test name
Test status
Simulation time 4720825121 ps
CPU time 36.29 seconds
Started May 21 02:52:42 PM PDT 24
Finished May 21 02:53:23 PM PDT 24
Peak memory 688144 kb
Host smart-3cbcb4ab-d0c9-47a5-be1a-84716b27e4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272046980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.272046980
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3491671585
Short name T1229
Test name
Test status
Simulation time 1263887097 ps
CPU time 7.02 seconds
Started May 21 02:52:42 PM PDT 24
Finished May 21 02:52:54 PM PDT 24
Peak memory 213220 kb
Host smart-45cc7f46-a66e-477f-ab27-fd0565f50f94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491671585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3491671585
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1169986146
Short name T423
Test name
Test status
Simulation time 23198227 ps
CPU time 0.62 seconds
Started May 21 02:52:53 PM PDT 24
Finished May 21 02:52:57 PM PDT 24
Peak memory 204608 kb
Host smart-e0ad08ad-2865-4a45-aa97-d79238608c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169986146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1169986146
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3243867508
Short name T1337
Test name
Test status
Simulation time 88931816 ps
CPU time 1.38 seconds
Started May 21 02:52:50 PM PDT 24
Finished May 21 02:52:54 PM PDT 24
Peak memory 213328 kb
Host smart-73c42ab2-cd10-4ac3-95ef-d20caf8b39d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243867508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3243867508
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2383296071
Short name T376
Test name
Test status
Simulation time 421141764 ps
CPU time 7.5 seconds
Started May 21 02:52:49 PM PDT 24
Finished May 21 02:52:58 PM PDT 24
Peak memory 295892 kb
Host smart-93f5c17b-7955-49f3-a16b-befbf253ab98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383296071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2383296071
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.65317626
Short name T721
Test name
Test status
Simulation time 3851972591 ps
CPU time 70.79 seconds
Started May 21 02:52:52 PM PDT 24
Finished May 21 02:54:06 PM PDT 24
Peak memory 686588 kb
Host smart-747c63b0-afb3-4cbd-bd6d-753322ef4db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65317626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.65317626
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2101848335
Short name T132
Test name
Test status
Simulation time 1909474543 ps
CPU time 112.82 seconds
Started May 21 02:52:49 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 463232 kb
Host smart-61741ccd-a1a4-4ac1-bdaa-f7abcc4e0a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101848335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2101848335
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.997276746
Short name T1009
Test name
Test status
Simulation time 715938572 ps
CPU time 0.81 seconds
Started May 21 02:52:49 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 204780 kb
Host smart-b42c2adc-bc9f-4dcf-8327-518ffbc8e609
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997276746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.997276746
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3352286046
Short name T709
Test name
Test status
Simulation time 745225910 ps
CPU time 4.11 seconds
Started May 21 02:52:51 PM PDT 24
Finished May 21 02:52:57 PM PDT 24
Peak memory 204992 kb
Host smart-3e7d663b-1242-4347-9a9e-b2e18c7b9c24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352286046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3352286046
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.4012957739
Short name T313
Test name
Test status
Simulation time 3126867605 ps
CPU time 91.45 seconds
Started May 21 02:52:50 PM PDT 24
Finished May 21 02:54:23 PM PDT 24
Peak memory 948052 kb
Host smart-0e662f75-eafd-4506-87a0-fc216b02733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012957739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.4012957739
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1563484586
Short name T1027
Test name
Test status
Simulation time 1903706958 ps
CPU time 18.98 seconds
Started May 21 02:52:56 PM PDT 24
Finished May 21 02:53:17 PM PDT 24
Peak memory 204960 kb
Host smart-aa587bf8-c36b-4987-ae4b-6d9dbd5a20a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563484586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1563484586
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3295394126
Short name T1136
Test name
Test status
Simulation time 2156346519 ps
CPU time 26.02 seconds
Started May 21 02:52:55 PM PDT 24
Finished May 21 02:53:23 PM PDT 24
Peak memory 383392 kb
Host smart-5c30a663-3562-496c-84e8-3fc2f80a0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295394126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3295394126
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.778831569
Short name T804
Test name
Test status
Simulation time 19591735 ps
CPU time 0.64 seconds
Started May 21 02:52:48 PM PDT 24
Finished May 21 02:52:49 PM PDT 24
Peak memory 204668 kb
Host smart-83b482d9-6e94-423f-b121-698a068c6107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778831569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.778831569
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2513483876
Short name T1171
Test name
Test status
Simulation time 6788532333 ps
CPU time 18.69 seconds
Started May 21 02:52:51 PM PDT 24
Finished May 21 02:53:12 PM PDT 24
Peak memory 213404 kb
Host smart-bbf16cea-806e-474f-8bfd-8d115218ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513483876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2513483876
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1144185364
Short name T1263
Test name
Test status
Simulation time 3795655070 ps
CPU time 32.93 seconds
Started May 21 02:52:50 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 402828 kb
Host smart-3a5d15f2-9964-48c9-8dca-e99b54841fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144185364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1144185364
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.2421037516
Short name T104
Test name
Test status
Simulation time 20172171769 ps
CPU time 612.36 seconds
Started May 21 02:52:50 PM PDT 24
Finished May 21 03:03:04 PM PDT 24
Peak memory 1747544 kb
Host smart-e8fd9198-b333-4dce-99f7-b8a4f63c8330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421037516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.2421037516
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3170305323
Short name T909
Test name
Test status
Simulation time 889656145 ps
CPU time 39.71 seconds
Started May 21 02:52:51 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 213208 kb
Host smart-33bf2c0d-dbef-44af-b403-141b8510e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170305323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3170305323
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3823934375
Short name T990
Test name
Test status
Simulation time 736511467 ps
CPU time 4.15 seconds
Started May 21 02:52:58 PM PDT 24
Finished May 21 02:53:04 PM PDT 24
Peak memory 205024 kb
Host smart-f37b67ff-75fa-4ab3-8881-5d1a25a1e4fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823934375 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3823934375
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1148490805
Short name T674
Test name
Test status
Simulation time 10330074624 ps
CPU time 27.22 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 345036 kb
Host smart-434a04ef-c9a5-4470-908a-c4fec856ffe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148490805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1148490805
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.37476691
Short name T73
Test name
Test status
Simulation time 10344005688 ps
CPU time 13.36 seconds
Started May 21 02:52:54 PM PDT 24
Finished May 21 02:53:10 PM PDT 24
Peak memory 283804 kb
Host smart-b3af485e-e2a9-4496-a7b4-36a29ca02761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37476691 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_fifo_reset_tx.37476691
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1855152621
Short name T13
Test name
Test status
Simulation time 1486607593 ps
CPU time 2.74 seconds
Started May 21 02:52:55 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 205096 kb
Host smart-52d66b8f-7088-4b4c-b7ee-2d754f11e673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855152621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1855152621
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3617670999
Short name T1092
Test name
Test status
Simulation time 1472901707 ps
CPU time 3.89 seconds
Started May 21 02:52:50 PM PDT 24
Finished May 21 02:52:56 PM PDT 24
Peak memory 205040 kb
Host smart-6e268228-d7af-41f6-8737-363d86f6cb44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617670999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3617670999
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3353727040
Short name T600
Test name
Test status
Simulation time 11970486554 ps
CPU time 96.12 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 1468448 kb
Host smart-caf0c23b-57a8-4783-8dae-2081519b9698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353727040 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3353727040
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.282760014
Short name T1023
Test name
Test status
Simulation time 852354301 ps
CPU time 11.18 seconds
Started May 21 02:52:57 PM PDT 24
Finished May 21 02:53:10 PM PDT 24
Peak memory 204992 kb
Host smart-83d96531-7d9b-40b5-b771-87533d78bd11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282760014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.282760014
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.240959480
Short name T5
Test name
Test status
Simulation time 5211432013 ps
CPU time 19.64 seconds
Started May 21 02:52:49 PM PDT 24
Finished May 21 02:53:09 PM PDT 24
Peak memory 222132 kb
Host smart-7c92c808-46dd-4327-8146-aa06bee05a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240959480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.240959480
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1519260063
Short name T409
Test name
Test status
Simulation time 37552521828 ps
CPU time 31.65 seconds
Started May 21 02:52:49 PM PDT 24
Finished May 21 02:53:22 PM PDT 24
Peak memory 672696 kb
Host smart-30a8fa82-d78e-400c-8330-0f5b75a67970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519260063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1519260063
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.4023209228
Short name T220
Test name
Test status
Simulation time 29988066840 ps
CPU time 615.8 seconds
Started May 21 02:52:53 PM PDT 24
Finished May 21 03:03:11 PM PDT 24
Peak memory 1781404 kb
Host smart-c605d66f-6a4c-4550-a601-5a784850594a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023209228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.4023209228
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.775936844
Short name T1178
Test name
Test status
Simulation time 1498867462 ps
CPU time 7.21 seconds
Started May 21 02:52:52 PM PDT 24
Finished May 21 02:53:02 PM PDT 24
Peak memory 221208 kb
Host smart-ecb0f3a9-9638-4dc2-9dff-2536e9e7ec3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775936844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.775936844
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2523868666
Short name T1302
Test name
Test status
Simulation time 46559254 ps
CPU time 0.66 seconds
Started May 21 02:47:38 PM PDT 24
Finished May 21 02:47:41 PM PDT 24
Peak memory 204644 kb
Host smart-caed3f82-2ec8-457d-a8b0-e353fe46d07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523868666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2523868666
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3650075771
Short name T876
Test name
Test status
Simulation time 327669645 ps
CPU time 1.27 seconds
Started May 21 02:47:26 PM PDT 24
Finished May 21 02:47:29 PM PDT 24
Peak memory 213240 kb
Host smart-26143648-2f86-46bb-b97c-25f42a262f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650075771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3650075771
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3348247895
Short name T1206
Test name
Test status
Simulation time 4422602807 ps
CPU time 8.67 seconds
Started May 21 02:47:25 PM PDT 24
Finished May 21 02:47:35 PM PDT 24
Peak memory 285764 kb
Host smart-147b10d3-8259-439c-a597-bec0ef7af752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348247895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3348247895
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2093474337
Short name T74
Test name
Test status
Simulation time 4934169244 ps
CPU time 128.45 seconds
Started May 21 02:47:26 PM PDT 24
Finished May 21 02:49:36 PM PDT 24
Peak memory 321080 kb
Host smart-b4cc5afa-87da-4ac8-b749-10d7bb6f8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093474337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2093474337
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1354097722
Short name T287
Test name
Test status
Simulation time 1430876243 ps
CPU time 39.94 seconds
Started May 21 02:47:20 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 554400 kb
Host smart-dab1cd38-d6ec-4a96-b88e-6457b444da37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354097722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1354097722
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1972746892
Short name T912
Test name
Test status
Simulation time 88266630 ps
CPU time 0.84 seconds
Started May 21 02:47:25 PM PDT 24
Finished May 21 02:47:27 PM PDT 24
Peak memory 204804 kb
Host smart-8aa19987-774e-40e3-92a8-e09c3059b9c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972746892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1972746892
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1167055011
Short name T380
Test name
Test status
Simulation time 163360673 ps
CPU time 4.86 seconds
Started May 21 02:47:26 PM PDT 24
Finished May 21 02:47:32 PM PDT 24
Peak memory 234832 kb
Host smart-b67f1116-aeee-4b98-b2a6-2c7c026644bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167055011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1167055011
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1017858151
Short name T1180
Test name
Test status
Simulation time 3847411157 ps
CPU time 82.87 seconds
Started May 21 02:47:19 PM PDT 24
Finished May 21 02:48:44 PM PDT 24
Peak memory 1002976 kb
Host smart-15bd1590-bd5e-4bdb-bab6-fc60a90f8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017858151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1017858151
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1198682426
Short name T698
Test name
Test status
Simulation time 576609764 ps
CPU time 8.48 seconds
Started May 21 02:47:33 PM PDT 24
Finished May 21 02:47:43 PM PDT 24
Peak memory 205012 kb
Host smart-09c4e1a8-9500-4db2-8c3b-ee7802553ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198682426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1198682426
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2336243622
Short name T437
Test name
Test status
Simulation time 11904970104 ps
CPU time 99.23 seconds
Started May 21 02:47:35 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 341728 kb
Host smart-9e50b881-bf27-4a54-9010-840c4a144d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336243622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2336243622
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.917446517
Short name T571
Test name
Test status
Simulation time 49379285 ps
CPU time 0.67 seconds
Started May 21 02:47:20 PM PDT 24
Finished May 21 02:47:23 PM PDT 24
Peak memory 204740 kb
Host smart-7dad6180-520a-47e6-90be-b3f9f761572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917446517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.917446517
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.141526370
Short name T440
Test name
Test status
Simulation time 1487634529 ps
CPU time 30.19 seconds
Started May 21 02:47:25 PM PDT 24
Finished May 21 02:47:56 PM PDT 24
Peak memory 433472 kb
Host smart-0bc46b05-f21b-477a-84ff-a951c634731a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141526370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.141526370
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3538222233
Short name T524
Test name
Test status
Simulation time 2203340860 ps
CPU time 113.6 seconds
Started May 21 02:47:21 PM PDT 24
Finished May 21 02:49:17 PM PDT 24
Peak memory 426948 kb
Host smart-e7c12cc2-4259-4917-8323-5b040ccee092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538222233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3538222233
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1221053034
Short name T622
Test name
Test status
Simulation time 782700546 ps
CPU time 14.41 seconds
Started May 21 02:47:26 PM PDT 24
Finished May 21 02:47:42 PM PDT 24
Peak memory 221396 kb
Host smart-a408686b-abf7-42c3-867e-9841aedec997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221053034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1221053034
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3988128600
Short name T157
Test name
Test status
Simulation time 114524109 ps
CPU time 0.91 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:47:39 PM PDT 24
Peak memory 223204 kb
Host smart-b3cfa1f8-b733-4193-b85d-0d4045e509ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988128600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3988128600
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2360830464
Short name T953
Test name
Test status
Simulation time 2648558330 ps
CPU time 3.79 seconds
Started May 21 02:47:34 PM PDT 24
Finished May 21 02:47:39 PM PDT 24
Peak memory 213316 kb
Host smart-5419f503-7fab-4f79-9f89-cb23784da30c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360830464 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2360830464
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3866307490
Short name T585
Test name
Test status
Simulation time 10098967919 ps
CPU time 15.35 seconds
Started May 21 02:47:32 PM PDT 24
Finished May 21 02:47:49 PM PDT 24
Peak memory 252608 kb
Host smart-0635d441-4844-4dfe-94cc-33933bc9a5c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866307490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3866307490
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.4127629295
Short name T902
Test name
Test status
Simulation time 10163830224 ps
CPU time 20.09 seconds
Started May 21 02:47:34 PM PDT 24
Finished May 21 02:47:55 PM PDT 24
Peak memory 346728 kb
Host smart-a87cead2-b184-4d71-89c6-73ee6234f8ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127629295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.4127629295
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3898850137
Short name T212
Test name
Test status
Simulation time 1991595961 ps
CPU time 2.87 seconds
Started May 21 02:47:34 PM PDT 24
Finished May 21 02:47:38 PM PDT 24
Peak memory 205012 kb
Host smart-77722241-8c3a-4fb0-ab1f-3ef737f0f0b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898850137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3898850137
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2422317751
Short name T708
Test name
Test status
Simulation time 2882689396 ps
CPU time 3.77 seconds
Started May 21 02:47:25 PM PDT 24
Finished May 21 02:47:29 PM PDT 24
Peak memory 205156 kb
Host smart-76919ea0-9dd3-4d3c-9e4b-6b393e9110b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422317751 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2422317751
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3201926424
Short name T844
Test name
Test status
Simulation time 21279944459 ps
CPU time 264.16 seconds
Started May 21 02:47:30 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 3546680 kb
Host smart-9cb68de9-7c84-48db-b9f8-129340946ba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201926424 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3201926424
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1198070291
Short name T955
Test name
Test status
Simulation time 2656108142 ps
CPU time 12.79 seconds
Started May 21 02:47:30 PM PDT 24
Finished May 21 02:47:44 PM PDT 24
Peak memory 205056 kb
Host smart-2931b4be-8d0a-4ed0-afb3-637382d1bd98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198070291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1198070291
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.682852729
Short name T1037
Test name
Test status
Simulation time 4160954666 ps
CPU time 11.76 seconds
Started May 21 02:47:25 PM PDT 24
Finished May 21 02:47:39 PM PDT 24
Peak memory 208084 kb
Host smart-a94ae17d-d905-4e1f-b42e-6ec201848563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682852729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.682852729
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3838107312
Short name T1080
Test name
Test status
Simulation time 37093020373 ps
CPU time 484.34 seconds
Started May 21 02:47:24 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 4200920 kb
Host smart-6555ba16-456a-4bff-b270-13f57feadd44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838107312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3838107312
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2995045755
Short name T250
Test name
Test status
Simulation time 32330029869 ps
CPU time 718.75 seconds
Started May 21 02:47:28 PM PDT 24
Finished May 21 02:59:28 PM PDT 24
Peak memory 1902924 kb
Host smart-73927dba-6e0a-4ad2-9b85-f366c121bd9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995045755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2995045755
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3952844257
Short name T1238
Test name
Test status
Simulation time 5740732340 ps
CPU time 6.58 seconds
Started May 21 02:47:30 PM PDT 24
Finished May 21 02:47:38 PM PDT 24
Peak memory 205144 kb
Host smart-e808d02d-40b2-40da-b71b-a399d5a4dd5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952844257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3952844257
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2266477000
Short name T399
Test name
Test status
Simulation time 189063744 ps
CPU time 0.69 seconds
Started May 21 02:53:00 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 204624 kb
Host smart-79f8e49f-8196-447f-bb7e-4879a9e1e7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266477000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2266477000
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2303337720
Short name T1063
Test name
Test status
Simulation time 1035076828 ps
CPU time 6.24 seconds
Started May 21 02:52:53 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 213232 kb
Host smart-ffdaffc1-1bf5-4efd-b70b-531c19ecc813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303337720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2303337720
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.654846265
Short name T116
Test name
Test status
Simulation time 582891107 ps
CPU time 15.3 seconds
Started May 21 02:52:53 PM PDT 24
Finished May 21 02:53:11 PM PDT 24
Peak memory 261364 kb
Host smart-521348bd-6e9d-4b24-816f-1f2d2577d9f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654846265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.654846265
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2378415477
Short name T865
Test name
Test status
Simulation time 3640497193 ps
CPU time 53.99 seconds
Started May 21 02:52:54 PM PDT 24
Finished May 21 02:53:50 PM PDT 24
Peak memory 647832 kb
Host smart-c45c385d-50d9-48c1-b64a-78aee76eb966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378415477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2378415477
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.406501417
Short name T1241
Test name
Test status
Simulation time 10670506890 ps
CPU time 98.17 seconds
Started May 21 02:52:57 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 845360 kb
Host smart-388b9cab-59b9-4a63-9a58-4c7dfa9cc3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406501417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.406501417
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3145470373
Short name T1243
Test name
Test status
Simulation time 75037623 ps
CPU time 0.83 seconds
Started May 21 02:52:53 PM PDT 24
Finished May 21 02:52:56 PM PDT 24
Peak memory 204804 kb
Host smart-c2451d32-5e7f-4b80-ab97-b791876909ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145470373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3145470373
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1758772198
Short name T932
Test name
Test status
Simulation time 459368814 ps
CPU time 6.79 seconds
Started May 21 02:52:55 PM PDT 24
Finished May 21 02:53:04 PM PDT 24
Peak memory 204976 kb
Host smart-51d8c697-8242-45fe-b070-87adf5ffc5ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758772198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1758772198
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1942738439
Short name T1205
Test name
Test status
Simulation time 19900101833 ps
CPU time 155.83 seconds
Started May 21 02:52:54 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 1329644 kb
Host smart-0c630f23-4231-4d0a-bd02-5298e5f5313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942738439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1942738439
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2849121955
Short name T886
Test name
Test status
Simulation time 1396165967 ps
CPU time 15.6 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:53:20 PM PDT 24
Peak memory 205040 kb
Host smart-22f4ed29-904a-4b04-bc33-d9c92a529b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849121955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2849121955
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1656423151
Short name T60
Test name
Test status
Simulation time 2396748921 ps
CPU time 76.63 seconds
Started May 21 02:53:04 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 337296 kb
Host smart-06755ae4-78a1-468e-be0f-e94c22c2e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656423151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1656423151
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2636065280
Short name T121
Test name
Test status
Simulation time 31298912 ps
CPU time 0.65 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:53:05 PM PDT 24
Peak memory 204664 kb
Host smart-e4d30a58-a1bd-42e7-aae2-fcb001509b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636065280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2636065280
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1145347384
Short name T57
Test name
Test status
Simulation time 377869293 ps
CPU time 15.32 seconds
Started May 21 02:52:56 PM PDT 24
Finished May 21 02:53:13 PM PDT 24
Peak memory 238860 kb
Host smart-74b66a54-534e-4b9f-a915-6499c1042c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145347384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1145347384
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.528071031
Short name T488
Test name
Test status
Simulation time 1180946932 ps
CPU time 20.07 seconds
Started May 21 02:52:55 PM PDT 24
Finished May 21 02:53:17 PM PDT 24
Peak memory 343496 kb
Host smart-04a5b077-e8a3-45a3-856e-8b9673e8ae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528071031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.528071031
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1504102666
Short name T109
Test name
Test status
Simulation time 28727353622 ps
CPU time 159.79 seconds
Started May 21 02:52:58 PM PDT 24
Finished May 21 02:55:39 PM PDT 24
Peak memory 1028324 kb
Host smart-3f2a8cbe-91d2-4563-af55-4e79e5bcd557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504102666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1504102666
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.550368842
Short name T445
Test name
Test status
Simulation time 744401215 ps
CPU time 14.95 seconds
Started May 21 02:52:59 PM PDT 24
Finished May 21 02:53:15 PM PDT 24
Peak memory 213188 kb
Host smart-9ee27f6f-012d-4fcf-bba5-40349ed7c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550368842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.550368842
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1230505228
Short name T693
Test name
Test status
Simulation time 3122235199 ps
CPU time 4.26 seconds
Started May 21 02:53:02 PM PDT 24
Finished May 21 02:53:10 PM PDT 24
Peak memory 213344 kb
Host smart-a7696605-b3a4-4a94-bd55-b266a61de51f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230505228 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1230505228
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1143517863
Short name T83
Test name
Test status
Simulation time 10252999711 ps
CPU time 28.54 seconds
Started May 21 02:53:02 PM PDT 24
Finished May 21 02:53:34 PM PDT 24
Peak memory 349764 kb
Host smart-9d4b9443-e71b-4358-90ea-5b071b61839d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143517863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1143517863
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4185994911
Short name T422
Test name
Test status
Simulation time 10493754254 ps
CPU time 16.24 seconds
Started May 21 02:53:00 PM PDT 24
Finished May 21 02:53:20 PM PDT 24
Peak memory 321812 kb
Host smart-50b6d2bf-1337-40dd-85f2-25ad337f8e0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185994911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4185994911
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2117164686
Short name T314
Test name
Test status
Simulation time 954584453 ps
CPU time 2.85 seconds
Started May 21 02:53:04 PM PDT 24
Finished May 21 02:53:11 PM PDT 24
Peak memory 205088 kb
Host smart-462a3ca1-cbac-4b57-92f1-580550450876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117164686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2117164686
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.4255248292
Short name T928
Test name
Test status
Simulation time 625601434 ps
CPU time 3.69 seconds
Started May 21 02:53:00 PM PDT 24
Finished May 21 02:53:07 PM PDT 24
Peak memory 204988 kb
Host smart-e12c0d39-6e0e-4c78-87aa-2980fc56dad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255248292 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.4255248292
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.564577552
Short name T930
Test name
Test status
Simulation time 12583653745 ps
CPU time 237.11 seconds
Started May 21 02:53:02 PM PDT 24
Finished May 21 02:57:03 PM PDT 24
Peak memory 3136584 kb
Host smart-3cbbc870-3adf-4394-8066-3b2c65faffa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564577552 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.564577552
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.465882906
Short name T831
Test name
Test status
Simulation time 1955004994 ps
CPU time 14.48 seconds
Started May 21 02:52:57 PM PDT 24
Finished May 21 02:53:13 PM PDT 24
Peak memory 204940 kb
Host smart-150c33be-db45-4825-b1ad-e4e00e2d5774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465882906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.465882906
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.1470424914
Short name T822
Test name
Test status
Simulation time 43714560090 ps
CPU time 1289.44 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 03:14:34 PM PDT 24
Peak memory 7975820 kb
Host smart-2f816678-f171-4c8e-8de1-8990ddd26561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470424914 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.1470424914
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2664753644
Short name T1165
Test name
Test status
Simulation time 1269275517 ps
CPU time 24.11 seconds
Started May 21 02:52:54 PM PDT 24
Finished May 21 02:53:21 PM PDT 24
Peak memory 218600 kb
Host smart-dfe05311-671c-4fd7-85f9-56e5e47484ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664753644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2664753644
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3866218093
Short name T821
Test name
Test status
Simulation time 35384951592 ps
CPU time 169.59 seconds
Started May 21 02:52:55 PM PDT 24
Finished May 21 02:55:46 PM PDT 24
Peak memory 2211104 kb
Host smart-2e34ab33-ad46-4e74-9a1e-ce19d0704633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866218093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3866218093
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.714578210
Short name T1278
Test name
Test status
Simulation time 18948777285 ps
CPU time 91.86 seconds
Started May 21 02:53:00 PM PDT 24
Finished May 21 02:54:33 PM PDT 24
Peak memory 1127384 kb
Host smart-7469a2e9-a1c4-4ea0-ab54-33710c1b34f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714578210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.714578210
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1845919380
Short name T680
Test name
Test status
Simulation time 5107588894 ps
CPU time 7.11 seconds
Started May 21 02:53:03 PM PDT 24
Finished May 21 02:53:14 PM PDT 24
Peak memory 213360 kb
Host smart-0c5d77ba-f6fb-40dc-8f4c-f9afdebbe152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845919380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1845919380
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1191909626
Short name T783
Test name
Test status
Simulation time 37656798 ps
CPU time 0.66 seconds
Started May 21 02:53:16 PM PDT 24
Finished May 21 02:53:23 PM PDT 24
Peak memory 204648 kb
Host smart-ceb1b3b1-0fc1-4e48-a37f-89df4edce2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191909626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1191909626
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2871059512
Short name T718
Test name
Test status
Simulation time 226013883 ps
CPU time 1.7 seconds
Started May 21 02:53:07 PM PDT 24
Finished May 21 02:53:12 PM PDT 24
Peak memory 214324 kb
Host smart-d8f817f8-25b9-43ca-8d43-e25d31b0d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871059512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2871059512
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1143913257
Short name T1207
Test name
Test status
Simulation time 510347228 ps
CPU time 25.42 seconds
Started May 21 02:53:04 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 314292 kb
Host smart-a6af06bc-1793-456e-abf0-d3516be6a190
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143913257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1143913257
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.787948575
Short name T150
Test name
Test status
Simulation time 1126643229 ps
CPU time 30.61 seconds
Started May 21 02:53:06 PM PDT 24
Finished May 21 02:53:40 PM PDT 24
Peak memory 476532 kb
Host smart-236d48d2-246f-4c54-bf2c-48588f3366ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787948575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.787948575
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3483931416
Short name T1328
Test name
Test status
Simulation time 1979186157 ps
CPU time 129.46 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:55:14 PM PDT 24
Peak memory 559932 kb
Host smart-94e540b1-bf7b-4919-ad88-395b78c0365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483931416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3483931416
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1546956973
Short name T1307
Test name
Test status
Simulation time 217596693 ps
CPU time 1.01 seconds
Started May 21 02:53:02 PM PDT 24
Finished May 21 02:53:07 PM PDT 24
Peak memory 205008 kb
Host smart-997ebf28-fdce-4486-bc71-778c86074477
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546956973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1546956973
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3961763883
Short name T454
Test name
Test status
Simulation time 405929224 ps
CPU time 6.34 seconds
Started May 21 02:53:08 PM PDT 24
Finished May 21 02:53:19 PM PDT 24
Peak memory 221396 kb
Host smart-3e985106-9a80-44cb-aa01-b9c59e6b8feb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961763883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3961763883
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.3560156185
Short name T1146
Test name
Test status
Simulation time 9639329342 ps
CPU time 155.52 seconds
Started May 21 02:53:02 PM PDT 24
Finished May 21 02:55:41 PM PDT 24
Peak memory 1514036 kb
Host smart-86c1be8e-2213-4b76-8d64-f5d3266a9ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560156185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.3560156185
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3587483863
Short name T1282
Test name
Test status
Simulation time 1062450368 ps
CPU time 4.37 seconds
Started May 21 02:53:12 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 205020 kb
Host smart-a7505a67-28b9-46d7-ac17-4fabd7e4bed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587483863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3587483863
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2826429031
Short name T61
Test name
Test status
Simulation time 6457765148 ps
CPU time 85.65 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:54:44 PM PDT 24
Peak memory 421244 kb
Host smart-de432828-0cb2-4639-84fc-8f7547ed444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826429031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2826429031
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1497249625
Short name T6
Test name
Test status
Simulation time 79381312 ps
CPU time 0.66 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:53:05 PM PDT 24
Peak memory 204724 kb
Host smart-393b8ede-32ed-468a-8ce5-2fdf85b93266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497249625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1497249625
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3155559506
Short name T818
Test name
Test status
Simulation time 552889918 ps
CPU time 4.29 seconds
Started May 21 02:53:06 PM PDT 24
Finished May 21 02:53:14 PM PDT 24
Peak memory 229440 kb
Host smart-64a5f21d-0616-4a0d-aa39-ae8f96d13d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155559506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3155559506
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1522217479
Short name T141
Test name
Test status
Simulation time 14029704257 ps
CPU time 30.07 seconds
Started May 21 02:53:01 PM PDT 24
Finished May 21 02:53:35 PM PDT 24
Peak memory 326852 kb
Host smart-dfaf2c81-5748-4692-b0b2-3949518ce46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522217479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1522217479
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.391690286
Short name T724
Test name
Test status
Simulation time 17940708208 ps
CPU time 1959.49 seconds
Started May 21 02:53:08 PM PDT 24
Finished May 21 03:25:51 PM PDT 24
Peak memory 2615044 kb
Host smart-3fa34576-58cf-4eb9-aac0-620940d3d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391690286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.391690286
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3558558563
Short name T1158
Test name
Test status
Simulation time 1468718804 ps
CPU time 34.19 seconds
Started May 21 02:53:05 PM PDT 24
Finished May 21 02:53:43 PM PDT 24
Peak memory 213224 kb
Host smart-fb541fde-66cc-4c73-aaa2-0047a7c4d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558558563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3558558563
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1289439815
Short name T331
Test name
Test status
Simulation time 914819532 ps
CPU time 2.65 seconds
Started May 21 02:53:16 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 205020 kb
Host smart-9339059a-e7ee-42e4-9db1-f6ff185f50a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289439815 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1289439815
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3078869437
Short name T660
Test name
Test status
Simulation time 10513544865 ps
CPU time 8.15 seconds
Started May 21 02:53:09 PM PDT 24
Finished May 21 02:53:22 PM PDT 24
Peak memory 231636 kb
Host smart-0bd01596-b917-4a8c-8363-04d201a10ae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078869437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3078869437
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1764227744
Short name T619
Test name
Test status
Simulation time 10056356435 ps
CPU time 81.68 seconds
Started May 21 02:53:07 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 593380 kb
Host smart-379363ef-2751-40c7-9e6e-51221d8e4788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764227744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1764227744
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3077991213
Short name T22
Test name
Test status
Simulation time 556121263 ps
CPU time 2.12 seconds
Started May 21 02:53:16 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 205060 kb
Host smart-6e4c14ce-94e4-4adb-af4c-27ad69420890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077991213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3077991213
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.4071141400
Short name T1292
Test name
Test status
Simulation time 1746849406 ps
CPU time 4.62 seconds
Started May 21 02:53:06 PM PDT 24
Finished May 21 02:53:14 PM PDT 24
Peak memory 208732 kb
Host smart-b9b48664-994b-4335-8ffb-308d751bbef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071141400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.4071141400
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2700866701
Short name T463
Test name
Test status
Simulation time 29735585581 ps
CPU time 97.37 seconds
Started May 21 02:53:08 PM PDT 24
Finished May 21 02:54:49 PM PDT 24
Peak memory 1689700 kb
Host smart-39a86136-a1fd-4b84-b6a6-852d4801e112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700866701 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2700866701
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2577058417
Short name T149
Test name
Test status
Simulation time 1159831655 ps
CPU time 18.61 seconds
Started May 21 02:53:05 PM PDT 24
Finished May 21 02:53:27 PM PDT 24
Peak memory 204964 kb
Host smart-6142b60b-1ea7-45bf-b355-c50ab89131b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577058417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2577058417
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3560452318
Short name T725
Test name
Test status
Simulation time 5890354942 ps
CPU time 63.69 seconds
Started May 21 02:53:08 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 208556 kb
Host smart-9b2835ba-1c6f-4c5d-b31a-db25d05b2af2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560452318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3560452318
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3419198622
Short name T1281
Test name
Test status
Simulation time 31720559130 ps
CPU time 276.61 seconds
Started May 21 02:53:09 PM PDT 24
Finished May 21 02:57:51 PM PDT 24
Peak memory 2929148 kb
Host smart-222598d7-8280-42d8-8774-36120eac527a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419198622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3419198622
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1898430729
Short name T348
Test name
Test status
Simulation time 21248515547 ps
CPU time 51.57 seconds
Started May 21 02:53:06 PM PDT 24
Finished May 21 02:54:02 PM PDT 24
Peak memory 693452 kb
Host smart-f03567aa-1db5-4c85-9899-a7b318d6ff10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898430729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1898430729
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2750198846
Short name T318
Test name
Test status
Simulation time 4712225576 ps
CPU time 6.67 seconds
Started May 21 02:53:06 PM PDT 24
Finished May 21 02:53:16 PM PDT 24
Peak memory 213324 kb
Host smart-fe722a40-03c2-4796-8b63-2abe8a110dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750198846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2750198846
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2467063836
Short name T800
Test name
Test status
Simulation time 14882179 ps
CPU time 0.62 seconds
Started May 21 02:53:18 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 204664 kb
Host smart-04711bec-b017-485b-83eb-dd8b8b58d53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467063836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2467063836
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2941663709
Short name T1046
Test name
Test status
Simulation time 350208679 ps
CPU time 1.89 seconds
Started May 21 02:53:16 PM PDT 24
Finished May 21 02:53:25 PM PDT 24
Peak memory 213264 kb
Host smart-e5211fdc-2cdd-47c8-bdf8-9dbef40d0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941663709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2941663709
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2759488328
Short name T887
Test name
Test status
Simulation time 325595860 ps
CPU time 5.76 seconds
Started May 21 02:53:13 PM PDT 24
Finished May 21 02:53:27 PM PDT 24
Peak memory 268800 kb
Host smart-21db644f-f699-44ca-baf1-8937061d456b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759488328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2759488328
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.4284885767
Short name T699
Test name
Test status
Simulation time 16428526677 ps
CPU time 41.77 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:54:01 PM PDT 24
Peak memory 492200 kb
Host smart-5f47ff52-4409-42b2-981a-dd5cd9a543b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284885767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.4284885767
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1124530150
Short name T987
Test name
Test status
Simulation time 1722271083 ps
CPU time 128.59 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 628776 kb
Host smart-0504f954-f628-4068-944b-0372c17022fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124530150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1124530150
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.4186840237
Short name T614
Test name
Test status
Simulation time 555992931 ps
CPU time 1.18 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:53:21 PM PDT 24
Peak memory 204924 kb
Host smart-c3131cd3-5a9a-41c7-add8-ce2fb9670372
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186840237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.4186840237
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.870582356
Short name T572
Test name
Test status
Simulation time 202377152 ps
CPU time 9.51 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:53:29 PM PDT 24
Peak memory 204972 kb
Host smart-f9e4efcb-559b-4092-9f94-6faddcf198b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870582356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
870582356
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2552981748
Short name T272
Test name
Test status
Simulation time 2613553216 ps
CPU time 162.31 seconds
Started May 21 02:53:10 PM PDT 24
Finished May 21 02:56:01 PM PDT 24
Peak memory 798936 kb
Host smart-0b521f04-7034-428c-a46c-97a310cf3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552981748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2552981748
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3046725163
Short name T1290
Test name
Test status
Simulation time 427574714 ps
CPU time 5.57 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 02:53:35 PM PDT 24
Peak memory 205032 kb
Host smart-d5900132-bb6a-43e3-83cd-8598f2a20412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046725163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3046725163
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.4082257175
Short name T120
Test name
Test status
Simulation time 95384756 ps
CPU time 0.65 seconds
Started May 21 02:53:10 PM PDT 24
Finished May 21 02:53:18 PM PDT 24
Peak memory 204716 kb
Host smart-cea0291a-7830-418c-ac41-d4f96829b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082257175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.4082257175
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.1527106507
Short name T40
Test name
Test status
Simulation time 3929889252 ps
CPU time 156.78 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 214204 kb
Host smart-b6fa415b-0ff8-4faa-87f3-3a325414d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527106507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1527106507
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4039656817
Short name T900
Test name
Test status
Simulation time 3842277580 ps
CPU time 46.56 seconds
Started May 21 02:53:12 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 294712 kb
Host smart-2bd6f29b-8cbc-45aa-8be1-c56678008d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039656817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4039656817
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.4208660185
Short name T940
Test name
Test status
Simulation time 26349148772 ps
CPU time 113.77 seconds
Started May 21 02:53:11 PM PDT 24
Finished May 21 02:55:14 PM PDT 24
Peak memory 594316 kb
Host smart-c2f531b2-a5ff-4625-96ff-8b4fa5a67e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208660185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.4208660185
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.815364831
Short name T1054
Test name
Test status
Simulation time 374965411 ps
CPU time 7.2 seconds
Started May 21 02:53:16 PM PDT 24
Finished May 21 02:53:30 PM PDT 24
Peak memory 213216 kb
Host smart-31079a51-9604-40d1-9425-2d51fcf28bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815364831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.815364831
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1294643330
Short name T453
Test name
Test status
Simulation time 505874728 ps
CPU time 2.93 seconds
Started May 21 02:53:18 PM PDT 24
Finished May 21 02:53:28 PM PDT 24
Peak memory 205004 kb
Host smart-1ba7cd30-462b-40db-94be-b818363bb6f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294643330 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1294643330
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1906674421
Short name T616
Test name
Test status
Simulation time 10053190165 ps
CPU time 67.37 seconds
Started May 21 02:53:19 PM PDT 24
Finished May 21 02:54:32 PM PDT 24
Peak memory 397980 kb
Host smart-5d476b1d-5157-432a-a914-7505c76bab36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906674421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1906674421
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1918450932
Short name T813
Test name
Test status
Simulation time 10111539955 ps
CPU time 80.12 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:54:43 PM PDT 24
Peak memory 493352 kb
Host smart-2e4628b9-2e05-4aa2-8fd9-66412010e773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918450932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1918450932
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1448983589
Short name T347
Test name
Test status
Simulation time 1046592669 ps
CPU time 3.4 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:53:27 PM PDT 24
Peak memory 205056 kb
Host smart-b662a891-ece0-4d84-aeb8-ed829c0e9d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448983589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1448983589
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3705391349
Short name T476
Test name
Test status
Simulation time 2903105735 ps
CPU time 4.4 seconds
Started May 21 02:53:19 PM PDT 24
Finished May 21 02:53:29 PM PDT 24
Peak memory 205184 kb
Host smart-d1c1bc16-81d7-4731-8018-8eb8abdbfe45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705391349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3705391349
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3387942691
Short name T232
Test name
Test status
Simulation time 19183797917 ps
CPU time 20.76 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:53:45 PM PDT 24
Peak memory 472908 kb
Host smart-a56b9286-7d9e-4256-bef3-d6b2ff7f6aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387942691 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3387942691
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.530805698
Short name T850
Test name
Test status
Simulation time 663289288 ps
CPU time 27.24 seconds
Started May 21 02:53:12 PM PDT 24
Finished May 21 02:53:47 PM PDT 24
Peak memory 204940 kb
Host smart-65ebd3c6-ceb8-4bc0-8b3a-d49fe8f143a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530805698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.530805698
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.33624052
Short name T363
Test name
Test status
Simulation time 1185092002 ps
CPU time 9.49 seconds
Started May 21 02:53:18 PM PDT 24
Finished May 21 02:53:34 PM PDT 24
Peak memory 208328 kb
Host smart-23b6c208-0821-4ab0-bcd3-4cc10c37c8e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stress_rd.33624052
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.4013975251
Short name T1284
Test name
Test status
Simulation time 29046677967 ps
CPU time 171.93 seconds
Started May 21 02:53:13 PM PDT 24
Finished May 21 02:56:13 PM PDT 24
Peak memory 2281644 kb
Host smart-efc7a7c0-7b45-4396-b548-f2a542479baa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013975251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.4013975251
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2360718023
Short name T1163
Test name
Test status
Simulation time 3589321657 ps
CPU time 9.76 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:53:34 PM PDT 24
Peak memory 282000 kb
Host smart-04a8b14f-3471-4c5f-a7a3-6839e6c3c22e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360718023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2360718023
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2604337037
Short name T438
Test name
Test status
Simulation time 2764936331 ps
CPU time 7.45 seconds
Started May 21 02:53:17 PM PDT 24
Finished May 21 02:53:31 PM PDT 24
Peak memory 219572 kb
Host smart-cb685206-9dd2-4342-89bf-94f0e5a25529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604337037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2604337037
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3020592926
Short name T838
Test name
Test status
Simulation time 55062672 ps
CPU time 0.61 seconds
Started May 21 02:53:27 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 204652 kb
Host smart-5b446712-db9c-4156-9cef-ecb423fb5a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020592926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3020592926
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1346207786
Short name T1233
Test name
Test status
Simulation time 66996148 ps
CPU time 1.73 seconds
Started May 21 02:53:25 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 213332 kb
Host smart-e431b738-395a-4f25-b36f-b5efc729cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346207786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1346207786
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2247521180
Short name T1283
Test name
Test status
Simulation time 161559163 ps
CPU time 3.43 seconds
Started May 21 02:53:25 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 226840 kb
Host smart-d7be23e1-5db5-40d3-82c1-cc464372225a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247521180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2247521180
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1332027305
Short name T356
Test name
Test status
Simulation time 7634817015 ps
CPU time 54.77 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:54:22 PM PDT 24
Peak memory 624468 kb
Host smart-c3b452e7-46ad-49bf-a000-a3a82fdaaeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332027305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1332027305
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2232155793
Short name T1279
Test name
Test status
Simulation time 6519751279 ps
CPU time 168.47 seconds
Started May 21 02:53:20 PM PDT 24
Finished May 21 02:56:14 PM PDT 24
Peak memory 680988 kb
Host smart-5f158169-208b-4d11-a193-9a71d15817bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232155793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2232155793
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3131191273
Short name T204
Test name
Test status
Simulation time 1049614937 ps
CPU time 0.99 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 02:53:30 PM PDT 24
Peak memory 204780 kb
Host smart-2d8be911-f9d3-410e-bb62-6820f9801a93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131191273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3131191273
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.871491164
Short name T1156
Test name
Test status
Simulation time 158563652 ps
CPU time 4.81 seconds
Started May 21 02:53:24 PM PDT 24
Finished May 21 02:53:35 PM PDT 24
Peak memory 233672 kb
Host smart-5d169500-60bc-44c9-b8fc-c6a137185bf1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871491164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
871491164
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1255110715
Short name T551
Test name
Test status
Simulation time 5488850916 ps
CPU time 127.37 seconds
Started May 21 02:53:20 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 1202932 kb
Host smart-40519020-5476-465f-ae26-3d09ecc94d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255110715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1255110715
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1440201685
Short name T450
Test name
Test status
Simulation time 532108316 ps
CPU time 6.33 seconds
Started May 21 02:53:28 PM PDT 24
Finished May 21 02:53:38 PM PDT 24
Peak memory 204984 kb
Host smart-0941c8e8-b768-401a-9bf1-24088dc33e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440201685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1440201685
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2359327974
Short name T993
Test name
Test status
Simulation time 6296842186 ps
CPU time 29.18 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:54:01 PM PDT 24
Peak memory 352232 kb
Host smart-b4e2f2ee-01aa-41bc-b19a-b38eda993756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359327974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2359327974
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3237490836
Short name T889
Test name
Test status
Simulation time 18353106 ps
CPU time 0.71 seconds
Started May 21 02:53:18 PM PDT 24
Finished May 21 02:53:26 PM PDT 24
Peak memory 204740 kb
Host smart-cb89a398-9c26-4568-9f15-bb797a775d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237490836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3237490836
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.948018747
Short name T1038
Test name
Test status
Simulation time 27669973016 ps
CPU time 285.19 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:58:13 PM PDT 24
Peak memory 214360 kb
Host smart-85eec8df-0d7c-4116-9439-45cd9d355aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948018747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.948018747
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3617938313
Short name T860
Test name
Test status
Simulation time 5524051377 ps
CPU time 20.87 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:53:49 PM PDT 24
Peak memory 262288 kb
Host smart-303b749a-4425-4116-b4aa-996e9bde3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617938313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3617938313
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3899894384
Short name T1172
Test name
Test status
Simulation time 2895524520 ps
CPU time 11.79 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 02:53:41 PM PDT 24
Peak memory 217472 kb
Host smart-4735947f-0fbe-4676-8c6b-40a0a1b06231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899894384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3899894384
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.886786808
Short name T722
Test name
Test status
Simulation time 2565388515 ps
CPU time 3.52 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:53:31 PM PDT 24
Peak memory 205140 kb
Host smart-977a462f-ddb8-4a48-a649-fdaaf84d48a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886786808 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.886786808
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3733091317
Short name T595
Test name
Test status
Simulation time 10098676669 ps
CPU time 70.6 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 02:54:39 PM PDT 24
Peak memory 461200 kb
Host smart-a43078d2-bf72-43c2-91d0-f0c48179b6cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733091317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3733091317
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2895970748
Short name T683
Test name
Test status
Simulation time 3429715783 ps
CPU time 3.04 seconds
Started May 21 02:53:25 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 205140 kb
Host smart-4a05be66-2ef9-44c3-9318-9d4efb9e21c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895970748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2895970748
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3213496547
Short name T1343
Test name
Test status
Simulation time 8171513698 ps
CPU time 5.62 seconds
Started May 21 02:53:27 PM PDT 24
Finished May 21 02:53:37 PM PDT 24
Peak memory 205192 kb
Host smart-d61bdb46-d21d-4cdf-8b3e-4b57b114a9d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213496547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3213496547
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2703610348
Short name T1245
Test name
Test status
Simulation time 19512300069 ps
CPU time 44.72 seconds
Started May 21 02:53:25 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 1000968 kb
Host smart-b324697a-423c-4c75-80bd-97342df7aa38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703610348 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2703610348
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3467328922
Short name T1143
Test name
Test status
Simulation time 942722951 ps
CPU time 36.38 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 204964 kb
Host smart-0445e0fc-7f8e-44d1-8bd6-ab43be7d2eec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467328922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3467328922
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2027952407
Short name T1010
Test name
Test status
Simulation time 551636166 ps
CPU time 9.07 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:53:37 PM PDT 24
Peak memory 211264 kb
Host smart-2444e492-1488-4cdb-8d47-19116dd8dfa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027952407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2027952407
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2680350858
Short name T369
Test name
Test status
Simulation time 42697509234 ps
CPU time 707.67 seconds
Started May 21 02:53:23 PM PDT 24
Finished May 21 03:05:17 PM PDT 24
Peak memory 5649448 kb
Host smart-f4145117-ec2a-4073-9698-e78488483191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680350858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2680350858
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2420786256
Short name T408
Test name
Test status
Simulation time 6046023755 ps
CPU time 85.02 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 570088 kb
Host smart-6ec6d566-61c9-4e97-b7ca-78fa73304687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420786256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2420786256
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3798013533
Short name T312
Test name
Test status
Simulation time 2418434100 ps
CPU time 6.52 seconds
Started May 21 02:53:22 PM PDT 24
Finished May 21 02:53:34 PM PDT 24
Peak memory 205180 kb
Host smart-6b806e7f-e8f9-4220-8877-ab6fbd16baee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798013533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3798013533
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3462536589
Short name T1254
Test name
Test status
Simulation time 23354867 ps
CPU time 0.6 seconds
Started May 21 02:53:35 PM PDT 24
Finished May 21 02:53:38 PM PDT 24
Peak memory 204636 kb
Host smart-84c0770e-5934-4507-9878-24749256d871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462536589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3462536589
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.550759604
Short name T402
Test name
Test status
Simulation time 439247980 ps
CPU time 1.46 seconds
Started May 21 02:53:27 PM PDT 24
Finished May 21 02:53:32 PM PDT 24
Peak memory 213300 kb
Host smart-b121c42a-8231-4850-a768-0293ac009389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550759604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.550759604
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2410972428
Short name T394
Test name
Test status
Simulation time 511851645 ps
CPU time 10.98 seconds
Started May 21 02:53:31 PM PDT 24
Finished May 21 02:53:45 PM PDT 24
Peak memory 308824 kb
Host smart-d265df55-de4b-4fe8-8e97-3a75c1af738b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410972428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2410972428
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2647751286
Short name T1089
Test name
Test status
Simulation time 2668807280 ps
CPU time 201.85 seconds
Started May 21 02:53:27 PM PDT 24
Finished May 21 02:56:53 PM PDT 24
Peak memory 842408 kb
Host smart-a0693e63-ba62-4f79-af54-e31d2b44466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647751286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2647751286
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3633948414
Short name T852
Test name
Test status
Simulation time 21460476173 ps
CPU time 42.24 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 481600 kb
Host smart-3414d618-c823-4fcd-96e8-824669fbfe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633948414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3633948414
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.542816398
Short name T906
Test name
Test status
Simulation time 265223700 ps
CPU time 1.1 seconds
Started May 21 02:53:31 PM PDT 24
Finished May 21 02:53:35 PM PDT 24
Peak memory 205036 kb
Host smart-87258c19-e072-44b1-87ff-9c72a0770db8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542816398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.542816398
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3744555486
Short name T620
Test name
Test status
Simulation time 640940950 ps
CPU time 3.5 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:53:36 PM PDT 24
Peak memory 204964 kb
Host smart-e071cad4-febd-42b5-b6ce-ad59d366a342
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744555486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3744555486
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2205489016
Short name T1022
Test name
Test status
Simulation time 10431110255 ps
CPU time 148.63 seconds
Started May 21 02:53:31 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 689236 kb
Host smart-2ba1ffa2-e86a-4928-9baf-75e5f0b330db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205489016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2205489016
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2259493443
Short name T732
Test name
Test status
Simulation time 848257076 ps
CPU time 3.04 seconds
Started May 21 02:53:37 PM PDT 24
Finished May 21 02:53:43 PM PDT 24
Peak memory 204956 kb
Host smart-695cb4fb-3a89-434f-a5ac-a5fa9ddf8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259493443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2259493443
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2881897336
Short name T641
Test name
Test status
Simulation time 4436396655 ps
CPU time 32.09 seconds
Started May 21 02:53:34 PM PDT 24
Finished May 21 02:54:09 PM PDT 24
Peak memory 439276 kb
Host smart-836b55f9-eb5f-4cbe-9744-83d3e7256fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881897336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2881897336
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2988364033
Short name T119
Test name
Test status
Simulation time 87270283 ps
CPU time 0.72 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:53:33 PM PDT 24
Peak memory 204648 kb
Host smart-7b230476-4825-4ad5-80ae-98d6b7a75ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988364033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2988364033
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.4044839990
Short name T764
Test name
Test status
Simulation time 12815100773 ps
CPU time 162.04 seconds
Started May 21 02:53:31 PM PDT 24
Finished May 21 02:56:16 PM PDT 24
Peak memory 601328 kb
Host smart-b3264fa3-edf8-4cc0-983e-eaa045036d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044839990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.4044839990
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2269314985
Short name T1148
Test name
Test status
Simulation time 9217129601 ps
CPU time 34.62 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 323896 kb
Host smart-7685e95d-f737-4c50-99ee-8ffb69029b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269314985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2269314985
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3049387158
Short name T105
Test name
Test status
Simulation time 30291039238 ps
CPU time 203.9 seconds
Started May 21 02:53:30 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 897336 kb
Host smart-f68eecd2-2c79-4b95-bc7e-587adeff352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049387158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3049387158
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.4081436846
Short name T1339
Test name
Test status
Simulation time 824042162 ps
CPU time 36.05 seconds
Started May 21 02:53:30 PM PDT 24
Finished May 21 02:54:09 PM PDT 24
Peak memory 213248 kb
Host smart-b76a2ffe-0353-414b-871e-1e4a38ee0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081436846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.4081436846
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.733355057
Short name T390
Test name
Test status
Simulation time 732485756 ps
CPU time 2.26 seconds
Started May 21 02:53:35 PM PDT 24
Finished May 21 02:53:41 PM PDT 24
Peak memory 204980 kb
Host smart-e388ac92-219a-445c-ad57-8bbc5d2f2f36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733355057 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.733355057
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1731789078
Short name T1280
Test name
Test status
Simulation time 10091428577 ps
CPU time 14.59 seconds
Started May 21 02:53:34 PM PDT 24
Finished May 21 02:53:51 PM PDT 24
Peak memory 253496 kb
Host smart-ca01b383-3402-46cb-934d-d8071026b946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731789078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1731789078
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2531869081
Short name T401
Test name
Test status
Simulation time 10032369419 ps
CPU time 71.97 seconds
Started May 21 02:53:35 PM PDT 24
Finished May 21 02:54:49 PM PDT 24
Peak memory 447028 kb
Host smart-b1ac2009-dbf0-40fd-93b8-048930ea80fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531869081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2531869081
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.902355645
Short name T1318
Test name
Test status
Simulation time 612611756 ps
CPU time 2.3 seconds
Started May 21 02:53:35 PM PDT 24
Finished May 21 02:53:41 PM PDT 24
Peak memory 205116 kb
Host smart-9c8bdf2e-502b-441d-b21c-2eb71b0b6968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902355645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.902355645
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1751346462
Short name T1149
Test name
Test status
Simulation time 5604561763 ps
CPU time 6.98 seconds
Started May 21 02:53:33 PM PDT 24
Finished May 21 02:53:43 PM PDT 24
Peak memory 214464 kb
Host smart-7f8a2af0-30b9-4795-b308-1dab7aff48a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751346462 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1751346462
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1358635794
Short name T627
Test name
Test status
Simulation time 13122328511 ps
CPU time 102.89 seconds
Started May 21 02:53:34 PM PDT 24
Finished May 21 02:55:20 PM PDT 24
Peak memory 1543216 kb
Host smart-1728b640-004a-4f33-b550-78b99a41a55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358635794 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1358635794
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3963170085
Short name T945
Test name
Test status
Simulation time 1593471344 ps
CPU time 34.74 seconds
Started May 21 02:53:30 PM PDT 24
Finished May 21 02:54:08 PM PDT 24
Peak memory 204932 kb
Host smart-fbb8231b-ef0d-4dd5-9acb-5998a16795ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963170085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3963170085
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2575238926
Short name T507
Test name
Test status
Simulation time 11101436598 ps
CPU time 42.53 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 205404 kb
Host smart-34283c65-fc07-407d-a01c-a29d0fb6d2c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575238926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2575238926
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2570558968
Short name T1140
Test name
Test status
Simulation time 32094227936 ps
CPU time 45.58 seconds
Started May 21 02:53:28 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 858008 kb
Host smart-6575f032-f94c-43f5-93c0-932bad743ab1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570558968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2570558968
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.4152079323
Short name T339
Test name
Test status
Simulation time 16491949847 ps
CPU time 64.97 seconds
Started May 21 02:53:29 PM PDT 24
Finished May 21 02:54:37 PM PDT 24
Peak memory 893424 kb
Host smart-e40c3ec0-eba1-4e84-a3f5-9ea97ee48708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152079323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.4152079323
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.4282577601
Short name T249
Test name
Test status
Simulation time 17473582213 ps
CPU time 7.99 seconds
Started May 21 02:53:37 PM PDT 24
Finished May 21 02:53:49 PM PDT 24
Peak memory 221352 kb
Host smart-b6fd92e8-8f29-472a-8415-5ce2a4552a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282577601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.4282577601
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3092565337
Short name T589
Test name
Test status
Simulation time 43075663 ps
CPU time 0.63 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:53:50 PM PDT 24
Peak memory 204652 kb
Host smart-6121f6b7-5837-446d-bdb1-9df84266273f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092565337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3092565337
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.817451208
Short name T958
Test name
Test status
Simulation time 596004043 ps
CPU time 5.17 seconds
Started May 21 02:53:38 PM PDT 24
Finished May 21 02:53:47 PM PDT 24
Peak memory 235584 kb
Host smart-c591d5f0-9178-4410-8711-b9bd9bc85628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817451208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.817451208
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.627324057
Short name T424
Test name
Test status
Simulation time 1606830224 ps
CPU time 20.94 seconds
Started May 21 02:53:36 PM PDT 24
Finished May 21 02:54:00 PM PDT 24
Peak memory 269920 kb
Host smart-75bbc309-4517-47ac-9da3-590716d6b9f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627324057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.627324057
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1142548248
Short name T1261
Test name
Test status
Simulation time 2785190452 ps
CPU time 88.97 seconds
Started May 21 02:53:38 PM PDT 24
Finished May 21 02:55:11 PM PDT 24
Peak memory 830496 kb
Host smart-44526eed-a597-4350-820b-2d6bc0858bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142548248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1142548248
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3118147725
Short name T736
Test name
Test status
Simulation time 2841647988 ps
CPU time 88.17 seconds
Started May 21 02:53:37 PM PDT 24
Finished May 21 02:55:09 PM PDT 24
Peak memory 819552 kb
Host smart-497f37aa-54fc-4eb9-9a6e-3b471a0d748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118147725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3118147725
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2877732928
Short name T561
Test name
Test status
Simulation time 442233405 ps
CPU time 1.06 seconds
Started May 21 02:53:36 PM PDT 24
Finished May 21 02:53:41 PM PDT 24
Peak memory 204968 kb
Host smart-037a9bbb-e11d-406c-8644-d991e8f8eea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877732928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2877732928
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.114188329
Short name T497
Test name
Test status
Simulation time 781297729 ps
CPU time 4.96 seconds
Started May 21 02:53:37 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 238368 kb
Host smart-742777fb-b143-4461-90e5-c098a5e97b06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114188329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
114188329
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3498005736
Short name T745
Test name
Test status
Simulation time 76008887162 ps
CPU time 452.04 seconds
Started May 21 02:53:35 PM PDT 24
Finished May 21 03:01:09 PM PDT 24
Peak memory 1557376 kb
Host smart-de06b5cf-db10-4934-8947-60b75f29869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498005736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3498005736
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2057364203
Short name T588
Test name
Test status
Simulation time 2119673227 ps
CPU time 4.48 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:53:54 PM PDT 24
Peak memory 205016 kb
Host smart-ce352efd-ad5c-4a7a-88a2-8416eae5f591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057364203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2057364203
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.1044794239
Short name T59
Test name
Test status
Simulation time 5565412874 ps
CPU time 84.05 seconds
Started May 21 02:53:39 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 378024 kb
Host smart-6fb7e0f6-4d89-4ff3-b783-1a2a7dcf65e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044794239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.1044794239
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2332324286
Short name T704
Test name
Test status
Simulation time 17772509 ps
CPU time 0.66 seconds
Started May 21 02:53:36 PM PDT 24
Finished May 21 02:53:39 PM PDT 24
Peak memory 204724 kb
Host smart-77e09dd8-77a7-4ed4-8fd7-31c09451c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332324286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2332324286
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4016534060
Short name T1338
Test name
Test status
Simulation time 12089563480 ps
CPU time 726.27 seconds
Started May 21 02:53:36 PM PDT 24
Finished May 21 03:05:46 PM PDT 24
Peak memory 2648740 kb
Host smart-b4da4597-d8fb-4a2b-8df0-15094d30e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016534060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4016534060
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2343445935
Short name T466
Test name
Test status
Simulation time 7726962244 ps
CPU time 62.58 seconds
Started May 21 02:53:38 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 286120 kb
Host smart-509f3ebd-282f-4676-8017-32b0d2e6fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343445935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2343445935
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2302151151
Short name T650
Test name
Test status
Simulation time 3271127641 ps
CPU time 37.24 seconds
Started May 21 02:53:36 PM PDT 24
Finished May 21 02:54:17 PM PDT 24
Peak memory 213328 kb
Host smart-7dd1844d-c646-46ad-ba76-f65f13685cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302151151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2302151151
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3531460150
Short name T166
Test name
Test status
Simulation time 2435090157 ps
CPU time 3.15 seconds
Started May 21 02:53:40 PM PDT 24
Finished May 21 02:53:47 PM PDT 24
Peak memory 205064 kb
Host smart-06588a9c-6673-4a68-8e3e-bb517e58993a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531460150 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3531460150
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3620831914
Short name T998
Test name
Test status
Simulation time 10102550600 ps
CPU time 72.19 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:55:01 PM PDT 24
Peak memory 564476 kb
Host smart-a970e1de-a979-441c-9609-6effb1fb0f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620831914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3620831914
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1352591030
Short name T1097
Test name
Test status
Simulation time 426636791 ps
CPU time 2.7 seconds
Started May 21 02:53:39 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 205012 kb
Host smart-b8fd1337-7912-4e2a-a14d-ce2d6540972b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352591030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1352591030
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1325691064
Short name T1127
Test name
Test status
Simulation time 6375753284 ps
CPU time 8.71 seconds
Started May 21 02:53:43 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 220260 kb
Host smart-74eaba6d-59ee-4a4c-9f7e-4f8c427c9442
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325691064 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1325691064
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1721017424
Short name T797
Test name
Test status
Simulation time 18288706598 ps
CPU time 105.39 seconds
Started May 21 02:53:42 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 1505796 kb
Host smart-212e8def-ea6e-4513-a578-1940b7ceb5d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721017424 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1721017424
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1003944905
Short name T1139
Test name
Test status
Simulation time 4558145966 ps
CPU time 17.29 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 205116 kb
Host smart-524301c0-e852-4a85-90ab-25184a384ebf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003944905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1003944905
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.898943222
Short name T1073
Test name
Test status
Simulation time 8719410050 ps
CPU time 28.24 seconds
Started May 21 02:53:43 PM PDT 24
Finished May 21 02:54:16 PM PDT 24
Peak memory 223808 kb
Host smart-ac4577a2-75e4-47d2-b804-de8888d348ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898943222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.898943222
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1579534835
Short name T115
Test name
Test status
Simulation time 8357997158 ps
CPU time 15.57 seconds
Started May 21 02:53:39 PM PDT 24
Finished May 21 02:53:59 PM PDT 24
Peak memory 205144 kb
Host smart-0edd56ba-ceb6-4100-8864-13bc2cc4c881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579534835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1579534835
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.4013546253
Short name T1264
Test name
Test status
Simulation time 29109540855 ps
CPU time 138.34 seconds
Started May 21 02:53:43 PM PDT 24
Finished May 21 02:56:07 PM PDT 24
Peak memory 1155608 kb
Host smart-748ccc78-f217-41a3-abaa-00c6fb73f0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013546253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.4013546253
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2191617442
Short name T501
Test name
Test status
Simulation time 1461973113 ps
CPU time 7.14 seconds
Started May 21 02:53:41 PM PDT 24
Finished May 21 02:53:52 PM PDT 24
Peak memory 213188 kb
Host smart-4069079d-6588-4335-9179-11961444df45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191617442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2191617442
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.4149873134
Short name T832
Test name
Test status
Simulation time 16125932 ps
CPU time 0.67 seconds
Started May 21 02:53:51 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 204660 kb
Host smart-d95ba07c-a3df-4862-84cf-9490bd2297e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149873134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.4149873134
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.358749306
Short name T762
Test name
Test status
Simulation time 279142002 ps
CPU time 5.11 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:53:55 PM PDT 24
Peak memory 234424 kb
Host smart-853c49c4-11b2-4792-a86a-53637ae996b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358749306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.358749306
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3723734444
Short name T1081
Test name
Test status
Simulation time 300829844 ps
CPU time 15.6 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 264208 kb
Host smart-74dd1e06-0e59-4cbf-bfe6-2ce400022c4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723734444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3723734444
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2672467062
Short name T1212
Test name
Test status
Simulation time 3444919098 ps
CPU time 122.95 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 953572 kb
Host smart-3d67fef4-966b-4fd2-9a09-69243bd55256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672467062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2672467062
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2416293868
Short name T1227
Test name
Test status
Simulation time 8053432814 ps
CPU time 130.29 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:56:00 PM PDT 24
Peak memory 644692 kb
Host smart-16a7b49e-49b0-47c0-9ebe-503ebcc99df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416293868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2416293868
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2534021119
Short name T113
Test name
Test status
Simulation time 517818667 ps
CPU time 1.01 seconds
Started May 21 02:53:40 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 204760 kb
Host smart-a68c55ab-7ddf-424e-ac60-72dcb21ce682
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534021119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2534021119
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2117482318
Short name T1286
Test name
Test status
Simulation time 200124252 ps
CPU time 10.92 seconds
Started May 21 02:53:41 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 240436 kb
Host smart-e31cc4a0-220f-498f-a98a-4428620875d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117482318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2117482318
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.225389042
Short name T1202
Test name
Test status
Simulation time 17670796117 ps
CPU time 74.41 seconds
Started May 21 02:53:43 PM PDT 24
Finished May 21 02:55:03 PM PDT 24
Peak memory 998016 kb
Host smart-1e02f0d1-d379-452a-bbd7-db61e1719655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225389042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.225389042
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3320228644
Short name T1273
Test name
Test status
Simulation time 4679874535 ps
CPU time 29.41 seconds
Started May 21 02:53:51 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 205096 kb
Host smart-cdbf07f5-d188-4d6d-a47c-4d11025b5112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320228644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3320228644
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1701475199
Short name T481
Test name
Test status
Simulation time 2099423214 ps
CPU time 97.47 seconds
Started May 21 02:53:51 PM PDT 24
Finished May 21 02:55:33 PM PDT 24
Peak memory 390392 kb
Host smart-f4e31074-3f6f-48ec-8687-73be4ab2bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701475199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1701475199
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2455634578
Short name T433
Test name
Test status
Simulation time 94916667 ps
CPU time 0.68 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:53:50 PM PDT 24
Peak memory 204712 kb
Host smart-37eb91e2-0229-45f6-a492-e97dd97ec8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455634578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2455634578
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2305485675
Short name T820
Test name
Test status
Simulation time 2553960554 ps
CPU time 17.05 seconds
Started May 21 02:53:40 PM PDT 24
Finished May 21 02:54:01 PM PDT 24
Peak memory 213284 kb
Host smart-9c3034be-f182-4c37-9314-fe76ceaed15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305485675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2305485675
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.406135176
Short name T1216
Test name
Test status
Simulation time 1377444924 ps
CPU time 25.65 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 302288 kb
Host smart-54760dd6-c3ec-43c3-a2b5-ebce2fb52715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406135176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.406135176
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.861560444
Short name T1301
Test name
Test status
Simulation time 90879746888 ps
CPU time 1973.37 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 03:26:44 PM PDT 24
Peak memory 5074444 kb
Host smart-1c4c6741-cfed-44bc-a306-17870b711872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861560444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.861560444
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1142613287
Short name T256
Test name
Test status
Simulation time 3481242635 ps
CPU time 36.32 seconds
Started May 21 02:53:46 PM PDT 24
Finished May 21 02:54:27 PM PDT 24
Peak memory 213328 kb
Host smart-15b8f454-0ac1-486f-be7a-51acdfb5e066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142613287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1142613287
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3459427735
Short name T25
Test name
Test status
Simulation time 666542607 ps
CPU time 3.48 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:53:54 PM PDT 24
Peak memory 205032 kb
Host smart-0934813d-f9e1-4ec1-ab70-17f8d9cd407f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459427735 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3459427735
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.377454344
Short name T1313
Test name
Test status
Simulation time 10433885850 ps
CPU time 7.69 seconds
Started May 21 02:53:47 PM PDT 24
Finished May 21 02:54:00 PM PDT 24
Peak memory 224068 kb
Host smart-66307380-64d2-4dd1-ab92-736ed5b23aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377454344 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.377454344
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.850043300
Short name T426
Test name
Test status
Simulation time 10592452718 ps
CPU time 5.01 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:53:55 PM PDT 24
Peak memory 240788 kb
Host smart-2346052f-14b3-40f9-9b2e-334cfc9b367a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850043300 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.850043300
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2108346143
Short name T964
Test name
Test status
Simulation time 1541257663 ps
CPU time 2.75 seconds
Started May 21 02:53:50 PM PDT 24
Finished May 21 02:53:57 PM PDT 24
Peak memory 205012 kb
Host smart-56b90ec4-e1f4-49a7-8623-adea93d54fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108346143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2108346143
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1905443340
Short name T921
Test name
Test status
Simulation time 2663829057 ps
CPU time 5.45 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 213300 kb
Host smart-c329285a-74a7-45c7-9926-0f60536d3bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905443340 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1905443340
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4226669290
Short name T563
Test name
Test status
Simulation time 5735802974 ps
CPU time 21.58 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:54:12 PM PDT 24
Peak memory 785480 kb
Host smart-a3285b6e-dabd-4fcb-b1bc-a840ee86ae68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226669290 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4226669290
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2228614071
Short name T787
Test name
Test status
Simulation time 3296261613 ps
CPU time 14.49 seconds
Started May 21 02:53:47 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 205056 kb
Host smart-a63cd523-b9d5-49d2-ad27-c9188d62f2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228614071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2228614071
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.4189937809
Short name T533
Test name
Test status
Simulation time 615797316 ps
CPU time 25.21 seconds
Started May 21 02:53:45 PM PDT 24
Finished May 21 02:54:16 PM PDT 24
Peak memory 204968 kb
Host smart-b204cff1-3225-449f-bdc8-df7b37dc63b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189937809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.4189937809
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.62976736
Short name T358
Test name
Test status
Simulation time 48002317941 ps
CPU time 189.72 seconds
Started May 21 02:53:46 PM PDT 24
Finished May 21 02:57:02 PM PDT 24
Peak memory 2287320 kb
Host smart-e4b82a3d-203a-42c2-938b-6b3a6f3a2920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62976736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stress_wr.62976736
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1478090343
Short name T664
Test name
Test status
Simulation time 32842050193 ps
CPU time 278.24 seconds
Started May 21 02:53:46 PM PDT 24
Finished May 21 02:58:29 PM PDT 24
Peak memory 1955260 kb
Host smart-7915cf91-6d76-4d81-9078-5a9d6d928f5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478090343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1478090343
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.154280073
Short name T295
Test name
Test status
Simulation time 1347669271 ps
CPU time 7.52 seconds
Started May 21 02:53:44 PM PDT 24
Finished May 21 02:53:57 PM PDT 24
Peak memory 210548 kb
Host smart-f8c66ebd-7b96-4d37-a53c-3d4b7aefe10e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154280073 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.154280073
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1739972188
Short name T618
Test name
Test status
Simulation time 20659413 ps
CPU time 0.62 seconds
Started May 21 02:54:03 PM PDT 24
Finished May 21 02:54:06 PM PDT 24
Peak memory 204660 kb
Host smart-807a4283-9d21-4da8-beb5-dc55c67b848f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739972188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1739972188
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.264974325
Short name T651
Test name
Test status
Simulation time 724309991 ps
CPU time 2.9 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:54:04 PM PDT 24
Peak memory 227848 kb
Host smart-6248c528-5e00-4d09-9c7b-7f8dfd434c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264974325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.264974325
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2334777042
Short name T1160
Test name
Test status
Simulation time 1069579310 ps
CPU time 5.45 seconds
Started May 21 02:53:54 PM PDT 24
Finished May 21 02:54:02 PM PDT 24
Peak memory 257868 kb
Host smart-66b3b89e-dfe3-4a3b-97d5-dc642d7ec854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334777042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2334777042
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2250756025
Short name T136
Test name
Test status
Simulation time 1853528335 ps
CPU time 68.4 seconds
Started May 21 02:53:50 PM PDT 24
Finished May 21 02:55:02 PM PDT 24
Peak memory 661812 kb
Host smart-0ae41967-6575-4bb4-987f-3de8d8694f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250756025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2250756025
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2685404634
Short name T418
Test name
Test status
Simulation time 2472953783 ps
CPU time 90.61 seconds
Started May 21 02:53:50 PM PDT 24
Finished May 21 02:55:25 PM PDT 24
Peak memory 818600 kb
Host smart-78e4db55-8826-4c95-adf7-546cb363faad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685404634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2685404634
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3086715010
Short name T205
Test name
Test status
Simulation time 361982960 ps
CPU time 0.89 seconds
Started May 21 02:53:52 PM PDT 24
Finished May 21 02:53:57 PM PDT 24
Peak memory 204808 kb
Host smart-339e708f-4840-44df-8098-a2ece23975b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086715010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3086715010
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3676846379
Short name T1069
Test name
Test status
Simulation time 360205989 ps
CPU time 4.08 seconds
Started May 21 02:53:54 PM PDT 24
Finished May 21 02:54:01 PM PDT 24
Peak memory 205108 kb
Host smart-0e52dfc8-8060-44d9-8cd7-0d1b04e31884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676846379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3676846379
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.3008066629
Short name T846
Test name
Test status
Simulation time 3611369740 ps
CPU time 86.72 seconds
Started May 21 02:53:51 PM PDT 24
Finished May 21 02:55:22 PM PDT 24
Peak memory 1076812 kb
Host smart-d0fe2bf4-7e48-4010-9214-73b22c7c6bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008066629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3008066629
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.661741689
Short name T216
Test name
Test status
Simulation time 1761108433 ps
CPU time 3.47 seconds
Started May 21 02:54:00 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 204952 kb
Host smart-8da774c7-dea1-468f-9a18-61caae540e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661741689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.661741689
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.4036456166
Short name T1044
Test name
Test status
Simulation time 5987425546 ps
CPU time 30.53 seconds
Started May 21 02:53:57 PM PDT 24
Finished May 21 02:54:29 PM PDT 24
Peak memory 346612 kb
Host smart-7cf085ad-b6ba-412d-9e9f-1a9d9094cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036456166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.4036456166
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.937316866
Short name T624
Test name
Test status
Simulation time 89303146 ps
CPU time 0.66 seconds
Started May 21 02:53:52 PM PDT 24
Finished May 21 02:53:56 PM PDT 24
Peak memory 204696 kb
Host smart-f98c2f34-16eb-4f6b-b76c-241075c0b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937316866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.937316866
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2244977435
Short name T1118
Test name
Test status
Simulation time 7615811486 ps
CPU time 747.6 seconds
Started May 21 02:53:51 PM PDT 24
Finished May 21 03:06:22 PM PDT 24
Peak memory 1608728 kb
Host smart-2c51b044-19ca-4446-a30e-16dedef99596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244977435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2244977435
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.784602999
Short name T142
Test name
Test status
Simulation time 6265850250 ps
CPU time 71.09 seconds
Started May 21 02:53:50 PM PDT 24
Finished May 21 02:55:05 PM PDT 24
Peak memory 310500 kb
Host smart-9c8a6927-18ac-497f-bc4f-3036ef094fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784602999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.784602999
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3530647056
Short name T38
Test name
Test status
Simulation time 8135468481 ps
CPU time 334.74 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:59:37 PM PDT 24
Peak memory 1740316 kb
Host smart-88932058-9ed6-4ed4-b4f9-ba5c4f489526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530647056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3530647056
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.490620216
Short name T780
Test name
Test status
Simulation time 2156223612 ps
CPU time 23.24 seconds
Started May 21 02:53:59 PM PDT 24
Finished May 21 02:54:26 PM PDT 24
Peak memory 213272 kb
Host smart-4207341f-7371-4795-b91d-5b50d380d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490620216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.490620216
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2708401685
Short name T895
Test name
Test status
Simulation time 1737697892 ps
CPU time 2.55 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 205044 kb
Host smart-5aaa447a-1227-48b4-8598-bc9a753ed9e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708401685 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2708401685
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2079019990
Short name T473
Test name
Test status
Simulation time 10145274019 ps
CPU time 14.94 seconds
Started May 21 02:53:57 PM PDT 24
Finished May 21 02:54:14 PM PDT 24
Peak memory 269796 kb
Host smart-91f2aaf2-d7cd-47d5-beda-055201a910de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079019990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2079019990
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1183325189
Short name T628
Test name
Test status
Simulation time 10171602236 ps
CPU time 48.18 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:54:50 PM PDT 24
Peak memory 381456 kb
Host smart-2632f36a-b832-493a-9789-a082e21ba997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183325189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1183325189
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1036119548
Short name T1322
Test name
Test status
Simulation time 306356705 ps
CPU time 2.46 seconds
Started May 21 02:53:57 PM PDT 24
Finished May 21 02:54:02 PM PDT 24
Peak memory 205096 kb
Host smart-01cb0646-2fd6-4836-9524-27683377b117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036119548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1036119548
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2875006312
Short name T274
Test name
Test status
Simulation time 1759626598 ps
CPU time 3.18 seconds
Started May 21 02:54:00 PM PDT 24
Finished May 21 02:54:07 PM PDT 24
Peak memory 204856 kb
Host smart-76691f00-464c-4b04-bd1c-147dff7e02e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875006312 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2875006312
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3212889812
Short name T782
Test name
Test status
Simulation time 10954158396 ps
CPU time 66.73 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:55:08 PM PDT 24
Peak memory 1160796 kb
Host smart-c791d1ff-3c65-4231-843a-fc0eae01024a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212889812 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3212889812
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3310568057
Short name T1276
Test name
Test status
Simulation time 4135932128 ps
CPU time 16.19 seconds
Started May 21 02:53:59 PM PDT 24
Finished May 21 02:54:19 PM PDT 24
Peak memory 205068 kb
Host smart-d437a307-3e01-47e6-80c8-ddde00607906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310568057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3310568057
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1110594961
Short name T1296
Test name
Test status
Simulation time 788288580 ps
CPU time 13.91 seconds
Started May 21 02:54:01 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 205036 kb
Host smart-07987588-01fd-44d5-8479-072871c381a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110594961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1110594961
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.356802860
Short name T640
Test name
Test status
Simulation time 12972709558 ps
CPU time 14.24 seconds
Started May 21 02:53:57 PM PDT 24
Finished May 21 02:54:13 PM PDT 24
Peak memory 205140 kb
Host smart-402e7920-8312-45b3-ac2f-ab37a70fd303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356802860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.356802860
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2397395189
Short name T505
Test name
Test status
Simulation time 17449081409 ps
CPU time 271.81 seconds
Started May 21 02:53:59 PM PDT 24
Finished May 21 02:58:35 PM PDT 24
Peak memory 2089656 kb
Host smart-d759404c-10c0-42a5-a609-67d1a87339e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397395189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2397395189
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1045368158
Short name T1076
Test name
Test status
Simulation time 1143531353 ps
CPU time 6.51 seconds
Started May 21 02:53:58 PM PDT 24
Finished May 21 02:54:09 PM PDT 24
Peak memory 221228 kb
Host smart-39f7146f-a040-43cf-990c-64082dac3a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045368158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1045368158
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1130927715
Short name T280
Test name
Test status
Simulation time 38415597 ps
CPU time 0.61 seconds
Started May 21 02:54:15 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 204656 kb
Host smart-7d78e220-5613-411c-b567-11179d2ec346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130927715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1130927715
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.508834404
Short name T1045
Test name
Test status
Simulation time 481047068 ps
CPU time 2.08 seconds
Started May 21 02:54:06 PM PDT 24
Finished May 21 02:54:11 PM PDT 24
Peak memory 213192 kb
Host smart-4bd552c6-00ed-4b0e-92fd-100634dded07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508834404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.508834404
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.474278682
Short name T1040
Test name
Test status
Simulation time 287905963 ps
CPU time 5.2 seconds
Started May 21 02:54:05 PM PDT 24
Finished May 21 02:54:14 PM PDT 24
Peak memory 259172 kb
Host smart-09de785f-02ea-428c-8695-2bbe2b1942b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474278682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.474278682
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3359077534
Short name T789
Test name
Test status
Simulation time 22202446074 ps
CPU time 82.45 seconds
Started May 21 02:54:05 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 645888 kb
Host smart-4156df97-7b39-4768-9726-158af2cdf5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359077534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3359077534
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3860221336
Short name T355
Test name
Test status
Simulation time 1246507488 ps
CPU time 78.9 seconds
Started May 21 02:54:05 PM PDT 24
Finished May 21 02:55:27 PM PDT 24
Peak memory 427984 kb
Host smart-17fb3dce-ed37-4fdd-bbf7-a43f43bcb31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860221336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3860221336
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3094871880
Short name T367
Test name
Test status
Simulation time 132900606 ps
CPU time 1.04 seconds
Started May 21 02:54:05 PM PDT 24
Finished May 21 02:54:09 PM PDT 24
Peak memory 204780 kb
Host smart-70b13578-e467-48ea-b18a-cea0e63279a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094871880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3094871880
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1452072287
Short name T746
Test name
Test status
Simulation time 1044762399 ps
CPU time 10.14 seconds
Started May 21 02:54:07 PM PDT 24
Finished May 21 02:54:19 PM PDT 24
Peak memory 204988 kb
Host smart-341f90b3-0499-4a1a-a945-55b13556e132
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452072287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1452072287
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2009721706
Short name T776
Test name
Test status
Simulation time 4347631973 ps
CPU time 132.75 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:56:20 PM PDT 24
Peak memory 1285024 kb
Host smart-281f0fdc-e837-40c7-8e05-8a63920b14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009721706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2009721706
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2422940945
Short name T1084
Test name
Test status
Simulation time 1482754078 ps
CPU time 15.81 seconds
Started May 21 02:54:12 PM PDT 24
Finished May 21 02:54:31 PM PDT 24
Peak memory 204980 kb
Host smart-622c7080-c553-480c-91d1-57c009a909d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422940945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2422940945
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.4205535996
Short name T703
Test name
Test status
Simulation time 8066993970 ps
CPU time 44.79 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:59 PM PDT 24
Peak memory 435596 kb
Host smart-96549686-234c-4b76-882a-b4fdecc699bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205535996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.4205535996
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.325493499
Short name T334
Test name
Test status
Simulation time 16886315 ps
CPU time 0.65 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:54:08 PM PDT 24
Peak memory 204744 kb
Host smart-d4d40fab-463c-4f89-b099-31e8861f7bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325493499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.325493499
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1557896785
Short name T1016
Test name
Test status
Simulation time 12862684197 ps
CPU time 145.21 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:56:32 PM PDT 24
Peak memory 982312 kb
Host smart-e5f36c69-30b0-4023-911e-e6aab882747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557896785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1557896785
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3720037112
Short name T957
Test name
Test status
Simulation time 5599056950 ps
CPU time 71.46 seconds
Started May 21 02:54:03 PM PDT 24
Finished May 21 02:55:17 PM PDT 24
Peak memory 336556 kb
Host smart-afa1bcf2-d56a-4070-a204-509f921c2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720037112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3720037112
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2501096553
Short name T108
Test name
Test status
Simulation time 19935349303 ps
CPU time 1090.35 seconds
Started May 21 02:54:10 PM PDT 24
Finished May 21 03:12:22 PM PDT 24
Peak memory 3801952 kb
Host smart-e8c6e7ca-f892-47db-a497-825cda15320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501096553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2501096553
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3161228475
Short name T1098
Test name
Test status
Simulation time 637528776 ps
CPU time 28.93 seconds
Started May 21 02:54:03 PM PDT 24
Finished May 21 02:54:35 PM PDT 24
Peak memory 213188 kb
Host smart-ffed2c77-e751-4b54-8b20-c4cd7cb0ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161228475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3161228475
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.202611196
Short name T1335
Test name
Test status
Simulation time 782643569 ps
CPU time 4.17 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 213224 kb
Host smart-f4e75f1e-fe72-4097-8c4e-7822d63b569b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202611196 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.202611196
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.4182318606
Short name T792
Test name
Test status
Simulation time 10147599411 ps
CPU time 28.93 seconds
Started May 21 02:54:07 PM PDT 24
Finished May 21 02:54:38 PM PDT 24
Peak memory 295664 kb
Host smart-4db6ecfb-5372-495b-af55-1c3982daac9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182318606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.4182318606
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2449557333
Short name T1051
Test name
Test status
Simulation time 10375035508 ps
CPU time 13.83 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 285496 kb
Host smart-879ec3d9-ef68-42b5-a923-934c93fa2091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449557333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2449557333
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.2706491263
Short name T1259
Test name
Test status
Simulation time 733259488 ps
CPU time 2.97 seconds
Started May 21 02:54:06 PM PDT 24
Finished May 21 02:54:12 PM PDT 24
Peak memory 205120 kb
Host smart-386057be-860e-4f18-80b7-a6bafa9388e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706491263 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.2706491263
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.4158224270
Short name T1170
Test name
Test status
Simulation time 6913035397 ps
CPU time 5.07 seconds
Started May 21 02:54:06 PM PDT 24
Finished May 21 02:54:14 PM PDT 24
Peak memory 205020 kb
Host smart-e293ed38-c489-4a13-a079-72eb040ab8b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158224270 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.4158224270
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.692101599
Short name T952
Test name
Test status
Simulation time 11540228906 ps
CPU time 13.14 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 510448 kb
Host smart-a49dad5a-b6d2-4c42-877c-0e5111795f5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692101599 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.692101599
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1651459047
Short name T1340
Test name
Test status
Simulation time 1435245167 ps
CPU time 23.12 seconds
Started May 21 02:54:10 PM PDT 24
Finished May 21 02:54:35 PM PDT 24
Peak memory 205020 kb
Host smart-f867d683-821e-405e-ba58-338cc6b26d5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651459047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1651459047
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1933617475
Short name T343
Test name
Test status
Simulation time 6563516179 ps
CPU time 68.18 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 02:55:16 PM PDT 24
Peak memory 209140 kb
Host smart-212f501e-e52b-4eee-81a8-f4187aa8d951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933617475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1933617475
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.250450089
Short name T1262
Test name
Test status
Simulation time 48357497916 ps
CPU time 374.75 seconds
Started May 21 02:54:04 PM PDT 24
Finished May 21 03:00:22 PM PDT 24
Peak memory 3492520 kb
Host smart-f9771ba2-07af-48a6-a9aa-972dbeba38ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250450089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.250450089
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3548929801
Short name T1062
Test name
Test status
Simulation time 33270067626 ps
CPU time 48.5 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:55:03 PM PDT 24
Peak memory 589840 kb
Host smart-fd22b4fd-d070-401d-a2db-f0ae7145ea84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548929801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3548929801
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_alert_test.520922410
Short name T689
Test name
Test status
Simulation time 27310783 ps
CPU time 0.61 seconds
Started May 21 02:54:17 PM PDT 24
Finished May 21 02:54:20 PM PDT 24
Peak memory 204676 kb
Host smart-15778519-6cc0-49bc-a78b-22582371abf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520922410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.520922410
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3785409866
Short name T44
Test name
Test status
Simulation time 308567737 ps
CPU time 1.83 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 213292 kb
Host smart-8981bad5-7cae-4040-ba1d-74b7a94c1961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785409866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3785409866
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2354239371
Short name T668
Test name
Test status
Simulation time 211679141 ps
CPU time 4.8 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:17 PM PDT 24
Peak memory 244232 kb
Host smart-7c118430-df5c-4cbb-8b7b-3a545da4a80e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354239371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2354239371
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.4193230771
Short name T1068
Test name
Test status
Simulation time 3035594307 ps
CPU time 103.34 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:55:57 PM PDT 24
Peak memory 781928 kb
Host smart-2d9cffe3-8054-4a56-bf90-447ed9368339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193230771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.4193230771
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.863355512
Short name T829
Test name
Test status
Simulation time 1693878362 ps
CPU time 122.52 seconds
Started May 21 02:54:12 PM PDT 24
Finished May 21 02:56:18 PM PDT 24
Peak memory 585288 kb
Host smart-f7974171-1a5e-441d-8202-1d85f775af9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863355512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.863355512
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2473310727
Short name T382
Test name
Test status
Simulation time 614589303 ps
CPU time 0.93 seconds
Started May 21 02:54:12 PM PDT 24
Finished May 21 02:54:16 PM PDT 24
Peak memory 204804 kb
Host smart-6cc471e5-f6da-446a-828f-72a92a368fcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473310727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2473310727
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2113063969
Short name T1277
Test name
Test status
Simulation time 1730967102 ps
CPU time 3.28 seconds
Started May 21 02:54:10 PM PDT 24
Finished May 21 02:54:15 PM PDT 24
Peak memory 204960 kb
Host smart-ee818acb-48d6-4edb-94b6-987ba6d51f62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113063969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2113063969
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3022732983
Short name T1239
Test name
Test status
Simulation time 3202034587 ps
CPU time 72.69 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:55:29 PM PDT 24
Peak memory 953476 kb
Host smart-ae503ac0-2ca5-4cef-b535-b7c819a0f804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022732983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3022732983
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.271041439
Short name T410
Test name
Test status
Simulation time 1961324991 ps
CPU time 7.61 seconds
Started May 21 02:54:16 PM PDT 24
Finished May 21 02:54:27 PM PDT 24
Peak memory 205060 kb
Host smart-8ac09807-9514-422e-8d2d-682ee323675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271041439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.271041439
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1865150250
Short name T34
Test name
Test status
Simulation time 1857804610 ps
CPU time 87.11 seconds
Started May 21 02:54:18 PM PDT 24
Finished May 21 02:55:48 PM PDT 24
Peak memory 352564 kb
Host smart-87d6b606-0ccf-4c3e-9260-3343d9f91f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865150250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1865150250
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1284574465
Short name T840
Test name
Test status
Simulation time 19476187 ps
CPU time 0.68 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:54:16 PM PDT 24
Peak memory 204692 kb
Host smart-ae0b3dce-b0fd-4d5a-8f60-06c6e666704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284574465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1284574465
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2089834725
Short name T1251
Test name
Test status
Simulation time 7485480390 ps
CPU time 306.14 seconds
Started May 21 02:54:12 PM PDT 24
Finished May 21 02:59:22 PM PDT 24
Peak memory 1816960 kb
Host smart-b8d72d66-d74e-4121-9f54-5a033bd34bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089834725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2089834725
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.488059796
Short name T416
Test name
Test status
Simulation time 2037780055 ps
CPU time 90.01 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:55:43 PM PDT 24
Peak memory 269976 kb
Host smart-dc739d8e-399c-4c14-b6bb-4d1f40e41da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488059796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.488059796
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.680702
Short name T929
Test name
Test status
Simulation time 1547370610 ps
CPU time 36.58 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 213240 kb
Host smart-c29cb0fc-5944-4f56-892a-32120e558212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.680702
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1713585153
Short name T289
Test name
Test status
Simulation time 1256592042 ps
CPU time 3.42 seconds
Started May 21 02:54:19 PM PDT 24
Finished May 21 02:54:25 PM PDT 24
Peak memory 204952 kb
Host smart-aaf2b7f6-7b0e-4e67-853d-797b1b7e619e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713585153 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1713585153
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.387036642
Short name T878
Test name
Test status
Simulation time 10457713781 ps
CPU time 14.96 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:54:31 PM PDT 24
Peak memory 269500 kb
Host smart-4960a174-341a-4a4c-855a-5c12785e4200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387036642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_acq.387036642
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3055312252
Short name T645
Test name
Test status
Simulation time 11407428020 ps
CPU time 5.11 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 242064 kb
Host smart-3990d149-ac7b-420a-8b03-c65ca4ba88bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055312252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3055312252
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2481254738
Short name T648
Test name
Test status
Simulation time 1259712156 ps
CPU time 2.15 seconds
Started May 21 02:54:17 PM PDT 24
Finished May 21 02:54:23 PM PDT 24
Peak memory 205076 kb
Host smart-7e3c53f8-d6f6-4e7e-8a06-ddcb2bc07582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481254738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2481254738
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3321223163
Short name T303
Test name
Test status
Simulation time 1092158736 ps
CPU time 5.58 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:18 PM PDT 24
Peak memory 219860 kb
Host smart-a6e7da98-c5d5-4183-9583-62579792860e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321223163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3321223163
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.3492298489
Short name T817
Test name
Test status
Simulation time 20478817504 ps
CPU time 39.78 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:53 PM PDT 24
Peak memory 725796 kb
Host smart-faac938c-ab75-49a3-8b78-a87029e2c2a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492298489 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3492298489
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.4008490063
Short name T1252
Test name
Test status
Simulation time 4810582304 ps
CPU time 11.44 seconds
Started May 21 02:54:13 PM PDT 24
Finished May 21 02:54:28 PM PDT 24
Peak memory 205084 kb
Host smart-eb7fcdec-57a4-480c-8f87-fd0bc148c74e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008490063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.4008490063
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4212176871
Short name T1114
Test name
Test status
Simulation time 2782489136 ps
CPU time 29.75 seconds
Started May 21 02:54:10 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 205144 kb
Host smart-3f421571-7547-4f0d-b7e4-2eaffd9b7348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212176871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4212176871
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.104580948
Short name T1082
Test name
Test status
Simulation time 59559734911 ps
CPU time 1884.39 seconds
Started May 21 02:54:12 PM PDT 24
Finished May 21 03:25:40 PM PDT 24
Peak memory 10104440 kb
Host smart-ad44b6e2-5930-4a04-95c6-bd07c98144fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104580948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.104580948
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3367310080
Short name T114
Test name
Test status
Simulation time 40944950495 ps
CPU time 1040.46 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 03:11:33 PM PDT 24
Peak memory 4901112 kb
Host smart-c859c4d4-eacd-4681-99c4-2bf1e2ffe797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367310080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3367310080
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2921933279
Short name T543
Test name
Test status
Simulation time 1279815614 ps
CPU time 8.08 seconds
Started May 21 02:54:11 PM PDT 24
Finished May 21 02:54:22 PM PDT 24
Peak memory 219224 kb
Host smart-7d703ebe-b539-483b-b0a2-f8d24ff49223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921933279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2921933279
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2200637281
Short name T834
Test name
Test status
Simulation time 38331010 ps
CPU time 0.62 seconds
Started May 21 02:47:43 PM PDT 24
Finished May 21 02:47:48 PM PDT 24
Peak memory 204656 kb
Host smart-a0a27a09-1100-4956-b7b4-01cdfcfc510a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200637281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2200637281
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.872311021
Short name T601
Test name
Test status
Simulation time 308781240 ps
CPU time 1.55 seconds
Started May 21 02:47:38 PM PDT 24
Finished May 21 02:47:42 PM PDT 24
Peak memory 213292 kb
Host smart-98546264-3160-40c1-ad22-29c3f87508c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872311021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.872311021
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.905564194
Short name T690
Test name
Test status
Simulation time 701621307 ps
CPU time 8.94 seconds
Started May 21 02:47:40 PM PDT 24
Finished May 21 02:47:51 PM PDT 24
Peak memory 277304 kb
Host smart-275688df-a23e-4efd-bac8-772677904674
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905564194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.905564194
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.913938436
Short name T338
Test name
Test status
Simulation time 1984567688 ps
CPU time 51.11 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:48:30 PM PDT 24
Peak memory 605112 kb
Host smart-713bd28c-d8c0-4e40-bf36-63d6ae4618c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913938436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.913938436
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1239672349
Short name T1327
Test name
Test status
Simulation time 36953073828 ps
CPU time 211.15 seconds
Started May 21 02:47:38 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 850988 kb
Host smart-6ad46cd9-71b5-4749-a375-57b399dacc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239672349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1239672349
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1173140525
Short name T1017
Test name
Test status
Simulation time 427071277 ps
CPU time 0.95 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:47:40 PM PDT 24
Peak memory 204796 kb
Host smart-5ca0a64f-591e-48fb-9b67-bd6f02ce9bc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173140525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1173140525
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2284215064
Short name T373
Test name
Test status
Simulation time 392074979 ps
CPU time 3.87 seconds
Started May 21 02:47:39 PM PDT 24
Finished May 21 02:47:46 PM PDT 24
Peak memory 205016 kb
Host smart-b2a75f60-5daf-4746-82e9-d7e2eb91f011
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284215064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2284215064
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3092118866
Short name T266
Test name
Test status
Simulation time 4373266151 ps
CPU time 340.82 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:53:20 PM PDT 24
Peak memory 1230448 kb
Host smart-478346e2-91b2-4190-8d6d-d65f2b8c0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092118866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3092118866
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1151291624
Short name T570
Test name
Test status
Simulation time 212520170 ps
CPU time 8.18 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:47:56 PM PDT 24
Peak memory 205036 kb
Host smart-3f3f1992-e2a2-44b3-b555-0186ee7f7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151291624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1151291624
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3752896038
Short name T1109
Test name
Test status
Simulation time 2600323726 ps
CPU time 25.16 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 329696 kb
Host smart-894e00fc-bae2-49fc-93d7-fc5204642751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752896038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3752896038
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.998671629
Short name T901
Test name
Test status
Simulation time 85797958 ps
CPU time 0.67 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:47:40 PM PDT 24
Peak memory 204732 kb
Host smart-50f418fb-471a-47da-a9b0-9aa20b9bbb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998671629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.998671629
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3700211914
Short name T1336
Test name
Test status
Simulation time 13220431885 ps
CPU time 88.98 seconds
Started May 21 02:47:39 PM PDT 24
Finished May 21 02:49:11 PM PDT 24
Peak memory 426180 kb
Host smart-d05e30b5-9242-4202-9d75-b6809178385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700211914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3700211914
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.580813284
Short name T307
Test name
Test status
Simulation time 1490259754 ps
CPU time 29.46 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:48:08 PM PDT 24
Peak memory 367140 kb
Host smart-6a99721e-507f-4550-b1c5-6acf5bc1a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580813284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.580813284
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2451249827
Short name T196
Test name
Test status
Simulation time 110059888017 ps
CPU time 749.03 seconds
Started May 21 02:47:39 PM PDT 24
Finished May 21 03:00:10 PM PDT 24
Peak memory 1699048 kb
Host smart-c47fbabc-aeae-4b0d-a91c-6115274abe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451249827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2451249827
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1856879995
Short name T733
Test name
Test status
Simulation time 3496303342 ps
CPU time 23.74 seconds
Started May 21 02:47:39 PM PDT 24
Finished May 21 02:48:05 PM PDT 24
Peak memory 213320 kb
Host smart-872f1a68-d6a6-4cbc-8bef-db78427fdb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856879995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1856879995
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2548070480
Short name T686
Test name
Test status
Simulation time 2813948159 ps
CPU time 3.59 seconds
Started May 21 02:47:48 PM PDT 24
Finished May 21 02:47:57 PM PDT 24
Peak memory 213284 kb
Host smart-9c308546-ec71-496e-9698-965566741647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548070480 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2548070480
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2540202895
Short name T869
Test name
Test status
Simulation time 10033456928 ps
CPU time 64.71 seconds
Started May 21 02:47:47 PM PDT 24
Finished May 21 02:48:56 PM PDT 24
Peak memory 488728 kb
Host smart-ed6aacd2-5875-4f04-91aa-88cb4f3b99b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540202895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2540202895
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1676195432
Short name T146
Test name
Test status
Simulation time 10068856335 ps
CPU time 15.07 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:48:03 PM PDT 24
Peak memory 287456 kb
Host smart-52fd350c-eb39-4de0-a2b7-d8c157dc7817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676195432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1676195432
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2888528527
Short name T833
Test name
Test status
Simulation time 2813969134 ps
CPU time 2.26 seconds
Started May 21 02:47:45 PM PDT 24
Finished May 21 02:47:52 PM PDT 24
Peak memory 205240 kb
Host smart-e0a28711-95f5-447e-8bff-7761304910e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888528527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2888528527
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.800086179
Short name T283
Test name
Test status
Simulation time 5086981695 ps
CPU time 6.45 seconds
Started May 21 02:47:43 PM PDT 24
Finished May 21 02:47:54 PM PDT 24
Peak memory 211960 kb
Host smart-cd2b5853-b8cd-42d8-9c97-5732b029f01d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800086179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.800086179
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.543786335
Short name T66
Test name
Test status
Simulation time 10792878007 ps
CPU time 4.3 seconds
Started May 21 02:47:46 PM PDT 24
Finished May 21 02:47:55 PM PDT 24
Peak memory 205132 kb
Host smart-0fe305b6-4451-4449-b29f-7e3f5ce02d03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543786335 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.543786335
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2294570109
Short name T687
Test name
Test status
Simulation time 2506580445 ps
CPU time 17.3 seconds
Started May 21 02:47:38 PM PDT 24
Finished May 21 02:47:57 PM PDT 24
Peak memory 205040 kb
Host smart-7fe51246-a50b-4000-9a42-99b75143b50e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294570109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2294570109
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1904045452
Short name T977
Test name
Test status
Simulation time 454109388 ps
CPU time 8.51 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 02:47:47 PM PDT 24
Peak memory 205004 kb
Host smart-836d464c-4694-46cd-bd60-6fa13f1f2389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904045452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1904045452
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3962839268
Short name T1130
Test name
Test status
Simulation time 65535100091 ps
CPU time 944.02 seconds
Started May 21 02:47:37 PM PDT 24
Finished May 21 03:03:23 PM PDT 24
Peak memory 5857420 kb
Host smart-8ba59fec-2eab-4ca0-aae1-2a08f223f693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962839268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3962839268
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3015469635
Short name T1289
Test name
Test status
Simulation time 29075070791 ps
CPU time 238.6 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:51:46 PM PDT 24
Peak memory 1739860 kb
Host smart-62c749a3-0c70-44ae-8656-580b54c765a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015469635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3015469635
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1075051818
Short name T539
Test name
Test status
Simulation time 6185533521 ps
CPU time 7.94 seconds
Started May 21 02:47:45 PM PDT 24
Finished May 21 02:47:57 PM PDT 24
Peak memory 215408 kb
Host smart-3b43bb97-2629-4b3d-8378-fb1851d4526a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075051818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1075051818
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3195904495
Short name T658
Test name
Test status
Simulation time 43408305 ps
CPU time 0.59 seconds
Started May 21 02:47:56 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 204568 kb
Host smart-1864c86c-87fe-4027-bb65-cc8b9a4bd3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195904495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3195904495
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2081644430
Short name T891
Test name
Test status
Simulation time 3006272384 ps
CPU time 2.83 seconds
Started May 21 02:47:51 PM PDT 24
Finished May 21 02:47:59 PM PDT 24
Peak memory 213416 kb
Host smart-1e325197-de06-4619-a8b0-9cf3bf339b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081644430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2081644430
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.127653507
Short name T639
Test name
Test status
Simulation time 1027913423 ps
CPU time 28.26 seconds
Started May 21 02:47:49 PM PDT 24
Finished May 21 02:48:22 PM PDT 24
Peak memory 317676 kb
Host smart-a1eda1e9-dffe-4101-ac27-867e7bacb91e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127653507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.127653507
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3503371414
Short name T537
Test name
Test status
Simulation time 40860789642 ps
CPU time 54.74 seconds
Started May 21 02:47:49 PM PDT 24
Finished May 21 02:48:49 PM PDT 24
Peak memory 562956 kb
Host smart-543a3bb4-3b60-4a69-b296-4aa96963d521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503371414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3503371414
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3615580306
Short name T944
Test name
Test status
Simulation time 2188233271 ps
CPU time 61.75 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:48:49 PM PDT 24
Peak memory 725564 kb
Host smart-3580aeba-b6d4-40ab-a71b-d646c4549f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615580306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3615580306
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.4125223828
Short name T328
Test name
Test status
Simulation time 365855002 ps
CPU time 0.8 seconds
Started May 21 02:47:48 PM PDT 24
Finished May 21 02:47:53 PM PDT 24
Peak memory 204796 kb
Host smart-aac25d93-f700-4da2-9c02-a84129ef94cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125223828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.4125223828
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1718818110
Short name T934
Test name
Test status
Simulation time 179243033 ps
CPU time 8.96 seconds
Started May 21 02:47:52 PM PDT 24
Finished May 21 02:48:06 PM PDT 24
Peak memory 204924 kb
Host smart-1fca4f9f-1c21-46b6-9b01-ff2ad4cc5583
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718818110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1718818110
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.655953973
Short name T101
Test name
Test status
Simulation time 28686623477 ps
CPU time 66.02 seconds
Started May 21 02:47:47 PM PDT 24
Finished May 21 02:48:57 PM PDT 24
Peak memory 917968 kb
Host smart-810f05b9-f54f-4171-ac7f-53acbf0a5049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655953973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.655953973
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2781564455
Short name T1094
Test name
Test status
Simulation time 2402222896 ps
CPU time 9.57 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:48:09 PM PDT 24
Peak memory 205060 kb
Host smart-e979681b-a027-40d8-b515-3bac78f422d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781564455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2781564455
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1955759370
Short name T591
Test name
Test status
Simulation time 1915026671 ps
CPU time 41.92 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:48:41 PM PDT 24
Peak memory 435616 kb
Host smart-b4ec867d-36d0-403c-9ef2-6c2d2fa2be2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955759370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1955759370
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3520690748
Short name T117
Test name
Test status
Simulation time 28345728 ps
CPU time 0.64 seconds
Started May 21 02:47:43 PM PDT 24
Finished May 21 02:47:47 PM PDT 24
Peak memory 204720 kb
Host smart-02639296-4fe5-43b5-bd09-e7cff1e82831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520690748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3520690748
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3520459250
Short name T786
Test name
Test status
Simulation time 4075553510 ps
CPU time 26.34 seconds
Started May 21 02:47:51 PM PDT 24
Finished May 21 02:48:22 PM PDT 24
Peak memory 383452 kb
Host smart-6e8473b9-06db-4d45-9ba9-b95bb2eedf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520459250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3520459250
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2696641861
Short name T741
Test name
Test status
Simulation time 7142338724 ps
CPU time 31.51 seconds
Started May 21 02:47:44 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 433096 kb
Host smart-29bb596f-04a7-4885-aea6-9e4284ac90b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696641861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2696641861
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2392921382
Short name T904
Test name
Test status
Simulation time 3089851889 ps
CPU time 13.52 seconds
Started May 21 02:47:52 PM PDT 24
Finished May 21 02:48:11 PM PDT 24
Peak memory 219252 kb
Host smart-f33acae7-087a-488f-9cc5-24510ebf35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392921382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2392921382
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.703152220
Short name T711
Test name
Test status
Simulation time 3164062201 ps
CPU time 3.65 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:48:03 PM PDT 24
Peak memory 213328 kb
Host smart-8f952ed0-bafc-497b-abb0-ecf29866416e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703152220 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.703152220
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.4186138276
Short name T871
Test name
Test status
Simulation time 10064470530 ps
CPU time 73.06 seconds
Started May 21 02:47:49 PM PDT 24
Finished May 21 02:49:06 PM PDT 24
Peak memory 442368 kb
Host smart-2ffb7852-0756-4dc2-b594-c7d7ceb507c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186138276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.4186138276
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.764281586
Short name T198
Test name
Test status
Simulation time 10094380976 ps
CPU time 57.23 seconds
Started May 21 02:47:57 PM PDT 24
Finished May 21 02:48:58 PM PDT 24
Peak memory 470624 kb
Host smart-df2052bd-9dc9-4648-a31b-63180d49cace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764281586 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.764281586
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3392182940
Short name T779
Test name
Test status
Simulation time 1553568784 ps
CPU time 2.46 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 205092 kb
Host smart-2ed6cdee-77de-4310-8923-63410cc14b94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392182940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3392182940
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2053866732
Short name T396
Test name
Test status
Simulation time 3279500340 ps
CPU time 4.8 seconds
Started May 21 02:47:51 PM PDT 24
Finished May 21 02:48:01 PM PDT 24
Peak memory 213308 kb
Host smart-33ea4afa-555b-4a70-baf8-1e22a036fa5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053866732 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2053866732
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2952852616
Short name T26
Test name
Test status
Simulation time 18043098942 ps
CPU time 34.05 seconds
Started May 21 02:47:49 PM PDT 24
Finished May 21 02:48:28 PM PDT 24
Peak memory 639904 kb
Host smart-e82a663e-b8ad-4e39-8396-64a8a9ee4285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952852616 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2952852616
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2040601421
Short name T479
Test name
Test status
Simulation time 752567008 ps
CPU time 9.77 seconds
Started May 21 02:47:52 PM PDT 24
Finished May 21 02:48:07 PM PDT 24
Peak memory 204956 kb
Host smart-3b23e053-db18-47cf-97d0-e7b6382be836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040601421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2040601421
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3607416971
Short name T229
Test name
Test status
Simulation time 1297060146 ps
CPU time 18.88 seconds
Started May 21 02:47:51 PM PDT 24
Finished May 21 02:48:14 PM PDT 24
Peak memory 232940 kb
Host smart-adbbf6f0-a69d-4d45-afdc-8ac56997f311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607416971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3607416971
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2648491388
Short name T1167
Test name
Test status
Simulation time 44203073521 ps
CPU time 108.36 seconds
Started May 21 02:47:50 PM PDT 24
Finished May 21 02:49:43 PM PDT 24
Peak memory 1571280 kb
Host smart-25b94ff8-b458-4bc9-b60d-6e64033576e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648491388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2648491388
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2737238811
Short name T1078
Test name
Test status
Simulation time 20564738898 ps
CPU time 971.22 seconds
Started May 21 02:47:50 PM PDT 24
Finished May 21 03:04:07 PM PDT 24
Peak memory 2341276 kb
Host smart-08fc3557-fe0f-40a5-b468-5401b79bd48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737238811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2737238811
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1206607952
Short name T360
Test name
Test status
Simulation time 1328619099 ps
CPU time 7.27 seconds
Started May 21 02:47:50 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 213260 kb
Host smart-6a899a1c-7973-4a69-8cb1-e2673e77164f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206607952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1206607952
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3714777737
Short name T1014
Test name
Test status
Simulation time 17987414 ps
CPU time 0.61 seconds
Started May 21 02:48:08 PM PDT 24
Finished May 21 02:48:10 PM PDT 24
Peak memory 204624 kb
Host smart-bb39db63-dce1-411a-b506-0ecf80b5be67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714777737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3714777737
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1855338700
Short name T319
Test name
Test status
Simulation time 339057269 ps
CPU time 2.28 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 02:48:08 PM PDT 24
Peak memory 213204 kb
Host smart-031bc0c7-67f1-4dd4-8855-ae3e195ab9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855338700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1855338700
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3704394810
Short name T276
Test name
Test status
Simulation time 929105872 ps
CPU time 12.63 seconds
Started May 21 02:47:56 PM PDT 24
Finished May 21 02:48:12 PM PDT 24
Peak memory 254736 kb
Host smart-8075bddf-8484-490d-961f-30953e238e56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704394810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3704394810
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.4096088213
Short name T564
Test name
Test status
Simulation time 5353907237 ps
CPU time 82.74 seconds
Started May 21 02:47:57 PM PDT 24
Finished May 21 02:49:23 PM PDT 24
Peak memory 670068 kb
Host smart-9942b018-20cc-41ec-a26e-b4468433587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096088213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4096088213
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2580126474
Short name T749
Test name
Test status
Simulation time 11436381947 ps
CPU time 86.24 seconds
Started May 21 02:47:54 PM PDT 24
Finished May 21 02:49:25 PM PDT 24
Peak memory 819568 kb
Host smart-703e1ae4-b631-45ef-bad6-14063128461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580126474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2580126474
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2322273046
Short name T638
Test name
Test status
Simulation time 97691645 ps
CPU time 0.84 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 204804 kb
Host smart-0e2bcdc0-b568-4373-888b-94610ca9ed53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322273046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2322273046
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2926845307
Short name T311
Test name
Test status
Simulation time 118239642 ps
CPU time 7.12 seconds
Started May 21 02:47:58 PM PDT 24
Finished May 21 02:48:08 PM PDT 24
Peak memory 223264 kb
Host smart-90d8a604-47f7-4472-8b2f-3704c09a178a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926845307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2926845307
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3969843249
Short name T237
Test name
Test status
Simulation time 5452432660 ps
CPU time 169.47 seconds
Started May 21 02:47:57 PM PDT 24
Finished May 21 02:50:50 PM PDT 24
Peak memory 805020 kb
Host smart-735d9ad5-0160-40fa-8246-e5d2728fb043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969843249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3969843249
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3902728063
Short name T397
Test name
Test status
Simulation time 1245122246 ps
CPU time 17.81 seconds
Started May 21 02:48:08 PM PDT 24
Finished May 21 02:48:29 PM PDT 24
Peak memory 306316 kb
Host smart-18ba541e-a307-42ae-92d7-875749544096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902728063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3902728063
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.128214074
Short name T1225
Test name
Test status
Simulation time 25826802 ps
CPU time 0.66 seconds
Started May 21 02:47:54 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 204716 kb
Host smart-ae93a45f-5194-440a-80b6-f26ec6cf9a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128214074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.128214074
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2709259524
Short name T950
Test name
Test status
Simulation time 882198673 ps
CPU time 9.5 seconds
Started May 21 02:48:02 PM PDT 24
Finished May 21 02:48:14 PM PDT 24
Peak memory 229452 kb
Host smart-9642b37b-e238-4800-9bd9-6a6145b37610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709259524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2709259524
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1413418807
Short name T629
Test name
Test status
Simulation time 1480299719 ps
CPU time 64.33 seconds
Started May 21 02:47:55 PM PDT 24
Finished May 21 02:49:04 PM PDT 24
Peak memory 267380 kb
Host smart-d57a4a0c-345b-4760-86d9-82cd2d53e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413418807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1413418807
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.237899778
Short name T162
Test name
Test status
Simulation time 11833465925 ps
CPU time 706.47 seconds
Started May 21 02:48:02 PM PDT 24
Finished May 21 02:59:51 PM PDT 24
Peak memory 1873396 kb
Host smart-e5aed64a-4f87-4afe-87d0-d8106021f0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237899778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.237899778
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.310534162
Short name T357
Test name
Test status
Simulation time 2549634617 ps
CPU time 28.59 seconds
Started May 21 02:48:01 PM PDT 24
Finished May 21 02:48:31 PM PDT 24
Peak memory 213348 kb
Host smart-018f6300-dcb8-4517-9653-b743e753fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310534162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.310534162
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2880950853
Short name T946
Test name
Test status
Simulation time 1074607871 ps
CPU time 4.77 seconds
Started May 21 02:48:12 PM PDT 24
Finished May 21 02:48:19 PM PDT 24
Peak memory 204964 kb
Host smart-1639206d-57d3-4682-a5ca-61ef66d75061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880950853 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2880950853
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2402182556
Short name T521
Test name
Test status
Simulation time 10056988666 ps
CPU time 17.03 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 02:48:23 PM PDT 24
Peak memory 283612 kb
Host smart-613e7b6f-50eb-4777-9b1c-8141bafc6b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402182556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2402182556
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3681712041
Short name T82
Test name
Test status
Simulation time 10069989355 ps
CPU time 79.54 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 02:49:25 PM PDT 24
Peak memory 553940 kb
Host smart-b7d64894-824b-4c8b-84cd-add82d991810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681712041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3681712041
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.719139887
Short name T470
Test name
Test status
Simulation time 1825013865 ps
CPU time 2.62 seconds
Started May 21 02:48:12 PM PDT 24
Finished May 21 02:48:16 PM PDT 24
Peak memory 205076 kb
Host smart-8e9f9acb-4b33-4561-85af-3d63ecbf404e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719139887 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.719139887
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1369233379
Short name T924
Test name
Test status
Simulation time 2097281895 ps
CPU time 6.15 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 02:48:12 PM PDT 24
Peak memory 219500 kb
Host smart-e40b015c-ac8d-40d0-969a-76326469b040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369233379 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1369233379
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2366402892
Short name T509
Test name
Test status
Simulation time 21408188833 ps
CPU time 157.01 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 02:50:43 PM PDT 24
Peak memory 1804772 kb
Host smart-aeb6ba6f-e458-4ca3-9b24-a77bf5bbde41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366402892 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2366402892
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3609020260
Short name T939
Test name
Test status
Simulation time 964752788 ps
CPU time 33.85 seconds
Started May 21 02:48:03 PM PDT 24
Finished May 21 02:48:39 PM PDT 24
Peak memory 204932 kb
Host smart-1a97b709-8ad6-4f90-95c3-8772b98ca49f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609020260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3609020260
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.70721181
Short name T766
Test name
Test status
Simulation time 400740829 ps
CPU time 7.16 seconds
Started May 21 02:48:03 PM PDT 24
Finished May 21 02:48:12 PM PDT 24
Peak memory 204944 kb
Host smart-99831568-268e-47e8-a611-dfbd44ac055b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70721181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_rd.70721181
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3417538040
Short name T612
Test name
Test status
Simulation time 13208546606 ps
CPU time 24.83 seconds
Started May 21 02:48:02 PM PDT 24
Finished May 21 02:48:29 PM PDT 24
Peak memory 205176 kb
Host smart-60fd1194-20be-4601-9a68-c57cd7e88fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417538040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3417538040
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2485280174
Short name T304
Test name
Test status
Simulation time 24188237539 ps
CPU time 1382.09 seconds
Started May 21 02:48:04 PM PDT 24
Finished May 21 03:11:08 PM PDT 24
Peak memory 2806864 kb
Host smart-a1205491-9b47-4112-beb4-c69d1688283a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485280174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2485280174
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3964719114
Short name T770
Test name
Test status
Simulation time 1485593731 ps
CPU time 8.33 seconds
Started May 21 02:48:02 PM PDT 24
Finished May 21 02:48:12 PM PDT 24
Peak memory 217908 kb
Host smart-016011c1-1f3a-4582-bb09-49bd449fd42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964719114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3964719114
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2535961596
Short name T364
Test name
Test status
Simulation time 15337258 ps
CPU time 0.61 seconds
Started May 21 02:48:13 PM PDT 24
Finished May 21 02:48:15 PM PDT 24
Peak memory 204668 kb
Host smart-0c78bd09-f921-4eac-bf98-44420c81d6fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535961596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2535961596
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.4121833427
Short name T1208
Test name
Test status
Simulation time 152178262 ps
CPU time 2.45 seconds
Started May 21 02:48:09 PM PDT 24
Finished May 21 02:48:14 PM PDT 24
Peak memory 213320 kb
Host smart-1403b407-fab6-4328-932a-e9590f4ad374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121833427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.4121833427
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2659671802
Short name T723
Test name
Test status
Simulation time 395690825 ps
CPU time 7.16 seconds
Started May 21 02:48:10 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 289672 kb
Host smart-1d48d964-1577-4e36-af99-e678eb5ad16e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659671802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2659671802
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1203592635
Short name T75
Test name
Test status
Simulation time 5431766694 ps
CPU time 77.73 seconds
Started May 21 02:48:13 PM PDT 24
Finished May 21 02:49:32 PM PDT 24
Peak memory 734876 kb
Host smart-6968f825-60a6-4359-b926-b23441571c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203592635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1203592635
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1175979253
Short name T604
Test name
Test status
Simulation time 2308597681 ps
CPU time 181.93 seconds
Started May 21 02:48:07 PM PDT 24
Finished May 21 02:51:11 PM PDT 24
Peak memory 771580 kb
Host smart-f63b67fd-82e4-4865-98aa-c16411084cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175979253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1175979253
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.815861342
Short name T1077
Test name
Test status
Simulation time 214893643 ps
CPU time 1 seconds
Started May 21 02:48:10 PM PDT 24
Finished May 21 02:48:14 PM PDT 24
Peak memory 204792 kb
Host smart-55421ff9-8b74-4c01-8a03-d46307e997de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815861342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.815861342
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1987140133
Short name T525
Test name
Test status
Simulation time 621239439 ps
CPU time 3.43 seconds
Started May 21 02:48:08 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 204992 kb
Host smart-26158953-2a49-4832-b1a2-cc29f2d9b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987140133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1987140133
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1425002924
Short name T103
Test name
Test status
Simulation time 27204547634 ps
CPU time 133.64 seconds
Started May 21 02:48:10 PM PDT 24
Finished May 21 02:50:26 PM PDT 24
Peak memory 1451688 kb
Host smart-f7692378-4b94-4424-bdfd-fadcb09366f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425002924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1425002924
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2292726618
Short name T830
Test name
Test status
Simulation time 1735834165 ps
CPU time 17.58 seconds
Started May 21 02:48:15 PM PDT 24
Finished May 21 02:48:35 PM PDT 24
Peak memory 205036 kb
Host smart-a11ee894-822f-48ff-b152-204f40cebce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292726618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2292726618
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.132353111
Short name T567
Test name
Test status
Simulation time 1779990420 ps
CPU time 26.35 seconds
Started May 21 02:48:15 PM PDT 24
Finished May 21 02:48:43 PM PDT 24
Peak memory 338148 kb
Host smart-1a64f0f1-2d4f-49b6-ae64-909e96cd3cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132353111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.132353111
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.824944270
Short name T739
Test name
Test status
Simulation time 29465755 ps
CPU time 0.72 seconds
Started May 21 02:48:09 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 204716 kb
Host smart-98d08c20-e195-490c-9e88-99553c603726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824944270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.824944270
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1461220912
Short name T991
Test name
Test status
Simulation time 51727399116 ps
CPU time 1510.45 seconds
Started May 21 02:48:07 PM PDT 24
Finished May 21 03:13:19 PM PDT 24
Peak memory 2501092 kb
Host smart-755cf200-0c8c-4c06-ab10-6580a2af7928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461220912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1461220912
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.542135844
Short name T1105
Test name
Test status
Simulation time 1473961389 ps
CPU time 76.48 seconds
Started May 21 02:48:09 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 372316 kb
Host smart-483d282e-9886-4c37-a7ff-88daba9228e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542135844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.542135844
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2378970239
Short name T1008
Test name
Test status
Simulation time 1199521465 ps
CPU time 11.42 seconds
Started May 21 02:48:08 PM PDT 24
Finished May 21 02:48:23 PM PDT 24
Peak memory 215224 kb
Host smart-ee906f69-e65c-431b-87fb-4b735f2871ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378970239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2378970239
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2770865027
Short name T279
Test name
Test status
Simulation time 729951680 ps
CPU time 3.33 seconds
Started May 21 02:48:14 PM PDT 24
Finished May 21 02:48:19 PM PDT 24
Peak memory 205000 kb
Host smart-30d0bf07-f72f-4365-8721-33f17a712346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770865027 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2770865027
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1008836483
Short name T547
Test name
Test status
Simulation time 10070912995 ps
CPU time 65.24 seconds
Started May 21 02:48:17 PM PDT 24
Finished May 21 02:49:24 PM PDT 24
Peak memory 468672 kb
Host smart-c628638e-cd21-404a-9abf-33b2e8b76989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008836483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1008836483
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.816860136
Short name T301
Test name
Test status
Simulation time 10415390675 ps
CPU time 7.54 seconds
Started May 21 02:48:13 PM PDT 24
Finished May 21 02:48:22 PM PDT 24
Peak memory 237036 kb
Host smart-e1020e98-c208-40b9-99a0-21f4531e74fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816860136 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.816860136
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2138061272
Short name T24
Test name
Test status
Simulation time 6775173460 ps
CPU time 2.64 seconds
Started May 21 02:48:16 PM PDT 24
Finished May 21 02:48:21 PM PDT 24
Peak memory 205236 kb
Host smart-fd1796c7-f4ab-4bdd-88d9-c9160ae5c105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138061272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2138061272
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3054514870
Short name T621
Test name
Test status
Simulation time 706769981 ps
CPU time 3.86 seconds
Started May 21 02:48:14 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 205204 kb
Host smart-8c8e12d1-63ea-4bfc-9d1e-dd4d13816cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054514870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3054514870
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1886267157
Short name T874
Test name
Test status
Simulation time 12872167928 ps
CPU time 27.68 seconds
Started May 21 02:48:15 PM PDT 24
Finished May 21 02:48:44 PM PDT 24
Peak memory 825408 kb
Host smart-c49055e9-d43d-4c8f-a0b9-8fb7fd74bebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886267157 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1886267157
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3422600866
Short name T809
Test name
Test status
Simulation time 3782318935 ps
CPU time 36.32 seconds
Started May 21 02:48:09 PM PDT 24
Finished May 21 02:48:48 PM PDT 24
Peak memory 205124 kb
Host smart-193aa9cf-5894-4407-82c0-dddbec014fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422600866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3422600866
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3888576135
Short name T863
Test name
Test status
Simulation time 3156257914 ps
CPU time 68.69 seconds
Started May 21 02:48:16 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 208268 kb
Host smart-422908ac-e6b7-40d3-9b9b-adfae6e32ad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888576135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3888576135
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.209935084
Short name T18
Test name
Test status
Simulation time 30198446600 ps
CPU time 236.68 seconds
Started May 21 02:48:10 PM PDT 24
Finished May 21 02:52:10 PM PDT 24
Peak memory 2534692 kb
Host smart-871d72b3-66c3-4750-9768-3ef59a186518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209935084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.209935084
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.221995916
Short name T271
Test name
Test status
Simulation time 25239822489 ps
CPU time 8.05 seconds
Started May 21 02:48:15 PM PDT 24
Finished May 21 02:48:25 PM PDT 24
Peak memory 221388 kb
Host smart-a9c88231-f027-428f-9c93-1a41ece9b723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221995916 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.221995916
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3151445183
Short name T826
Test name
Test status
Simulation time 18442738 ps
CPU time 0.64 seconds
Started May 21 02:48:31 PM PDT 24
Finished May 21 02:48:34 PM PDT 24
Peak memory 204668 kb
Host smart-717557c2-a9ed-45f3-a0f1-639a59c68d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151445183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3151445183
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2620785524
Short name T743
Test name
Test status
Simulation time 4867962516 ps
CPU time 13.91 seconds
Started May 21 02:48:21 PM PDT 24
Finished May 21 02:48:38 PM PDT 24
Peak memory 248236 kb
Host smart-4ec3a7e3-6fe1-451b-bd81-a7bc02f30b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620785524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2620785524
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3627856202
Short name T1021
Test name
Test status
Simulation time 476580408 ps
CPU time 4.65 seconds
Started May 21 02:48:19 PM PDT 24
Finished May 21 02:48:25 PM PDT 24
Peak memory 252304 kb
Host smart-7cb9f6b8-6839-4a06-80ac-97ce068ad7c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627856202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3627856202
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3546058194
Short name T637
Test name
Test status
Simulation time 2463315613 ps
CPU time 74.08 seconds
Started May 21 02:48:19 PM PDT 24
Finished May 21 02:49:36 PM PDT 24
Peak memory 414612 kb
Host smart-5e706d65-e3b4-416e-87e5-5c53b24c5d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546058194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3546058194
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3649864069
Short name T801
Test name
Test status
Simulation time 5940274174 ps
CPU time 49.59 seconds
Started May 21 02:48:15 PM PDT 24
Finished May 21 02:49:06 PM PDT 24
Peak memory 573664 kb
Host smart-402a6040-268b-476b-93ee-46b18a5f4a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649864069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3649864069
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2382105114
Short name T883
Test name
Test status
Simulation time 156373764 ps
CPU time 1.24 seconds
Started May 21 02:48:18 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 205000 kb
Host smart-4a075846-969b-422f-b3cd-060d121384d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382105114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2382105114
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.4068535079
Short name T717
Test name
Test status
Simulation time 166396505 ps
CPU time 9.52 seconds
Started May 21 02:48:18 PM PDT 24
Finished May 21 02:48:29 PM PDT 24
Peak memory 234000 kb
Host smart-15f3c7f6-3efb-466a-9a71-1a54a2070150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068535079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
4068535079
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1566535241
Short name T839
Test name
Test status
Simulation time 7886853874 ps
CPU time 292.71 seconds
Started May 21 02:48:13 PM PDT 24
Finished May 21 02:53:07 PM PDT 24
Peak memory 1165352 kb
Host smart-c54f3759-64db-4fd8-bb14-da19b387af8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566535241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1566535241
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1354536019
Short name T388
Test name
Test status
Simulation time 514089918 ps
CPU time 9.3 seconds
Started May 21 02:48:25 PM PDT 24
Finished May 21 02:48:36 PM PDT 24
Peak memory 205012 kb
Host smart-17bfd70c-4f3a-4835-97b8-4dee4fcf906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354536019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1354536019
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1470966454
Short name T213
Test name
Test status
Simulation time 4380582933 ps
CPU time 36.75 seconds
Started May 21 02:48:26 PM PDT 24
Finished May 21 02:49:04 PM PDT 24
Peak memory 381924 kb
Host smart-11f87614-9a77-4994-99cb-8d8a99c2e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470966454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1470966454
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.566815520
Short name T961
Test name
Test status
Simulation time 16837421 ps
CPU time 0.67 seconds
Started May 21 02:48:14 PM PDT 24
Finished May 21 02:48:16 PM PDT 24
Peak memory 204876 kb
Host smart-7847d6aa-108e-450a-8f53-a988a29bc4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566815520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.566815520
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.79315192
Short name T452
Test name
Test status
Simulation time 1375628374 ps
CPU time 35.02 seconds
Started May 21 02:48:22 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 354020 kb
Host smart-a4d37fa5-ba01-4b1b-a049-122cd3f723dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79315192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.79315192
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1085313712
Short name T573
Test name
Test status
Simulation time 2650445995 ps
CPU time 70.22 seconds
Started May 21 02:48:14 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 353796 kb
Host smart-44970838-ada8-494c-9f26-dc5e391db0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085313712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1085313712
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1125861738
Short name T197
Test name
Test status
Simulation time 42919928370 ps
CPU time 275.89 seconds
Started May 21 02:48:22 PM PDT 24
Finished May 21 02:53:00 PM PDT 24
Peak memory 1193948 kb
Host smart-87c94a1d-6d0c-4634-a41e-7417e8072554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125861738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1125861738
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3150361523
Short name T1258
Test name
Test status
Simulation time 1052371615 ps
CPU time 47.22 seconds
Started May 21 02:48:18 PM PDT 24
Finished May 21 02:49:06 PM PDT 24
Peak memory 221412 kb
Host smart-dd384a9e-59a5-4e75-bc0d-8d281b5fc60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150361523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3150361523
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.254421824
Short name T286
Test name
Test status
Simulation time 3296196660 ps
CPU time 3.96 seconds
Started May 21 02:48:24 PM PDT 24
Finished May 21 02:48:30 PM PDT 24
Peak memory 205140 kb
Host smart-d0892d92-0277-48e9-b595-dc6db24840cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254421824 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.254421824
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.721751283
Short name T342
Test name
Test status
Simulation time 10173905694 ps
CPU time 34.09 seconds
Started May 21 02:48:25 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 377644 kb
Host smart-6c3cc52d-7dcb-4ffe-85e2-31ad88dbac60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721751283 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.721751283
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.297116998
Short name T824
Test name
Test status
Simulation time 10041091877 ps
CPU time 81.69 seconds
Started May 21 02:48:25 PM PDT 24
Finished May 21 02:49:48 PM PDT 24
Peak memory 471024 kb
Host smart-0fe63d40-cece-4dfe-ba6e-8cc6f97eb744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297116998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.297116998
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1301611640
Short name T1199
Test name
Test status
Simulation time 355492866 ps
CPU time 2.45 seconds
Started May 21 02:48:27 PM PDT 24
Finished May 21 02:48:30 PM PDT 24
Peak memory 205016 kb
Host smart-50799e45-530b-4852-b591-53503bdb44c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301611640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1301611640
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.746908677
Short name T796
Test name
Test status
Simulation time 1132074209 ps
CPU time 5.59 seconds
Started May 21 02:48:23 PM PDT 24
Finished May 21 02:48:31 PM PDT 24
Peak memory 216108 kb
Host smart-10ea4bee-f023-4d04-9769-06dcacd80c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746908677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.746908677
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3406825931
Short name T4
Test name
Test status
Simulation time 12624181393 ps
CPU time 15.22 seconds
Started May 21 02:48:19 PM PDT 24
Finished May 21 02:48:38 PM PDT 24
Peak memory 423656 kb
Host smart-293578e7-6557-4bc2-ab98-1864b6cc18c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406825931 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3406825931
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.4291035684
Short name T370
Test name
Test status
Simulation time 1373816971 ps
CPU time 8.45 seconds
Started May 21 02:48:20 PM PDT 24
Finished May 21 02:48:31 PM PDT 24
Peak memory 204992 kb
Host smart-360376f5-f201-404d-ac0f-6c56092b90d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291035684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.4291035684
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1066718004
Short name T855
Test name
Test status
Simulation time 640389921 ps
CPU time 28.09 seconds
Started May 21 02:48:22 PM PDT 24
Finished May 21 02:48:53 PM PDT 24
Peak memory 205004 kb
Host smart-00dfc0a6-e3c2-469e-b290-8c1f61d85671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066718004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1066718004
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1731129725
Short name T1100
Test name
Test status
Simulation time 32086346307 ps
CPU time 324.76 seconds
Started May 21 02:48:22 PM PDT 24
Finished May 21 02:53:49 PM PDT 24
Peak memory 3247716 kb
Host smart-6ce0ce7c-d04c-47bd-983c-30aa54858555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731129725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1731129725
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.9703249
Short name T1232
Test name
Test status
Simulation time 23476458684 ps
CPU time 144.69 seconds
Started May 21 02:48:19 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 1361408 kb
Host smart-1b63bcde-969d-4e2c-8dc7-f829902151b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9703249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_stretch.9703249
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3868229383
Short name T1305
Test name
Test status
Simulation time 5678537770 ps
CPU time 6.23 seconds
Started May 21 02:48:19 PM PDT 24
Finished May 21 02:48:27 PM PDT 24
Peak memory 213360 kb
Host smart-6165b793-9d68-4285-89d8-4a6718607ab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868229383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3868229383
Directory /workspace/9.i2c_target_timeout/latest
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