Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	9	51	85.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	9	51	85.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	924266	1			T1	2		T2	1		T3	347
all_values[1]	924266	1			T1	2		T2	1		T3	347
all_values[2]	924266	1			T1	2		T2	1		T3	347
all_values[3]	924266	1			T1	2		T2	1		T3	347
all_values[4]	924266	1			T1	2		T2	1		T3	347
all_values[5]	924266	1			T1	2		T2	1		T3	347
all_values[6]	924266	1			T1	2		T2	1		T3	347
all_values[7]	924266	1			T1	2		T2	1		T3	347
all_values[8]	924266	1			T1	2		T2	1		T3	347
all_values[9]	924266	1			T1	2		T2	1		T3	347
all_values[10]	924266	1			T1	2		T2	1		T3	347
all_values[11]	924266	1			T1	2		T2	1		T3	347
all_values[12]	924266	1			T1	2		T2	1		T3	347
all_values[13]	924266	1			T1	2		T2	1		T3	347
all_values[14]	924266	1			T1	2		T2	1		T3	347

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11313473

1

T1

30

T2

15

T3

4448

auto[1]

2550517

1

T3

757

T5

164

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11377247

1

T1

30

T2

15

T3

5205

auto[1]

2486743

1

T9

63

T93

55779

T138

251909

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	9	51	85.00	9

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83698	1			T1	2		T2	1		T3	7
all_values[0]	auto[0]	auto[1]	20731	1			T93	11		T138	1626		T223	2
all_values[0]	auto[1]	auto[0]	658078	1			T3	340		T5	79		T6	2
all_values[0]	auto[1]	auto[1]	161759	1			T9	4		T93	3707		T138	15169
all_values[1]	auto[0]	auto[0]	758813	1			T1	2		T2	1		T3	347
all_values[1]	auto[0]	auto[1]	165000	1			T9	3		T93	3708		T138	16789
all_values[1]	auto[1]	auto[0]	217	1			T7	1		T224	2		T48	9
all_values[1]	auto[1]	auto[1]	236	1			T9	1		T93	12		T138	3
all_values[2]	auto[0]	auto[0]	747086	1			T1	2		T2	1		T3	347
all_values[2]	auto[0]	auto[1]	176999	1			T9	4		T93	3714		T138	16790
all_values[2]	auto[1]	auto[1]	181	1			T9	2		T93	5		T138	5
all_values[3]	auto[0]	auto[0]	780228	1			T1	2		T2	1		T3	347
all_values[3]	auto[0]	auto[1]	143838	1			T9	2		T93	3715		T138	16787
all_values[3]	auto[1]	auto[1]	200	1			T9	2		T93	3		T138	7
all_values[4]	auto[0]	auto[0]	758262	1			T1	2		T2	1		T3	347
all_values[4]	auto[0]	auto[1]	165825	1			T9	5		T93	3714		T138	16791
all_values[4]	auto[1]	auto[0]	18	1			T41	1		T225	1		T226	1
all_values[4]	auto[1]	auto[1]	161	1			T9	1		T93	4		T138	4
all_values[5]	auto[0]	auto[0]	742050	1			T1	2		T2	1		T3	347
all_values[5]	auto[0]	auto[1]	182019	1			T93	3717		T138	16790		T139	2
all_values[5]	auto[1]	auto[1]	197	1			T93	1		T138	2		T139	3
all_values[6]	auto[0]	auto[0]	779949	1			T1	2		T2	1		T3	347
all_values[6]	auto[0]	auto[1]	144116	1			T9	5		T93	3715		T138	16788
all_values[6]	auto[1]	auto[1]	201	1			T9	1		T93	5		T138	3
all_values[7]	auto[0]	auto[0]	716430	1			T1	2		T2	1		T3	290
all_values[7]	auto[0]	auto[1]	177835	1			T9	2		T93	3574		T138	16540
all_values[7]	auto[1]	auto[0]	25365	1			T3	57		T7	130		T9	180
all_values[7]	auto[1]	auto[1]	4636	1			T9	4		T93	146		T138	255
all_values[8]	auto[0]	auto[0]	774927	1			T1	2		T2	1		T3	347
all_values[8]	auto[0]	auto[1]	149127	1			T93	3712		T138	16791		T139	5
all_values[8]	auto[1]	auto[1]	212	1			T93	7		T138	4		T139	4
all_values[9]	auto[0]	auto[0]	133435	1			T1	2		T2	1		T3	330
all_values[9]	auto[0]	auto[1]	13527	1			T9	3		T93	114		T138	1730
all_values[9]	auto[1]	auto[0]	608356	1			T3	17		T5	5		T7	27
all_values[9]	auto[1]	auto[1]	168948	1			T9	3		T93	3605		T138	15064
all_values[10]	auto[0]	auto[0]	747080	1			T1	2		T2	1		T3	347
all_values[10]	auto[0]	auto[1]	177005	1			T9	3		T93	3714		T138	16791
all_values[10]	auto[1]	auto[1]	181	1			T9	1		T93	5		T138	4
all_values[11]	auto[0]	auto[0]	2753	1			T1	2		T2	1		T3	4
all_values[11]	auto[0]	auto[1]	555	1			T93	12		T138	30		T227	24
all_values[11]	auto[1]	auto[0]	739049	1			T3	343		T5	80		T6	2
all_values[11]	auto[1]	auto[1]	181909	1			T9	5		T93	3708		T138	16765
all_values[12]	auto[0]	auto[0]	776702	1			T1	2		T2	1		T3	347
all_values[12]	auto[0]	auto[1]	147397	1			T9	4		T93	3709		T138	16791
all_values[12]	auto[1]	auto[1]	167	1			T9	2		T93	2		T138	4
all_values[13]	auto[0]	auto[0]	791109	1			T1	2		T2	1		T3	347
all_values[13]	auto[0]	auto[1]	132913	1			T93	3714		T138	16789		T139	3
all_values[13]	auto[1]	auto[1]	244	1			T93	6		T138	6		T139	6
all_values[14]	auto[0]	auto[0]	753642	1			T1	2		T2	1		T3	347
all_values[14]	auto[0]	auto[1]	170422	1			T9	5		T93	3719		T138	16786
all_values[14]	auto[1]	auto[1]	202	1			T9	1		T93	1		T138	5