Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_stretch_cg

Group : i2c_env_pkg::i2c_scl_stretch_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group i2c_env_pkg::i2c_scl_stretch_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_fifo_size	2	0	2	100.00	100	1	1	0
cp_host_mode_stretch	1	0	1	100.00	100	1	1	0
cp_target_scl_stretch_addr_write	1	0	1	100.00	100	1	1	0
cp_tx_fifo_size	2	0	2	100.00	100	1	1	0

Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_target_scl_stretch_read	4	0	4	100.00	100	1	1	0

Summary for Variable cp_acq_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_acq_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

90441562

1

T6

2767

T8

1693

T11

30263

empty

92210181

1

T3

65247

T6

438

T7

138076

---

Summary for Variable cp_host_mode_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

stretch

57544128

1

T3

61716

T7

684977

T9

328183

---

Summary for Variable cp_target_scl_stretch_addr_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_target_scl_stretch_addr_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

addr_write_byte_stretch

260702

1

T18

3033

T19

1867

T20

12522

---

Summary for Variable cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_tx_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

47755742

1

T6

1082

T8

1239

T11

28541

empty

134896024

1

T3

65247

T6

2123

T7

138076

---

Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins

cp_acq_fifo_size

cp_tx_fifo_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

not_empty

2

1

T204

2

-

-

-

-

empty

empty

1281879

1

T6

438

T11

3270

T28

1124

User Defined Cross Bins for cp_target_scl_stretch_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_byte_stretch

450833

1

T6

1685

T8

201

T11

1770

scl_stretch_read_request

47956821

1

T6

2767

T8

1440

T11

29844