Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	924266	1			T1	2		T2	1		T3	347
all_pins[1]	924266	1			T1	2		T2	1		T3	347
all_pins[2]	924266	1			T1	2		T2	1		T3	347
all_pins[3]	924266	1			T1	2		T2	1		T3	347
all_pins[4]	924266	1			T1	2		T2	1		T3	347
all_pins[5]	924266	1			T1	2		T2	1		T3	347
all_pins[6]	924266	1			T1	2		T2	1		T3	347
all_pins[7]	924266	1			T1	2		T2	1		T3	347
all_pins[8]	924266	1			T1	2		T2	1		T3	347
all_pins[9]	924266	1			T1	2		T2	1		T3	347
all_pins[10]	924266	1			T1	2		T2	1		T3	347
all_pins[11]	924266	1			T1	2		T2	1		T3	347
all_pins[12]	924266	1			T1	2		T2	1		T3	347
all_pins[13]	924266	1			T1	2		T2	1		T3	347
all_pins[14]	924266	1			T1	2		T2	1		T3	347

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11318162	1			T1	30		T2	15		T3	4444
values[0x1]	2545828	1			T3	761		T5	5		T6	4
transitions[0x0=>0x1]	2545131	1			T3	761		T5	5		T6	4
transitions[0x1=>0x0]	2544115	1			T3	760		T5	5		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	107639	1			T1	2		T2	1		T3	7
all_pins[0]	values[0x1]	816627	1			T3	340		T6	2		T7	1130
all_pins[0]	transitions[0x0=>0x1]	816272	1			T3	340		T6	2		T7	1128
all_pins[0]	transitions[0x1=>0x0]	54	1			T93	1		T224	2		T138	1
all_pins[1]	values[0x0]	923857	1			T1	2		T2	1		T3	347
all_pins[1]	values[0x1]	409	1			T7	2		T93	12		T224	2
all_pins[1]	transitions[0x0=>0x1]	388	1			T7	2		T93	12		T224	2
all_pins[1]	transitions[0x1=>0x0]	78	1			T9	2		T93	1		T138	2
all_pins[2]	values[0x0]	924167	1			T1	2		T2	1		T3	347
all_pins[2]	values[0x1]	99	1			T9	2		T93	1		T138	2
all_pins[2]	transitions[0x0=>0x1]	81	1			T9	1		T93	1		T138	2
all_pins[2]	transitions[0x1=>0x0]	77	1			T9	1		T93	1		T138	2
all_pins[3]	values[0x0]	924171	1			T1	2		T2	1		T3	347
all_pins[3]	values[0x1]	95	1			T9	2		T93	1		T138	2
all_pins[3]	transitions[0x0=>0x1]	77	1			T9	2		T93	1		T138	2
all_pins[3]	transitions[0x1=>0x0]	69	1			T41	1		T93	3		T162	1
all_pins[4]	values[0x0]	924179	1			T1	2		T2	1		T3	347
all_pins[4]	values[0x1]	87	1			T41	1		T93	3		T162	1
all_pins[4]	transitions[0x0=>0x1]	73	1			T41	1		T93	2		T162	1
all_pins[4]	transitions[0x1=>0x0]	82	1			T223	1		T227	5		T256	1
all_pins[5]	values[0x0]	924170	1			T1	2		T2	1		T3	347
all_pins[5]	values[0x1]	96	1			T93	1		T223	2		T227	5
all_pins[5]	transitions[0x0=>0x1]	71	1			T93	1		T223	2		T227	2
all_pins[5]	transitions[0x1=>0x0]	61	1			T93	1		T139	4		T223	2
all_pins[6]	values[0x0]	924180	1			T1	2		T2	1		T3	347
all_pins[6]	values[0x1]	86	1			T93	1		T139	4		T223	2
all_pins[6]	transitions[0x0=>0x1]	66	1			T93	1		T139	4		T223	1
all_pins[6]	transitions[0x1=>0x0]	33170	1			T3	61		T7	143		T9	215
all_pins[7]	values[0x0]	891076	1			T1	2		T2	1		T3	286
all_pins[7]	values[0x1]	33190	1			T3	61		T7	143		T9	215
all_pins[7]	transitions[0x0=>0x1]	33160	1			T3	61		T7	143		T9	215
all_pins[7]	transitions[0x1=>0x0]	71	1			T93	2		T138	2		T139	1
all_pins[8]	values[0x0]	924165	1			T1	2		T2	1		T3	347
all_pins[8]	values[0x1]	101	1			T93	2		T138	2		T139	1
all_pins[8]	transitions[0x0=>0x1]	82	1			T93	1		T138	1		T223	2
all_pins[8]	transitions[0x1=>0x0]	777198	1			T3	17		T5	5		T7	27
all_pins[9]	values[0x0]	147049	1			T1	2		T2	1		T3	330
all_pins[9]	values[0x1]	777217	1			T3	17		T5	5		T7	27
all_pins[9]	transitions[0x0=>0x1]	777189	1			T3	17		T5	5		T7	27
all_pins[9]	transitions[0x1=>0x0]	67	1			T93	4		T138	3		T139	1
all_pins[10]	values[0x0]	924171	1			T1	2		T2	1		T3	347
all_pins[10]	values[0x1]	95	1			T93	4		T138	4		T139	1
all_pins[10]	transitions[0x0=>0x1]	66	1			T93	2		T138	3		T139	1
all_pins[10]	transitions[0x1=>0x0]	917397	1			T3	343		T6	2		T7	1131
all_pins[11]	values[0x0]	6840	1			T1	2		T2	1		T3	4
all_pins[11]	values[0x1]	917426	1			T3	343		T6	2		T7	1131
all_pins[11]	transitions[0x0=>0x1]	917407	1			T3	343		T6	2		T7	1131
all_pins[11]	transitions[0x1=>0x0]	55	1			T139	2		T256	1		T101	3
all_pins[12]	values[0x0]	924192	1			T1	2		T2	1		T3	347
all_pins[12]	values[0x1]	74	1			T139	2		T227	2		T256	2
all_pins[12]	transitions[0x0=>0x1]	51	1			T227	2		T256	2		T101	3
all_pins[12]	transitions[0x1=>0x0]	95	1			T93	2		T139	2		T223	2
all_pins[13]	values[0x0]	924148	1			T1	2		T2	1		T3	347
all_pins[13]	values[0x1]	118	1			T93	2		T139	4		T223	2
all_pins[13]	transitions[0x0=>0x1]	80	1			T93	1		T139	3		T223	1
all_pins[13]	transitions[0x1=>0x0]	70	1			T138	3		T139	1		T223	3
all_pins[14]	values[0x0]	924158	1			T1	2		T2	1		T3	347
all_pins[14]	values[0x1]	108	1			T93	1		T138	3		T139	2
all_pins[14]	transitions[0x0=>0x1]	68	1			T93	1		T138	3		T139	2
all_pins[14]	transitions[0x1=>0x0]	815571	1			T3	339		T6	1		T7	1130