Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	458	1			T9	4		T93	11		T138	11
all_values[1]	458	1			T9	4		T93	11		T138	11
all_values[2]	458	1			T9	4		T93	11		T138	11
all_values[3]	458	1			T9	4		T93	11		T138	11
all_values[4]	458	1			T9	4		T93	11		T138	11
all_values[5]	458	1			T9	4		T93	11		T138	11
all_values[6]	458	1			T9	4		T93	11		T138	11
all_values[7]	458	1			T9	4		T93	11		T138	11
all_values[8]	458	1			T9	4		T93	11		T138	11
all_values[9]	458	1			T9	4		T93	11		T138	11
all_values[10]	458	1			T9	4		T93	11		T138	11
all_values[11]	458	1			T9	4		T93	11		T138	11
all_values[12]	458	1			T9	4		T93	11		T138	11
all_values[13]	458	1			T9	4		T93	11		T138	11
all_values[14]	458	1			T9	4		T93	11		T138	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3665

1

T9

32

T93

87

T138

80

auto[1]

3205

1

T9

28

T93

78

T138

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1175

1

T9

21

T93

20

T138

16

auto[1]

5695

1

T9

39

T93

145

T138

149

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4136

1

T9

40

T93

97

T138

105

auto[1]

2734

1

T9

20

T93

68

T138

60

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T9	2		T139	2		T223	2
all_values[0]	auto[0]	auto[0]	auto[1]	98	1			T9	1		T93	4		T138	1
all_values[0]	auto[0]	auto[1]	auto[0]	24	1			T93	2		T139	1		T96	1
all_values[0]	auto[0]	auto[1]	auto[1]	107	1			T93	2		T138	4		T139	2
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T9	1		T93	1		T138	2
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T93	2		T138	4		T227	2
all_values[1]	auto[0]	auto[0]	auto[0]	52	1			T138	3		T51	2		T233	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T9	1		T93	6		T138	2
all_values[1]	auto[0]	auto[1]	auto[0]	50	1			T9	2		T256	3		T243	4
all_values[1]	auto[0]	auto[1]	auto[1]	94	1			T93	1		T138	3		T139	3
all_values[1]	auto[1]	auto[0]	auto[1]	95	1			T9	1		T93	2		T138	2
all_values[1]	auto[1]	auto[1]	auto[1]	75	1			T93	2		T138	1		T139	2
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T257	1		T104	3		T106	2
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T93	4		T138	2		T139	2
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T93	1		T258	5		T243	4
all_values[2]	auto[0]	auto[1]	auto[1]	110	1			T9	2		T93	1		T138	4
all_values[2]	auto[1]	auto[0]	auto[1]	92	1			T93	4		T138	3		T139	2
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T9	2		T93	1		T138	2
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T9	2		T93	1		T138	1
all_values[3]	auto[0]	auto[0]	auto[1]	105	1			T93	1		T138	4		T139	1
all_values[3]	auto[0]	auto[1]	auto[0]	34	1			T93	1		T227	4		T256	3
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T9	1		T93	5		T138	3
all_values[3]	auto[1]	auto[0]	auto[1]	97	1			T93	2		T138	3		T227	3
all_values[3]	auto[1]	auto[1]	auto[1]	77	1			T9	1		T93	1		T139	3
all_values[4]	auto[0]	auto[0]	auto[0]	59	1			T93	1		T139	1		T96	1
all_values[4]	auto[0]	auto[0]	auto[1]	103	1			T9	3		T93	4		T138	4
all_values[4]	auto[0]	auto[1]	auto[0]	36	1			T93	1		T139	1		T259	1
all_values[4]	auto[0]	auto[1]	auto[1]	99	1			T93	1		T138	3		T139	4
all_values[4]	auto[1]	auto[0]	auto[1]	94	1			T9	1		T93	2		T138	3
all_values[4]	auto[1]	auto[1]	auto[1]	67	1			T93	2		T138	1		T139	1
all_values[5]	auto[0]	auto[0]	auto[0]	49	1			T138	3		T139	3		T227	4
all_values[5]	auto[0]	auto[0]	auto[1]	106	1			T93	3		T138	3		T139	2
all_values[5]	auto[0]	auto[1]	auto[0]	23	1			T9	4		T93	2		T139	1
all_values[5]	auto[0]	auto[1]	auto[1]	100	1			T93	3		T138	3		T223	1
all_values[5]	auto[1]	auto[0]	auto[1]	98	1			T93	2		T138	1		T223	1
all_values[5]	auto[1]	auto[1]	auto[1]	82	1			T93	1		T138	1		T139	1
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T138	1		T243	2		T51	2
all_values[6]	auto[0]	auto[0]	auto[1]	101	1			T9	2		T93	3		T138	2
all_values[6]	auto[0]	auto[1]	auto[0]	30	1			T138	3		T259	1		T258	5
all_values[6]	auto[0]	auto[1]	auto[1]	103	1			T93	2		T138	3		T139	2
all_values[6]	auto[1]	auto[0]	auto[1]	109	1			T9	2		T93	2		T138	2
all_values[6]	auto[1]	auto[1]	auto[1]	71	1			T93	4		T139	2		T223	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T139	1		T223	2		T101	1
all_values[7]	auto[0]	auto[0]	auto[1]	98	1			T93	4		T138	1		T139	1
all_values[7]	auto[0]	auto[1]	auto[0]	38	1			T139	2		T223	2		T258	1
all_values[7]	auto[0]	auto[1]	auto[1]	97	1			T9	1		T93	1		T138	6
all_values[7]	auto[1]	auto[0]	auto[1]	92	1			T93	5		T138	2		T139	2
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T9	3		T93	1		T138	2
all_values[8]	auto[0]	auto[0]	auto[0]	45	1			T227	1		T256	2		T96	1
all_values[8]	auto[0]	auto[0]	auto[1]	93	1			T93	3		T138	2		T139	3
all_values[8]	auto[0]	auto[1]	auto[0]	40	1			T9	4		T93	1		T227	3
all_values[8]	auto[0]	auto[1]	auto[1]	95	1			T138	4		T223	3		T227	3
all_values[8]	auto[1]	auto[0]	auto[1]	94	1			T93	3		T138	1		T139	2
all_values[8]	auto[1]	auto[1]	auto[1]	91	1			T93	4		T138	4		T139	2
all_values[9]	auto[0]	auto[0]	auto[0]	52	1			T138	1		T223	2		T227	1
all_values[9]	auto[0]	auto[0]	auto[1]	98	1			T9	1		T93	1		T138	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T93	1		T139	1		T103	1
all_values[9]	auto[0]	auto[1]	auto[1]	84	1			T93	4		T138	5		T139	2
all_values[9]	auto[1]	auto[0]	auto[1]	111	1			T9	3		T93	2		T138	1
all_values[9]	auto[1]	auto[1]	auto[1]	88	1			T93	3		T138	3		T223	2
all_values[10]	auto[0]	auto[0]	auto[0]	41	1			T9	2		T139	3		T223	1
all_values[10]	auto[0]	auto[0]	auto[1]	113	1			T9	1		T93	3		T223	2
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T93	1		T139	2		T256	1
all_values[10]	auto[0]	auto[1]	auto[1]	94	1			T93	2		T138	7		T139	1
all_values[10]	auto[1]	auto[0]	auto[1]	97	1			T9	1		T93	1		T138	2
all_values[10]	auto[1]	auto[1]	auto[1]	84	1			T93	4		T138	2		T139	1
all_values[11]	auto[0]	auto[0]	auto[0]	53	1			T9	1		T223	7		T96	1
all_values[11]	auto[0]	auto[0]	auto[1]	97	1			T93	6		T138	1		T139	3
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T139	1		T259	1		T101	1
all_values[11]	auto[0]	auto[1]	auto[1]	102	1			T9	2		T93	2		T138	3
all_values[11]	auto[1]	auto[0]	auto[1]	98	1			T9	1		T93	1		T138	5
all_values[11]	auto[1]	auto[1]	auto[1]	84	1			T93	2		T138	2		T139	1
all_values[12]	auto[0]	auto[0]	auto[0]	47	1			T93	5		T223	3		T96	4
all_values[12]	auto[0]	auto[0]	auto[1]	97	1			T9	2		T93	1		T138	6
all_values[12]	auto[0]	auto[1]	auto[0]	38	1			T93	3		T259	1		T258	1
all_values[12]	auto[0]	auto[1]	auto[1]	109	1			T138	1		T139	3		T227	3
all_values[12]	auto[1]	auto[0]	auto[1]	95	1			T9	2		T93	1		T138	4
all_values[12]	auto[1]	auto[1]	auto[1]	72	1			T93	1		T139	2		T227	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T223	1		T227	1		T101	1
all_values[13]	auto[0]	auto[0]	auto[1]	88	1			T93	3		T138	5		T227	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1			T9	4		T223	2		T259	1
all_values[13]	auto[0]	auto[1]	auto[1]	97	1			T93	1		T138	3		T139	1
all_values[13]	auto[1]	auto[0]	auto[1]	108	1			T93	2		T138	2		T139	3
all_values[13]	auto[1]	auto[1]	auto[1]	102	1			T93	5		T138	1		T139	3
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T138	2		T223	1		T96	2
all_values[14]	auto[0]	auto[0]	auto[1]	92	1			T93	3		T138	1		T227	3
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T138	2		T139	1		T256	2
all_values[14]	auto[0]	auto[1]	auto[1]	96	1			T9	2		T93	3		T138	2
all_values[14]	auto[1]	auto[0]	auto[1]	106	1			T9	2		T93	1		T138	1
all_values[14]	auto[1]	auto[1]	auto[1]	88	1			T93	4		T138	3		T139	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal