SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
91.03 | 96.59 | 89.81 | 97.67 | 70.24 | 93.62 | 98.44 | 90.84 |
T1308 | /workspace/coverage/default/39.i2c_host_fifo_overflow.262257461 | May 23 12:36:25 PM PDT 24 | May 23 12:37:27 PM PDT 24 | 4302618078 ps | ||
T1309 | /workspace/coverage/default/34.i2c_target_stress_wr.1222038620 | May 23 12:36:04 PM PDT 24 | May 23 12:36:36 PM PDT 24 | 23711084638 ps | ||
T1310 | /workspace/coverage/default/17.i2c_target_stress_rd.2903125676 | May 23 12:34:11 PM PDT 24 | May 23 12:34:38 PM PDT 24 | 2277724088 ps | ||
T1311 | /workspace/coverage/default/14.i2c_target_fifo_reset_tx.340973763 | May 23 12:33:59 PM PDT 24 | May 23 12:34:32 PM PDT 24 | 10121984395 ps | ||
T1312 | /workspace/coverage/default/14.i2c_host_fifo_full.3615601258 | May 23 12:33:49 PM PDT 24 | May 23 12:34:55 PM PDT 24 | 4092092992 ps | ||
T1313 | /workspace/coverage/default/17.i2c_host_mode_toggle.532501073 | May 23 12:34:13 PM PDT 24 | May 23 12:35:39 PM PDT 24 | 9786412887 ps | ||
T1314 | /workspace/coverage/default/12.i2c_host_fifo_reset_rx.368756862 | May 23 12:33:35 PM PDT 24 | May 23 12:33:48 PM PDT 24 | 813869948 ps | ||
T1315 | /workspace/coverage/default/42.i2c_target_stress_wr.3721421957 | May 23 12:37:00 PM PDT 24 | May 23 12:38:42 PM PDT 24 | 38262332864 ps | ||
T1316 | /workspace/coverage/default/44.i2c_host_stretch_timeout.2483497933 | May 23 12:36:57 PM PDT 24 | May 23 12:37:15 PM PDT 24 | 835752442 ps | ||
T1317 | /workspace/coverage/default/21.i2c_host_perf.3161514076 | May 23 12:34:40 PM PDT 24 | May 23 12:35:20 PM PDT 24 | 3186706322 ps | ||
T1318 | /workspace/coverage/default/31.i2c_target_intr_stress_wr.1232763195 | May 23 12:35:41 PM PDT 24 | May 23 12:35:49 PM PDT 24 | 9880345203 ps | ||
T1319 | /workspace/coverage/default/32.i2c_host_stretch_timeout.3705683540 | May 23 12:35:45 PM PDT 24 | May 23 12:36:09 PM PDT 24 | 520018818 ps | ||
T233 | /workspace/coverage/default/27.i2c_host_stress_all.2951881473 | May 23 12:35:15 PM PDT 24 | May 23 01:00:21 PM PDT 24 | 58563149177 ps | ||
T1320 | /workspace/coverage/default/40.i2c_target_stress_wr.1541060951 | May 23 12:36:45 PM PDT 24 | May 23 12:43:33 PM PDT 24 | 35708501803 ps | ||
T1321 | /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3120727851 | May 23 12:34:31 PM PDT 24 | May 23 12:35:38 PM PDT 24 | 10125648391 ps | ||
T1322 | /workspace/coverage/default/32.i2c_host_mode_toggle.2382594741 | May 23 12:35:45 PM PDT 24 | May 23 12:37:15 PM PDT 24 | 1970458129 ps | ||
T1323 | /workspace/coverage/default/8.i2c_host_stretch_timeout.1021900701 | May 23 12:33:13 PM PDT 24 | May 23 12:33:28 PM PDT 24 | 756324464 ps | ||
T1324 | /workspace/coverage/default/22.i2c_target_fifo_reset_tx.4257263843 | May 23 12:34:41 PM PDT 24 | May 23 12:34:57 PM PDT 24 | 10415019077 ps | ||
T1325 | /workspace/coverage/default/17.i2c_host_may_nack.593668463 | May 23 12:34:11 PM PDT 24 | May 23 12:34:23 PM PDT 24 | 1487573821 ps | ||
T1326 | /workspace/coverage/default/1.i2c_host_may_nack.566954234 | May 23 12:32:35 PM PDT 24 | May 23 12:32:48 PM PDT 24 | 1146056506 ps | ||
T1327 | /workspace/coverage/default/10.i2c_target_smoke.1720629064 | May 23 12:33:24 PM PDT 24 | May 23 12:34:01 PM PDT 24 | 900422162 ps | ||
T1328 | /workspace/coverage/default/15.i2c_host_smoke.1285427765 | May 23 12:34:03 PM PDT 24 | May 23 12:34:35 PM PDT 24 | 1535280253 ps | ||
T1329 | /workspace/coverage/default/22.i2c_host_smoke.2336527261 | May 23 12:34:41 PM PDT 24 | May 23 12:35:11 PM PDT 24 | 6777901768 ps | ||
T1330 | /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4062905737 | May 23 12:37:33 PM PDT 24 | May 23 12:37:50 PM PDT 24 | 293376560 ps | ||
T1331 | /workspace/coverage/default/14.i2c_target_stress_wr.3733070859 | May 23 12:33:51 PM PDT 24 | May 23 12:34:03 PM PDT 24 | 15989759207 ps | ||
T1332 | /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2800038277 | May 23 12:35:32 PM PDT 24 | May 23 12:35:39 PM PDT 24 | 190122534 ps | ||
T1333 | /workspace/coverage/default/47.i2c_target_bad_addr.4280662234 | May 23 12:37:17 PM PDT 24 | May 23 12:37:23 PM PDT 24 | 650645250 ps | ||
T1334 | /workspace/coverage/default/37.i2c_target_timeout.233255992 | May 23 12:36:26 PM PDT 24 | May 23 12:36:36 PM PDT 24 | 1367442641 ps | ||
T1335 | /workspace/coverage/default/15.i2c_target_bad_addr.2984898126 | May 23 12:33:58 PM PDT 24 | May 23 12:34:03 PM PDT 24 | 1688263018 ps | ||
T1336 | /workspace/coverage/default/42.i2c_host_smoke.170767938 | May 23 12:36:40 PM PDT 24 | May 23 12:37:13 PM PDT 24 | 37715364196 ps | ||
T1337 | /workspace/coverage/default/49.i2c_host_smoke.2114959014 | May 23 12:37:34 PM PDT 24 | May 23 12:38:02 PM PDT 24 | 6370009947 ps | ||
T1338 | /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3469087371 | May 23 12:33:13 PM PDT 24 | May 23 12:34:43 PM PDT 24 | 10082727573 ps | ||
T1339 | /workspace/coverage/default/29.i2c_target_stretch.1733533470 | May 23 12:35:31 PM PDT 24 | May 23 12:40:15 PM PDT 24 | 18159630299 ps | ||
T1340 | /workspace/coverage/default/12.i2c_target_bad_addr.588469732 | May 23 12:33:48 PM PDT 24 | May 23 12:33:56 PM PDT 24 | 857506846 ps | ||
T1341 | /workspace/coverage/default/0.i2c_target_intr_smoke.2919481364 | May 23 12:32:35 PM PDT 24 | May 23 12:32:41 PM PDT 24 | 1220710606 ps | ||
T1342 | /workspace/coverage/default/12.i2c_target_fifo_reset_tx.400376433 | May 23 12:33:49 PM PDT 24 | May 23 12:35:00 PM PDT 24 | 10054928870 ps | ||
T1343 | /workspace/coverage/default/36.i2c_target_smoke.3372337957 | May 23 12:36:08 PM PDT 24 | May 23 12:36:39 PM PDT 24 | 3024657620 ps | ||
T1344 | /workspace/coverage/default/31.i2c_target_hrst.292933861 | May 23 12:35:46 PM PDT 24 | May 23 12:35:51 PM PDT 24 | 407567946 ps | ||
T1345 | /workspace/coverage/default/35.i2c_target_stress_wr.2644486768 | May 23 12:36:11 PM PDT 24 | May 23 12:37:02 PM PDT 24 | 62551393624 ps | ||
T135 | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1906325794 | May 23 12:26:47 PM PDT 24 | May 23 12:26:50 PM PDT 24 | 78438377 ps | ||
T136 | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4185250165 | May 23 12:26:51 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 1682737349 ps | ||
T137 | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.256324805 | May 23 12:26:50 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 47636666 ps | ||
T82 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3189515520 | May 23 12:26:53 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 56148893 ps | ||
T104 | /workspace/coverage/cover_reg_top/45.i2c_intr_test.1587875907 | May 23 12:27:08 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 34292401 ps | ||
T105 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.174039779 | May 23 12:27:02 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 50811835 ps | ||
T106 | /workspace/coverage/cover_reg_top/23.i2c_intr_test.542449974 | May 23 12:27:08 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 20901890 ps | ||
T107 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3845513048 | May 23 12:27:12 PM PDT 24 | May 23 12:27:16 PM PDT 24 | 31735111 ps | ||
T83 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4082728586 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 128542522 ps | ||
T84 | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2171552843 | May 23 12:27:01 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 73611921 ps | ||
T1346 | /workspace/coverage/cover_reg_top/4.i2c_intr_test.661987336 | May 23 12:26:52 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 34612055 ps | ||
T210 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3177915637 | May 23 12:26:49 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 61675281 ps | ||
T1347 | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1606066153 | May 23 12:26:57 PM PDT 24 | May 23 12:27:00 PM PDT 24 | 42172246 ps | ||
T172 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3206664053 | May 23 12:26:56 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 37704034 ps | ||
T173 | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3452905773 | May 23 12:26:51 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 74532767 ps | ||
T183 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3327129123 | May 23 12:26:49 PM PDT 24 | May 23 12:26:54 PM PDT 24 | 40373957 ps | ||
T211 | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.4106157007 | May 23 12:26:49 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 69652254 ps | ||
T140 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.743618674 | May 23 12:27:02 PM PDT 24 | May 23 12:27:08 PM PDT 24 | 77166448 ps | ||
T85 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2921830527 | May 23 12:26:51 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 52158038 ps | ||
T86 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1097673562 | May 23 12:26:50 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 82623803 ps | ||
T195 | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1014767253 | May 23 12:26:38 PM PDT 24 | May 23 12:26:42 PM PDT 24 | 24583810 ps | ||
T1348 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.46633796 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 51484050 ps | ||
T184 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.726335192 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 65876880 ps | ||
T180 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4282026443 | May 23 12:26:47 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 271045363 ps | ||
T1349 | /workspace/coverage/cover_reg_top/2.i2c_intr_test.2312880426 | May 23 12:26:41 PM PDT 24 | May 23 12:26:45 PM PDT 24 | 76797171 ps | ||
T212 | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.966494374 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 97318916 ps | ||
T213 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3497349760 | May 23 12:26:38 PM PDT 24 | May 23 12:26:43 PM PDT 24 | 36832854 ps | ||
T181 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2814300113 | May 23 12:26:37 PM PDT 24 | May 23 12:26:42 PM PDT 24 | 514200361 ps | ||
T182 | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2235436453 | May 23 12:27:09 PM PDT 24 | May 23 12:27:15 PM PDT 24 | 282883606 ps | ||
T198 | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.642063148 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 42592723 ps | ||
T185 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3606249366 | May 23 12:26:51 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 19078698 ps | ||
T1350 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.553445136 | May 23 12:27:53 PM PDT 24 | May 23 12:27:57 PM PDT 24 | 61424956 ps | ||
T188 | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1835016902 | May 23 12:27:01 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 23794390 ps | ||
T186 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.719463100 | May 23 12:26:48 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 260802374 ps | ||
T1351 | /workspace/coverage/cover_reg_top/21.i2c_intr_test.4094894440 | May 23 12:27:06 PM PDT 24 | May 23 12:27:11 PM PDT 24 | 44856698 ps | ||
T187 | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3542039354 | May 23 12:26:47 PM PDT 24 | May 23 12:26:51 PM PDT 24 | 91769304 ps | ||
T1352 | /workspace/coverage/cover_reg_top/32.i2c_intr_test.3224992449 | May 23 12:26:59 PM PDT 24 | May 23 12:27:03 PM PDT 24 | 25170958 ps | ||
T1353 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4013861742 | May 23 12:26:41 PM PDT 24 | May 23 12:26:50 PM PDT 24 | 1747214850 ps | ||
T1354 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.788776713 | May 23 12:26:51 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 20163079 ps | ||
T1355 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.691684402 | May 23 12:27:09 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 31600184 ps | ||
T1356 | /workspace/coverage/cover_reg_top/7.i2c_intr_test.971146473 | May 23 12:26:49 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 56086746 ps | ||
T1357 | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4271432999 | May 23 12:26:51 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 81418292 ps | ||
T87 | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1995281172 | May 23 12:26:52 PM PDT 24 | May 23 12:27:00 PM PDT 24 | 153552539 ps | ||
T193 | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1204767905 | May 23 12:26:47 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 518495693 ps | ||
T88 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.147845332 | May 23 12:27:04 PM PDT 24 | May 23 12:27:11 PM PDT 24 | 805259669 ps | ||
T1358 | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.236574057 | May 23 12:26:49 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 93690110 ps | ||
T1359 | /workspace/coverage/cover_reg_top/33.i2c_intr_test.362560605 | May 23 12:27:10 PM PDT 24 | May 23 12:27:14 PM PDT 24 | 29696633 ps | ||
T199 | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1741290347 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 16799288 ps | ||
T1360 | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3312098785 | May 23 12:27:04 PM PDT 24 | May 23 12:27:10 PM PDT 24 | 21024001 ps | ||
T1361 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2384098457 | May 23 12:27:00 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 715137178 ps | ||
T1362 | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1493955863 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 48599681 ps | ||
T1363 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1011640148 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 20112448 ps | ||
T89 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.280837295 | May 23 12:27:05 PM PDT 24 | May 23 12:27:11 PM PDT 24 | 172501408 ps | ||
T90 | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2859874279 | May 23 12:26:47 PM PDT 24 | May 23 12:26:51 PM PDT 24 | 28083535 ps | ||
T91 | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.262769784 | May 23 12:26:58 PM PDT 24 | May 23 12:27:02 PM PDT 24 | 22107643 ps | ||
T134 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3338243396 | May 23 12:27:00 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 541162025 ps | ||
T200 | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1155036031 | May 23 12:26:52 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 23514162 ps | ||
T1364 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2295141198 | May 23 12:26:41 PM PDT 24 | May 23 12:26:45 PM PDT 24 | 127376476 ps | ||
T1365 | /workspace/coverage/cover_reg_top/26.i2c_intr_test.3858584376 | May 23 12:27:09 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 28312905 ps | ||
T1366 | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2527191956 | May 23 12:26:57 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 63088102 ps | ||
T1367 | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2453324173 | May 23 12:27:03 PM PDT 24 | May 23 12:27:09 PM PDT 24 | 123008614 ps | ||
T1368 | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1493266880 | May 23 12:27:01 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 917281548 ps | ||
T1369 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.828399658 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 85249398 ps | ||
T201 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1954803190 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 22274101 ps | ||
T189 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3792625323 | May 23 12:26:52 PM PDT 24 | May 23 12:26:59 PM PDT 24 | 1465484987 ps | ||
T1370 | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1636900518 | May 23 12:26:53 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 205991367 ps | ||
T1371 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.425719206 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 18140112 ps | ||
T1372 | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2488435808 | May 23 12:26:51 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 18766757 ps | ||
T1373 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1545066473 | May 23 12:26:49 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 53194878 ps | ||
T1374 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.980290446 | May 23 12:26:53 PM PDT 24 | May 23 12:26:59 PM PDT 24 | 133660138 ps | ||
T238 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.889374716 | May 23 12:26:51 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 155433237 ps | ||
T196 | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3457685030 | May 23 12:26:43 PM PDT 24 | May 23 12:26:48 PM PDT 24 | 750150076 ps | ||
T1375 | /workspace/coverage/cover_reg_top/22.i2c_intr_test.3857023385 | May 23 12:27:10 PM PDT 24 | May 23 12:27:15 PM PDT 24 | 45025401 ps | ||
T1376 | /workspace/coverage/cover_reg_top/14.i2c_intr_test.1083694350 | May 23 12:26:49 PM PDT 24 | May 23 12:26:54 PM PDT 24 | 46145599 ps | ||
T1377 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3037836898 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 73552051 ps | ||
T1378 | /workspace/coverage/cover_reg_top/41.i2c_intr_test.3283631007 | May 23 12:27:10 PM PDT 24 | May 23 12:27:15 PM PDT 24 | 15846427 ps | ||
T1379 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3482191335 | May 23 12:27:02 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 115318276 ps | ||
T197 | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3784285909 | May 23 12:27:03 PM PDT 24 | May 23 12:27:09 PM PDT 24 | 264028674 ps | ||
T1380 | /workspace/coverage/cover_reg_top/43.i2c_intr_test.3028356636 | May 23 12:27:02 PM PDT 24 | May 23 12:27:08 PM PDT 24 | 41773994 ps | ||
T202 | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.180289451 | May 23 12:26:50 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 158277249 ps | ||
T203 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2321348302 | May 23 12:27:45 PM PDT 24 | May 23 12:27:48 PM PDT 24 | 18185053 ps | ||
T1381 | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1711161227 | May 23 12:26:49 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 30789713 ps | ||
T1382 | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3505895896 | May 23 12:26:49 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 78719371 ps | ||
T1383 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.1270745214 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 28512407 ps | ||
T1384 | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3753657096 | May 23 12:27:01 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 408258011 ps | ||
T1385 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3795176213 | May 23 12:26:52 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 16491164 ps | ||
T204 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.834677731 | May 23 12:26:57 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 21581003 ps | ||
T1386 | /workspace/coverage/cover_reg_top/0.i2c_intr_test.3997892494 | May 23 12:26:36 PM PDT 24 | May 23 12:26:38 PM PDT 24 | 48350377 ps | ||
T1387 | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3757705283 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 33282222 ps | ||
T1388 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3594823147 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 74838489 ps | ||
T1389 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2955373013 | May 23 12:26:38 PM PDT 24 | May 23 12:26:42 PM PDT 24 | 80742933 ps | ||
T1390 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.1894632078 | May 23 12:27:04 PM PDT 24 | May 23 12:27:10 PM PDT 24 | 20700834 ps | ||
T1391 | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3529866733 | May 23 12:26:52 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 41563780 ps | ||
T1392 | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1725802867 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 17479890 ps | ||
T1393 | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3915271131 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 1341298862 ps | ||
T1394 | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3481560044 | May 23 12:26:51 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 23209888 ps | ||
T191 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2730814217 | May 23 12:26:57 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 75811427 ps | ||
T1395 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3849978155 | May 23 12:26:53 PM PDT 24 | May 23 12:26:59 PM PDT 24 | 30411813 ps | ||
T1396 | /workspace/coverage/cover_reg_top/25.i2c_intr_test.4201604509 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 16145405 ps | ||
T1397 | /workspace/coverage/cover_reg_top/1.i2c_intr_test.3187101439 | May 23 12:27:43 PM PDT 24 | May 23 12:27:46 PM PDT 24 | 24490862 ps | ||
T1398 | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3871490561 | May 23 12:27:43 PM PDT 24 | May 23 12:27:49 PM PDT 24 | 565187900 ps | ||
T1399 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.2182138441 | May 23 12:27:08 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 17624899 ps | ||
T1400 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1797281674 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 213975883 ps | ||
T190 | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.168212316 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 209786755 ps | ||
T1401 | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1944339229 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 18953700 ps | ||
T1402 | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.566904994 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 116464466 ps | ||
T1403 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1070846100 | May 23 12:27:04 PM PDT 24 | May 23 12:27:09 PM PDT 24 | 19499935 ps | ||
T1404 | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3580140291 | May 23 12:26:56 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 167410199 ps | ||
T1405 | /workspace/coverage/cover_reg_top/19.i2c_intr_test.2093633914 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 86744083 ps | ||
T1406 | /workspace/coverage/cover_reg_top/10.i2c_intr_test.1860785193 | May 23 12:26:51 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 42972857 ps | ||
T1407 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.4244175627 | May 23 12:26:49 PM PDT 24 | May 23 12:26:54 PM PDT 24 | 289328137 ps | ||
T1408 | /workspace/coverage/cover_reg_top/39.i2c_intr_test.1692040165 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 46374147 ps | ||
T1409 | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.294374235 | May 23 12:27:09 PM PDT 24 | May 23 12:27:15 PM PDT 24 | 310858322 ps | ||
T194 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1662803249 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 268466922 ps | ||
T205 | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3115534778 | May 23 12:26:45 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 29302405 ps | ||
T1410 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.27505546 | May 23 12:26:49 PM PDT 24 | May 23 12:26:54 PM PDT 24 | 24034766 ps | ||
T1411 | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2927843387 | May 23 12:27:08 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 41096864 ps | ||
T1412 | /workspace/coverage/cover_reg_top/36.i2c_intr_test.3711183756 | May 23 12:27:01 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 19034121 ps | ||
T206 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3815774471 | May 23 12:26:39 PM PDT 24 | May 23 12:26:43 PM PDT 24 | 95796273 ps | ||
T1413 | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3128248762 | May 23 12:27:02 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 42616711 ps | ||
T1414 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.1684167106 | May 23 12:27:07 PM PDT 24 | May 23 12:27:12 PM PDT 24 | 15164361 ps | ||
T1415 | /workspace/coverage/cover_reg_top/49.i2c_intr_test.2968910185 | May 23 12:27:12 PM PDT 24 | May 23 12:27:16 PM PDT 24 | 27855414 ps | ||
T1416 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4101515468 | May 23 12:26:37 PM PDT 24 | May 23 12:26:41 PM PDT 24 | 698133449 ps | ||
T1417 | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2194637865 | May 23 12:27:11 PM PDT 24 | May 23 12:27:15 PM PDT 24 | 15866625 ps | ||
T1418 | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2346836583 | May 23 12:26:49 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 16785137 ps | ||
T1419 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1810155451 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 30226462 ps | ||
T1420 | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1409218488 | May 23 12:26:48 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 102942670 ps | ||
T1421 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.1383639188 | May 23 12:27:09 PM PDT 24 | May 23 12:27:13 PM PDT 24 | 19409147 ps | ||
T1422 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2354990119 | May 23 12:26:59 PM PDT 24 | May 23 12:27:03 PM PDT 24 | 54309374 ps | ||
T1423 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.591525047 | May 23 12:26:38 PM PDT 24 | May 23 12:26:44 PM PDT 24 | 763398044 ps | ||
T1424 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2081770639 | May 23 12:26:50 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 178880679 ps | ||
T1425 | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3379042459 | May 23 12:26:49 PM PDT 24 | May 23 12:26:54 PM PDT 24 | 43266909 ps | ||
T1426 | /workspace/coverage/cover_reg_top/27.i2c_intr_test.2319354482 | May 23 12:27:02 PM PDT 24 | May 23 12:27:08 PM PDT 24 | 17733343 ps | ||
T1427 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2386223428 | May 23 12:27:03 PM PDT 24 | May 23 12:27:09 PM PDT 24 | 42232842 ps | ||
T1428 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.705446459 | May 23 12:26:52 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 80066158 ps | ||
T1429 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.1853640550 | May 23 12:27:02 PM PDT 24 | May 23 12:27:07 PM PDT 24 | 53590620 ps | ||
T1430 | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.26116865 | May 23 12:26:47 PM PDT 24 | May 23 12:26:53 PM PDT 24 | 61612521 ps | ||
T1431 | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2988871697 | May 23 12:26:48 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 31362114 ps | ||
T1432 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3283487640 | May 23 12:26:48 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 113141468 ps | ||
T1433 | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1407060722 | May 23 12:26:49 PM PDT 24 | May 23 12:26:52 PM PDT 24 | 21902952 ps | ||
T1434 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.3444338644 | May 23 12:27:07 PM PDT 24 | May 23 12:27:12 PM PDT 24 | 17748495 ps | ||
T1435 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2759248541 | May 23 12:26:41 PM PDT 24 | May 23 12:26:47 PM PDT 24 | 273735827 ps | ||
T1436 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3243312254 | May 23 12:26:46 PM PDT 24 | May 23 12:26:51 PM PDT 24 | 231298158 ps | ||
T192 | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.702522992 | May 23 12:26:49 PM PDT 24 | May 23 12:26:55 PM PDT 24 | 163340542 ps | ||
T207 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.443957192 | May 23 12:26:46 PM PDT 24 | May 23 12:26:49 PM PDT 24 | 60984368 ps | ||
T1437 | /workspace/coverage/cover_reg_top/3.i2c_intr_test.2657999649 | May 23 12:26:38 PM PDT 24 | May 23 12:26:42 PM PDT 24 | 16825930 ps | ||
T1438 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.253244115 | May 23 12:26:50 PM PDT 24 | May 23 12:26:56 PM PDT 24 | 55409018 ps | ||
T208 | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3345426309 | May 23 12:27:31 PM PDT 24 | May 23 12:27:33 PM PDT 24 | 30500259 ps | ||
T1439 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1177360630 | May 23 12:26:51 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 94019318 ps | ||
T1440 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2837690838 | May 23 12:26:55 PM PDT 24 | May 23 12:27:01 PM PDT 24 | 117209601 ps | ||
T1441 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3126366940 | May 23 12:27:47 PM PDT 24 | May 23 12:27:50 PM PDT 24 | 191535316 ps | ||
T1442 | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2510313825 | May 23 12:27:02 PM PDT 24 | May 23 12:27:06 PM PDT 24 | 80185930 ps | ||
T209 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1725008394 | May 23 12:26:50 PM PDT 24 | May 23 12:26:57 PM PDT 24 | 276539547 ps | ||
T1443 | /workspace/coverage/cover_reg_top/17.i2c_intr_test.3031052009 | May 23 12:27:01 PM PDT 24 | May 23 12:27:05 PM PDT 24 | 35660254 ps | ||
T1444 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.2779552569 | May 23 12:27:02 PM PDT 24 | May 23 12:27:08 PM PDT 24 | 25052954 ps | ||
T1445 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.514849000 | May 23 12:26:53 PM PDT 24 | May 23 12:26:58 PM PDT 24 | 16649277 ps | ||
T1446 | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.203275533 | May 23 12:27:04 PM PDT 24 | May 23 12:27:10 PM PDT 24 | 354970106 ps | ||
T1447 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2719753634 | May 23 12:27:00 PM PDT 24 | May 23 12:27:04 PM PDT 24 | 33227308 ps |
Test location | /workspace/coverage/default/35.i2c_host_stress_all.2607889196 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 46066969160 ps |
CPU time | 2611.3 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 01:19:47 PM PDT 24 |
Peak memory | 1948956 kb |
Host | smart-cc4065dd-36cf-4883-ab17-1697a8d10dd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607889196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2607889196 |
Directory | /workspace/35.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/0.i2c_target_fifo_reset_tx.971348800 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 10270041519 ps |
CPU time | 16.24 seconds |
Started | May 23 12:32:32 PM PDT 24 |
Finished | May 23 12:32:50 PM PDT 24 |
Peak memory | 259656 kb |
Host | smart-3cb24748-355b-4f48-a5a8-3fe77dd08d5c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971348800 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.i2c_target_fifo_reset_tx.971348800 |
Directory | /workspace/0.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/0.i2c_target_glitch.371339633 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 9513810656 ps |
CPU time | 10.89 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-36ee55e2-ed87-48dc-87d4-237edae428ce |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371339633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.371339633 |
Directory | /workspace/0.i2c_target_glitch/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4082728586 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 128542522 ps |
CPU time | 0.84 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 203416 kb |
Host | smart-6326ad40-8be2-4b83-8a44-70a890ef9029 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082728586 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4082728586 |
Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.i2c_host_stress_all.1913943021 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 14707691940 ps |
CPU time | 715.03 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:46:48 PM PDT 24 |
Peak memory | 3070912 kb |
Host | smart-ba10ea9e-31b4-4fb1-bc68-44671cadd80a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913943021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1913943021 |
Directory | /workspace/24.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/4.i2c_sec_cm.4256377168 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 67756024 ps |
CPU time | 0.96 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:03 PM PDT 24 |
Peak memory | 223040 kb |
Host | smart-40a8a1fe-23ab-48c7-8b71-7b96b76b9620 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256377168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.4256377168 |
Directory | /workspace/4.i2c_sec_cm/latest |
Test location | /workspace/coverage/default/42.i2c_host_stress_all.2084693032 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 86011195851 ps |
CPU time | 1042.32 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:54:22 PM PDT 24 |
Peak memory | 3697184 kb |
Host | smart-9b77f235-2ee8-4c5e-b8e5-b82013884fcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084693032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2084693032 |
Directory | /workspace/42.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/20.i2c_host_override.2223953304 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 100973728 ps |
CPU time | 0.62 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:34 PM PDT 24 |
Peak memory | 204628 kb |
Host | smart-3ceabbe2-ef22-4269-88c6-46a604129dbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223953304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2223953304 |
Directory | /workspace/20.i2c_host_override/latest |
Test location | /workspace/coverage/default/36.i2c_host_may_nack.1230142707 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1473889468 ps |
CPU time | 18.17 seconds |
Started | May 23 12:36:14 PM PDT 24 |
Finished | May 23 12:36:35 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-324113b7-5b71-4966-bd7a-a7b82ae27c20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230142707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1230142707 |
Directory | /workspace/36.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/23.i2c_host_stress_all.2573797421 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 28066681713 ps |
CPU time | 1962.59 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 01:07:32 PM PDT 24 |
Peak memory | 2373420 kb |
Host | smart-2fac9ba0-b631-4814-b2f7-a4985bfa1d94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573797421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2573797421 |
Directory | /workspace/23.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/30.i2c_target_intr_stress_wr.130986331 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 15232722956 ps |
CPU time | 66.47 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:36:40 PM PDT 24 |
Peak memory | 1055864 kb |
Host | smart-e66d1601-a135-4629-9b4d-43a710caa7a3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130986331 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.130986331 |
Directory | /workspace/30.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.4282026443 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 271045363 ps |
CPU time | 2.41 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203532 kb |
Host | smart-9f1213e3-4034-45b2-9cbf-fcfebdaf494a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282026443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.4282026443 |
Directory | /workspace/9.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1906325794 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 78438377 ps |
CPU time | 0.74 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:50 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-c08b5c35-88c9-4bb0-bef8-85b454fe7384 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906325794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1906325794 |
Directory | /workspace/15.i2c_csr_rw/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3316897131 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 205255074 ps |
CPU time | 1.14 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:33:13 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-0f86d5ec-03c6-4d11-9f23-deaee4ec5068 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316897131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm t.3316897131 |
Directory | /workspace/8.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/29.i2c_host_stress_all.3274601717 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 69099827677 ps |
CPU time | 556.97 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:44:49 PM PDT 24 |
Peak memory | 2031540 kb |
Host | smart-a82bcbd0-8334-4cf3-a9cf-0bb4778626d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274601717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3274601717 |
Directory | /workspace/29.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/0.i2c_target_timeout.3183177393 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 5441962225 ps |
CPU time | 7.78 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:43 PM PDT 24 |
Peak memory | 221204 kb |
Host | smart-9aa9fc74-fc47-435b-9c8b-9d664fee22d5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183177393 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.i2c_target_timeout.3183177393 |
Directory | /workspace/0.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/26.i2c_host_stress_all.1244127266 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 24767598834 ps |
CPU time | 1610 seconds |
Started | May 23 12:35:01 PM PDT 24 |
Finished | May 23 01:01:53 PM PDT 24 |
Peak memory | 1606636 kb |
Host | smart-416430b7-c55e-448d-9591-f98074304fed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244127266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.1244127266 |
Directory | /workspace/26.i2c_host_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3542039354 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 91769304 ps |
CPU time | 2.39 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:51 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-3cbb352d-6c02-4c92-a21f-62bc8634f9c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542039354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3542039354 |
Directory | /workspace/5.i2c_tl_errors/latest |
Test location | /workspace/coverage/default/24.i2c_target_bad_addr.3446073724 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 4488030981 ps |
CPU time | 5.59 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:34:58 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-7c6776e8-0f3f-4758-8b74-e6af2edd8e6e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446073724 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3446073724 |
Directory | /workspace/24.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/0.i2c_alert_test.1292979982 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 52318250 ps |
CPU time | 0.64 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:39 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-ce7072f7-97a8-47c5-b565-9ea9ffe507ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292979982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1292979982 |
Directory | /workspace/0.i2c_alert_test/latest |
Test location | /workspace/coverage/default/14.i2c_target_fifo_reset_acq.1523572069 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 10111375149 ps |
CPU time | 46.16 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:46 PM PDT 24 |
Peak memory | 419612 kb |
Host | smart-4949f748-8356-4874-b2a0-fe5ea7ccf991 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523572069 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.1523572069 |
Directory | /workspace/14.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/18.i2c_host_stress_all.1430553797 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 10684230058 ps |
CPU time | 361.99 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:40:17 PM PDT 24 |
Peak memory | 1349716 kb |
Host | smart-e4cb5113-ba62-4006-b4df-00e5612bb49d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430553797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1430553797 |
Directory | /workspace/18.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/11.i2c_host_mode_toggle.3876368776 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 9877938174 ps |
CPU time | 31.13 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:34:10 PM PDT 24 |
Peak memory | 412032 kb |
Host | smart-14760536-4573-4c6c-8fe1-9b10c3f822e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876368776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3876368776 |
Directory | /workspace/11.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_reset_rx.806682793 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 149452974 ps |
CPU time | 8.69 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 230484 kb |
Host | smart-7d41e92a-ea8c-4493-83b3-1da6a8492a8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806682793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx. 806682793 |
Directory | /workspace/16.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_full.1499507650 |
Short name | T1296 |
Test name | |
Test status | |
Simulation time | 6565075529 ps |
CPU time | 194.7 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:37:21 PM PDT 24 |
Peak memory | 778492 kb |
Host | smart-12113a57-c70d-4ed9-b73f-9190a38089a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499507650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1499507650 |
Directory | /workspace/15.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/14.i2c_host_stress_all.549095577 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 25676401220 ps |
CPU time | 258.59 seconds |
Started | May 23 12:33:50 PM PDT 24 |
Finished | May 23 12:38:11 PM PDT 24 |
Peak memory | 1755548 kb |
Host | smart-d94f1d6e-ded3-45e9-81d7-6d1307a92d92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549095577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.549095577 |
Directory | /workspace/14.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2629132555 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 10048371049 ps |
CPU time | 90.38 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:35:09 PM PDT 24 |
Peak memory | 482592 kb |
Host | smart-29caab74-54a7-41f1-a6d2-14d39376431f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629132555 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.i2c_target_fifo_reset_tx.2629132555 |
Directory | /workspace/10.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/19.i2c_target_stretch.2641687424 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 34737839036 ps |
CPU time | 2021.95 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 01:08:17 PM PDT 24 |
Peak memory | 7915316 kb |
Host | smart-7215bbee-2ff2-4110-a1d9-f43562d657a6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641687424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ target_stretch.2641687424 |
Directory | /workspace/19.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/27.i2c_host_stress_all.2951881473 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 58563149177 ps |
CPU time | 1504.17 seconds |
Started | May 23 12:35:15 PM PDT 24 |
Finished | May 23 01:00:21 PM PDT 24 |
Peak memory | 2299364 kb |
Host | smart-57224382-d56c-479e-a003-c5227a18f530 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951881473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2951881473 |
Directory | /workspace/27.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_watermark.711705795 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 16723011244 ps |
CPU time | 247.98 seconds |
Started | May 23 12:37:07 PM PDT 24 |
Finished | May 23 12:41:17 PM PDT 24 |
Peak memory | 1054844 kb |
Host | smart-7d11e5ec-7e7b-462a-bee8-c07fccd44b46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711705795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.711705795 |
Directory | /workspace/45.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/45.i2c_host_stress_all.284375755 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 156241730600 ps |
CPU time | 694.9 seconds |
Started | May 23 12:37:04 PM PDT 24 |
Finished | May 23 12:48:41 PM PDT 24 |
Peak memory | 1876968 kb |
Host | smart-dbda7396-621d-4940-a6c2-e5c49a6013eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284375755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.284375755 |
Directory | /workspace/45.i2c_host_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.702522992 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 163340542 ps |
CPU time | 2.26 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-f5bb61af-626c-48b0-ab61-f185d102220c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702522992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.702522992 |
Directory | /workspace/13.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.834677731 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 21581003 ps |
CPU time | 0.78 seconds |
Started | May 23 12:26:57 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-5dc96381-766c-43fe-bcbc-bac87216cfea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834677731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.834677731 |
Directory | /workspace/4.i2c_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.i2c_host_mode_toggle.4081171851 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 823731361 ps |
CPU time | 16.21 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 270012 kb |
Host | smart-b948c4d5-a3df-4456-a29c-abc5be64c8b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081171851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.4081171851 |
Directory | /workspace/0.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/0.i2c_host_stretch_timeout.3448617429 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 3083527916 ps |
CPU time | 14.13 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 221408 kb |
Host | smart-d05098fa-a484-4fca-88be-c734b0ccf51f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448617429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3448617429 |
Directory | /workspace/0.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/0.i2c_target_hrst.3669854731 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 2359459847 ps |
CPU time | 3.02 seconds |
Started | May 23 12:32:32 PM PDT 24 |
Finished | May 23 12:32:36 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-ac801d6b-2872-45fe-b90d-b3006f712dc3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669854731 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.3669854731 |
Directory | /workspace/0.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/1.i2c_target_hrst.64109968 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 371506674 ps |
CPU time | 2.38 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:49 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-9ed0a5fa-3cd3-43e2-9b9e-3ce5c7bda855 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64109968 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.i2c_target_hrst.64109968 |
Directory | /workspace/1.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_watermark.2698154592 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 4201922676 ps |
CPU time | 337.89 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:39:38 PM PDT 24 |
Peak memory | 1216676 kb |
Host | smart-de20d43f-4178-4eb1-9dc9-cc80537e1e5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698154592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2698154592 |
Directory | /workspace/15.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/21.i2c_target_bad_addr.2456158303 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 722503974 ps |
CPU time | 3.88 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:34:50 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-f55b3972-b4c8-4d80-bd19-810b30937d72 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456158303 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2456158303 |
Directory | /workspace/21.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/33.i2c_target_stress_rd.604820331 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 5806133342 ps |
CPU time | 61.62 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:36:57 PM PDT 24 |
Peak memory | 208156 kb |
Host | smart-305d5e23-b8cc-4da9-80b1-4840e875bde7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604820331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c _target_stress_rd.604820331 |
Directory | /workspace/33.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2295141198 |
Short name | T1364 |
Test name | |
Test status | |
Simulation time | 127376476 ps |
CPU time | 0.8 seconds |
Started | May 23 12:26:41 PM PDT 24 |
Finished | May 23 12:26:45 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-4ad11c3e-8ae2-4429-9cff-51c4ede14c11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295141198 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2295141198 |
Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.743618674 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 77166448 ps |
CPU time | 1.12 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:08 PM PDT 24 |
Peak memory | 203472 kb |
Host | smart-f32c61b7-2e4d-490d-bdaa-83cdad3e9552 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743618674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou tstanding.743618674 |
Directory | /workspace/17.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3457685030 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 750150076 ps |
CPU time | 2.34 seconds |
Started | May 23 12:26:43 PM PDT 24 |
Finished | May 23 12:26:48 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-09ca832a-050a-44d7-8dc9-e87fec320ddd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457685030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3457685030 |
Directory | /workspace/2.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1463913549 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 10270965885 ps |
CPU time | 10.04 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:34:01 PM PDT 24 |
Peak memory | 235848 kb |
Host | smart-9d00e3fb-eea1-4fc0-bf58-a40717de5d54 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463913549 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.1463913549 |
Directory | /workspace/12.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/30.i2c_host_error_intr.1037829071 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 519180489 ps |
CPU time | 3.41 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 221232 kb |
Host | smart-9c98e29a-4b7e-48b6-8af3-b1cb97548fa3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037829071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1037829071 |
Directory | /workspace/30.i2c_host_error_intr/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1725008394 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 276539547 ps |
CPU time | 2.17 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203516 kb |
Host | smart-daec5a50-6fc6-4e4b-8f12-38b86ed5df8c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725008394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1725008394 |
Directory | /workspace/0.i2c_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2759248541 |
Short name | T1435 |
Test name | |
Test status | |
Simulation time | 273735827 ps |
CPU time | 2.96 seconds |
Started | May 23 12:26:41 PM PDT 24 |
Finished | May 23 12:26:47 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-8e60da56-88be-4f61-8d25-e2e88671feaa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759248541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2759248541 |
Directory | /workspace/0.i2c_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.553445136 |
Short name | T1350 |
Test name | |
Test status | |
Simulation time | 61424956 ps |
CPU time | 0.73 seconds |
Started | May 23 12:27:53 PM PDT 24 |
Finished | May 23 12:27:57 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-67bb227a-a28f-4f2c-9d40-312cc9f3f130 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553445136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.553445136 |
Directory | /workspace/0.i2c_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1014767253 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 24583810 ps |
CPU time | 0.79 seconds |
Started | May 23 12:26:38 PM PDT 24 |
Finished | May 23 12:26:42 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-08603e22-c18b-4397-85f8-a5d92db6ad53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014767253 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1014767253 |
Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3115534778 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 29302405 ps |
CPU time | 0.85 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 202264 kb |
Host | smart-277d78d4-f43e-41cc-ba4b-c283fe178641 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115534778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3115534778 |
Directory | /workspace/0.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.3997892494 |
Short name | T1386 |
Test name | |
Test status | |
Simulation time | 48350377 ps |
CPU time | 0.68 seconds |
Started | May 23 12:26:36 PM PDT 24 |
Finished | May 23 12:26:38 PM PDT 24 |
Peak memory | 203396 kb |
Host | smart-53653653-2b0c-40a4-ab20-2db4d26b6a93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997892494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3997892494 |
Directory | /workspace/0.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2955373013 |
Short name | T1389 |
Test name | |
Test status | |
Simulation time | 80742933 ps |
CPU time | 0.86 seconds |
Started | May 23 12:26:38 PM PDT 24 |
Finished | May 23 12:26:42 PM PDT 24 |
Peak memory | 203576 kb |
Host | smart-f4dd5777-f311-4a96-9b32-7ba888f2dca3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955373013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.2955373013 |
Directory | /workspace/0.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3126366940 |
Short name | T1441 |
Test name | |
Test status | |
Simulation time | 191535316 ps |
CPU time | 1.23 seconds |
Started | May 23 12:27:47 PM PDT 24 |
Finished | May 23 12:27:50 PM PDT 24 |
Peak memory | 203556 kb |
Host | smart-9e03ca6b-9e40-4f1b-ad45-7a08556ef492 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126366940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3126366940 |
Directory | /workspace/0.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.591525047 |
Short name | T1423 |
Test name | |
Test status | |
Simulation time | 763398044 ps |
CPU time | 2.33 seconds |
Started | May 23 12:26:38 PM PDT 24 |
Finished | May 23 12:26:44 PM PDT 24 |
Peak memory | 203556 kb |
Host | smart-82f8d818-4d59-4c06-bdf2-84067f3c7be4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591525047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.591525047 |
Directory | /workspace/0.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4101515468 |
Short name | T1416 |
Test name | |
Test status | |
Simulation time | 698133449 ps |
CPU time | 2.02 seconds |
Started | May 23 12:26:37 PM PDT 24 |
Finished | May 23 12:26:41 PM PDT 24 |
Peak memory | 203444 kb |
Host | smart-af33182a-4d46-4cc7-85d1-42fb66cd46cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101515468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.4101515468 |
Directory | /workspace/1.i2c_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3871490561 |
Short name | T1398 |
Test name | |
Test status | |
Simulation time | 565187900 ps |
CPU time | 3.17 seconds |
Started | May 23 12:27:43 PM PDT 24 |
Finished | May 23 12:27:49 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-5e7a20b2-689d-419f-a235-8235266f3a96 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871490561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3871490561 |
Directory | /workspace/1.i2c_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1954803190 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 22274101 ps |
CPU time | 0.75 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 201468 kb |
Host | smart-f1d9852a-1e83-4602-8816-18841c7ce619 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954803190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1954803190 |
Directory | /workspace/1.i2c_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3345426309 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 30500259 ps |
CPU time | 0.77 seconds |
Started | May 23 12:27:31 PM PDT 24 |
Finished | May 23 12:27:33 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-03b01613-e458-4ce5-b216-7af6ea718fd5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345426309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3345426309 |
Directory | /workspace/1.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.3187101439 |
Short name | T1397 |
Test name | |
Test status | |
Simulation time | 24490862 ps |
CPU time | 0.63 seconds |
Started | May 23 12:27:43 PM PDT 24 |
Finished | May 23 12:27:46 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-e3849c96-ee43-46ad-b996-2fd4e2f197ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187101439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3187101439 |
Directory | /workspace/1.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3497349760 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 36832854 ps |
CPU time | 0.85 seconds |
Started | May 23 12:26:38 PM PDT 24 |
Finished | May 23 12:26:43 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-be57f59f-c155-4abe-8d8f-844cf6d4eb4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497349760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.3497349760 |
Directory | /workspace/1.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.566904994 |
Short name | T1402 |
Test name | |
Test status | |
Simulation time | 116464466 ps |
CPU time | 1.39 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-55bd6243-b75a-4c17-ae0e-b5bb0565b5cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566904994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.566904994 |
Directory | /workspace/1.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2814300113 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 514200361 ps |
CPU time | 2.42 seconds |
Started | May 23 12:26:37 PM PDT 24 |
Finished | May 23 12:26:42 PM PDT 24 |
Peak memory | 203544 kb |
Host | smart-a8a02331-728a-4903-baf1-db6b2f5dbe8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814300113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2814300113 |
Directory | /workspace/1.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3606249366 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 19078698 ps |
CPU time | 0.85 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203220 kb |
Host | smart-5e238b2a-0efd-4010-91d8-0d7ce409fb89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606249366 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3606249366 |
Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3795176213 |
Short name | T1385 |
Test name | |
Test status | |
Simulation time | 16491164 ps |
CPU time | 0.69 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-da03b3bc-41d6-453c-9f09-7daeaa06568b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795176213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3795176213 |
Directory | /workspace/10.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.1860785193 |
Short name | T1406 |
Test name | |
Test status | |
Simulation time | 42972857 ps |
CPU time | 0.67 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-1bead9f7-6735-460a-90f5-71249b91023d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860785193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1860785193 |
Directory | /workspace/10.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3177915637 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 61675281 ps |
CPU time | 0.85 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-5f7aa1e3-eb32-4421-a41c-20185bc4aaf2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177915637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.3177915637 |
Directory | /workspace/10.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.236574057 |
Short name | T1358 |
Test name | |
Test status | |
Simulation time | 93690110 ps |
CPU time | 2.07 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-ce4e6baa-e9b5-47a3-8d23-cc88d169ee80 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236574057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.236574057 |
Directory | /workspace/10.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.168212316 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 209786755 ps |
CPU time | 1.47 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-81b84fcf-20ba-466f-a289-308f3eb30bdb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168212316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.168212316 |
Directory | /workspace/10.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.203275533 |
Short name | T1446 |
Test name | |
Test status | |
Simulation time | 354970106 ps |
CPU time | 0.95 seconds |
Started | May 23 12:27:04 PM PDT 24 |
Finished | May 23 12:27:10 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-b5cd7fbf-ffb9-4ca2-8717-e9145631ffa9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203275533 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.203275533 |
Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1407060722 |
Short name | T1433 |
Test name | |
Test status | |
Simulation time | 21902952 ps |
CPU time | 0.71 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-d2e02082-ec07-46f7-acd9-b4861e957f64 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407060722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1407060722 |
Directory | /workspace/11.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.3312098785 |
Short name | T1360 |
Test name | |
Test status | |
Simulation time | 21024001 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:04 PM PDT 24 |
Finished | May 23 12:27:10 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-81015e90-8494-4323-9dae-52f8e686d7e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312098785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3312098785 |
Directory | /workspace/11.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.4106157007 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 69652254 ps |
CPU time | 0.86 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203484 kb |
Host | smart-66876c05-dcf4-41e0-9f5e-59c2ede30cd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106157007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.4106157007 |
Directory | /workspace/11.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1995281172 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 153552539 ps |
CPU time | 2.59 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:27:00 PM PDT 24 |
Peak memory | 203472 kb |
Host | smart-826a19cb-27fb-4730-871e-4a28c21491b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995281172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1995281172 |
Directory | /workspace/11.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2730814217 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 75811427 ps |
CPU time | 1.5 seconds |
Started | May 23 12:26:57 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-cc15b719-6cb9-44a3-8c29-35ca8c078b37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730814217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2730814217 |
Directory | /workspace/11.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3189515520 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 56148893 ps |
CPU time | 0.69 seconds |
Started | May 23 12:26:53 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-f113387b-cc09-4a33-ad04-82c105093534 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189515520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3189515520 |
Directory | /workspace/12.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2346836583 |
Short name | T1418 |
Test name | |
Test status | |
Simulation time | 16785137 ps |
CPU time | 0.61 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-25ec2e1a-637e-4b57-aad5-6fd37b525c46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346836583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2346836583 |
Directory | /workspace/12.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.726335192 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 65876880 ps |
CPU time | 1.6 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203576 kb |
Host | smart-33b93466-b9b3-4876-b774-4b77b5acafc9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726335192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.726335192 |
Directory | /workspace/12.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1662803249 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 268466922 ps |
CPU time | 1.44 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-c241d88e-b42d-4c2b-867f-2c0049cc94f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662803249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1662803249 |
Directory | /workspace/12.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2527191956 |
Short name | T1366 |
Test name | |
Test status | |
Simulation time | 63088102 ps |
CPU time | 0.81 seconds |
Started | May 23 12:26:57 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203600 kb |
Host | smart-9e87906a-676e-4c9a-a88d-5bded362ffca |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527191956 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2527191956 |
Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1741290347 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 16799288 ps |
CPU time | 0.71 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203416 kb |
Host | smart-52b9d08f-f273-4e5c-9450-ce819a3983c8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741290347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1741290347 |
Directory | /workspace/13.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.174039779 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 50811835 ps |
CPU time | 0.66 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-bca56500-5119-40c6-ad4f-3a750fae5899 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174039779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.174039779 |
Directory | /workspace/13.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3283487640 |
Short name | T1432 |
Test name | |
Test status | |
Simulation time | 113141468 ps |
CPU time | 0.96 seconds |
Started | May 23 12:26:48 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-80daaea4-22c8-4d0e-8172-5ce1ca2cb496 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283487640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3283487640 |
Directory | /workspace/13.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1810155451 |
Short name | T1419 |
Test name | |
Test status | |
Simulation time | 30226462 ps |
CPU time | 1.31 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203576 kb |
Host | smart-7740a5bf-f877-4339-8c50-b67d0677cc09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810155451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1810155451 |
Directory | /workspace/13.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3505895896 |
Short name | T1382 |
Test name | |
Test status | |
Simulation time | 78719371 ps |
CPU time | 0.77 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-2d3e716c-fb1e-4d56-8e6e-8bd6f7d2a720 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505895896 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3505895896 |
Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2510313825 |
Short name | T1442 |
Test name | |
Test status | |
Simulation time | 80185930 ps |
CPU time | 0.79 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-7c6203d6-6069-4de3-bf0a-6cea08692a47 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510313825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2510313825 |
Directory | /workspace/14.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.1083694350 |
Short name | T1376 |
Test name | |
Test status | |
Simulation time | 46145599 ps |
CPU time | 0.66 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:54 PM PDT 24 |
Peak memory | 203508 kb |
Host | smart-dddc8099-bb15-40b3-afeb-4df1f66e1d76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083694350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1083694350 |
Directory | /workspace/14.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3753657096 |
Short name | T1384 |
Test name | |
Test status | |
Simulation time | 408258011 ps |
CPU time | 1.83 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-37c235bf-fc28-4d75-8cdb-2085cb7c9186 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753657096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3753657096 |
Directory | /workspace/14.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.889374716 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 155433237 ps |
CPU time | 1.56 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203744 kb |
Host | smart-638d1c84-5e15-4335-8f68-b997ef8d1800 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889374716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.889374716 |
Directory | /workspace/14.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3379042459 |
Short name | T1425 |
Test name | |
Test status | |
Simulation time | 43266909 ps |
CPU time | 0.78 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:54 PM PDT 24 |
Peak memory | 203448 kb |
Host | smart-91720013-1038-48a6-ac56-d615b4e8ba63 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379042459 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3379042459 |
Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.788776713 |
Short name | T1354 |
Test name | |
Test status | |
Simulation time | 20163079 ps |
CPU time | 0.7 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 203356 kb |
Host | smart-2c32cdbc-1486-4e99-bb78-cc7f026b32cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788776713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.788776713 |
Directory | /workspace/15.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.705446459 |
Short name | T1428 |
Test name | |
Test status | |
Simulation time | 80066158 ps |
CPU time | 1.1 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-a8483582-2377-4ada-9a03-94192fe8bba3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705446459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou tstanding.705446459 |
Directory | /workspace/15.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.4244175627 |
Short name | T1407 |
Test name | |
Test status | |
Simulation time | 289328137 ps |
CPU time | 1.75 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:54 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-82d384ec-d089-421c-b2bc-9ad730ddf36d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244175627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4244175627 |
Directory | /workspace/15.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.253244115 |
Short name | T1438 |
Test name | |
Test status | |
Simulation time | 55409018 ps |
CPU time | 1.64 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 203740 kb |
Host | smart-43ed2aa8-8677-4fa7-af2a-ebac5a13d233 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253244115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.253244115 |
Directory | /workspace/15.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3482191335 |
Short name | T1379 |
Test name | |
Test status | |
Simulation time | 115318276 ps |
CPU time | 0.98 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203488 kb |
Host | smart-651d837c-8a39-45f9-ac3c-3128db579220 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482191335 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3482191335 |
Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.966494374 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 97318916 ps |
CPU time | 0.78 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-55c942c8-e203-4387-b5ff-6b3e277c0d87 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966494374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.966494374 |
Directory | /workspace/16.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3128248762 |
Short name | T1413 |
Test name | |
Test status | |
Simulation time | 42616711 ps |
CPU time | 0.65 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203356 kb |
Host | smart-09dbac7c-e216-4417-87bd-467f62022849 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128248762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3128248762 |
Directory | /workspace/16.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2171552843 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 73611921 ps |
CPU time | 1.21 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-a60e0512-448d-4f62-bbe3-96afb610c84d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171552843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.2171552843 |
Directory | /workspace/16.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4271432999 |
Short name | T1357 |
Test name | |
Test status | |
Simulation time | 81418292 ps |
CPU time | 2.16 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203744 kb |
Host | smart-59648d6a-5d06-46e0-b5c4-1efa00f880ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271432999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.4271432999 |
Directory | /workspace/16.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3915271131 |
Short name | T1393 |
Test name | |
Test status | |
Simulation time | 1341298862 ps |
CPU time | 1.53 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-6955cd94-ddea-4b03-bc4e-9b6adfaebb57 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915271131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3915271131 |
Directory | /workspace/16.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.280837295 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 172501408 ps |
CPU time | 0.93 seconds |
Started | May 23 12:27:05 PM PDT 24 |
Finished | May 23 12:27:11 PM PDT 24 |
Peak memory | 203572 kb |
Host | smart-58f86332-2202-4ed7-9833-8142d9728a5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280837295 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.280837295 |
Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1944339229 |
Short name | T1401 |
Test name | |
Test status | |
Simulation time | 18953700 ps |
CPU time | 0.73 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-693147e1-6a0e-40a5-8798-ff76db37e4d6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944339229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1944339229 |
Directory | /workspace/17.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.3031052009 |
Short name | T1443 |
Test name | |
Test status | |
Simulation time | 35660254 ps |
CPU time | 0.61 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-d0a1678e-0421-452e-ab5a-5683cee2e216 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031052009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3031052009 |
Directory | /workspace/17.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1493266880 |
Short name | T1368 |
Test name | |
Test status | |
Simulation time | 917281548 ps |
CPU time | 1.45 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-0033b2fa-5f23-4f8d-9984-959ef480376d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493266880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1493266880 |
Directory | /workspace/17.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3784285909 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 264028674 ps |
CPU time | 1.56 seconds |
Started | May 23 12:27:03 PM PDT 24 |
Finished | May 23 12:27:09 PM PDT 24 |
Peak memory | 203524 kb |
Host | smart-3734b837-0585-413a-adfd-52fadb634866 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784285909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3784285909 |
Directory | /workspace/17.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1835016902 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 23794390 ps |
CPU time | 1.08 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203636 kb |
Host | smart-b764c9e8-a78f-4781-86f1-64f8471712b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835016902 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1835016902 |
Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2927843387 |
Short name | T1411 |
Test name | |
Test status | |
Simulation time | 41096864 ps |
CPU time | 0.79 seconds |
Started | May 23 12:27:08 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-f127c1d9-319f-4bd8-b012-1adafb79c12d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927843387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2927843387 |
Directory | /workspace/18.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.425719206 |
Short name | T1371 |
Test name | |
Test status | |
Simulation time | 18140112 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-4edb66cf-ecff-41a1-ae82-dee1ea2b9208 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425719206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.425719206 |
Directory | /workspace/18.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2453324173 |
Short name | T1367 |
Test name | |
Test status | |
Simulation time | 123008614 ps |
CPU time | 1.18 seconds |
Started | May 23 12:27:03 PM PDT 24 |
Finished | May 23 12:27:09 PM PDT 24 |
Peak memory | 203628 kb |
Host | smart-5d814f75-b01d-43fd-a184-a7cf5d3f5d5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453324173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.2453324173 |
Directory | /workspace/18.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.147845332 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 805259669 ps |
CPU time | 2.23 seconds |
Started | May 23 12:27:04 PM PDT 24 |
Finished | May 23 12:27:11 PM PDT 24 |
Peak memory | 203576 kb |
Host | smart-9130bfc2-ebb2-4a76-aced-f574566b389d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147845332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.147845332 |
Directory | /workspace/18.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.294374235 |
Short name | T1409 |
Test name | |
Test status | |
Simulation time | 310858322 ps |
CPU time | 1.61 seconds |
Started | May 23 12:27:09 PM PDT 24 |
Finished | May 23 12:27:15 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-ef601796-e355-46dc-983a-bbe76f048f55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294374235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.294374235 |
Directory | /workspace/18.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1011640148 |
Short name | T1363 |
Test name | |
Test status | |
Simulation time | 20112448 ps |
CPU time | 0.92 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-db7a0012-88d9-4511-b4e1-6fef498efa6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011640148 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1011640148 |
Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.262769784 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 22107643 ps |
CPU time | 0.69 seconds |
Started | May 23 12:26:58 PM PDT 24 |
Finished | May 23 12:27:02 PM PDT 24 |
Peak memory | 203284 kb |
Host | smart-7701107b-b6ef-446e-b958-5733c8de90ce |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262769784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.262769784 |
Directory | /workspace/19.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.2093633914 |
Short name | T1405 |
Test name | |
Test status | |
Simulation time | 86744083 ps |
CPU time | 0.69 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203368 kb |
Host | smart-e6bd2dec-f338-48aa-bdc9-ad3431682fab |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093633914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2093633914 |
Directory | /workspace/19.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2719753634 |
Short name | T1447 |
Test name | |
Test status | |
Simulation time | 33227308 ps |
CPU time | 0.9 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-22f1ed75-1a3e-4550-aeda-0503e6fe0946 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719753634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.2719753634 |
Directory | /workspace/19.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2384098457 |
Short name | T1361 |
Test name | |
Test status | |
Simulation time | 715137178 ps |
CPU time | 2.91 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203584 kb |
Host | smart-d83d6fb4-0397-41e6-b459-be9bd274212a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384098457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2384098457 |
Directory | /workspace/19.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2235436453 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 282883606 ps |
CPU time | 1.57 seconds |
Started | May 23 12:27:09 PM PDT 24 |
Finished | May 23 12:27:15 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-b72719a3-3a70-476b-9541-7d128896ad56 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235436453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2235436453 |
Directory | /workspace/19.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3815774471 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 95796273 ps |
CPU time | 1.25 seconds |
Started | May 23 12:26:39 PM PDT 24 |
Finished | May 23 12:26:43 PM PDT 24 |
Peak memory | 203520 kb |
Host | smart-d09a4373-93ff-4d14-aa67-e757fa8ba313 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815774471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3815774471 |
Directory | /workspace/2.i2c_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4013861742 |
Short name | T1353 |
Test name | |
Test status | |
Simulation time | 1747214850 ps |
CPU time | 5.72 seconds |
Started | May 23 12:26:41 PM PDT 24 |
Finished | May 23 12:26:50 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-c2852fd2-925e-441f-a898-9796370131cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013861742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.4013861742 |
Directory | /workspace/2.i2c_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.443957192 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 60984368 ps |
CPU time | 0.72 seconds |
Started | May 23 12:26:46 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 203200 kb |
Host | smart-1d6405d6-bab7-4c04-8bb9-e32bb8b1bae7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443957192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.443957192 |
Directory | /workspace/2.i2c_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2321348302 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 18185053 ps |
CPU time | 0.75 seconds |
Started | May 23 12:27:45 PM PDT 24 |
Finished | May 23 12:27:48 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-a3aa77b0-9cfb-4da6-9808-f9d1ae4cb7db |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321348302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2321348302 |
Directory | /workspace/2.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.2312880426 |
Short name | T1349 |
Test name | |
Test status | |
Simulation time | 76797171 ps |
CPU time | 0.65 seconds |
Started | May 23 12:26:41 PM PDT 24 |
Finished | May 23 12:26:45 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-eb5738a8-3d3b-4c2a-9d1f-6799a4afe28f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312880426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2312880426 |
Directory | /workspace/2.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1177360630 |
Short name | T1439 |
Test name | |
Test status | |
Simulation time | 94019318 ps |
CPU time | 1.12 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203564 kb |
Host | smart-318f673e-5202-403b-bf26-ac022d72a9ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177360630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.1177360630 |
Directory | /workspace/2.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3243312254 |
Short name | T1436 |
Test name | |
Test status | |
Simulation time | 231298158 ps |
CPU time | 2.26 seconds |
Started | May 23 12:26:46 PM PDT 24 |
Finished | May 23 12:26:51 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-61913bfd-2c6c-49b2-a72c-0654e8a3c48d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243312254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3243312254 |
Directory | /workspace/2.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.2386223428 |
Short name | T1427 |
Test name | |
Test status | |
Simulation time | 42232842 ps |
CPU time | 0.69 seconds |
Started | May 23 12:27:03 PM PDT 24 |
Finished | May 23 12:27:09 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-8b2cbd99-5e49-4d99-baaf-d5840cdb5121 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386223428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2386223428 |
Directory | /workspace/20.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.4094894440 |
Short name | T1351 |
Test name | |
Test status | |
Simulation time | 44856698 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:06 PM PDT 24 |
Finished | May 23 12:27:11 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-8ee7f407-e9c8-4a9b-8749-7a6ed7fb96f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094894440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4094894440 |
Directory | /workspace/21.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.3857023385 |
Short name | T1375 |
Test name | |
Test status | |
Simulation time | 45025401 ps |
CPU time | 0.69 seconds |
Started | May 23 12:27:10 PM PDT 24 |
Finished | May 23 12:27:15 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-43e21fdd-caae-4f9f-9714-87115ae0f4e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857023385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3857023385 |
Directory | /workspace/22.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.542449974 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 20901890 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:08 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-3f066a3b-8e18-4ebe-8981-7ca0670af8bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542449974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.542449974 |
Directory | /workspace/23.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.2779552569 |
Short name | T1444 |
Test name | |
Test status | |
Simulation time | 25052954 ps |
CPU time | 0.66 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:08 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-bbc9f9d1-fc71-4108-b2a6-aa75aa56c271 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779552569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2779552569 |
Directory | /workspace/24.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.4201604509 |
Short name | T1396 |
Test name | |
Test status | |
Simulation time | 16145405 ps |
CPU time | 0.68 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-9dcf3501-d816-43c8-b8d2-3b15b4a6f51b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201604509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.4201604509 |
Directory | /workspace/25.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.3858584376 |
Short name | T1365 |
Test name | |
Test status | |
Simulation time | 28312905 ps |
CPU time | 0.64 seconds |
Started | May 23 12:27:09 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-c0f647af-c507-4358-b2da-ef0674b081ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858584376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3858584376 |
Directory | /workspace/26.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.2319354482 |
Short name | T1426 |
Test name | |
Test status | |
Simulation time | 17733343 ps |
CPU time | 0.68 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:08 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-a9b9cdb3-a249-4aa7-882f-bfdd0bd32247 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319354482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2319354482 |
Directory | /workspace/27.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.1894632078 |
Short name | T1390 |
Test name | |
Test status | |
Simulation time | 20700834 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:04 PM PDT 24 |
Finished | May 23 12:27:10 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-97b3993e-3c7f-4ad5-9de0-3c6b1fe01611 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894632078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1894632078 |
Directory | /workspace/28.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.1070846100 |
Short name | T1403 |
Test name | |
Test status | |
Simulation time | 19499935 ps |
CPU time | 0.64 seconds |
Started | May 23 12:27:04 PM PDT 24 |
Finished | May 23 12:27:09 PM PDT 24 |
Peak memory | 203428 kb |
Host | smart-6873e2ad-2a8c-4180-b3f9-5b807dafd95b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070846100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1070846100 |
Directory | /workspace/29.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3338243396 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 541162025 ps |
CPU time | 2.32 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203520 kb |
Host | smart-0ea539f7-3bae-4213-8e67-78b6a46d4373 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338243396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3338243396 |
Directory | /workspace/3.i2c_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1797281674 |
Short name | T1400 |
Test name | |
Test status | |
Simulation time | 213975883 ps |
CPU time | 0.77 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 201772 kb |
Host | smart-502d46f0-871f-4536-81fe-9917d35e4edc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797281674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1797281674 |
Directory | /workspace/3.i2c_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3206664053 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 37704034 ps |
CPU time | 1.04 seconds |
Started | May 23 12:26:56 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-4106f3d1-b528-46a8-9321-ff5c255b2824 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206664053 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3206664053 |
Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3529866733 |
Short name | T1391 |
Test name | |
Test status | |
Simulation time | 41563780 ps |
CPU time | 0.79 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203368 kb |
Host | smart-2ac9f03d-644d-4b8c-b712-f1f66bacd1db |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529866733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3529866733 |
Directory | /workspace/3.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.2657999649 |
Short name | T1437 |
Test name | |
Test status | |
Simulation time | 16825930 ps |
CPU time | 0.65 seconds |
Started | May 23 12:26:38 PM PDT 24 |
Finished | May 23 12:26:42 PM PDT 24 |
Peak memory | 203356 kb |
Host | smart-dbc997f2-f40e-41d0-b488-63efaff00ac3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657999649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2657999649 |
Directory | /workspace/3.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.256324805 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 47636666 ps |
CPU time | 1.09 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-c87bc057-b1dd-406d-8ca9-b7e260663dd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256324805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out standing.256324805 |
Directory | /workspace/3.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.26116865 |
Short name | T1430 |
Test name | |
Test status | |
Simulation time | 61612521 ps |
CPU time | 3.11 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203556 kb |
Host | smart-d51d3377-59b0-4786-bddd-dfad56799040 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.26116865 |
Directory | /workspace/3.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.1383639188 |
Short name | T1421 |
Test name | |
Test status | |
Simulation time | 19409147 ps |
CPU time | 0.64 seconds |
Started | May 23 12:27:09 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203384 kb |
Host | smart-b1c0a555-0e56-4979-b0ca-13b3284a74e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383639188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1383639188 |
Directory | /workspace/30.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.828399658 |
Short name | T1369 |
Test name | |
Test status | |
Simulation time | 85249398 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-115311e3-450d-4194-a457-59f1caf01523 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828399658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.828399658 |
Directory | /workspace/31.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.3224992449 |
Short name | T1352 |
Test name | |
Test status | |
Simulation time | 25170958 ps |
CPU time | 0.72 seconds |
Started | May 23 12:26:59 PM PDT 24 |
Finished | May 23 12:27:03 PM PDT 24 |
Peak memory | 203432 kb |
Host | smart-efc9bcad-bb8d-4839-8102-9014bb9f1014 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224992449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3224992449 |
Directory | /workspace/32.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.362560605 |
Short name | T1359 |
Test name | |
Test status | |
Simulation time | 29696633 ps |
CPU time | 0.66 seconds |
Started | May 23 12:27:10 PM PDT 24 |
Finished | May 23 12:27:14 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-815caee1-ade5-4b02-b388-1b50746be348 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362560605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.362560605 |
Directory | /workspace/33.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1493955863 |
Short name | T1362 |
Test name | |
Test status | |
Simulation time | 48599681 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-e35fc3d4-c7ff-4071-813a-ec687b168bf0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493955863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1493955863 |
Directory | /workspace/34.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.3444338644 |
Short name | T1434 |
Test name | |
Test status | |
Simulation time | 17748495 ps |
CPU time | 0.74 seconds |
Started | May 23 12:27:07 PM PDT 24 |
Finished | May 23 12:27:12 PM PDT 24 |
Peak memory | 203536 kb |
Host | smart-5310b14b-1ae0-44e7-bbf0-1a4d88d4fa62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444338644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3444338644 |
Directory | /workspace/35.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.3711183756 |
Short name | T1412 |
Test name | |
Test status | |
Simulation time | 19034121 ps |
CPU time | 0.7 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:06 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-d3bbf1c8-b2d5-4f6d-8b79-74dadddfdf60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711183756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3711183756 |
Directory | /workspace/36.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.1853640550 |
Short name | T1429 |
Test name | |
Test status | |
Simulation time | 53590620 ps |
CPU time | 0.72 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-7b4a56a6-e656-4f87-818e-22eebd37e1cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853640550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1853640550 |
Directory | /workspace/37.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1725802867 |
Short name | T1392 |
Test name | |
Test status | |
Simulation time | 17479890 ps |
CPU time | 0.66 seconds |
Started | May 23 12:27:00 PM PDT 24 |
Finished | May 23 12:27:04 PM PDT 24 |
Peak memory | 203332 kb |
Host | smart-cf0bd9cc-d04a-489b-b327-60962b1da741 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725802867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1725802867 |
Directory | /workspace/38.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.1692040165 |
Short name | T1408 |
Test name | |
Test status | |
Simulation time | 46374147 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:07 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-8aad84ae-8c1e-4d17-a930-f481620d8e03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692040165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1692040165 |
Directory | /workspace/39.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2354990119 |
Short name | T1422 |
Test name | |
Test status | |
Simulation time | 54309374 ps |
CPU time | 1.27 seconds |
Started | May 23 12:26:59 PM PDT 24 |
Finished | May 23 12:27:03 PM PDT 24 |
Peak memory | 203476 kb |
Host | smart-73fe0f94-938d-4160-9a77-3d37180f3714 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354990119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2354990119 |
Directory | /workspace/4.i2c_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4185250165 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1682737349 ps |
CPU time | 5.78 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-06d22b8c-56f3-405b-be22-1e2fb2537f2b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185250165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4185250165 |
Directory | /workspace/4.i2c_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2921830527 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 52158038 ps |
CPU time | 0.78 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-6f17aede-a87e-4065-8b68-25d9dc947656 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921830527 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2921830527 |
Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.642063148 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 42592723 ps |
CPU time | 0.72 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-f13ffde7-8b1b-4364-94d9-dbb6d30a06cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642063148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.642063148 |
Directory | /workspace/4.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.661987336 |
Short name | T1346 |
Test name | |
Test status | |
Simulation time | 34612055 ps |
CPU time | 0.7 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-7071dad0-de18-42c3-89e3-28a92dc31e94 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661987336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.661987336 |
Directory | /workspace/4.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.980290446 |
Short name | T1374 |
Test name | |
Test status | |
Simulation time | 133660138 ps |
CPU time | 0.86 seconds |
Started | May 23 12:26:53 PM PDT 24 |
Finished | May 23 12:26:59 PM PDT 24 |
Peak memory | 203460 kb |
Host | smart-26b77e94-6fd4-4a64-87c9-57af7bd486ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980290446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out standing.980290446 |
Directory | /workspace/4.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3327129123 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 40373957 ps |
CPU time | 1.08 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:54 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-9420c2ef-4892-4b6f-95bc-af0a0e38f359 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327129123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3327129123 |
Directory | /workspace/4.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1204767905 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 518495693 ps |
CPU time | 2.14 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-399a55d5-db5d-4b9f-a330-06f700e8d1b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204767905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1204767905 |
Directory | /workspace/4.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.46633796 |
Short name | T1348 |
Test name | |
Test status | |
Simulation time | 51484050 ps |
CPU time | 0.71 seconds |
Started | May 23 12:27:01 PM PDT 24 |
Finished | May 23 12:27:05 PM PDT 24 |
Peak memory | 203364 kb |
Host | smart-1d395914-536c-4e34-afd2-657e705fd388 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46633796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.46633796 |
Directory | /workspace/40.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.3283631007 |
Short name | T1378 |
Test name | |
Test status | |
Simulation time | 15846427 ps |
CPU time | 0.7 seconds |
Started | May 23 12:27:10 PM PDT 24 |
Finished | May 23 12:27:15 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-e13a035f-2320-4c5b-acff-b02d5a7eddb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283631007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3283631007 |
Directory | /workspace/41.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.2182138441 |
Short name | T1399 |
Test name | |
Test status | |
Simulation time | 17624899 ps |
CPU time | 0.66 seconds |
Started | May 23 12:27:08 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-4a167ee0-6a0c-482f-a2ac-7ccd424c409a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182138441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2182138441 |
Directory | /workspace/42.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.3028356636 |
Short name | T1380 |
Test name | |
Test status | |
Simulation time | 41773994 ps |
CPU time | 0.7 seconds |
Started | May 23 12:27:02 PM PDT 24 |
Finished | May 23 12:27:08 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-56eefd2a-a183-45ba-ba2a-f46fcc9d3084 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028356636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3028356636 |
Directory | /workspace/43.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.1684167106 |
Short name | T1414 |
Test name | |
Test status | |
Simulation time | 15164361 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:07 PM PDT 24 |
Finished | May 23 12:27:12 PM PDT 24 |
Peak memory | 203336 kb |
Host | smart-7e91e16d-474d-43dd-b271-de1a81e24dba |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684167106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1684167106 |
Directory | /workspace/44.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.1587875907 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 34292401 ps |
CPU time | 0.68 seconds |
Started | May 23 12:27:08 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-9ee5dc9b-d82d-4a54-a311-3035673dc1e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587875907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1587875907 |
Directory | /workspace/45.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2194637865 |
Short name | T1417 |
Test name | |
Test status | |
Simulation time | 15866625 ps |
CPU time | 0.67 seconds |
Started | May 23 12:27:11 PM PDT 24 |
Finished | May 23 12:27:15 PM PDT 24 |
Peak memory | 203300 kb |
Host | smart-3e020471-88e5-4030-992a-1643e58c6bc9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194637865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2194637865 |
Directory | /workspace/46.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.691684402 |
Short name | T1355 |
Test name | |
Test status | |
Simulation time | 31600184 ps |
CPU time | 0.64 seconds |
Started | May 23 12:27:09 PM PDT 24 |
Finished | May 23 12:27:13 PM PDT 24 |
Peak memory | 203416 kb |
Host | smart-9b3065ed-473b-4e08-93ac-0cf23be40319 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691684402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.691684402 |
Directory | /workspace/47.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3845513048 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 31735111 ps |
CPU time | 0.68 seconds |
Started | May 23 12:27:12 PM PDT 24 |
Finished | May 23 12:27:16 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-a8fac008-3b38-4727-8052-504d37b2e7b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845513048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3845513048 |
Directory | /workspace/48.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.2968910185 |
Short name | T1415 |
Test name | |
Test status | |
Simulation time | 27855414 ps |
CPU time | 0.64 seconds |
Started | May 23 12:27:12 PM PDT 24 |
Finished | May 23 12:27:16 PM PDT 24 |
Peak memory | 203232 kb |
Host | smart-c8a6ea31-83e9-4804-9aba-ed48fae0e62b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968910185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2968910185 |
Directory | /workspace/49.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2859874279 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 28083535 ps |
CPU time | 0.85 seconds |
Started | May 23 12:26:47 PM PDT 24 |
Finished | May 23 12:26:51 PM PDT 24 |
Peak memory | 203536 kb |
Host | smart-f50a6c7d-b4e5-4dc8-9b5d-11a53d33947c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859874279 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2859874279 |
Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.180289451 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 158277249 ps |
CPU time | 0.81 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203516 kb |
Host | smart-e78aef1e-c63c-4b68-a57b-7c37bf6424f1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180289451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.180289451 |
Directory | /workspace/5.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.2488435808 |
Short name | T1372 |
Test name | |
Test status | |
Simulation time | 18766757 ps |
CPU time | 0.7 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-f61b4d77-64bd-49f5-ac19-7b27e174c44a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488435808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2488435808 |
Directory | /workspace/5.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3849978155 |
Short name | T1395 |
Test name | |
Test status | |
Simulation time | 30411813 ps |
CPU time | 1.16 seconds |
Started | May 23 12:26:53 PM PDT 24 |
Finished | May 23 12:26:59 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-dfb944c4-f2c7-48be-ba1a-a02aceddf97b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849978155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.3849978155 |
Directory | /workspace/5.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3792625323 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 1465484987 ps |
CPU time | 2.4 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:59 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-54a0cba3-d679-4fc8-a300-6f127eee040e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792625323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3792625323 |
Directory | /workspace/5.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3452905773 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 74532767 ps |
CPU time | 1.11 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:56 PM PDT 24 |
Peak memory | 211828 kb |
Host | smart-0c655638-e693-4047-b87d-45cb9767de6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452905773 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3452905773 |
Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3757705283 |
Short name | T1387 |
Test name | |
Test status | |
Simulation time | 33282222 ps |
CPU time | 0.7 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-6cf68952-f474-4898-9556-5304cb1291c1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757705283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3757705283 |
Directory | /workspace/6.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.514849000 |
Short name | T1445 |
Test name | |
Test status | |
Simulation time | 16649277 ps |
CPU time | 0.67 seconds |
Started | May 23 12:26:53 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203360 kb |
Host | smart-7ae38044-a0b5-48a6-b637-5524446b709c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514849000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.514849000 |
Directory | /workspace/6.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1097673562 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 82623803 ps |
CPU time | 0.91 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-d6086143-9296-4b51-917e-eb68a7e472c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097673562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.1097673562 |
Directory | /workspace/6.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2837690838 |
Short name | T1440 |
Test name | |
Test status | |
Simulation time | 117209601 ps |
CPU time | 1.58 seconds |
Started | May 23 12:26:55 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203612 kb |
Host | smart-fa6d704b-e055-4bcf-82ce-dcf8b0917fac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837690838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2837690838 |
Directory | /workspace/6.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2081770639 |
Short name | T1424 |
Test name | |
Test status | |
Simulation time | 178880679 ps |
CPU time | 1.44 seconds |
Started | May 23 12:26:50 PM PDT 24 |
Finished | May 23 12:26:55 PM PDT 24 |
Peak memory | 203572 kb |
Host | smart-d4faecfb-5697-42a0-9498-a4aebe121083 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081770639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2081770639 |
Directory | /workspace/6.i2c_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2988871697 |
Short name | T1431 |
Test name | |
Test status | |
Simulation time | 31362114 ps |
CPU time | 1.41 seconds |
Started | May 23 12:26:48 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 211812 kb |
Host | smart-5af85d18-c69d-4769-b081-4f89e445d508 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988871697 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2988871697 |
Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3481560044 |
Short name | T1394 |
Test name | |
Test status | |
Simulation time | 23209888 ps |
CPU time | 0.72 seconds |
Started | May 23 12:26:51 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203432 kb |
Host | smart-573c5254-e838-4c58-b1fa-eefbc8400aac |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481560044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3481560044 |
Directory | /workspace/7.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.971146473 |
Short name | T1356 |
Test name | |
Test status | |
Simulation time | 56086746 ps |
CPU time | 0.69 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203340 kb |
Host | smart-9da140c9-849f-4bfe-9d60-d0b07088af3b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971146473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.971146473 |
Directory | /workspace/7.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1409218488 |
Short name | T1420 |
Test name | |
Test status | |
Simulation time | 102942670 ps |
CPU time | 1.18 seconds |
Started | May 23 12:26:48 PM PDT 24 |
Finished | May 23 12:26:52 PM PDT 24 |
Peak memory | 203416 kb |
Host | smart-d2fce33f-ea33-4bb4-a333-522e39d9cf16 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409218488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.1409218488 |
Directory | /workspace/7.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.719463100 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 260802374 ps |
CPU time | 2.03 seconds |
Started | May 23 12:26:48 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203484 kb |
Host | smart-6c4dafce-cdd7-44ef-abff-e676fb8eb605 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719463100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.719463100 |
Directory | /workspace/7.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1545066473 |
Short name | T1373 |
Test name | |
Test status | |
Simulation time | 53194878 ps |
CPU time | 0.78 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203412 kb |
Host | smart-2f508f63-b67d-4ed5-a00f-a8a9708dd2ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545066473 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1545066473 |
Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1711161227 |
Short name | T1381 |
Test name | |
Test status | |
Simulation time | 30789713 ps |
CPU time | 0.77 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:53 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-4188cd5e-7718-497c-b0d7-88d99d3ef99a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711161227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1711161227 |
Directory | /workspace/8.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.1270745214 |
Short name | T1383 |
Test name | |
Test status | |
Simulation time | 28512407 ps |
CPU time | 0.64 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203432 kb |
Host | smart-0ba18219-195f-499b-9f40-fdc04a66faac |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270745214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1270745214 |
Directory | /workspace/8.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1636900518 |
Short name | T1370 |
Test name | |
Test status | |
Simulation time | 205991367 ps |
CPU time | 0.95 seconds |
Started | May 23 12:26:53 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203336 kb |
Host | smart-d4f81c16-32a2-44de-8970-3918c087863e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636900518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.1636900518 |
Directory | /workspace/8.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3594823147 |
Short name | T1388 |
Test name | |
Test status | |
Simulation time | 74838489 ps |
CPU time | 1.12 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:58 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-1dc06d14-17a3-4dc5-a74f-09f4ee882c7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594823147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3594823147 |
Directory | /workspace/8.i2c_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3037836898 |
Short name | T1377 |
Test name | |
Test status | |
Simulation time | 73552051 ps |
CPU time | 0.76 seconds |
Started | May 23 12:26:45 PM PDT 24 |
Finished | May 23 12:26:49 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-615a169d-2356-43f9-8055-d9c95c3c1ac0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037836898 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3037836898 |
Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1155036031 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 23514162 ps |
CPU time | 0.79 seconds |
Started | May 23 12:26:52 PM PDT 24 |
Finished | May 23 12:26:57 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-a5ec241b-dca3-4986-98c4-fd7cc982b2a5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155036031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1155036031 |
Directory | /workspace/9.i2c_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.1606066153 |
Short name | T1347 |
Test name | |
Test status | |
Simulation time | 42172246 ps |
CPU time | 0.67 seconds |
Started | May 23 12:26:57 PM PDT 24 |
Finished | May 23 12:27:00 PM PDT 24 |
Peak memory | 203408 kb |
Host | smart-1fc4d76b-06c3-4dfa-87be-b99f9b4f2261 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606066153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1606066153 |
Directory | /workspace/9.i2c_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.27505546 |
Short name | T1410 |
Test name | |
Test status | |
Simulation time | 24034766 ps |
CPU time | 0.87 seconds |
Started | May 23 12:26:49 PM PDT 24 |
Finished | May 23 12:26:54 PM PDT 24 |
Peak memory | 203596 kb |
Host | smart-ac825a8f-9323-4d64-984f-dc7859d36ebb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27505546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outs tanding.27505546 |
Directory | /workspace/9.i2c_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3580140291 |
Short name | T1404 |
Test name | |
Test status | |
Simulation time | 167410199 ps |
CPU time | 2.07 seconds |
Started | May 23 12:26:56 PM PDT 24 |
Finished | May 23 12:27:01 PM PDT 24 |
Peak memory | 203612 kb |
Host | smart-813680c9-f05d-4e53-8c53-c156e4f42d3e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580140291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3580140291 |
Directory | /workspace/9.i2c_tl_errors/latest |
Test location | /workspace/coverage/default/0.i2c_host_error_intr.2598331216 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 283937625 ps |
CPU time | 1.87 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:36 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-b04bbdd4-2621-4dda-a203-0ce56af3d759 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598331216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2598331216 |
Directory | /workspace/0.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2585009061 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 671626008 ps |
CPU time | 6.67 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:44 PM PDT 24 |
Peak memory | 258588 kb |
Host | smart-8cf9dcc0-0ec4-42ca-8eef-3e936e186a85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585009061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt y.2585009061 |
Directory | /workspace/0.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_full.1932967572 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1639458223 ps |
CPU time | 105.57 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 506628 kb |
Host | smart-3c8726a1-216b-47e3-b95b-6a91a4044ea6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932967572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1932967572 |
Directory | /workspace/0.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_overflow.2202705881 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 7507621743 ps |
CPU time | 44.54 seconds |
Started | May 23 12:32:32 PM PDT 24 |
Finished | May 23 12:33:18 PM PDT 24 |
Peak memory | 617372 kb |
Host | smart-c996c383-669a-46e5-9539-c275d0d198fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202705881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2202705881 |
Directory | /workspace/0.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3260469115 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 442998826 ps |
CPU time | 0.89 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:39 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-035bf4a7-c247-4ba5-b2eb-5c0f606ae94a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260469115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm t.3260469115 |
Directory | /workspace/0.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3303956476 |
Short name | T1261 |
Test name | |
Test status | |
Simulation time | 400161081 ps |
CPU time | 8.38 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:45 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-e9e1cd3f-a9e7-431a-a19a-b932f4055ca7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303956476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx. 3303956476 |
Directory | /workspace/0.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/0.i2c_host_fifo_watermark.1074599014 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3875031896 ps |
CPU time | 110.43 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:34:29 PM PDT 24 |
Peak memory | 1139712 kb |
Host | smart-8356262e-4d3c-46a7-b639-545b44e3c219 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074599014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1074599014 |
Directory | /workspace/0.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/0.i2c_host_may_nack.2725112545 |
Short name | T1089 |
Test name | |
Test status | |
Simulation time | 1644905766 ps |
CPU time | 6.67 seconds |
Started | May 23 12:32:39 PM PDT 24 |
Finished | May 23 12:32:47 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-40f0c702-16a6-4d65-b3b8-9cc4402ac8ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725112545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2725112545 |
Directory | /workspace/0.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/0.i2c_host_override.581611503 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 25658037 ps |
CPU time | 0.65 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:37 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-087c1365-1c58-44ce-8173-de9df7fa19a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581611503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.581611503 |
Directory | /workspace/0.i2c_host_override/latest |
Test location | /workspace/coverage/default/0.i2c_host_perf.2244175990 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 10039722158 ps |
CPU time | 109.2 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 229536 kb |
Host | smart-57f82d7a-1b1b-4afa-802b-c6cdce1a990a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244175990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2244175990 |
Directory | /workspace/0.i2c_host_perf/latest |
Test location | /workspace/coverage/default/0.i2c_host_smoke.579313634 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 1200968695 ps |
CPU time | 22.92 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:33:01 PM PDT 24 |
Peak memory | 317176 kb |
Host | smart-31422304-33e0-4c3d-a9f1-79e08e9ad6a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579313634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.579313634 |
Directory | /workspace/0.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/0.i2c_host_stress_all.1739146136 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 29255329662 ps |
CPU time | 308.6 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:37:46 PM PDT 24 |
Peak memory | 1772548 kb |
Host | smart-55da1048-d340-46cb-b23f-a00bd112822c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739146136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1739146136 |
Directory | /workspace/0.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/0.i2c_sec_cm.1329330637 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 115533832 ps |
CPU time | 0.94 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:35 PM PDT 24 |
Peak memory | 223008 kb |
Host | smart-19c86476-edf9-46fb-b91b-21306aacb29d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329330637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1329330637 |
Directory | /workspace/0.i2c_sec_cm/latest |
Test location | /workspace/coverage/default/0.i2c_target_bad_addr.1387152171 |
Short name | T1197 |
Test name | |
Test status | |
Simulation time | 2483956587 ps |
CPU time | 4.46 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:41 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-ddd64af3-f83d-4ae6-b0d9-648b07b3e62f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387152171 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1387152171 |
Directory | /workspace/0.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3998017055 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 10185343982 ps |
CPU time | 14.78 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 285260 kb |
Host | smart-98e612b5-339b-42b4-9103-d219b22cde11 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998017055 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.3998017055 |
Directory | /workspace/0.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/0.i2c_target_intr_smoke.2919481364 |
Short name | T1341 |
Test name | |
Test status | |
Simulation time | 1220710606 ps |
CPU time | 3.57 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:41 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-64936291-8380-4a86-984d-c8871ece171f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919481364 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.i2c_target_intr_smoke.2919481364 |
Directory | /workspace/0.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/0.i2c_target_intr_stress_wr.2900160113 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 6601791138 ps |
CPU time | 4.98 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:43 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-d226e9a9-a3b5-4a72-a373-04307a915e02 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900160113 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.2900160113 |
Directory | /workspace/0.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/0.i2c_target_smoke.1881229318 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 1230157480 ps |
CPU time | 46.11 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:22 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-d946994a-48c2-4cc6-9dd2-a8d10865a92b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881229318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar get_smoke.1881229318 |
Directory | /workspace/0.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/0.i2c_target_stress_rd.1794166454 |
Short name | T1131 |
Test name | |
Test status | |
Simulation time | 892590963 ps |
CPU time | 14.15 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:53 PM PDT 24 |
Peak memory | 212092 kb |
Host | smart-4b907036-18de-410b-866e-28a9ff76d8b9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794166454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c _target_stress_rd.1794166454 |
Directory | /workspace/0.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/0.i2c_target_stress_wr.1625434217 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 29760324814 ps |
CPU time | 21.53 seconds |
Started | May 23 12:32:40 PM PDT 24 |
Finished | May 23 12:33:03 PM PDT 24 |
Peak memory | 524920 kb |
Host | smart-bbe16c9f-9299-4bde-b713-b06bb851a59a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625434217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c _target_stress_wr.1625434217 |
Directory | /workspace/0.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/0.i2c_target_stretch.810501883 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 38448885708 ps |
CPU time | 2057.05 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 01:06:57 PM PDT 24 |
Peak memory | 3611232 kb |
Host | smart-cf754b4f-e0e2-4dbe-806d-f6d5942ae795 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810501883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta rget_stretch.810501883 |
Directory | /workspace/0.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/1.i2c_alert_test.682168897 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 28736792 ps |
CPU time | 0.63 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:36 PM PDT 24 |
Peak memory | 204468 kb |
Host | smart-08f13449-5e42-4b71-93ee-3c5169ad59e0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682168897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.682168897 |
Directory | /workspace/1.i2c_alert_test/latest |
Test location | /workspace/coverage/default/1.i2c_host_error_intr.2693028179 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 410553312 ps |
CPU time | 1.69 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:32:42 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-1493858d-0012-4c17-9991-27c379c809c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693028179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2693028179 |
Directory | /workspace/1.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.969244525 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 393651283 ps |
CPU time | 20.43 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:57 PM PDT 24 |
Peak memory | 288200 kb |
Host | smart-5c2e5130-9378-4100-90b9-b0ab555211fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969244525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty .969244525 |
Directory | /workspace/1.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_full.3695861789 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1429800411 ps |
CPU time | 69.06 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:33:47 PM PDT 24 |
Peak memory | 213080 kb |
Host | smart-10f97fa6-3f8a-457c-a6db-1312b3777edc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695861789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3695861789 |
Directory | /workspace/1.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_overflow.2223540875 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 2552607168 ps |
CPU time | 76.9 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:53 PM PDT 24 |
Peak memory | 789368 kb |
Host | smart-8ec1ee52-d7af-4cea-85fd-4a3a6b9541d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223540875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2223540875 |
Directory | /workspace/1.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.166651378 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 324300412 ps |
CPU time | 1.01 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:32:41 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-75aaac83-5c66-4d1a-8f53-b0b7176b323c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166651378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt .166651378 |
Directory | /workspace/1.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_reset_rx.719967976 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 663628472 ps |
CPU time | 4.73 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 12:32:43 PM PDT 24 |
Peak memory | 234828 kb |
Host | smart-eb53d71b-9680-4580-801f-6ddf8c84002a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719967976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.719967976 |
Directory | /workspace/1.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/1.i2c_host_fifo_watermark.3900702566 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 14003877968 ps |
CPU time | 262.76 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:36:57 PM PDT 24 |
Peak memory | 1042852 kb |
Host | smart-6b39e1cd-4c65-4234-9c8c-732be3d0a0d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900702566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3900702566 |
Directory | /workspace/1.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/1.i2c_host_may_nack.566954234 |
Short name | T1326 |
Test name | |
Test status | |
Simulation time | 1146056506 ps |
CPU time | 10.71 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-e18fc9a9-5ee1-4448-b41d-8af575004b20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566954234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.566954234 |
Directory | /workspace/1.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/1.i2c_host_mode_toggle.2467872543 |
Short name | T1134 |
Test name | |
Test status | |
Simulation time | 2096026072 ps |
CPU time | 40.11 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 236204 kb |
Host | smart-fe459fd6-3b26-4a08-8406-6f5f15bfcf11 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467872543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2467872543 |
Directory | /workspace/1.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/1.i2c_host_override.12234861 |
Short name | T1122 |
Test name | |
Test status | |
Simulation time | 48650333 ps |
CPU time | 0.64 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:37 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-35965b14-dd9a-43a0-a3ab-ee3c2c77b8a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12234861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.12234861 |
Directory | /workspace/1.i2c_host_override/latest |
Test location | /workspace/coverage/default/1.i2c_host_perf.4285090078 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 7699873159 ps |
CPU time | 32.11 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:07 PM PDT 24 |
Peak memory | 429420 kb |
Host | smart-b0dd3355-3bde-45f3-883b-53f277e5879b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285090078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.4285090078 |
Directory | /workspace/1.i2c_host_perf/latest |
Test location | /workspace/coverage/default/1.i2c_host_smoke.3647812989 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 3662829221 ps |
CPU time | 30.69 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 356092 kb |
Host | smart-6335e9bf-d9a4-4c7b-8c2b-b7271b85da05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647812989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3647812989 |
Directory | /workspace/1.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/1.i2c_host_stretch_timeout.204575564 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 3595088491 ps |
CPU time | 15.57 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 12:32:55 PM PDT 24 |
Peak memory | 215688 kb |
Host | smart-b51f0d7b-8195-471a-b99f-2b2dd84b8334 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204575564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.204575564 |
Directory | /workspace/1.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/1.i2c_sec_cm.2028248811 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 41735000 ps |
CPU time | 0.83 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:36 PM PDT 24 |
Peak memory | 221980 kb |
Host | smart-44d00697-1afc-4891-b2c2-dcdb42881fd8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028248811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2028248811 |
Directory | /workspace/1.i2c_sec_cm/latest |
Test location | /workspace/coverage/default/1.i2c_target_bad_addr.3359196960 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 837115896 ps |
CPU time | 4.35 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-b4616082-63fd-4f83-aa55-ce05914ccc1b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359196960 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3359196960 |
Directory | /workspace/1.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/1.i2c_target_fifo_reset_acq.875027989 |
Short name | T1129 |
Test name | |
Test status | |
Simulation time | 10308862751 ps |
CPU time | 14.09 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 245632 kb |
Host | smart-62f8f566-0149-4a6c-9faf-038be78e5e16 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875027989 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.i2c_target_fifo_reset_acq.875027989 |
Directory | /workspace/1.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/1.i2c_target_fifo_reset_tx.4048072010 |
Short name | T1141 |
Test name | |
Test status | |
Simulation time | 10035020127 ps |
CPU time | 71.24 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 481940 kb |
Host | smart-16e01ff8-f4cf-4144-867c-efaf2cf81e62 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048072010 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.i2c_target_fifo_reset_tx.4048072010 |
Directory | /workspace/1.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/1.i2c_target_glitch.1174332811 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 23340809038 ps |
CPU time | 10.07 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-919d8ddf-7813-4090-8c5e-608570905d37 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174332811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1174332811 |
Directory | /workspace/1.i2c_target_glitch/latest |
Test location | /workspace/coverage/default/1.i2c_target_intr_smoke.3929047220 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 4944281476 ps |
CPU time | 6.63 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:32:46 PM PDT 24 |
Peak memory | 220760 kb |
Host | smart-cbf056a5-9595-49cc-b999-9d484d94db8f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929047220 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.i2c_target_intr_smoke.3929047220 |
Directory | /workspace/1.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/1.i2c_target_intr_stress_wr.3636579237 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 12510140013 ps |
CPU time | 209.96 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:36:20 PM PDT 24 |
Peak memory | 3046196 kb |
Host | smart-d6d5797a-221a-4b7f-8352-4534562cb63b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636579237 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3636579237 |
Directory | /workspace/1.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/1.i2c_target_smoke.1193391096 |
Short name | T1294 |
Test name | |
Test status | |
Simulation time | 1817160013 ps |
CPU time | 30.4 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-2d0b3859-b2ca-40e8-b7dd-53545666a350 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193391096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar get_smoke.1193391096 |
Directory | /workspace/1.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/1.i2c_target_stress_rd.2230709454 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 1419119792 ps |
CPU time | 56.52 seconds |
Started | May 23 12:32:39 PM PDT 24 |
Finished | May 23 12:33:37 PM PDT 24 |
Peak memory | 205856 kb |
Host | smart-568e24cf-7755-46c5-86ee-22ac9e85df05 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230709454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c _target_stress_rd.2230709454 |
Directory | /workspace/1.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/1.i2c_target_stress_wr.2102982423 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 39829832983 ps |
CPU time | 32.31 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:08 PM PDT 24 |
Peak memory | 716376 kb |
Host | smart-0edaa853-fdc4-48f4-b7c1-7b16ff73bded |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102982423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c _target_stress_wr.2102982423 |
Directory | /workspace/1.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/1.i2c_target_timeout.1406240485 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 5634358209 ps |
CPU time | 7.27 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:54 PM PDT 24 |
Peak memory | 212056 kb |
Host | smart-4c6a49ef-25f1-4fac-96d1-19c78c914eae |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406240485 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.i2c_target_timeout.1406240485 |
Directory | /workspace/1.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/10.i2c_alert_test.2453327628 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 39397041 ps |
CPU time | 0.63 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:40 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-80f77ef8-2b33-4a70-926a-8a245170d132 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453327628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2453327628 |
Directory | /workspace/10.i2c_alert_test/latest |
Test location | /workspace/coverage/default/10.i2c_host_error_intr.1481865590 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 64375359 ps |
CPU time | 1.72 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:33:28 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-07a1f28d-3563-4d7d-a393-aefdfb12a6f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481865590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1481865590 |
Directory | /workspace/10.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2139477325 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 288698012 ps |
CPU time | 6.8 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 263928 kb |
Host | smart-ddab967c-5ff7-4a67-ba0c-70d8d3798f3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139477325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp ty.2139477325 |
Directory | /workspace/10.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_full.3617644766 |
Short name | T1162 |
Test name | |
Test status | |
Simulation time | 5678026510 ps |
CPU time | 109.05 seconds |
Started | May 23 12:33:22 PM PDT 24 |
Finished | May 23 12:35:13 PM PDT 24 |
Peak memory | 896964 kb |
Host | smart-794a3020-4752-459f-88a7-2de7c412ef66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617644766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3617644766 |
Directory | /workspace/10.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_overflow.501150140 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1973615962 ps |
CPU time | 139.99 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:35:45 PM PDT 24 |
Peak memory | 650772 kb |
Host | smart-d8f06bd4-b286-4320-a7f6-f8caa4ce3907 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501150140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.501150140 |
Directory | /workspace/10.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.968323873 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 134775331 ps |
CPU time | 1.04 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-4b1cd9b3-e6e3-43b1-b886-e38915c7c906 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968323873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm t.968323873 |
Directory | /workspace/10.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2761054333 |
Short name | T1095 |
Test name | |
Test status | |
Simulation time | 426248504 ps |
CPU time | 6.63 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-e949c317-9d24-4adc-b65f-488bba2a455f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761054333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx .2761054333 |
Directory | /workspace/10.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/10.i2c_host_fifo_watermark.1983576543 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 7822145224 ps |
CPU time | 280.24 seconds |
Started | May 23 12:33:22 PM PDT 24 |
Finished | May 23 12:38:04 PM PDT 24 |
Peak memory | 1118256 kb |
Host | smart-3d08941e-d98c-4e1e-b60a-ccff7f3d9dd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983576543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1983576543 |
Directory | /workspace/10.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/10.i2c_host_may_nack.3077345079 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 4091830624 ps |
CPU time | 7.36 seconds |
Started | May 23 12:33:34 PM PDT 24 |
Finished | May 23 12:33:42 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-8d69a1e1-2244-4567-80c7-c458c04fd3f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077345079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3077345079 |
Directory | /workspace/10.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/10.i2c_host_mode_toggle.1994876137 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 12294281028 ps |
CPU time | 35.5 seconds |
Started | May 23 12:33:39 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 360196 kb |
Host | smart-c7cfdc64-2ce5-491c-97af-2deb8d0523c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994876137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1994876137 |
Directory | /workspace/10.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/10.i2c_host_override.24497348 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 28025638 ps |
CPU time | 0.67 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-67d707e6-cf04-4d7a-9017-ff4c2f8b0f79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24497348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.24497348 |
Directory | /workspace/10.i2c_host_override/latest |
Test location | /workspace/coverage/default/10.i2c_host_perf.215773926 |
Short name | T1145 |
Test name | |
Test status | |
Simulation time | 453988361 ps |
CPU time | 4.84 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 236964 kb |
Host | smart-f27adc7e-ac74-4a02-9b07-683e91406192 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215773926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.215773926 |
Directory | /workspace/10.i2c_host_perf/latest |
Test location | /workspace/coverage/default/10.i2c_host_smoke.300833973 |
Short name | T1111 |
Test name | |
Test status | |
Simulation time | 5464196737 ps |
CPU time | 20.47 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:46 PM PDT 24 |
Peak memory | 287492 kb |
Host | smart-d23adb37-2387-4218-af23-67d3ea107060 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300833973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.300833973 |
Directory | /workspace/10.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/10.i2c_host_stress_all.3054397712 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 9769943883 ps |
CPU time | 1049.81 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:50:55 PM PDT 24 |
Peak memory | 2100984 kb |
Host | smart-2b454281-3455-4a27-8c63-1a3cd8db3795 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054397712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3054397712 |
Directory | /workspace/10.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/10.i2c_host_stretch_timeout.177256484 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 670679137 ps |
CPU time | 30.79 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 213076 kb |
Host | smart-65bc6472-2a07-45e9-84e4-b710b8b48c56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177256484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.177256484 |
Directory | /workspace/10.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/10.i2c_target_bad_addr.3749344314 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 7568028526 ps |
CPU time | 5.62 seconds |
Started | May 23 12:33:31 PM PDT 24 |
Finished | May 23 12:33:38 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-02201ae0-d48a-4ef0-ad68-5218c32d2a3f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749344314 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3749344314 |
Directory | /workspace/10.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1168352950 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 10176794297 ps |
CPU time | 14.02 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:51 PM PDT 24 |
Peak memory | 279288 kb |
Host | smart-ecc1539c-e70c-40c5-a060-c63468ef35be |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168352950 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.1168352950 |
Directory | /workspace/10.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/10.i2c_target_hrst.1818899474 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1736493166 ps |
CPU time | 2.69 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:41 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-0d17e37d-6ea3-46bd-bdba-2db646297f4e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818899474 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.1818899474 |
Directory | /workspace/10.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/10.i2c_target_intr_smoke.4228771133 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 5144981433 ps |
CPU time | 3.96 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:43 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-e778f63e-e384-4e44-acc1-c8941196c6ae |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228771133 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.i2c_target_intr_smoke.4228771133 |
Directory | /workspace/10.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/10.i2c_target_intr_stress_wr.3739112912 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 8658724905 ps |
CPU time | 26.23 seconds |
Started | May 23 12:33:33 PM PDT 24 |
Finished | May 23 12:34:00 PM PDT 24 |
Peak memory | 532468 kb |
Host | smart-aace7388-44b1-4710-9be6-1120f891b276 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739112912 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3739112912 |
Directory | /workspace/10.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/10.i2c_target_smoke.1720629064 |
Short name | T1327 |
Test name | |
Test status | |
Simulation time | 900422162 ps |
CPU time | 33.02 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:34:01 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-a5f8af16-a073-4375-a2fb-d280eee3ce9c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720629064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta rget_smoke.1720629064 |
Directory | /workspace/10.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/10.i2c_target_stress_rd.2337185823 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 3095708901 ps |
CPU time | 10.8 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:33:38 PM PDT 24 |
Peak memory | 210668 kb |
Host | smart-dd6a4b19-9892-4e13-9139-e484bca08cf7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337185823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2 c_target_stress_rd.2337185823 |
Directory | /workspace/10.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/10.i2c_target_stress_wr.4292055311 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 57596662031 ps |
CPU time | 189.4 seconds |
Started | May 23 12:33:25 PM PDT 24 |
Finished | May 23 12:36:38 PM PDT 24 |
Peak memory | 2352452 kb |
Host | smart-6184b3d0-5fef-4f70-95ed-9484119422fa |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292055311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2 c_target_stress_wr.4292055311 |
Directory | /workspace/10.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/10.i2c_target_timeout.64014878 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 15054408010 ps |
CPU time | 7.09 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:46 PM PDT 24 |
Peak memory | 213804 kb |
Host | smart-0a1ea9b1-2221-48a5-b0c8-bee8182a4d10 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64014878 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.64014878 |
Directory | /workspace/10.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/11.i2c_alert_test.2017158096 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 20662255 ps |
CPU time | 0.62 seconds |
Started | May 23 12:33:37 PM PDT 24 |
Finished | May 23 12:33:40 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-504e8721-fa7f-40a6-9661-109af1393f83 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017158096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2017158096 |
Directory | /workspace/11.i2c_alert_test/latest |
Test location | /workspace/coverage/default/11.i2c_host_error_intr.2486103572 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 618234371 ps |
CPU time | 4.12 seconds |
Started | May 23 12:33:34 PM PDT 24 |
Finished | May 23 12:33:39 PM PDT 24 |
Peak memory | 214252 kb |
Host | smart-fee005af-392a-4540-8818-9a320f0d4c6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486103572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2486103572 |
Directory | /workspace/11.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.750391961 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 772937802 ps |
CPU time | 20.9 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:59 PM PDT 24 |
Peak memory | 291368 kb |
Host | smart-7c2aea3d-c4d4-47ff-bfe5-3a4f6f2baa89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750391961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt y.750391961 |
Directory | /workspace/11.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_full.783174899 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 2532352580 ps |
CPU time | 93.41 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 821304 kb |
Host | smart-cd84de6b-4dd1-468d-a74a-7a128fd44175 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783174899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.783174899 |
Directory | /workspace/11.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_overflow.2295555997 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 2783827809 ps |
CPU time | 89.85 seconds |
Started | May 23 12:33:33 PM PDT 24 |
Finished | May 23 12:35:04 PM PDT 24 |
Peak memory | 898700 kb |
Host | smart-73c86df3-b2b6-426d-a36c-4f3aeb47d58f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295555997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2295555997 |
Directory | /workspace/11.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2330702009 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 79111303 ps |
CPU time | 0.88 seconds |
Started | May 23 12:33:39 PM PDT 24 |
Finished | May 23 12:33:42 PM PDT 24 |
Peak memory | 204628 kb |
Host | smart-93ac474e-ace1-4d70-8523-f2039982e3bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330702009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f mt.2330702009 |
Directory | /workspace/11.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2583523778 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 665731823 ps |
CPU time | 4.22 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:41 PM PDT 24 |
Peak memory | 203840 kb |
Host | smart-a41b059c-dca1-41e9-86b2-3bf6601f3c96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583523778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx .2583523778 |
Directory | /workspace/11.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/11.i2c_host_fifo_watermark.1671251827 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 12233473888 ps |
CPU time | 196.72 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:36:55 PM PDT 24 |
Peak memory | 903972 kb |
Host | smart-4f5400fc-77ea-4d05-8826-5ccb7a247e30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671251827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1671251827 |
Directory | /workspace/11.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/11.i2c_host_may_nack.3684213858 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 1190965879 ps |
CPU time | 4.09 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:42 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-08166152-7d65-45ca-8fdf-4dd568ea0b67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3684213858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3684213858 |
Directory | /workspace/11.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/11.i2c_host_override.1275142365 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 62140761 ps |
CPU time | 0.64 seconds |
Started | May 23 12:33:38 PM PDT 24 |
Finished | May 23 12:33:41 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-a7e94ea9-a915-4710-bf23-f7e183da64ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275142365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1275142365 |
Directory | /workspace/11.i2c_host_override/latest |
Test location | /workspace/coverage/default/11.i2c_host_perf.2009846955 |
Short name | T1196 |
Test name | |
Test status | |
Simulation time | 6249483190 ps |
CPU time | 51.46 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:34:29 PM PDT 24 |
Peak memory | 227996 kb |
Host | smart-de561c4a-794b-4587-8313-3a3cb7331ed3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009846955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2009846955 |
Directory | /workspace/11.i2c_host_perf/latest |
Test location | /workspace/coverage/default/11.i2c_host_smoke.1700776971 |
Short name | T1156 |
Test name | |
Test status | |
Simulation time | 6720578934 ps |
CPU time | 77.36 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 317536 kb |
Host | smart-be6125d1-d3d3-4e31-b5ba-ac7bf639596c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700776971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1700776971 |
Directory | /workspace/11.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/11.i2c_host_stress_all.1449296063 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 22683170043 ps |
CPU time | 390.08 seconds |
Started | May 23 12:33:33 PM PDT 24 |
Finished | May 23 12:40:04 PM PDT 24 |
Peak memory | 1455320 kb |
Host | smart-f338faba-a3ba-49b2-912a-17521b4f282c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449296063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1449296063 |
Directory | /workspace/11.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/11.i2c_host_stretch_timeout.4055175379 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 2813135335 ps |
CPU time | 10.37 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:47 PM PDT 24 |
Peak memory | 221288 kb |
Host | smart-7bb34446-ccea-4fd8-8584-d05b69fb62d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055175379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4055175379 |
Directory | /workspace/11.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/11.i2c_target_bad_addr.3534370673 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 4318290474 ps |
CPU time | 4.6 seconds |
Started | May 23 12:33:38 PM PDT 24 |
Finished | May 23 12:33:45 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-648ee2ad-17bf-4db8-b32d-efa70b95d249 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534370673 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3534370673 |
Directory | /workspace/11.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2276085265 |
Short name | T1242 |
Test name | |
Test status | |
Simulation time | 10100212766 ps |
CPU time | 66.04 seconds |
Started | May 23 12:33:39 PM PDT 24 |
Finished | May 23 12:34:47 PM PDT 24 |
Peak memory | 431272 kb |
Host | smart-d6728a2e-f95e-4636-bdf8-ebf1268fcef6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276085265 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.2276085265 |
Directory | /workspace/11.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1269078973 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 10104133265 ps |
CPU time | 77.77 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:34:57 PM PDT 24 |
Peak memory | 480560 kb |
Host | smart-0c000aa3-af20-4b53-b8e7-fa175c26d22d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269078973 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.i2c_target_fifo_reset_tx.1269078973 |
Directory | /workspace/11.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/11.i2c_target_hrst.2671276368 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 953328136 ps |
CPU time | 2.39 seconds |
Started | May 23 12:33:37 PM PDT 24 |
Finished | May 23 12:33:42 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-956bc0aa-9300-4fae-be81-eaef6a91a2d8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671276368 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.2671276368 |
Directory | /workspace/11.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/11.i2c_target_intr_smoke.359169520 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 1667948679 ps |
CPU time | 4.97 seconds |
Started | May 23 12:33:33 PM PDT 24 |
Finished | May 23 12:33:39 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-ccfa7fcc-313f-4e64-a384-57bc766a8034 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359169520 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.359169520 |
Directory | /workspace/11.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/11.i2c_target_intr_stress_wr.1334476306 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 9261675163 ps |
CPU time | 6.7 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:46 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-78ae76a4-410b-4cc8-ac05-5e7b8027565a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334476306 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1334476306 |
Directory | /workspace/11.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/11.i2c_target_smoke.2089111095 |
Short name | T1052 |
Test name | |
Test status | |
Simulation time | 2300072223 ps |
CPU time | 39.06 seconds |
Started | May 23 12:33:34 PM PDT 24 |
Finished | May 23 12:34:14 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-fdee9eac-06df-437e-b0c2-5432746c72fb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089111095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta rget_smoke.2089111095 |
Directory | /workspace/11.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/11.i2c_target_stress_rd.4115703786 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 3636325403 ps |
CPU time | 30.03 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:34:10 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-8fee7a13-6444-4624-b91b-a6cb9a1201f8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115703786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2 c_target_stress_rd.4115703786 |
Directory | /workspace/11.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/11.i2c_target_stress_wr.376733081 |
Short name | T1178 |
Test name | |
Test status | |
Simulation time | 48769057833 ps |
CPU time | 346.68 seconds |
Started | May 23 12:33:37 PM PDT 24 |
Finished | May 23 12:39:27 PM PDT 24 |
Peak memory | 3577880 kb |
Host | smart-3e7dfa3e-8564-4c2f-af9d-643b568b22f5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376733081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c _target_stress_wr.376733081 |
Directory | /workspace/11.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/11.i2c_target_stretch.3555989036 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 35801902423 ps |
CPU time | 797.83 seconds |
Started | May 23 12:33:34 PM PDT 24 |
Finished | May 23 12:46:53 PM PDT 24 |
Peak memory | 2133656 kb |
Host | smart-93566011-d24d-4d25-833a-cf17e294d95d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555989036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ target_stretch.3555989036 |
Directory | /workspace/11.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/11.i2c_target_timeout.4079606896 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 1263111001 ps |
CPU time | 7.07 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:46 PM PDT 24 |
Peak memory | 211780 kb |
Host | smart-9d582bb9-573e-4533-b984-71e7914505d1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079606896 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.i2c_target_timeout.4079606896 |
Directory | /workspace/11.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/12.i2c_alert_test.3219027963 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 28247253 ps |
CPU time | 0.7 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:33:48 PM PDT 24 |
Peak memory | 204452 kb |
Host | smart-79c9c7c2-26f8-458a-ac17-8edb669da2fd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219027963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3219027963 |
Directory | /workspace/12.i2c_alert_test/latest |
Test location | /workspace/coverage/default/12.i2c_host_error_intr.2367329791 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 138464210 ps |
CPU time | 1.24 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:40 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-db9c9a6b-07d7-473f-9622-f881c967113b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367329791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2367329791 |
Directory | /workspace/12.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.4282694483 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 1443215971 ps |
CPU time | 19.1 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 278780 kb |
Host | smart-a31dc98f-5749-4601-b252-3ee8818d6fe4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282694483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp ty.4282694483 |
Directory | /workspace/12.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_full.400727349 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 4859358463 ps |
CPU time | 91.46 seconds |
Started | May 23 12:33:37 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 787836 kb |
Host | smart-e3682087-531f-495c-bd8a-2c3151099484 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400727349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.400727349 |
Directory | /workspace/12.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_overflow.1674853818 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 3988437181 ps |
CPU time | 46.35 seconds |
Started | May 23 12:33:34 PM PDT 24 |
Finished | May 23 12:34:22 PM PDT 24 |
Peak memory | 527880 kb |
Host | smart-f274d5d4-02c0-4418-a4c3-c12f1267ffd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674853818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1674853818 |
Directory | /workspace/12.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.49478454 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 118280992 ps |
CPU time | 0.98 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:40 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-7a2f6c43-cf63-4577-a44a-6cc220d94140 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49478454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt .49478454 |
Directory | /workspace/12.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_reset_rx.368756862 |
Short name | T1314 |
Test name | |
Test status | |
Simulation time | 813869948 ps |
CPU time | 10.42 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:48 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-0cf3b224-d7a3-4d0f-9c27-fe7c2ddd9c1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368756862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx. 368756862 |
Directory | /workspace/12.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/12.i2c_host_fifo_watermark.2508391328 |
Short name | T1148 |
Test name | |
Test status | |
Simulation time | 3568615490 ps |
CPU time | 190.37 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:36:48 PM PDT 24 |
Peak memory | 913032 kb |
Host | smart-d5f88f39-5ad3-4907-98a6-e2596bb7c59c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508391328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2508391328 |
Directory | /workspace/12.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/12.i2c_host_may_nack.3620544648 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 690883818 ps |
CPU time | 8.23 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:57 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-24a3ed63-eeb0-4439-98d0-8b1095fbfb62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620544648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3620544648 |
Directory | /workspace/12.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/12.i2c_host_mode_toggle.2402693925 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 1469634266 ps |
CPU time | 25.93 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 293852 kb |
Host | smart-27810488-9670-45fd-a2f5-029519f6d712 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402693925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2402693925 |
Directory | /workspace/12.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/12.i2c_host_override.4177994369 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 29088405 ps |
CPU time | 0.73 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:33:37 PM PDT 24 |
Peak memory | 204456 kb |
Host | smart-e07dc1f2-9090-46b5-b9b5-91d2393a4515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177994369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4177994369 |
Directory | /workspace/12.i2c_host_override/latest |
Test location | /workspace/coverage/default/12.i2c_host_perf.632776118 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 748828437 ps |
CPU time | 11.2 seconds |
Started | May 23 12:33:36 PM PDT 24 |
Finished | May 23 12:33:51 PM PDT 24 |
Peak memory | 229060 kb |
Host | smart-59930dfb-1d22-41da-91ab-919b41b09986 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632776118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.632776118 |
Directory | /workspace/12.i2c_host_perf/latest |
Test location | /workspace/coverage/default/12.i2c_host_smoke.3453407797 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 7374025484 ps |
CPU time | 31.36 seconds |
Started | May 23 12:33:33 PM PDT 24 |
Finished | May 23 12:34:06 PM PDT 24 |
Peak memory | 345412 kb |
Host | smart-a1272bce-ef90-4124-a325-0941305eaed9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453407797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3453407797 |
Directory | /workspace/12.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/12.i2c_host_stretch_timeout.1639634695 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 1150034179 ps |
CPU time | 24.13 seconds |
Started | May 23 12:33:35 PM PDT 24 |
Finished | May 23 12:34:02 PM PDT 24 |
Peak memory | 213000 kb |
Host | smart-c4d783f6-c3a6-4565-8619-e8767b7d651c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639634695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1639634695 |
Directory | /workspace/12.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/12.i2c_target_bad_addr.588469732 |
Short name | T1340 |
Test name | |
Test status | |
Simulation time | 857506846 ps |
CPU time | 4.09 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-4c795979-b3ed-4584-bd70-3d400c279e55 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588469732 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.588469732 |
Directory | /workspace/12.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/12.i2c_target_fifo_reset_tx.400376433 |
Short name | T1342 |
Test name | |
Test status | |
Simulation time | 10054928870 ps |
CPU time | 67.04 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:35:00 PM PDT 24 |
Peak memory | 430868 kb |
Host | smart-bd90e87e-040a-4bb8-b9ea-eb11f1784e75 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400376433 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.i2c_target_fifo_reset_tx.400376433 |
Directory | /workspace/12.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/12.i2c_target_hrst.964282116 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 1620915851 ps |
CPU time | 2.64 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:53 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-3a4afa24-003f-4812-b6fa-0cb7ba2a8da4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964282116 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.i2c_target_hrst.964282116 |
Directory | /workspace/12.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/12.i2c_target_intr_smoke.1876441186 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1999137332 ps |
CPU time | 5.95 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 212868 kb |
Host | smart-44dcacbf-4f20-4837-bae3-e1815740fa8c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876441186 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.i2c_target_intr_smoke.1876441186 |
Directory | /workspace/12.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/12.i2c_target_intr_stress_wr.2525959793 |
Short name | T1291 |
Test name | |
Test status | |
Simulation time | 10319107738 ps |
CPU time | 19.87 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 478164 kb |
Host | smart-708d1078-80ea-489b-bf72-5d21da29bc26 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525959793 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2525959793 |
Directory | /workspace/12.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/12.i2c_target_smoke.889628666 |
Short name | T1201 |
Test name | |
Test status | |
Simulation time | 2046904040 ps |
CPU time | 16.36 seconds |
Started | May 23 12:33:37 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-836f9af8-0652-4980-a714-48d65cb18984 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889628666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar get_smoke.889628666 |
Directory | /workspace/12.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/12.i2c_target_stress_rd.3583737116 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 3062217643 ps |
CPU time | 50.13 seconds |
Started | May 23 12:33:39 PM PDT 24 |
Finished | May 23 12:34:31 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-0795b70d-56c3-4e1a-b2b1-6d65ba35eaf7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583737116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2 c_target_stress_rd.3583737116 |
Directory | /workspace/12.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/12.i2c_target_stress_wr.3626833624 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 15833135914 ps |
CPU time | 16.65 seconds |
Started | May 23 12:33:39 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-f35dc3d1-6161-44e6-bd0d-6067fdd52712 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626833624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2 c_target_stress_wr.3626833624 |
Directory | /workspace/12.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/12.i2c_target_stretch.2738071498 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 19274862473 ps |
CPU time | 1171.64 seconds |
Started | May 23 12:33:50 PM PDT 24 |
Finished | May 23 12:53:25 PM PDT 24 |
Peak memory | 4541212 kb |
Host | smart-0c7d1e64-afa2-4053-9b4a-fb6b41e9e40c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738071498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ target_stretch.2738071498 |
Directory | /workspace/12.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/12.i2c_target_timeout.2061765507 |
Short name | T1307 |
Test name | |
Test status | |
Simulation time | 5489762498 ps |
CPU time | 6.66 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:57 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-a99c12a5-9fc6-42d5-b73a-a935330d02ab |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061765507 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.i2c_target_timeout.2061765507 |
Directory | /workspace/12.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/13.i2c_alert_test.3945461566 |
Short name | T1275 |
Test name | |
Test status | |
Simulation time | 53605167 ps |
CPU time | 0.6 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:52 PM PDT 24 |
Peak memory | 204460 kb |
Host | smart-23bcc398-69a3-47d7-8b5e-6a64974ccfd8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945461566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3945461566 |
Directory | /workspace/13.i2c_alert_test/latest |
Test location | /workspace/coverage/default/13.i2c_host_error_intr.2842878248 |
Short name | T1257 |
Test name | |
Test status | |
Simulation time | 473876571 ps |
CPU time | 1.77 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:33:49 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-6bc2e422-fd94-4c64-9a45-af385699335a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842878248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2842878248 |
Directory | /workspace/13.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3775830953 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 795404657 ps |
CPU time | 3.62 seconds |
Started | May 23 12:33:52 PM PDT 24 |
Finished | May 23 12:33:57 PM PDT 24 |
Peak memory | 234524 kb |
Host | smart-c850f0ca-f0e1-4e63-a8a2-71dd55d0e3df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775830953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp ty.3775830953 |
Directory | /workspace/13.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_full.3937866509 |
Short name | T1130 |
Test name | |
Test status | |
Simulation time | 6740939398 ps |
CPU time | 118.62 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 623448 kb |
Host | smart-2fb70fe3-ed58-44b8-8ebd-a56f675c3756 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937866509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3937866509 |
Directory | /workspace/13.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_overflow.2070681445 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 2428871878 ps |
CPU time | 159.68 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:36:28 PM PDT 24 |
Peak memory | 650516 kb |
Host | smart-6c017d87-a0f2-4241-aab7-3f376afcefa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070681445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2070681445 |
Directory | /workspace/13.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1027650584 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 172207626 ps |
CPU time | 1.18 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:51 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-5a3072e5-5a11-44fd-b306-a5e98c10da19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027650584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f mt.1027650584 |
Directory | /workspace/13.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1565036451 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1625161830 ps |
CPU time | 12.31 seconds |
Started | May 23 12:33:45 PM PDT 24 |
Finished | May 23 12:33:59 PM PDT 24 |
Peak memory | 247116 kb |
Host | smart-602fb1c3-0ad8-41c4-832d-04cffc72235a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565036451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx .1565036451 |
Directory | /workspace/13.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/13.i2c_host_fifo_watermark.297168470 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 3764880397 ps |
CPU time | 103.66 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:35:31 PM PDT 24 |
Peak memory | 1032572 kb |
Host | smart-5c37d312-0276-43e0-90eb-446ea04581a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297168470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.297168470 |
Directory | /workspace/13.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/13.i2c_host_may_nack.986286501 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 384635824 ps |
CPU time | 4.95 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:55 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-b2fffe50-f7ca-4e7d-bb99-ccbe9e9e6005 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986286501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.986286501 |
Directory | /workspace/13.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/13.i2c_host_mode_toggle.229200479 |
Short name | T1217 |
Test name | |
Test status | |
Simulation time | 2751409362 ps |
CPU time | 128.4 seconds |
Started | May 23 12:33:45 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 376764 kb |
Host | smart-de681dcf-34e8-4f15-827e-b6be3b8da6fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229200479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.229200479 |
Directory | /workspace/13.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/13.i2c_host_override.1072795085 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 82598680 ps |
CPU time | 0.68 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:33:48 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-3e669b95-b753-41a5-b19a-16d98d9d8772 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072795085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1072795085 |
Directory | /workspace/13.i2c_host_override/latest |
Test location | /workspace/coverage/default/13.i2c_host_perf.3772791380 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 7387555134 ps |
CPU time | 524.53 seconds |
Started | May 23 12:33:45 PM PDT 24 |
Finished | May 23 12:42:31 PM PDT 24 |
Peak memory | 1052120 kb |
Host | smart-7dc53301-f088-497c-adf3-3cb816e3b366 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772791380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3772791380 |
Directory | /workspace/13.i2c_host_perf/latest |
Test location | /workspace/coverage/default/13.i2c_host_smoke.4078445639 |
Short name | T1091 |
Test name | |
Test status | |
Simulation time | 1269495755 ps |
CPU time | 62.05 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:34:54 PM PDT 24 |
Peak memory | 403932 kb |
Host | smart-074ffb3f-3c38-43db-a251-d3db07a7b318 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078445639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.4078445639 |
Directory | /workspace/13.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/13.i2c_host_stress_all.1741061071 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 30763063823 ps |
CPU time | 328.74 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:39:19 PM PDT 24 |
Peak memory | 407620 kb |
Host | smart-6591cc9d-e3a3-4244-bd87-2d5c20f2ae72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741061071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1741061071 |
Directory | /workspace/13.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/13.i2c_host_stretch_timeout.2258229725 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 443134059 ps |
CPU time | 20.29 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:34:12 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-61226c0d-0e39-4acd-abe5-af81665cef45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258229725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2258229725 |
Directory | /workspace/13.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/13.i2c_target_bad_addr.1243075821 |
Short name | T1222 |
Test name | |
Test status | |
Simulation time | 699664733 ps |
CPU time | 3.3 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:55 PM PDT 24 |
Peak memory | 213100 kb |
Host | smart-c43f814e-1905-4968-b17e-f8b5536d8f73 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243075821 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1243075821 |
Directory | /workspace/13.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2490782923 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 10035019201 ps |
CPU time | 67.74 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 412652 kb |
Host | smart-4a022fd8-4819-4445-b014-cd850605bed7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490782923 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.2490782923 |
Directory | /workspace/13.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3561662869 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 10332416246 ps |
CPU time | 9.85 seconds |
Started | May 23 12:33:52 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 258312 kb |
Host | smart-47cd553f-e580-4d50-ab2f-04d61c94e403 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561662869 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.i2c_target_fifo_reset_tx.3561662869 |
Directory | /workspace/13.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/13.i2c_target_hrst.2606386194 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 1937263285 ps |
CPU time | 2.46 seconds |
Started | May 23 12:33:50 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-d9b956ef-ea2a-470e-b362-bc5b1a45c570 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606386194 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.2606386194 |
Directory | /workspace/13.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/13.i2c_target_intr_smoke.3331723458 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 1706124635 ps |
CPU time | 8.11 seconds |
Started | May 23 12:33:50 PM PDT 24 |
Finished | May 23 12:34:01 PM PDT 24 |
Peak memory | 219964 kb |
Host | smart-dfdb9abf-0a43-4d91-8482-d9634294ef47 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331723458 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.i2c_target_intr_smoke.3331723458 |
Directory | /workspace/13.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/13.i2c_target_intr_stress_wr.1362929922 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 18300227324 ps |
CPU time | 373.48 seconds |
Started | May 23 12:33:46 PM PDT 24 |
Finished | May 23 12:40:01 PM PDT 24 |
Peak memory | 4362208 kb |
Host | smart-154b4a81-f667-4577-827a-31cc044e6ddf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362929922 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1362929922 |
Directory | /workspace/13.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/13.i2c_target_smoke.2441274275 |
Short name | T1041 |
Test name | |
Test status | |
Simulation time | 1645377604 ps |
CPU time | 35.11 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:34:24 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-4e4049fc-51ee-47de-8fa3-441cfccf48dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441274275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta rget_smoke.2441274275 |
Directory | /workspace/13.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/13.i2c_target_stress_rd.2222538718 |
Short name | T1218 |
Test name | |
Test status | |
Simulation time | 3240858422 ps |
CPU time | 61.35 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:34:53 PM PDT 24 |
Peak memory | 208844 kb |
Host | smart-f83f77d5-1b07-417c-8e8f-0b6a3ff40f61 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222538718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2 c_target_stress_rd.2222538718 |
Directory | /workspace/13.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/13.i2c_target_stress_wr.17203816 |
Short name | T1298 |
Test name | |
Test status | |
Simulation time | 44007810082 ps |
CPU time | 46.3 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 834484 kb |
Host | smart-f34cec8d-74b3-4ab3-8280-856521f101b1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ= i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ target_stress_wr.17203816 |
Directory | /workspace/13.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/13.i2c_target_stretch.329968373 |
Short name | T1140 |
Test name | |
Test status | |
Simulation time | 36854349016 ps |
CPU time | 2245.4 seconds |
Started | May 23 12:33:51 PM PDT 24 |
Finished | May 23 01:11:19 PM PDT 24 |
Peak memory | 4241556 kb |
Host | smart-e248b9b4-6b5f-4b9f-8116-e686f5b3806d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329968373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t arget_stretch.329968373 |
Directory | /workspace/13.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/13.i2c_target_timeout.350753833 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 1181192576 ps |
CPU time | 6.31 seconds |
Started | May 23 12:33:45 PM PDT 24 |
Finished | May 23 12:33:53 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-22bf2d87-518a-44d7-addb-2806897eb82b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350753833 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.i2c_target_timeout.350753833 |
Directory | /workspace/13.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/14.i2c_alert_test.1900565502 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 44975634 ps |
CPU time | 0.63 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-85bd513a-660c-4464-892e-7e8d7b50a987 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900565502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1900565502 |
Directory | /workspace/14.i2c_alert_test/latest |
Test location | /workspace/coverage/default/14.i2c_host_error_intr.67381415 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 624144742 ps |
CPU time | 3.18 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:52 PM PDT 24 |
Peak memory | 213092 kb |
Host | smart-229f622d-8f76-41dd-9e00-3c53cdc967e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67381415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.67381415 |
Directory | /workspace/14.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1079929176 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 2348433190 ps |
CPU time | 8.24 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:33:59 PM PDT 24 |
Peak memory | 305296 kb |
Host | smart-fc7ede66-4e05-42c2-9ef2-147cc9a17930 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079929176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp ty.1079929176 |
Directory | /workspace/14.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_full.3615601258 |
Short name | T1312 |
Test name | |
Test status | |
Simulation time | 4092092992 ps |
CPU time | 63.14 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 713864 kb |
Host | smart-8cf2ca62-2ced-4fd8-99ac-d3f6a8601a97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615601258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3615601258 |
Directory | /workspace/14.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_overflow.4154665748 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 1284375086 ps |
CPU time | 87.74 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:35:19 PM PDT 24 |
Peak memory | 523512 kb |
Host | smart-a3ef63d0-2242-46aa-a4e5-439087ac292a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154665748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4154665748 |
Directory | /workspace/14.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1470336526 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 405116435 ps |
CPU time | 1.01 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:51 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-e7caad18-8b93-43a2-aa69-b5c005edac52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470336526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f mt.1470336526 |
Directory | /workspace/14.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1968655652 |
Short name | T1214 |
Test name | |
Test status | |
Simulation time | 173673800 ps |
CPU time | 4.19 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-a20a0687-f54d-4395-920b-a612dee497bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968655652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx .1968655652 |
Directory | /workspace/14.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/14.i2c_host_fifo_watermark.1554848247 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 9269102874 ps |
CPU time | 126.2 seconds |
Started | May 23 12:33:48 PM PDT 24 |
Finished | May 23 12:35:57 PM PDT 24 |
Peak memory | 1147520 kb |
Host | smart-df372c91-4dd9-4220-9a9d-2197db92ff4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554848247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1554848247 |
Directory | /workspace/14.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/14.i2c_host_may_nack.1745588143 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 1086190937 ps |
CPU time | 3.76 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:05 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-a8c06a29-b75e-49e9-8d01-c12b8cfc8d35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745588143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1745588143 |
Directory | /workspace/14.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/14.i2c_host_mode_toggle.1127091524 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 7819872652 ps |
CPU time | 93.01 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:35:38 PM PDT 24 |
Peak memory | 370744 kb |
Host | smart-3cbac760-c8e0-4a16-9299-6135e48d0ef6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127091524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1127091524 |
Directory | /workspace/14.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/14.i2c_host_override.2762717176 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 68359659 ps |
CPU time | 0.63 seconds |
Started | May 23 12:33:51 PM PDT 24 |
Finished | May 23 12:33:54 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-e3d0523a-fad6-4704-bebd-47bb29416f65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762717176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2762717176 |
Directory | /workspace/14.i2c_host_override/latest |
Test location | /workspace/coverage/default/14.i2c_host_perf.961270876 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 862228212 ps |
CPU time | 8.5 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 284256 kb |
Host | smart-f2042f04-2dd3-4e32-826f-4c5e150decda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961270876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.961270876 |
Directory | /workspace/14.i2c_host_perf/latest |
Test location | /workspace/coverage/default/14.i2c_host_smoke.3728082971 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1362725080 ps |
CPU time | 70.23 seconds |
Started | May 23 12:33:50 PM PDT 24 |
Finished | May 23 12:35:03 PM PDT 24 |
Peak memory | 337072 kb |
Host | smart-593855d1-d4cb-4ef2-a1d4-5c1fe19b36b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728082971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3728082971 |
Directory | /workspace/14.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/14.i2c_host_stretch_timeout.316549218 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 2924353111 ps |
CPU time | 11.82 seconds |
Started | May 23 12:33:47 PM PDT 24 |
Finished | May 23 12:34:02 PM PDT 24 |
Peak memory | 219908 kb |
Host | smart-86f34f33-96b8-4a63-944a-a48a188a7c07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316549218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.316549218 |
Directory | /workspace/14.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/14.i2c_target_bad_addr.2079329331 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 636580622 ps |
CPU time | 3.46 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:34:08 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-bfc1a334-9904-4625-8346-5a69e928ab28 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079329331 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2079329331 |
Directory | /workspace/14.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/14.i2c_target_fifo_reset_tx.340973763 |
Short name | T1311 |
Test name | |
Test status | |
Simulation time | 10121984395 ps |
CPU time | 29.84 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:32 PM PDT 24 |
Peak memory | 387364 kb |
Host | smart-40cd5f44-5cd3-4eb4-9658-6ef23d50c7dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340973763 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.i2c_target_fifo_reset_tx.340973763 |
Directory | /workspace/14.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/14.i2c_target_hrst.2749266304 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 413760382 ps |
CPU time | 2.46 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-c3a2287e-3c25-4905-9cb7-e36593ca24b2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749266304 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.2749266304 |
Directory | /workspace/14.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/14.i2c_target_intr_smoke.2186368861 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 852983891 ps |
CPU time | 4.86 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:34:08 PM PDT 24 |
Peak memory | 207752 kb |
Host | smart-0a8393fd-48cb-425f-b4c1-823f0371e7aa |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186368861 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.i2c_target_intr_smoke.2186368861 |
Directory | /workspace/14.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/14.i2c_target_intr_stress_wr.1540866631 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 16205627270 ps |
CPU time | 295.17 seconds |
Started | May 23 12:34:04 PM PDT 24 |
Finished | May 23 12:39:01 PM PDT 24 |
Peak memory | 3718040 kb |
Host | smart-99572241-f11b-4d56-9f1c-120042b860fe |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540866631 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1540866631 |
Directory | /workspace/14.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/14.i2c_target_smoke.1994839754 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 1571743010 ps |
CPU time | 68.16 seconds |
Started | May 23 12:33:49 PM PDT 24 |
Finished | May 23 12:35:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-4b306d2f-8506-45b5-8b99-d9fe8da29153 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994839754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta rget_smoke.1994839754 |
Directory | /workspace/14.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/14.i2c_target_stress_rd.1879919173 |
Short name | T1286 |
Test name | |
Test status | |
Simulation time | 6180638510 ps |
CPU time | 25.91 seconds |
Started | May 23 12:33:57 PM PDT 24 |
Finished | May 23 12:34:24 PM PDT 24 |
Peak memory | 224452 kb |
Host | smart-c2f5d250-42f0-487f-b374-f264843605dd |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879919173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2 c_target_stress_rd.1879919173 |
Directory | /workspace/14.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/14.i2c_target_stress_wr.3733070859 |
Short name | T1331 |
Test name | |
Test status | |
Simulation time | 15989759207 ps |
CPU time | 9.27 seconds |
Started | May 23 12:33:51 PM PDT 24 |
Finished | May 23 12:34:03 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-ce699d2f-a9ff-4945-9b57-63f2ac1dd425 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733070859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2 c_target_stress_wr.3733070859 |
Directory | /workspace/14.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/14.i2c_target_stretch.3489277896 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 27300769673 ps |
CPU time | 519.53 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:42:40 PM PDT 24 |
Peak memory | 3097164 kb |
Host | smart-49185aad-b852-46f8-9872-35a772ba5ad2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489277896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ target_stretch.3489277896 |
Directory | /workspace/14.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/14.i2c_target_timeout.2206554145 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 3008025981 ps |
CPU time | 7.64 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-1609a631-7c36-493c-8534-964c090f7662 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206554145 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.i2c_target_timeout.2206554145 |
Directory | /workspace/14.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/15.i2c_alert_test.532912561 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 84583727 ps |
CPU time | 0.64 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-713ccc63-e3eb-4eba-8f2a-a126c251d135 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532912561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.532912561 |
Directory | /workspace/15.i2c_alert_test/latest |
Test location | /workspace/coverage/default/15.i2c_host_error_intr.2629391574 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 2098302904 ps |
CPU time | 12.66 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:15 PM PDT 24 |
Peak memory | 257872 kb |
Host | smart-8a10c68a-a079-4b1e-8197-da5850c9cb37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629391574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2629391574 |
Directory | /workspace/15.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.4079222801 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 387484795 ps |
CPU time | 7 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:34:10 PM PDT 24 |
Peak memory | 279192 kb |
Host | smart-9d80fee3-1502-42e2-9108-2225e6394d62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079222801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp ty.4079222801 |
Directory | /workspace/15.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_overflow.1273834700 |
Short name | T1207 |
Test name | |
Test status | |
Simulation time | 5862975022 ps |
CPU time | 89.61 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:35:34 PM PDT 24 |
Peak memory | 490032 kb |
Host | smart-21f8d176-5f90-4545-b205-1c624b658b0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273834700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1273834700 |
Directory | /workspace/15.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.888806636 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 1264169602 ps |
CPU time | 0.98 seconds |
Started | May 23 12:33:57 PM PDT 24 |
Finished | May 23 12:34:00 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-18796088-df56-4905-8d9e-c5faa0ef0e37 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888806636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm t.888806636 |
Directory | /workspace/15.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3180284258 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 192773053 ps |
CPU time | 3.48 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 225512 kb |
Host | smart-fff353a8-c4df-4a09-81a1-7dd84333697e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180284258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx .3180284258 |
Directory | /workspace/15.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/15.i2c_host_may_nack.1243641016 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 513631875 ps |
CPU time | 8.17 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:08 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-ad38e1b7-d66e-466d-b348-8bf835db361a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243641016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1243641016 |
Directory | /workspace/15.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/15.i2c_host_mode_toggle.947902403 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 2159070760 ps |
CPU time | 108.18 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:35:53 PM PDT 24 |
Peak memory | 438976 kb |
Host | smart-d499a8a9-b81d-4998-9f75-b9f223d89ab5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947902403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.947902403 |
Directory | /workspace/15.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/15.i2c_host_override.234333003 |
Short name | T1151 |
Test name | |
Test status | |
Simulation time | 151982580 ps |
CPU time | 0.62 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:01 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-1e93f9b8-137f-40f7-b539-3d1e3e770078 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234333003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.234333003 |
Directory | /workspace/15.i2c_host_override/latest |
Test location | /workspace/coverage/default/15.i2c_host_perf.2924271988 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 70536373500 ps |
CPU time | 710.68 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:45:54 PM PDT 24 |
Peak memory | 214824 kb |
Host | smart-4d3cb36e-ba62-45d7-907a-daa58b5f9c10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924271988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2924271988 |
Directory | /workspace/15.i2c_host_perf/latest |
Test location | /workspace/coverage/default/15.i2c_host_smoke.1285427765 |
Short name | T1328 |
Test name | |
Test status | |
Simulation time | 1535280253 ps |
CPU time | 29.72 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 441452 kb |
Host | smart-a141a50e-b619-472b-bb1a-6185b500e1d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285427765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1285427765 |
Directory | /workspace/15.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/15.i2c_host_stretch_timeout.2899391265 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 1079153181 ps |
CPU time | 24.51 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:30 PM PDT 24 |
Peak memory | 213104 kb |
Host | smart-656a0d0d-61d0-4478-a052-b1463cf8b41c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899391265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2899391265 |
Directory | /workspace/15.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/15.i2c_target_bad_addr.2984898126 |
Short name | T1335 |
Test name | |
Test status | |
Simulation time | 1688263018 ps |
CPU time | 2.53 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:03 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-c8b56fc9-6023-41d1-808d-145e7ae3f262 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984898126 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2984898126 |
Directory | /workspace/15.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1793240000 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 10115404092 ps |
CPU time | 18.82 seconds |
Started | May 23 12:34:04 PM PDT 24 |
Finished | May 23 12:34:25 PM PDT 24 |
Peak memory | 303948 kb |
Host | smart-68d91f21-7b1e-4d63-ba1f-a073f1e16f5d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793240000 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.1793240000 |
Directory | /workspace/15.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3115920012 |
Short name | T1283 |
Test name | |
Test status | |
Simulation time | 10053520011 ps |
CPU time | 69.89 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:35:12 PM PDT 24 |
Peak memory | 507232 kb |
Host | smart-6b289656-7250-4965-a077-6b65a5fb6c19 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115920012 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.i2c_target_fifo_reset_tx.3115920012 |
Directory | /workspace/15.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/15.i2c_target_hrst.1391357325 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 662093650 ps |
CPU time | 2.77 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-dc35f194-dc5f-4989-bc4f-8affd096945b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391357325 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_hrst.1391357325 |
Directory | /workspace/15.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/15.i2c_target_intr_smoke.4074229450 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1557520302 ps |
CPU time | 4.22 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:34:08 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-4c95da6f-f590-4fd5-90c5-657ef1a3a580 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074229450 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.i2c_target_intr_smoke.4074229450 |
Directory | /workspace/15.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/15.i2c_target_intr_stress_wr.2203199678 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 22494686427 ps |
CPU time | 156.39 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:36:42 PM PDT 24 |
Peak memory | 2485308 kb |
Host | smart-d4149b42-ed2c-4294-b9e8-60749fc7ad0d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203199678 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2203199678 |
Directory | /workspace/15.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/15.i2c_target_smoke.100807212 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 10223331304 ps |
CPU time | 16.6 seconds |
Started | May 23 12:33:57 PM PDT 24 |
Finished | May 23 12:34:15 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-763135a6-6c0d-4030-9f5e-c44e63025d26 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100807212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar get_smoke.100807212 |
Directory | /workspace/15.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/15.i2c_target_stress_rd.2092965587 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 5081279686 ps |
CPU time | 23.18 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:24 PM PDT 24 |
Peak memory | 227740 kb |
Host | smart-9fcc46e3-a3be-4afd-b259-a505ffd2ec71 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092965587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2 c_target_stress_rd.2092965587 |
Directory | /workspace/15.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/15.i2c_target_stress_wr.403260314 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 38387804644 ps |
CPU time | 77.87 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:35:20 PM PDT 24 |
Peak memory | 1246272 kb |
Host | smart-4b6015f8-5a81-4cef-8ae1-4999d3130419 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403260314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c _target_stress_wr.403260314 |
Directory | /workspace/15.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/15.i2c_target_stretch.207735828 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 10318296514 ps |
CPU time | 146.99 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:36:31 PM PDT 24 |
Peak memory | 664280 kb |
Host | smart-9d9dd212-d983-4c20-8dfa-b87f034dc607 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207735828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t arget_stretch.207735828 |
Directory | /workspace/15.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/15.i2c_target_timeout.1826319063 |
Short name | T1106 |
Test name | |
Test status | |
Simulation time | 1249536984 ps |
CPU time | 6.94 seconds |
Started | May 23 12:33:56 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-f41d1305-378a-4733-b4f0-23c689f8818d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826319063 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.i2c_target_timeout.1826319063 |
Directory | /workspace/15.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/16.i2c_alert_test.2740659419 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 23065781 ps |
CPU time | 0.64 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:03 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-8e519427-332a-4d30-9108-62063b43db94 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740659419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2740659419 |
Directory | /workspace/16.i2c_alert_test/latest |
Test location | /workspace/coverage/default/16.i2c_host_error_intr.3237813263 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 566897038 ps |
CPU time | 4.06 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 216936 kb |
Host | smart-dce95fec-245b-4488-b0f7-944e382fae06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237813263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3237813263 |
Directory | /workspace/16.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3409760230 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 832598107 ps |
CPU time | 9.4 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:11 PM PDT 24 |
Peak memory | 285808 kb |
Host | smart-1233e5e2-7f34-4ce7-8c50-6bc364a36a0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409760230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp ty.3409760230 |
Directory | /workspace/16.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_full.2756489514 |
Short name | T1155 |
Test name | |
Test status | |
Simulation time | 20356123133 ps |
CPU time | 105.58 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 558792 kb |
Host | smart-f138e071-441e-4f4a-bb1b-fc1c495e2eb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756489514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2756489514 |
Directory | /workspace/16.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_overflow.2679885046 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 9401883945 ps |
CPU time | 186.53 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:37:11 PM PDT 24 |
Peak memory | 788980 kb |
Host | smart-ef34cd56-ed9e-45e6-ad04-27f1a8be30e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679885046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2679885046 |
Directory | /workspace/16.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3306918790 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 320582299 ps |
CPU time | 0.89 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-9789bcc9-6896-4ca3-836b-0a5778daf879 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306918790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f mt.3306918790 |
Directory | /workspace/16.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/16.i2c_host_fifo_watermark.982416865 |
Short name | T1278 |
Test name | |
Test status | |
Simulation time | 8034455001 ps |
CPU time | 126.4 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 1223128 kb |
Host | smart-bdf713fd-8115-40be-adbe-04dcd4ff6334 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982416865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.982416865 |
Directory | /workspace/16.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/16.i2c_host_may_nack.1435889509 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 6842393175 ps |
CPU time | 7.87 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:13 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-55faf208-f915-408f-bfa1-2a04850218ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435889509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1435889509 |
Directory | /workspace/16.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/16.i2c_host_mode_toggle.3688737880 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 5621224027 ps |
CPU time | 27.18 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:34:30 PM PDT 24 |
Peak memory | 346532 kb |
Host | smart-b23d2157-4bbf-4151-8de2-b35cccca1d47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688737880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3688737880 |
Directory | /workspace/16.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/16.i2c_host_override.362139020 |
Short name | T1105 |
Test name | |
Test status | |
Simulation time | 29572676 ps |
CPU time | 0.73 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-75499db4-7eca-4909-ba11-68557c31471d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362139020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.362139020 |
Directory | /workspace/16.i2c_host_override/latest |
Test location | /workspace/coverage/default/16.i2c_host_perf.3412190024 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 1312670894 ps |
CPU time | 40.31 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:34:45 PM PDT 24 |
Peak memory | 217976 kb |
Host | smart-81859bcc-0e8c-4360-b5e6-c40731d6d239 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412190024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3412190024 |
Directory | /workspace/16.i2c_host_perf/latest |
Test location | /workspace/coverage/default/16.i2c_host_smoke.4264571650 |
Short name | T1165 |
Test name | |
Test status | |
Simulation time | 7248053426 ps |
CPU time | 22.55 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 324572 kb |
Host | smart-b9c0340c-2995-4221-be79-c49a33a524bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264571650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.4264571650 |
Directory | /workspace/16.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/16.i2c_host_stress_all.2369075930 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 34235477390 ps |
CPU time | 463.17 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:41:48 PM PDT 24 |
Peak memory | 1874356 kb |
Host | smart-7b1c6213-6459-4484-afdb-07950d32e9e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369075930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2369075930 |
Directory | /workspace/16.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/16.i2c_host_stretch_timeout.2499561335 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 2649700505 ps |
CPU time | 31.96 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:34 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-2f0a315b-4ce8-4b26-9402-bc1ee4b44b86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499561335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2499561335 |
Directory | /workspace/16.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/16.i2c_target_bad_addr.1323678719 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 749331401 ps |
CPU time | 3.97 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 213016 kb |
Host | smart-d764d292-ece3-4216-b3b7-b5d52538bb4b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323678719 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1323678719 |
Directory | /workspace/16.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2002364979 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 10871769223 ps |
CPU time | 3.39 seconds |
Started | May 23 12:34:04 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 207636 kb |
Host | smart-612438ab-c6a5-4fac-bb67-03b3258d6b67 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002364979 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.2002364979 |
Directory | /workspace/16.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1104750383 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 10109388042 ps |
CPU time | 86.56 seconds |
Started | May 23 12:34:00 PM PDT 24 |
Finished | May 23 12:35:29 PM PDT 24 |
Peak memory | 602512 kb |
Host | smart-54b3715c-9dcf-49f0-99e4-8310cc772489 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104750383 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.i2c_target_fifo_reset_tx.1104750383 |
Directory | /workspace/16.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/16.i2c_target_hrst.1945671406 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 1001098006 ps |
CPU time | 2.17 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-a8e8a482-84aa-4024-9338-75e4f07b0624 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945671406 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.1945671406 |
Directory | /workspace/16.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/16.i2c_target_intr_smoke.3438475817 |
Short name | T1221 |
Test name | |
Test status | |
Simulation time | 1772749221 ps |
CPU time | 4.6 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:10 PM PDT 24 |
Peak memory | 207156 kb |
Host | smart-b8ec46dd-4519-45ce-b170-0ababad882b8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438475817 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.i2c_target_intr_smoke.3438475817 |
Directory | /workspace/16.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/16.i2c_target_intr_stress_wr.578081025 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 3512851417 ps |
CPU time | 10.63 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 547964 kb |
Host | smart-5adcbf1c-e6e8-4609-9152-b580613fd797 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578081025 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.578081025 |
Directory | /workspace/16.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/16.i2c_target_smoke.1353055110 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 2062439896 ps |
CPU time | 6.53 seconds |
Started | May 23 12:33:59 PM PDT 24 |
Finished | May 23 12:34:09 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-bc4e1d32-3b7f-432c-9413-014277bf65d9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353055110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta rget_smoke.1353055110 |
Directory | /workspace/16.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/16.i2c_target_stress_rd.1912305258 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 7386501563 ps |
CPU time | 31.73 seconds |
Started | May 23 12:34:03 PM PDT 24 |
Finished | May 23 12:34:37 PM PDT 24 |
Peak memory | 234836 kb |
Host | smart-fdcc3adf-e70c-400f-819b-8c169a67888b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912305258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2 c_target_stress_rd.1912305258 |
Directory | /workspace/16.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/16.i2c_target_stress_wr.1032639287 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 32771694038 ps |
CPU time | 118.71 seconds |
Started | May 23 12:34:02 PM PDT 24 |
Finished | May 23 12:36:03 PM PDT 24 |
Peak memory | 1789980 kb |
Host | smart-49a5bce5-b20d-48ae-a9b3-72224d5e6cab |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032639287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2 c_target_stress_wr.1032639287 |
Directory | /workspace/16.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/16.i2c_target_stretch.1593410400 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 5839080151 ps |
CPU time | 158.9 seconds |
Started | May 23 12:34:01 PM PDT 24 |
Finished | May 23 12:36:43 PM PDT 24 |
Peak memory | 1520200 kb |
Host | smart-c29c5930-cf32-4423-a727-5a3a8af6646d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593410400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ target_stretch.1593410400 |
Directory | /workspace/16.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/16.i2c_target_timeout.3437539882 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 4437702080 ps |
CPU time | 7.32 seconds |
Started | May 23 12:33:58 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 219304 kb |
Host | smart-fb89aceb-c92d-413b-9472-9c8364871628 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437539882 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.i2c_target_timeout.3437539882 |
Directory | /workspace/16.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/17.i2c_alert_test.2701929830 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 22811834 ps |
CPU time | 0.59 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:13 PM PDT 24 |
Peak memory | 204460 kb |
Host | smart-0b7970e0-e483-4820-99c4-f0aa72aea690 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701929830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2701929830 |
Directory | /workspace/17.i2c_alert_test/latest |
Test location | /workspace/coverage/default/17.i2c_host_error_intr.3244564581 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 5068530269 ps |
CPU time | 8.74 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:34:21 PM PDT 24 |
Peak memory | 236324 kb |
Host | smart-b08f6137-dcf5-4e43-b85f-192a6a8d5227 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244564581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3244564581 |
Directory | /workspace/17.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.318560328 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 356131233 ps |
CPU time | 7.05 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:20 PM PDT 24 |
Peak memory | 275564 kb |
Host | smart-0a31c3fa-2076-4922-941b-2ce2cef3b3cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318560328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt y.318560328 |
Directory | /workspace/17.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_full.2766408438 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 2870871578 ps |
CPU time | 100.08 seconds |
Started | May 23 12:34:09 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 910964 kb |
Host | smart-3f120fe7-2dcf-4ad6-8cc4-04dbbeb99e88 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766408438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2766408438 |
Directory | /workspace/17.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_overflow.959533040 |
Short name | T1260 |
Test name | |
Test status | |
Simulation time | 2476609044 ps |
CPU time | 78.65 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:33 PM PDT 24 |
Peak memory | 796796 kb |
Host | smart-58caddac-bcdc-48af-a7b2-acf55787f26e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959533040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.959533040 |
Directory | /workspace/17.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.402844475 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 315862533 ps |
CPU time | 0.9 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 204588 kb |
Host | smart-e2e78ce0-0b64-462e-bf93-95672f5edcd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402844475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm t.402844475 |
Directory | /workspace/17.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2972567120 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 183744772 ps |
CPU time | 4.45 seconds |
Started | May 23 12:34:09 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 238232 kb |
Host | smart-38c0dad0-b21e-4db2-8519-074c21c320e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972567120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx .2972567120 |
Directory | /workspace/17.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/17.i2c_host_fifo_watermark.372108784 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 17138908328 ps |
CPU time | 103.65 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:35:56 PM PDT 24 |
Peak memory | 1195048 kb |
Host | smart-10dd18e4-18ce-4069-92a6-46fceb6fefce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372108784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.372108784 |
Directory | /workspace/17.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/17.i2c_host_may_nack.593668463 |
Short name | T1325 |
Test name | |
Test status | |
Simulation time | 1487573821 ps |
CPU time | 10.13 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-7ca7b0d5-1ef3-4c4d-b788-5dc3ecbd3bc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593668463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.593668463 |
Directory | /workspace/17.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/17.i2c_host_mode_toggle.532501073 |
Short name | T1313 |
Test name | |
Test status | |
Simulation time | 9786412887 ps |
CPU time | 83.88 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 413448 kb |
Host | smart-7233572b-411e-4c8e-8878-0eac0701b03b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532501073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.532501073 |
Directory | /workspace/17.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/17.i2c_host_override.710917789 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 19024161 ps |
CPU time | 0.63 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:14 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-5c59e63c-2e82-4362-b427-e51ad43c2e29 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710917789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.710917789 |
Directory | /workspace/17.i2c_host_override/latest |
Test location | /workspace/coverage/default/17.i2c_host_perf.288825814 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 25618258621 ps |
CPU time | 296.9 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:39:10 PM PDT 24 |
Peak memory | 259392 kb |
Host | smart-4f9d9de2-e8f1-4c1b-995e-10a6b503ab6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288825814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.288825814 |
Directory | /workspace/17.i2c_host_perf/latest |
Test location | /workspace/coverage/default/17.i2c_host_smoke.3431527903 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 7723530018 ps |
CPU time | 82.17 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 294416 kb |
Host | smart-48866a63-e957-40c7-aeb6-125dc77955c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431527903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3431527903 |
Directory | /workspace/17.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/17.i2c_host_stress_all.1853268946 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 14310108907 ps |
CPU time | 1884.77 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 01:05:39 PM PDT 24 |
Peak memory | 3082360 kb |
Host | smart-3c3c5d4a-c6c0-4597-b941-27d425475f47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853268946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1853268946 |
Directory | /workspace/17.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/17.i2c_host_stretch_timeout.4261256719 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 2229949914 ps |
CPU time | 26.6 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:34:42 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-49538c47-982b-4224-b368-32dc0158d4ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261256719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.4261256719 |
Directory | /workspace/17.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/17.i2c_target_bad_addr.745883130 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 576534474 ps |
CPU time | 3.32 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:34:18 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-a134559b-a44f-4837-b6d4-4de9ff229764 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745883130 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.745883130 |
Directory | /workspace/17.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1437332124 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 10106013638 ps |
CPU time | 71.94 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:26 PM PDT 24 |
Peak memory | 432332 kb |
Host | smart-4b660f8e-9835-4612-8c97-4a98f35ca75c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437332124 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.1437332124 |
Directory | /workspace/17.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/17.i2c_target_fifo_reset_tx.391867903 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 10095181073 ps |
CPU time | 73.58 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:28 PM PDT 24 |
Peak memory | 537584 kb |
Host | smart-436082a3-162b-4d52-a830-b3caf10c4a28 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391867903 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.i2c_target_fifo_reset_tx.391867903 |
Directory | /workspace/17.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/17.i2c_target_hrst.3577362680 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 1714807483 ps |
CPU time | 2.72 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:34:15 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-5f266191-4d50-4c07-83d7-f8ac7de42394 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577362680 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.3577362680 |
Directory | /workspace/17.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/17.i2c_target_intr_smoke.2261276377 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1740411238 ps |
CPU time | 5.4 seconds |
Started | May 23 12:34:08 PM PDT 24 |
Finished | May 23 12:34:15 PM PDT 24 |
Peak memory | 207204 kb |
Host | smart-04851d8e-3507-43cd-8769-ab1108b20931 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261276377 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 17.i2c_target_intr_smoke.2261276377 |
Directory | /workspace/17.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/17.i2c_target_intr_stress_wr.1109659216 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 18784785019 ps |
CPU time | 46.51 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 779460 kb |
Host | smart-f96c5857-c591-48cf-b647-759606dbde13 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109659216 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1109659216 |
Directory | /workspace/17.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/17.i2c_target_smoke.2183687870 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 4116690919 ps |
CPU time | 42.71 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:57 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-3f30bcbc-a7ba-4124-960a-58b4194c0666 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183687870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta rget_smoke.2183687870 |
Directory | /workspace/17.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/17.i2c_target_stress_rd.2903125676 |
Short name | T1310 |
Test name | |
Test status | |
Simulation time | 2277724088 ps |
CPU time | 24.46 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:38 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-520a1006-3913-432a-bb84-00ad2e7ffab7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903125676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2 c_target_stress_rd.2903125676 |
Directory | /workspace/17.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/17.i2c_target_stress_wr.3339358789 |
Short name | T1152 |
Test name | |
Test status | |
Simulation time | 20328078316 ps |
CPU time | 11.29 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:24 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-bb49d4c2-c33d-4946-9a2d-e7ba72705d50 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339358789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2 c_target_stress_wr.3339358789 |
Directory | /workspace/17.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/17.i2c_target_stretch.1448160898 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 9485658776 ps |
CPU time | 270.43 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:38:46 PM PDT 24 |
Peak memory | 2036712 kb |
Host | smart-6a912c50-6609-429b-be0b-1904f0912a61 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448160898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ target_stretch.1448160898 |
Directory | /workspace/17.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/17.i2c_target_timeout.4092691083 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1432839828 ps |
CPU time | 6.85 seconds |
Started | May 23 12:34:08 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 220716 kb |
Host | smart-7e5d7c3e-24d2-4f7e-9ff2-460703bf8049 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092691083 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.i2c_target_timeout.4092691083 |
Directory | /workspace/17.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/18.i2c_alert_test.3412853297 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 15891400 ps |
CPU time | 0.63 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:33 PM PDT 24 |
Peak memory | 204468 kb |
Host | smart-b8297fb1-ead0-47c3-a676-89de068da490 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412853297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3412853297 |
Directory | /workspace/18.i2c_alert_test/latest |
Test location | /workspace/coverage/default/18.i2c_host_error_intr.122875417 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 331901421 ps |
CPU time | 2.23 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:34:18 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-4b1fac76-65b7-4c9f-9dac-aa0985752c97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122875417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.122875417 |
Directory | /workspace/18.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2324045571 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 1427926206 ps |
CPU time | 8.46 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:22 PM PDT 24 |
Peak memory | 284700 kb |
Host | smart-64cecd5e-2505-4cb1-b09f-eb71b19468b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324045571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp ty.2324045571 |
Directory | /workspace/18.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_full.2183080006 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 4603189897 ps |
CPU time | 73.61 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:28 PM PDT 24 |
Peak memory | 757404 kb |
Host | smart-657a2186-06f3-47a4-b54f-761ce488ed36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183080006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2183080006 |
Directory | /workspace/18.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_overflow.2762805979 |
Short name | T1199 |
Test name | |
Test status | |
Simulation time | 4361682165 ps |
CPU time | 64.18 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:35:20 PM PDT 24 |
Peak memory | 738516 kb |
Host | smart-8ef22cff-af98-4312-877a-afb58e9f65e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762805979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2762805979 |
Directory | /workspace/18.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4027778035 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 163944130 ps |
CPU time | 1.21 seconds |
Started | May 23 12:34:15 PM PDT 24 |
Finished | May 23 12:34:18 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-1ca6a32e-1f2b-4cce-9c3e-1e919bbb827d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027778035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f mt.4027778035 |
Directory | /workspace/18.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_reset_rx.4096187017 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 383589740 ps |
CPU time | 4.15 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:34:19 PM PDT 24 |
Peak memory | 204772 kb |
Host | smart-5216fd97-fee6-46b9-8feb-53018314e8e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096187017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx .4096187017 |
Directory | /workspace/18.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/18.i2c_host_fifo_watermark.2023052579 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 16555312077 ps |
CPU time | 294.51 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:39:07 PM PDT 24 |
Peak memory | 1192540 kb |
Host | smart-2335c4df-c160-414e-937d-47616050b1ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023052579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2023052579 |
Directory | /workspace/18.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/18.i2c_host_may_nack.3876268267 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 137214013 ps |
CPU time | 6.14 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:40 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-03ab7751-c35a-48ef-85ed-5d20ebbf55ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876268267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3876268267 |
Directory | /workspace/18.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/18.i2c_host_mode_toggle.2541205907 |
Short name | T1164 |
Test name | |
Test status | |
Simulation time | 1469147856 ps |
CPU time | 25.46 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 267592 kb |
Host | smart-d4255c03-2efc-4363-af3b-aa29ce6d7285 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541205907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2541205907 |
Directory | /workspace/18.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/18.i2c_host_override.3569955569 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 27120131 ps |
CPU time | 0.66 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:14 PM PDT 24 |
Peak memory | 204456 kb |
Host | smart-b118c8f5-fc14-4d0b-9890-e6fc8f36d4e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569955569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3569955569 |
Directory | /workspace/18.i2c_host_override/latest |
Test location | /workspace/coverage/default/18.i2c_host_perf.1517536875 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 26612933804 ps |
CPU time | 275.71 seconds |
Started | May 23 12:34:15 PM PDT 24 |
Finished | May 23 12:38:53 PM PDT 24 |
Peak memory | 229716 kb |
Host | smart-f46f83ed-de01-408a-915c-0f859a47f8a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517536875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1517536875 |
Directory | /workspace/18.i2c_host_perf/latest |
Test location | /workspace/coverage/default/18.i2c_host_smoke.1774697200 |
Short name | T1154 |
Test name | |
Test status | |
Simulation time | 1496877942 ps |
CPU time | 65.5 seconds |
Started | May 23 12:34:10 PM PDT 24 |
Finished | May 23 12:35:17 PM PDT 24 |
Peak memory | 331024 kb |
Host | smart-975ac842-02c6-4b74-ad98-25496ff05717 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774697200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1774697200 |
Directory | /workspace/18.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/18.i2c_host_stretch_timeout.3795861453 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 8457619079 ps |
CPU time | 11.65 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:25 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-848413a9-4984-4a51-bfbe-ac10a33e3243 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795861453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3795861453 |
Directory | /workspace/18.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/18.i2c_target_bad_addr.1120738375 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 746819620 ps |
CPU time | 3.82 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-66af59b4-dcfd-4df3-8fd7-90228f23c8a8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120738375 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1120738375 |
Directory | /workspace/18.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3829448853 |
Short name | T1073 |
Test name | |
Test status | |
Simulation time | 10112285756 ps |
CPU time | 72.96 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:44 PM PDT 24 |
Peak memory | 493964 kb |
Host | smart-3de5b123-e81e-42fd-9868-e0095106a5ed |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829448853 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.3829448853 |
Directory | /workspace/18.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/18.i2c_target_fifo_reset_tx.350775921 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 10053959968 ps |
CPU time | 78.53 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:35:53 PM PDT 24 |
Peak memory | 589756 kb |
Host | smart-f2325927-23ee-4b2f-add0-b18009943e18 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350775921 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.i2c_target_fifo_reset_tx.350775921 |
Directory | /workspace/18.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/18.i2c_target_hrst.1297995363 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 400857634 ps |
CPU time | 2.84 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-93caf519-df50-4223-8973-2f10e3ef27dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297995363 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.1297995363 |
Directory | /workspace/18.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/18.i2c_target_intr_smoke.3208157704 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 2397632451 ps |
CPU time | 5.94 seconds |
Started | May 23 12:34:13 PM PDT 24 |
Finished | May 23 12:34:22 PM PDT 24 |
Peak memory | 214152 kb |
Host | smart-80ac76e6-bd08-4e6a-844b-39d010569393 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208157704 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.i2c_target_intr_smoke.3208157704 |
Directory | /workspace/18.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/18.i2c_target_intr_stress_wr.1526918594 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 8861555110 ps |
CPU time | 3.21 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:34:18 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-671537d0-2672-4ae2-8061-2831a500003b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526918594 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1526918594 |
Directory | /workspace/18.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/18.i2c_target_smoke.2806638819 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 936358128 ps |
CPU time | 27.37 seconds |
Started | May 23 12:34:14 PM PDT 24 |
Finished | May 23 12:34:44 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-ab22e1df-7f0b-45db-b568-1b92486d4e43 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806638819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta rget_smoke.2806638819 |
Directory | /workspace/18.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/18.i2c_target_stress_rd.252291093 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 3184790720 ps |
CPU time | 15.83 seconds |
Started | May 23 12:34:11 PM PDT 24 |
Finished | May 23 12:34:29 PM PDT 24 |
Peak memory | 212660 kb |
Host | smart-4c67993d-5458-4d15-8054-fb4448985a3d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252291093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c _target_stress_rd.252291093 |
Directory | /workspace/18.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/18.i2c_target_stress_wr.722896888 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 53771253788 ps |
CPU time | 81.06 seconds |
Started | May 23 12:34:12 PM PDT 24 |
Finished | May 23 12:35:36 PM PDT 24 |
Peak memory | 1262956 kb |
Host | smart-fc2789df-9043-42fa-b6f1-a9bd56eb240c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722896888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c _target_stress_wr.722896888 |
Directory | /workspace/18.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/18.i2c_target_stretch.170973472 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 27982098451 ps |
CPU time | 243.66 seconds |
Started | May 23 12:34:14 PM PDT 24 |
Finished | May 23 12:38:20 PM PDT 24 |
Peak memory | 1687576 kb |
Host | smart-b25d0816-96ac-4fcf-a81c-8af1ea5b6fd4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170973472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t arget_stretch.170973472 |
Directory | /workspace/18.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/18.i2c_target_timeout.1293554148 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1584158682 ps |
CPU time | 7.89 seconds |
Started | May 23 12:34:09 PM PDT 24 |
Finished | May 23 12:34:19 PM PDT 24 |
Peak memory | 221092 kb |
Host | smart-89adbe14-f7a6-4b8d-952a-45093842ddaf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293554148 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.i2c_target_timeout.1293554148 |
Directory | /workspace/18.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/19.i2c_alert_test.942423722 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 17180697 ps |
CPU time | 0.65 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:34:32 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-26637d1f-1d5d-4237-9adc-ad2cb87f0d62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942423722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.942423722 |
Directory | /workspace/19.i2c_alert_test/latest |
Test location | /workspace/coverage/default/19.i2c_host_error_intr.3645251523 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 933677652 ps |
CPU time | 11.39 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:34:41 PM PDT 24 |
Peak memory | 249772 kb |
Host | smart-11b4701f-7242-4a6a-b66e-8b9e8ed21fe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645251523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3645251523 |
Directory | /workspace/19.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2586935606 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 1857123626 ps |
CPU time | 3.13 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:34:38 PM PDT 24 |
Peak memory | 233832 kb |
Host | smart-936ee707-b47d-401a-935e-779e6ceefabd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586935606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp ty.2586935606 |
Directory | /workspace/19.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_full.1426891685 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 2759490147 ps |
CPU time | 62.62 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 628360 kb |
Host | smart-752b59be-1d9c-4d28-9941-cb06659c0e4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426891685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1426891685 |
Directory | /workspace/19.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_overflow.3476906060 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 4990648422 ps |
CPU time | 83.47 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 501816 kb |
Host | smart-545835b7-5738-47ca-80a5-38191f5ae448 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476906060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3476906060 |
Directory | /workspace/19.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3748391363 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 99245082 ps |
CPU time | 0.94 seconds |
Started | May 23 12:34:34 PM PDT 24 |
Finished | May 23 12:34:38 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-de46fc3b-b0b4-4c14-86bb-8594da696674 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748391363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f mt.3748391363 |
Directory | /workspace/19.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_reset_rx.436629088 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 891032623 ps |
CPU time | 13.53 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:47 PM PDT 24 |
Peak memory | 252184 kb |
Host | smart-08b4df89-5fe2-4ca2-a53b-3b6848df9958 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436629088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx. 436629088 |
Directory | /workspace/19.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/19.i2c_host_fifo_watermark.487170535 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 46729808635 ps |
CPU time | 157.18 seconds |
Started | May 23 12:34:32 PM PDT 24 |
Finished | May 23 12:37:13 PM PDT 24 |
Peak memory | 1367644 kb |
Host | smart-8df1804a-1651-4cc5-b4cc-7148a4adc7b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487170535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.487170535 |
Directory | /workspace/19.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/19.i2c_host_may_nack.2389830033 |
Short name | T1169 |
Test name | |
Test status | |
Simulation time | 842648408 ps |
CPU time | 3.41 seconds |
Started | May 23 12:34:27 PM PDT 24 |
Finished | May 23 12:34:32 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-4f1a8d01-6db0-4c07-8f71-facbc0d8ab7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389830033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2389830033 |
Directory | /workspace/19.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/19.i2c_host_mode_toggle.842902521 |
Short name | T1287 |
Test name | |
Test status | |
Simulation time | 1043648315 ps |
CPU time | 20.86 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 286052 kb |
Host | smart-69d1236c-20fe-42a1-9c8a-5d4085917a63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842902521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.842902521 |
Directory | /workspace/19.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/19.i2c_host_override.822230020 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 51999764 ps |
CPU time | 0.63 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:34:32 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-b49f70fd-774f-4b1b-9cb2-df24c9027f68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822230020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.822230020 |
Directory | /workspace/19.i2c_host_override/latest |
Test location | /workspace/coverage/default/19.i2c_host_perf.2255964695 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 12436898431 ps |
CPU time | 44.3 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:14 PM PDT 24 |
Peak memory | 461360 kb |
Host | smart-31847399-24d3-46fc-9a3a-430aeb42236e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255964695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2255964695 |
Directory | /workspace/19.i2c_host_perf/latest |
Test location | /workspace/coverage/default/19.i2c_host_smoke.2001055349 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 4429974486 ps |
CPU time | 29.3 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:00 PM PDT 24 |
Peak memory | 383808 kb |
Host | smart-3b60fbc3-7383-4b3f-b3cd-4b1e38a8160d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001055349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2001055349 |
Directory | /workspace/19.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/19.i2c_host_stretch_timeout.1717798000 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 606236206 ps |
CPU time | 10.71 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:43 PM PDT 24 |
Peak memory | 213000 kb |
Host | smart-414bc0fc-68bb-4b6b-9f94-2a101e9bf934 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717798000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1717798000 |
Directory | /workspace/19.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/19.i2c_target_bad_addr.2478229485 |
Short name | T1259 |
Test name | |
Test status | |
Simulation time | 2238385218 ps |
CPU time | 5.17 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:39 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-920aa26b-0ec6-4134-8d3c-9f71a700fa01 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478229485 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2478229485 |
Directory | /workspace/19.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2527227137 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 10122157413 ps |
CPU time | 13.01 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:34:47 PM PDT 24 |
Peak memory | 279052 kb |
Host | smart-68b0e26a-e6bf-4e2b-8ab4-6c9300daf59f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527227137 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.2527227137 |
Directory | /workspace/19.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1658666242 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 10127916511 ps |
CPU time | 76.82 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 560976 kb |
Host | smart-b275cd51-725d-4b76-a86d-de8f73111ea4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658666242 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.i2c_target_fifo_reset_tx.1658666242 |
Directory | /workspace/19.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/19.i2c_target_hrst.4272662745 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 533177775 ps |
CPU time | 2.04 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-16e99792-1c8c-4207-9aaa-15b445e2f7cf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272662745 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.4272662745 |
Directory | /workspace/19.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/19.i2c_target_intr_smoke.4174699413 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 2720095844 ps |
CPU time | 6.66 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:40 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-2e91b696-a56a-4364-99b1-8d0bf818b805 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174699413 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.i2c_target_intr_smoke.4174699413 |
Directory | /workspace/19.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/19.i2c_target_intr_stress_wr.1571965088 |
Short name | T1104 |
Test name | |
Test status | |
Simulation time | 21311923888 ps |
CPU time | 512.74 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:43:04 PM PDT 24 |
Peak memory | 5028268 kb |
Host | smart-2065bf8e-5dbd-43b7-883c-1ccfef8fff9e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571965088 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1571965088 |
Directory | /workspace/19.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/19.i2c_target_smoke.408284450 |
Short name | T1251 |
Test name | |
Test status | |
Simulation time | 2066002936 ps |
CPU time | 17.53 seconds |
Started | May 23 12:34:27 PM PDT 24 |
Finished | May 23 12:34:46 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-2716ec79-82cd-48e6-afc1-32acfaa71025 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408284450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar get_smoke.408284450 |
Directory | /workspace/19.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/19.i2c_target_stress_rd.2437017835 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 3920728000 ps |
CPU time | 8.17 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:40 PM PDT 24 |
Peak memory | 209776 kb |
Host | smart-0f8a6bb0-358b-4d48-bc4c-55e0dec62569 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437017835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2 c_target_stress_rd.2437017835 |
Directory | /workspace/19.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/19.i2c_target_stress_wr.783001072 |
Short name | T1061 |
Test name | |
Test status | |
Simulation time | 7434311264 ps |
CPU time | 13.68 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-bb4ac341-9bbf-46dd-8b1b-3285b9b0e2b7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783001072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c _target_stress_wr.783001072 |
Directory | /workspace/19.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/19.i2c_target_timeout.1400050151 |
Short name | T1231 |
Test name | |
Test status | |
Simulation time | 4601201846 ps |
CPU time | 6.15 seconds |
Started | May 23 12:34:32 PM PDT 24 |
Finished | May 23 12:34:42 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-f4f9e2f6-0b50-4e59-af07-6d62fc58eb54 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400050151 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.i2c_target_timeout.1400050151 |
Directory | /workspace/19.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/2.i2c_alert_test.601161804 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 17582313 ps |
CPU time | 0.64 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-f22cf455-b0a0-4c37-8706-3a4ccde2971a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601161804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.601161804 |
Directory | /workspace/2.i2c_alert_test/latest |
Test location | /workspace/coverage/default/2.i2c_host_error_intr.2289726724 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 208363920 ps |
CPU time | 1.62 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:32:42 PM PDT 24 |
Peak memory | 213088 kb |
Host | smart-f08a91b6-3f59-4fdc-b76c-75de44c5c9ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289726724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2289726724 |
Directory | /workspace/2.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3868994579 |
Short name | T1193 |
Test name | |
Test status | |
Simulation time | 2093038354 ps |
CPU time | 10.94 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 315856 kb |
Host | smart-d0d98659-33d7-4956-8837-96c72a291591 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868994579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt y.3868994579 |
Directory | /workspace/2.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_full.399545371 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 4075761139 ps |
CPU time | 71.43 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:33:46 PM PDT 24 |
Peak memory | 703880 kb |
Host | smart-d45e78e6-dc83-469c-82a9-0ef9f65d238c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399545371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.399545371 |
Directory | /workspace/2.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_overflow.3532716633 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 2142145851 ps |
CPU time | 62.09 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:33:42 PM PDT 24 |
Peak memory | 590648 kb |
Host | smart-8756bbca-9444-4850-8834-79fe699439b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532716633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3532716633 |
Directory | /workspace/2.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2342430363 |
Short name | T1100 |
Test name | |
Test status | |
Simulation time | 1374851448 ps |
CPU time | 0.99 seconds |
Started | May 23 12:32:39 PM PDT 24 |
Finished | May 23 12:32:42 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-c1138094-d8fc-41c1-842a-045ccb0a94ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342430363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm t.2342430363 |
Directory | /workspace/2.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3187265969 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 144705541 ps |
CPU time | 7.48 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 12:32:47 PM PDT 24 |
Peak memory | 226800 kb |
Host | smart-4f717d2c-8a50-4f04-a47d-6c3f4dd49ff2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187265969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx. 3187265969 |
Directory | /workspace/2.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/2.i2c_host_fifo_watermark.697605078 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2988568410 ps |
CPU time | 78.6 seconds |
Started | May 23 12:32:40 PM PDT 24 |
Finished | May 23 12:34:00 PM PDT 24 |
Peak memory | 918304 kb |
Host | smart-0f5b91d9-5ad9-4ca5-80cf-c37256a8e966 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697605078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.697605078 |
Directory | /workspace/2.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/2.i2c_host_may_nack.2101917661 |
Short name | T1280 |
Test name | |
Test status | |
Simulation time | 454258728 ps |
CPU time | 6.18 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:54 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-b6324e06-a83c-4fa0-a6ba-b54bb56d43a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101917661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2101917661 |
Directory | /workspace/2.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/2.i2c_host_mode_toggle.3047401994 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 8130033292 ps |
CPU time | 96.48 seconds |
Started | May 23 12:32:45 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 338356 kb |
Host | smart-231a3f1e-4b7c-4540-b99f-f9e25ecb4019 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047401994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3047401994 |
Directory | /workspace/2.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/2.i2c_host_override.2222695502 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 17307701 ps |
CPU time | 0.63 seconds |
Started | May 23 12:32:38 PM PDT 24 |
Finished | May 23 12:32:40 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-09778bdb-6ab0-4fe1-9af9-fa57357b39b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222695502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2222695502 |
Directory | /workspace/2.i2c_host_override/latest |
Test location | /workspace/coverage/default/2.i2c_host_perf.579596084 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 2384520959 ps |
CPU time | 22.29 seconds |
Started | May 23 12:32:37 PM PDT 24 |
Finished | May 23 12:33:01 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-4a8066d8-4841-4863-bba6-5ed7361222f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579596084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.579596084 |
Directory | /workspace/2.i2c_host_perf/latest |
Test location | /workspace/coverage/default/2.i2c_host_smoke.1226702031 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 6137541203 ps |
CPU time | 27.52 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:04 PM PDT 24 |
Peak memory | 307348 kb |
Host | smart-783a85eb-5abb-40cd-bb5e-1e33ef4e5c41 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226702031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1226702031 |
Directory | /workspace/2.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/2.i2c_host_stress_all.4221502772 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 124204027191 ps |
CPU time | 306.3 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:37:45 PM PDT 24 |
Peak memory | 1761232 kb |
Host | smart-83912d9f-b552-4dbc-a838-b634e1e37c5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221502772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.4221502772 |
Directory | /workspace/2.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/2.i2c_host_stretch_timeout.3339251491 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 3405215187 ps |
CPU time | 13.93 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 221204 kb |
Host | smart-47c99ebe-5fa0-4e6d-aab9-90364e062152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339251491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3339251491 |
Directory | /workspace/2.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/2.i2c_sec_cm.1029543989 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 434159356 ps |
CPU time | 0.93 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:50 PM PDT 24 |
Peak memory | 221968 kb |
Host | smart-5e21f673-517e-49d0-959c-c58adeee954f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029543989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1029543989 |
Directory | /workspace/2.i2c_sec_cm/latest |
Test location | /workspace/coverage/default/2.i2c_target_bad_addr.620115325 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 986087257 ps |
CPU time | 5.7 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:54 PM PDT 24 |
Peak memory | 221228 kb |
Host | smart-366a8e31-a23c-430f-bd6a-21434bd363c3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620115325 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.620115325 |
Directory | /workspace/2.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/2.i2c_target_fifo_reset_acq.4072705592 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 10213893396 ps |
CPU time | 11.27 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 261436 kb |
Host | smart-ead7b32d-bf7a-44a7-b3d5-171d74a9009c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072705592 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.4072705592 |
Directory | /workspace/2.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3120543623 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 10061525010 ps |
CPU time | 68.16 seconds |
Started | May 23 12:32:45 PM PDT 24 |
Finished | May 23 12:33:54 PM PDT 24 |
Peak memory | 463380 kb |
Host | smart-1d8f563c-67b0-4172-b7da-b288e4f384a3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120543623 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.i2c_target_fifo_reset_tx.3120543623 |
Directory | /workspace/2.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/2.i2c_target_hrst.2415230335 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 352406179 ps |
CPU time | 1.45 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-ab93a1a1-5f4e-410c-983e-3f3ad18bf320 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415230335 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_hrst.2415230335 |
Directory | /workspace/2.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/2.i2c_target_intr_smoke.404382795 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 3953357693 ps |
CPU time | 6.07 seconds |
Started | May 23 12:32:35 PM PDT 24 |
Finished | May 23 12:32:44 PM PDT 24 |
Peak memory | 221052 kb |
Host | smart-c699a6ed-1e00-4bdb-8bf6-c5674540cc0e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404382795 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.404382795 |
Directory | /workspace/2.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/2.i2c_target_intr_stress_wr.1154030566 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 1937220657 ps |
CPU time | 14.06 seconds |
Started | May 23 12:32:36 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 634064 kb |
Host | smart-b4815198-646e-45ac-8890-762551c4e4d1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154030566 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1154030566 |
Directory | /workspace/2.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/2.i2c_target_smoke.2409932215 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 5301782888 ps |
CPU time | 45.44 seconds |
Started | May 23 12:32:34 PM PDT 24 |
Finished | May 23 12:33:22 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-8e78fcc1-c597-4cd9-afe8-cf0ca77fd346 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409932215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar get_smoke.2409932215 |
Directory | /workspace/2.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/2.i2c_target_stress_rd.2124287775 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 1897221303 ps |
CPU time | 29.73 seconds |
Started | May 23 12:32:31 PM PDT 24 |
Finished | May 23 12:33:02 PM PDT 24 |
Peak memory | 225024 kb |
Host | smart-e48acef2-cdb1-4aa5-b0f6-69ad24a4e2ba |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124287775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c _target_stress_rd.2124287775 |
Directory | /workspace/2.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/2.i2c_target_stress_wr.3194506437 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 22107554990 ps |
CPU time | 4.06 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:39 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-41ba407b-0372-42c9-96e1-f348bc1196cd |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194506437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c _target_stress_wr.3194506437 |
Directory | /workspace/2.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/2.i2c_target_stretch.3243470950 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 18580217565 ps |
CPU time | 287.82 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 1074332 kb |
Host | smart-7558b375-002c-4b42-8e75-dfbad0faa60a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243470950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t arget_stretch.3243470950 |
Directory | /workspace/2.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/2.i2c_target_timeout.2132598726 |
Short name | T1051 |
Test name | |
Test status | |
Simulation time | 12151746318 ps |
CPU time | 7.4 seconds |
Started | May 23 12:32:33 PM PDT 24 |
Finished | May 23 12:32:42 PM PDT 24 |
Peak memory | 221204 kb |
Host | smart-8297cc09-9877-4d7b-80ed-4bbf9dc38f34 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132598726 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.i2c_target_timeout.2132598726 |
Directory | /workspace/2.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/20.i2c_alert_test.1413556061 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 103400315 ps |
CPU time | 0.61 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:34:45 PM PDT 24 |
Peak memory | 204500 kb |
Host | smart-8434318c-4c97-4a59-9c38-73c1b12b89e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413556061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1413556061 |
Directory | /workspace/20.i2c_alert_test/latest |
Test location | /workspace/coverage/default/20.i2c_host_error_intr.3577604987 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 233863059 ps |
CPU time | 1.23 seconds |
Started | May 23 12:34:32 PM PDT 24 |
Finished | May 23 12:34:37 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-347b5564-63b5-4fab-aa3b-897b7d4ba937 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577604987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3577604987 |
Directory | /workspace/20.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1302330006 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 526404173 ps |
CPU time | 6.02 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:34:41 PM PDT 24 |
Peak memory | 259848 kb |
Host | smart-e7239f83-b4ac-4054-9843-1b97b9be1abd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302330006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp ty.1302330006 |
Directory | /workspace/20.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_full.3926541851 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 10226835713 ps |
CPU time | 68.21 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:35:41 PM PDT 24 |
Peak memory | 765116 kb |
Host | smart-1e62501a-1e32-47a6-861b-b1579462befd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926541851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3926541851 |
Directory | /workspace/20.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_overflow.1208959471 |
Short name | T1305 |
Test name | |
Test status | |
Simulation time | 2308494399 ps |
CPU time | 66.04 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 754800 kb |
Host | smart-5a978166-402e-49fb-a7e3-8cbcc0413a06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208959471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1208959471 |
Directory | /workspace/20.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1715838956 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 118715030 ps |
CPU time | 1.02 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:35 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-f8d3e1ba-21fa-4886-bde6-97645d0a624b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715838956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f mt.1715838956 |
Directory | /workspace/20.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3015819911 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 722509889 ps |
CPU time | 4.87 seconds |
Started | May 23 12:34:27 PM PDT 24 |
Finished | May 23 12:34:34 PM PDT 24 |
Peak memory | 240412 kb |
Host | smart-a2565059-c1ac-47b2-b260-8d07ac99b841 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015819911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx .3015819911 |
Directory | /workspace/20.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/20.i2c_host_fifo_watermark.3150141596 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 7754995065 ps |
CPU time | 90.05 seconds |
Started | May 23 12:34:33 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 1131984 kb |
Host | smart-baca21c9-a86b-47a6-8acb-d46824044e63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150141596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3150141596 |
Directory | /workspace/20.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/20.i2c_host_may_nack.1168310038 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 964585064 ps |
CPU time | 18.7 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:35:03 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-6880dd52-a1c9-4d49-9ee2-cc5045861292 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168310038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1168310038 |
Directory | /workspace/20.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/20.i2c_host_mode_toggle.507023385 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 6599306595 ps |
CPU time | 25.4 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:35:09 PM PDT 24 |
Peak memory | 363428 kb |
Host | smart-83c9d743-8f70-4a33-968f-06a4d85f9c8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507023385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.507023385 |
Directory | /workspace/20.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/20.i2c_host_smoke.2220839692 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 2494563500 ps |
CPU time | 60.45 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 312132 kb |
Host | smart-9f24c597-d69b-4ef7-8d7f-bcfa96b81e9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220839692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2220839692 |
Directory | /workspace/20.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/20.i2c_host_stress_all.3557897243 |
Short name | T1185 |
Test name | |
Test status | |
Simulation time | 26804755906 ps |
CPU time | 569.91 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:44:05 PM PDT 24 |
Peak memory | 1343796 kb |
Host | smart-86aa8067-748b-47cc-9c62-ef109e0adafd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557897243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3557897243 |
Directory | /workspace/20.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/20.i2c_host_stretch_timeout.2386663978 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 2221891396 ps |
CPU time | 24.9 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:34:54 PM PDT 24 |
Peak memory | 213132 kb |
Host | smart-55c355dc-3261-40bb-973b-430e416b094f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386663978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2386663978 |
Directory | /workspace/20.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/20.i2c_target_bad_addr.3416728040 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 691752786 ps |
CPU time | 3.86 seconds |
Started | May 23 12:34:40 PM PDT 24 |
Finished | May 23 12:34:46 PM PDT 24 |
Peak memory | 213152 kb |
Host | smart-ab955329-29be-4fe2-a0cd-b8235b43c09e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416728040 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3416728040 |
Directory | /workspace/20.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3120727851 |
Short name | T1321 |
Test name | |
Test status | |
Simulation time | 10125648391 ps |
CPU time | 62.55 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:35:38 PM PDT 24 |
Peak memory | 483200 kb |
Host | smart-4f587107-3fbf-4d2f-81bc-2a9f1cd5f134 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120727851 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.3120727851 |
Directory | /workspace/20.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1679436823 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 10091582407 ps |
CPU time | 32.18 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:35:05 PM PDT 24 |
Peak memory | 325256 kb |
Host | smart-697bebc0-ed61-45ba-9b8a-e2015c777a83 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679436823 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 20.i2c_target_fifo_reset_tx.1679436823 |
Directory | /workspace/20.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/20.i2c_target_hrst.1927305438 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 8296563469 ps |
CPU time | 2.64 seconds |
Started | May 23 12:34:40 PM PDT 24 |
Finished | May 23 12:34:45 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-6c2e2625-760c-49c5-b07a-eabd4b94965c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927305438 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_hrst.1927305438 |
Directory | /workspace/20.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/20.i2c_target_intr_smoke.482289060 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 380097867 ps |
CPU time | 2.62 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:34:38 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-659cc7a9-ce32-4a89-9871-ffaadbddca78 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482289060 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.482289060 |
Directory | /workspace/20.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/20.i2c_target_intr_stress_wr.1612547138 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 4827435372 ps |
CPU time | 11.5 seconds |
Started | May 23 12:34:29 PM PDT 24 |
Finished | May 23 12:34:45 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-d1b9adb0-414a-451b-9ff0-e0046ecd69be |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612547138 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1612547138 |
Directory | /workspace/20.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/20.i2c_target_smoke.1381515358 |
Short name | T1062 |
Test name | |
Test status | |
Simulation time | 1167136057 ps |
CPU time | 10.31 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:34:44 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-d7f8917e-11da-4e64-8d08-dff60e3da893 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381515358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta rget_smoke.1381515358 |
Directory | /workspace/20.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/20.i2c_target_stress_rd.2807625916 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 8756794760 ps |
CPU time | 38.29 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:35:14 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-6ecd433d-1fbe-421c-a273-a54cb425b741 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807625916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2 c_target_stress_rd.2807625916 |
Directory | /workspace/20.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/20.i2c_target_stress_wr.235402487 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 38549652798 ps |
CPU time | 493.92 seconds |
Started | May 23 12:34:31 PM PDT 24 |
Finished | May 23 12:42:49 PM PDT 24 |
Peak memory | 4470848 kb |
Host | smart-7c579edf-af42-4c0c-9bf1-5ddb517cfe31 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235402487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c _target_stress_wr.235402487 |
Directory | /workspace/20.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/20.i2c_target_stretch.3354665562 |
Short name | T1103 |
Test name | |
Test status | |
Simulation time | 15943484718 ps |
CPU time | 48.95 seconds |
Started | May 23 12:34:28 PM PDT 24 |
Finished | May 23 12:35:20 PM PDT 24 |
Peak memory | 707624 kb |
Host | smart-a0b85ec6-b4db-40e2-b0ca-1c30b2b63b24 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354665562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ target_stretch.3354665562 |
Directory | /workspace/20.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/20.i2c_target_timeout.1413483951 |
Short name | T1087 |
Test name | |
Test status | |
Simulation time | 5330117353 ps |
CPU time | 6.79 seconds |
Started | May 23 12:34:30 PM PDT 24 |
Finished | May 23 12:34:41 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-34c3d481-a3ba-4e5c-9149-6be7aa8c099e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413483951 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.i2c_target_timeout.1413483951 |
Directory | /workspace/20.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/21.i2c_alert_test.3855698470 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 29230742 ps |
CPU time | 0.61 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:34:47 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-dd8cd806-8f9e-4a18-a42e-eb0cd735bb8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855698470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3855698470 |
Directory | /workspace/21.i2c_alert_test/latest |
Test location | /workspace/coverage/default/21.i2c_host_error_intr.3403857985 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 292194711 ps |
CPU time | 5.1 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 227536 kb |
Host | smart-4a3017cd-10ef-4489-acff-e6da7d0ff9b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403857985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3403857985 |
Directory | /workspace/21.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1512659595 |
Short name | T1228 |
Test name | |
Test status | |
Simulation time | 539491327 ps |
CPU time | 14.06 seconds |
Started | May 23 12:34:39 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 258032 kb |
Host | smart-9eb2fedf-a07d-4901-bb34-41e7ea368342 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512659595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp ty.1512659595 |
Directory | /workspace/21.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_full.2453020164 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 40300587473 ps |
CPU time | 111.25 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:36:35 PM PDT 24 |
Peak memory | 908296 kb |
Host | smart-c5971200-3456-4807-9a04-1dfefb7a48d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453020164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2453020164 |
Directory | /workspace/21.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_overflow.1137780919 |
Short name | T1077 |
Test name | |
Test status | |
Simulation time | 10239528899 ps |
CPU time | 189.3 seconds |
Started | May 23 12:34:40 PM PDT 24 |
Finished | May 23 12:37:51 PM PDT 24 |
Peak memory | 773216 kb |
Host | smart-8f1fd35c-2ddb-46cd-8485-afe48937ad62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137780919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1137780919 |
Directory | /workspace/21.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.405637736 |
Short name | T1076 |
Test name | |
Test status | |
Simulation time | 98339653 ps |
CPU time | 0.91 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:34:46 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-b5c689f2-d18c-4f4f-8783-a0ac270d1631 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405637736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm t.405637736 |
Directory | /workspace/21.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2501840372 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 710631051 ps |
CPU time | 4.62 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:47 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-3ba719a9-d23d-4899-bf3d-6479884d36b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501840372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx .2501840372 |
Directory | /workspace/21.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/21.i2c_host_fifo_watermark.4190810136 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 4131394665 ps |
CPU time | 296.73 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:39:41 PM PDT 24 |
Peak memory | 1189720 kb |
Host | smart-bf81ff8b-45da-490a-8a6e-168d4db3d151 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190810136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.4190810136 |
Directory | /workspace/21.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/21.i2c_host_may_nack.3863103900 |
Short name | T1170 |
Test name | |
Test status | |
Simulation time | 1137229838 ps |
CPU time | 7.64 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:51 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-4109a75f-46a5-4b7c-8f02-9a93e1f6bf75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863103900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3863103900 |
Directory | /workspace/21.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/21.i2c_host_mode_toggle.1906228787 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2410039141 ps |
CPU time | 52.76 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 478212 kb |
Host | smart-0057a944-52ac-4ac0-a3e8-e07f9116dbee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906228787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1906228787 |
Directory | /workspace/21.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/21.i2c_host_override.2280168462 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 26740961 ps |
CPU time | 0.63 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:44 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-b85b8c05-0d97-4c6a-8833-9298fc29a75e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280168462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2280168462 |
Directory | /workspace/21.i2c_host_override/latest |
Test location | /workspace/coverage/default/21.i2c_host_perf.3161514076 |
Short name | T1317 |
Test name | |
Test status | |
Simulation time | 3186706322 ps |
CPU time | 38.58 seconds |
Started | May 23 12:34:40 PM PDT 24 |
Finished | May 23 12:35:20 PM PDT 24 |
Peak memory | 366844 kb |
Host | smart-299da14d-0150-4c4d-8add-190404fdcb24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161514076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3161514076 |
Directory | /workspace/21.i2c_host_perf/latest |
Test location | /workspace/coverage/default/21.i2c_host_smoke.1524833664 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1822727128 ps |
CPU time | 36.92 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:35:22 PM PDT 24 |
Peak memory | 386060 kb |
Host | smart-a888c0bc-21f6-42e6-aabb-458fa03f51d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524833664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1524833664 |
Directory | /workspace/21.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/21.i2c_host_stress_all.3813038360 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 16541592815 ps |
CPU time | 744.86 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:47:09 PM PDT 24 |
Peak memory | 2276436 kb |
Host | smart-b2603414-665f-4c43-9488-3aebab40c50a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813038360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3813038360 |
Directory | /workspace/21.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/21.i2c_host_stretch_timeout.3225487233 |
Short name | T1094 |
Test name | |
Test status | |
Simulation time | 888356363 ps |
CPU time | 16.2 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:35:02 PM PDT 24 |
Peak memory | 218308 kb |
Host | smart-077f7689-672d-4f73-b006-224871365581 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225487233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3225487233 |
Directory | /workspace/21.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1602850549 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 10607177530 ps |
CPU time | 4.86 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:34:51 PM PDT 24 |
Peak memory | 223744 kb |
Host | smart-504a3683-22e7-4584-9ebd-c5e8f2e54468 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602850549 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.1602850549 |
Directory | /workspace/21.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/21.i2c_target_fifo_reset_tx.286940844 |
Short name | T1208 |
Test name | |
Test status | |
Simulation time | 10047275086 ps |
CPU time | 84.1 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:36:10 PM PDT 24 |
Peak memory | 581040 kb |
Host | smart-6388f775-a17f-43d4-ad87-e1ca7b6fe66b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286940844 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.i2c_target_fifo_reset_tx.286940844 |
Directory | /workspace/21.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/21.i2c_target_hrst.2449717561 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 873991698 ps |
CPU time | 2.84 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-c7725882-8622-4e9d-8e75-a82fcb377916 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449717561 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.2449717561 |
Directory | /workspace/21.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/21.i2c_target_intr_smoke.832112245 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 1167515083 ps |
CPU time | 5.7 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:34:53 PM PDT 24 |
Peak memory | 214404 kb |
Host | smart-4a005a6f-175d-4dc2-912b-edc0c941a89f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832112245 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.832112245 |
Directory | /workspace/21.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/21.i2c_target_intr_stress_wr.3768431918 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 31650971705 ps |
CPU time | 26.71 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 722712 kb |
Host | smart-cd3ae58d-6f94-4800-8546-cd5a9652bd0e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768431918 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3768431918 |
Directory | /workspace/21.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/21.i2c_target_smoke.3084078955 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 2781716996 ps |
CPU time | 10.77 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:53 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-9c771e5c-215a-4938-bf7f-4bee19e2f825 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084078955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta rget_smoke.3084078955 |
Directory | /workspace/21.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/21.i2c_target_stress_rd.2254146858 |
Short name | T1263 |
Test name | |
Test status | |
Simulation time | 809145394 ps |
CPU time | 11.47 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 212596 kb |
Host | smart-ce31e7ed-d039-4462-8db9-f8b8f03ae630 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254146858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2 c_target_stress_rd.2254146858 |
Directory | /workspace/21.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/21.i2c_target_stress_wr.1935771595 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 23728647018 ps |
CPU time | 15.03 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:58 PM PDT 24 |
Peak memory | 293208 kb |
Host | smart-beb3b9d7-e11b-4506-8a7e-d81a2c9660fe |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935771595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2 c_target_stress_wr.1935771595 |
Directory | /workspace/21.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/21.i2c_target_stretch.1088919985 |
Short name | T1059 |
Test name | |
Test status | |
Simulation time | 14956961255 ps |
CPU time | 481.21 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:42:46 PM PDT 24 |
Peak memory | 1601868 kb |
Host | smart-c27b9119-dbc9-4161-af13-92950494f578 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088919985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ target_stretch.1088919985 |
Directory | /workspace/21.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/21.i2c_target_timeout.2328063462 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 2584022099 ps |
CPU time | 6.88 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:34:53 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-c12ebfe0-2ab6-4843-a1e9-42c6815a71dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328063462 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.i2c_target_timeout.2328063462 |
Directory | /workspace/21.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/22.i2c_alert_test.2143822480 |
Short name | T1284 |
Test name | |
Test status | |
Simulation time | 15002922 ps |
CPU time | 0.62 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-a5092592-8192-4202-b405-2e1b00a792a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143822480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2143822480 |
Directory | /workspace/22.i2c_alert_test/latest |
Test location | /workspace/coverage/default/22.i2c_host_error_intr.3067752947 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 300645405 ps |
CPU time | 1.4 seconds |
Started | May 23 12:34:48 PM PDT 24 |
Finished | May 23 12:34:51 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-b38f218f-5693-457b-b763-dd54f8758ea6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067752947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3067752947 |
Directory | /workspace/22.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2145566685 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 2447929639 ps |
CPU time | 6.58 seconds |
Started | May 23 12:34:48 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 255940 kb |
Host | smart-608ed639-c88d-4523-8e56-bcb6c2d68ceb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145566685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp ty.2145566685 |
Directory | /workspace/22.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_full.1144274046 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 4188631672 ps |
CPU time | 108.24 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 371844 kb |
Host | smart-953373f2-dad7-4825-b63a-221b1c11c1b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144274046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1144274046 |
Directory | /workspace/22.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_overflow.751280315 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 10897649887 ps |
CPU time | 78.21 seconds |
Started | May 23 12:34:48 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 692744 kb |
Host | smart-17f4393d-60b3-4830-8a16-63c00aa3f531 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751280315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.751280315 |
Directory | /workspace/22.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2865783503 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 306585040 ps |
CPU time | 0.79 seconds |
Started | May 23 12:34:48 PM PDT 24 |
Finished | May 23 12:34:50 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-40edb253-a38d-4120-9ad5-4709442e648e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865783503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f mt.2865783503 |
Directory | /workspace/22.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3333606545 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 3053037938 ps |
CPU time | 9.27 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-eb1763e2-b517-45f9-a8d4-faff4f7580ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333606545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx .3333606545 |
Directory | /workspace/22.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/22.i2c_host_fifo_watermark.2811009967 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 21603855880 ps |
CPU time | 431.86 seconds |
Started | May 23 12:34:49 PM PDT 24 |
Finished | May 23 12:42:02 PM PDT 24 |
Peak memory | 1526192 kb |
Host | smart-311d3187-ec2c-4d03-ae1c-f1e1b41f24dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811009967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2811009967 |
Directory | /workspace/22.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/22.i2c_host_may_nack.3083335210 |
Short name | T1200 |
Test name | |
Test status | |
Simulation time | 2508094405 ps |
CPU time | 27.75 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-1936dcf4-cbdc-44c3-90f2-903a83f5f1b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083335210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3083335210 |
Directory | /workspace/22.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/22.i2c_host_mode_toggle.43338481 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 13377126718 ps |
CPU time | 22.03 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:35:04 PM PDT 24 |
Peak memory | 345840 kb |
Host | smart-63d24552-8be2-42f6-a4a8-87b877d97ea4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43338481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.43338481 |
Directory | /workspace/22.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/22.i2c_host_override.1804424152 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 17774374 ps |
CPU time | 0.64 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 204536 kb |
Host | smart-88f884ac-b985-4b9b-9f75-6c7b742bc0dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804424152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1804424152 |
Directory | /workspace/22.i2c_host_override/latest |
Test location | /workspace/coverage/default/22.i2c_host_perf.165095916 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 12481959328 ps |
CPU time | 374.78 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:41:04 PM PDT 24 |
Peak memory | 2116656 kb |
Host | smart-dcb464fc-f84c-4669-a03a-c7ee05d9de6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165095916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.165095916 |
Directory | /workspace/22.i2c_host_perf/latest |
Test location | /workspace/coverage/default/22.i2c_host_smoke.2336527261 |
Short name | T1329 |
Test name | |
Test status | |
Simulation time | 6777901768 ps |
CPU time | 28.78 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 286072 kb |
Host | smart-f826d08d-e9d1-4e36-b47b-1daf77ecd34d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336527261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2336527261 |
Directory | /workspace/22.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/22.i2c_host_stress_all.1374199474 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 51356741738 ps |
CPU time | 475.83 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:42:41 PM PDT 24 |
Peak memory | 1713964 kb |
Host | smart-de144bef-7a96-400c-b917-41695270a061 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374199474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1374199474 |
Directory | /workspace/22.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/22.i2c_host_stretch_timeout.58121348 |
Short name | T1243 |
Test name | |
Test status | |
Simulation time | 1354351193 ps |
CPU time | 13.35 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:35:01 PM PDT 24 |
Peak memory | 221272 kb |
Host | smart-8bcc6710-a1e4-4126-a0de-576fb6d65855 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58121348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.58121348 |
Directory | /workspace/22.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/22.i2c_target_bad_addr.1340844832 |
Short name | T1063 |
Test name | |
Test status | |
Simulation time | 909748797 ps |
CPU time | 2.76 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:34:48 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-a762e182-d119-49ed-8661-c2893bc5131f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340844832 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1340844832 |
Directory | /workspace/22.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3993007437 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 10038140663 ps |
CPU time | 66.79 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 424024 kb |
Host | smart-eef0c484-3142-4c75-9faf-31f0d6181971 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993007437 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.3993007437 |
Directory | /workspace/22.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/22.i2c_target_fifo_reset_tx.4257263843 |
Short name | T1324 |
Test name | |
Test status | |
Simulation time | 10415019077 ps |
CPU time | 14.54 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:57 PM PDT 24 |
Peak memory | 270988 kb |
Host | smart-cbdadc8e-8e21-4122-9b01-d5f565439ffb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257263843 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 22.i2c_target_fifo_reset_tx.4257263843 |
Directory | /workspace/22.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/22.i2c_target_hrst.3286068975 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 721151337 ps |
CPU time | 2.36 seconds |
Started | May 23 12:34:41 PM PDT 24 |
Finished | May 23 12:34:45 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-05ddb205-8d95-49e2-95db-2d790a7a4925 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286068975 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.3286068975 |
Directory | /workspace/22.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/22.i2c_target_intr_smoke.3806015971 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 1040155487 ps |
CPU time | 5.32 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:34:54 PM PDT 24 |
Peak memory | 212988 kb |
Host | smart-7e4edceb-f3f5-4917-aaf6-b25e6cb48e40 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806015971 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 22.i2c_target_intr_smoke.3806015971 |
Directory | /workspace/22.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/22.i2c_target_intr_stress_wr.430708029 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 27539833232 ps |
CPU time | 51.77 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:35:41 PM PDT 24 |
Peak memory | 1085512 kb |
Host | smart-c8e66256-d3c6-42f3-a1b9-16773f7a0aca |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430708029 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.430708029 |
Directory | /workspace/22.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/22.i2c_target_smoke.779486613 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 1086784694 ps |
CPU time | 45.21 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:35:31 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-3ff8734d-2894-4cc5-b010-6b0914f8af05 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779486613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar get_smoke.779486613 |
Directory | /workspace/22.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/22.i2c_target_stress_rd.2554399857 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 2273377745 ps |
CPU time | 51.98 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:35:36 PM PDT 24 |
Peak memory | 205872 kb |
Host | smart-c99590bf-0b21-4ecb-8350-19b57b55e38d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554399857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2 c_target_stress_rd.2554399857 |
Directory | /workspace/22.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/22.i2c_target_stress_wr.3423490135 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 47669724318 ps |
CPU time | 117.59 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:36:43 PM PDT 24 |
Peak memory | 1801860 kb |
Host | smart-21b4b316-0e72-4244-a9e9-83fc2a0a72b2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423490135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2 c_target_stress_wr.3423490135 |
Directory | /workspace/22.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/22.i2c_target_stretch.655846724 |
Short name | T1183 |
Test name | |
Test status | |
Simulation time | 27098565610 ps |
CPU time | 250.64 seconds |
Started | May 23 12:34:48 PM PDT 24 |
Finished | May 23 12:39:01 PM PDT 24 |
Peak memory | 1611120 kb |
Host | smart-45f40945-3b42-4a2e-9398-9be946001634 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655846724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t arget_stretch.655846724 |
Directory | /workspace/22.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/22.i2c_target_timeout.3512627293 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1295664606 ps |
CPU time | 7.37 seconds |
Started | May 23 12:34:46 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 219640 kb |
Host | smart-739b85dc-6a79-4492-98ef-e6cdecda770f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512627293 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.i2c_target_timeout.3512627293 |
Directory | /workspace/22.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/23.i2c_alert_test.2808870536 |
Short name | T1271 |
Test name | |
Test status | |
Simulation time | 22154060 ps |
CPU time | 0.62 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-687d4330-c946-4957-80b7-6f474cb0cdbf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808870536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2808870536 |
Directory | /workspace/23.i2c_alert_test/latest |
Test location | /workspace/coverage/default/23.i2c_host_error_intr.1729981415 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 115612835 ps |
CPU time | 2.22 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:34:48 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-28211157-9650-4eec-8726-a4b3c3bca449 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729981415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1729981415 |
Directory | /workspace/23.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3731050202 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 713675481 ps |
CPU time | 19.56 seconds |
Started | May 23 12:34:42 PM PDT 24 |
Finished | May 23 12:35:04 PM PDT 24 |
Peak memory | 285020 kb |
Host | smart-fc7903a4-235f-4fb3-9d9e-5964a67400eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731050202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp ty.3731050202 |
Directory | /workspace/23.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_full.119514419 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 9449915042 ps |
CPU time | 71.04 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:35:56 PM PDT 24 |
Peak memory | 608944 kb |
Host | smart-61369d46-3fa1-4af4-9812-6eddaf2d235a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119514419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.119514419 |
Directory | /workspace/23.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_overflow.2780592177 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 4411930236 ps |
CPU time | 49.51 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 619088 kb |
Host | smart-5b3fead1-3583-4e00-a002-9597f077c61b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780592177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2780592177 |
Directory | /workspace/23.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3202622013 |
Short name | T1142 |
Test name | |
Test status | |
Simulation time | 1257751992 ps |
CPU time | 0.93 seconds |
Started | May 23 12:34:45 PM PDT 24 |
Finished | May 23 12:34:48 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-819df409-c409-48ee-8b35-35f4da768d16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202622013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f mt.3202622013 |
Directory | /workspace/23.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1660887536 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 256698556 ps |
CPU time | 3.92 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 225356 kb |
Host | smart-776b32f3-18fe-4bfb-a93c-65fe6fd96ee4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660887536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx .1660887536 |
Directory | /workspace/23.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/23.i2c_host_fifo_watermark.3720440788 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 19729968559 ps |
CPU time | 396.35 seconds |
Started | May 23 12:34:44 PM PDT 24 |
Finished | May 23 12:41:22 PM PDT 24 |
Peak memory | 1385280 kb |
Host | smart-b2c89299-9d87-4959-a8e1-6ad87be52ae3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720440788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3720440788 |
Directory | /workspace/23.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/23.i2c_host_may_nack.2028031174 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 241411001 ps |
CPU time | 10.16 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:03 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-c5a9f2c8-cd0a-436b-9793-f37d00a7d4be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028031174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2028031174 |
Directory | /workspace/23.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/23.i2c_host_mode_toggle.3550103743 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3894367055 ps |
CPU time | 37.92 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:40 PM PDT 24 |
Peak memory | 372636 kb |
Host | smart-688e7199-2232-461f-b305-aef363fd066d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550103743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3550103743 |
Directory | /workspace/23.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/23.i2c_host_override.384569344 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 73406096 ps |
CPU time | 0.64 seconds |
Started | May 23 12:34:47 PM PDT 24 |
Finished | May 23 12:34:50 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-218e7c48-c7b3-400d-9b35-8eec821b6ca3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384569344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.384569344 |
Directory | /workspace/23.i2c_host_override/latest |
Test location | /workspace/coverage/default/23.i2c_host_perf.4137155870 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 459131261 ps |
CPU time | 9.74 seconds |
Started | May 23 12:34:46 PM PDT 24 |
Finished | May 23 12:34:57 PM PDT 24 |
Peak memory | 229384 kb |
Host | smart-436373ec-793d-4425-a925-b09404d83ece |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137155870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.4137155870 |
Directory | /workspace/23.i2c_host_perf/latest |
Test location | /workspace/coverage/default/23.i2c_host_smoke.1711949115 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1180448909 ps |
CPU time | 57.5 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:35:43 PM PDT 24 |
Peak memory | 329908 kb |
Host | smart-f0c358e0-02c0-4d6f-9734-ffe93b7f53ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711949115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1711949115 |
Directory | /workspace/23.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/23.i2c_host_stretch_timeout.3647634674 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3199089078 ps |
CPU time | 13.91 seconds |
Started | May 23 12:34:43 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 221336 kb |
Host | smart-677a9bee-805c-40ac-a51d-8c975fef3698 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647634674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3647634674 |
Directory | /workspace/23.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/23.i2c_target_bad_addr.1958027080 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 1631675506 ps |
CPU time | 4.24 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 212992 kb |
Host | smart-26b6dbff-8fce-4e4c-8e46-191cc9c28d88 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958027080 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1958027080 |
Directory | /workspace/23.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1436430489 |
Short name | T1053 |
Test name | |
Test status | |
Simulation time | 10114730970 ps |
CPU time | 26.95 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:20 PM PDT 24 |
Peak memory | 301936 kb |
Host | smart-7d37c905-15bf-49e8-9147-04a2a6e4b3d6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436430489 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.1436430489 |
Directory | /workspace/23.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1498459210 |
Short name | T1212 |
Test name | |
Test status | |
Simulation time | 10089379010 ps |
CPU time | 77.81 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:36:10 PM PDT 24 |
Peak memory | 469452 kb |
Host | smart-b571b3d4-28c5-4c33-a8f5-6a2236ddfe9e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498459210 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 23.i2c_target_fifo_reset_tx.1498459210 |
Directory | /workspace/23.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/23.i2c_target_hrst.3004776979 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 1571248926 ps |
CPU time | 2.55 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:04 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-38664b77-6240-4050-8cb6-e9ddf0449975 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004776979 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.3004776979 |
Directory | /workspace/23.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/23.i2c_target_intr_smoke.3370231976 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 1548830306 ps |
CPU time | 6.39 seconds |
Started | May 23 12:34:55 PM PDT 24 |
Finished | May 23 12:35:03 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-19e0680c-ca4a-4a41-8a7c-00be1dac7270 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370231976 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 23.i2c_target_intr_smoke.3370231976 |
Directory | /workspace/23.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/23.i2c_target_intr_stress_wr.2706657522 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 20440712578 ps |
CPU time | 46.04 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:38 PM PDT 24 |
Peak memory | 833308 kb |
Host | smart-82d70107-2486-4ec1-bc84-96172123d1f2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706657522 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2706657522 |
Directory | /workspace/23.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/23.i2c_target_smoke.1828652189 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 796189319 ps |
CPU time | 30.77 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:23 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-c2115954-5d51-4d7d-9df4-6e8a8a17b41a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828652189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta rget_smoke.1828652189 |
Directory | /workspace/23.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/23.i2c_target_stress_rd.242020727 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 4768910474 ps |
CPU time | 14.58 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:07 PM PDT 24 |
Peak memory | 215868 kb |
Host | smart-783f1271-2b2d-474d-9158-d09c0b5770d9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242020727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c _target_stress_rd.242020727 |
Directory | /workspace/23.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/23.i2c_target_stress_wr.182037464 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 25205434361 ps |
CPU time | 78.16 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:36:15 PM PDT 24 |
Peak memory | 1218368 kb |
Host | smart-39aa01d3-e09a-4a5b-97aa-765fbe19b8ce |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182037464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c _target_stress_wr.182037464 |
Directory | /workspace/23.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/23.i2c_target_stretch.3688903242 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 6856545161 ps |
CPU time | 65.34 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:36:07 PM PDT 24 |
Peak memory | 464588 kb |
Host | smart-20b0213e-22f3-4df3-b488-3693e3c85eaf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688903242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ target_stretch.3688903242 |
Directory | /workspace/23.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/23.i2c_target_timeout.1075860569 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1234611380 ps |
CPU time | 6.85 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:35:02 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-826c51c1-8f8d-4345-b8dd-8f5ec18ad188 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075860569 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.i2c_target_timeout.1075860569 |
Directory | /workspace/23.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/24.i2c_alert_test.876113587 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 36688476 ps |
CPU time | 0.59 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-a421bcad-14a8-4d63-99b1-8920f59b9acf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876113587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.876113587 |
Directory | /workspace/24.i2c_alert_test/latest |
Test location | /workspace/coverage/default/24.i2c_host_error_intr.531216623 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 324643293 ps |
CPU time | 2.6 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:35:01 PM PDT 24 |
Peak memory | 230452 kb |
Host | smart-425951a5-461e-43e2-9e8b-c3f913288c50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=531216623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.531216623 |
Directory | /workspace/24.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.514854079 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 5332096002 ps |
CPU time | 5.97 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:35:01 PM PDT 24 |
Peak memory | 276444 kb |
Host | smart-3cbf136d-fdb5-456f-b217-5c8e7b9cad68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514854079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt y.514854079 |
Directory | /workspace/24.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_full.2741194724 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 3587941648 ps |
CPU time | 56.22 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:35:50 PM PDT 24 |
Peak memory | 563820 kb |
Host | smart-e7492f37-7cce-4ad7-8970-25408290a669 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741194724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2741194724 |
Directory | /workspace/24.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_overflow.1770392019 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 2389036373 ps |
CPU time | 66.08 seconds |
Started | May 23 12:34:52 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 315660 kb |
Host | smart-dd503df9-af7d-473d-931a-9d2b1be34e70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770392019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1770392019 |
Directory | /workspace/24.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2554258313 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 507822619 ps |
CPU time | 0.96 seconds |
Started | May 23 12:34:52 PM PDT 24 |
Finished | May 23 12:34:55 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-edc478b0-37b6-42b1-9ef3-d0609cac2f60 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554258313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f mt.2554258313 |
Directory | /workspace/24.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2186978789 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 292727810 ps |
CPU time | 4.15 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 231268 kb |
Host | smart-924b4aaa-3cfe-4c63-9d62-3d42232c4f62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186978789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx .2186978789 |
Directory | /workspace/24.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/24.i2c_host_fifo_watermark.4097955045 |
Short name | T1247 |
Test name | |
Test status | |
Simulation time | 13483729790 ps |
CPU time | 100.15 seconds |
Started | May 23 12:34:49 PM PDT 24 |
Finished | May 23 12:36:31 PM PDT 24 |
Peak memory | 1044948 kb |
Host | smart-4ad4012b-6cd3-4de6-abff-ad2bc4fbabaa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097955045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.4097955045 |
Directory | /workspace/24.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/24.i2c_host_may_nack.2120132178 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 309909563 ps |
CPU time | 2.37 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:35:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-6ffbbce5-f6dc-4f25-ac5d-403e08ba3aa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120132178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2120132178 |
Directory | /workspace/24.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/24.i2c_host_mode_toggle.4062611207 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 1130221275 ps |
CPU time | 21.24 seconds |
Started | May 23 12:34:55 PM PDT 24 |
Finished | May 23 12:35:17 PM PDT 24 |
Peak memory | 298972 kb |
Host | smart-a34b41c7-b7d1-462e-8e78-faf3524e2cdc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062611207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.4062611207 |
Directory | /workspace/24.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/24.i2c_host_override.503574889 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 90461267 ps |
CPU time | 0.69 seconds |
Started | May 23 12:34:52 PM PDT 24 |
Finished | May 23 12:34:54 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-19897300-5931-4655-afdc-7567de040d46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503574889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.503574889 |
Directory | /workspace/24.i2c_host_override/latest |
Test location | /workspace/coverage/default/24.i2c_host_perf.1439575317 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 2808813519 ps |
CPU time | 38.6 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:35:33 PM PDT 24 |
Peak memory | 221948 kb |
Host | smart-6b44c3bd-c10e-4493-af52-247a303ed71d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439575317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1439575317 |
Directory | /workspace/24.i2c_host_perf/latest |
Test location | /workspace/coverage/default/24.i2c_host_smoke.383997327 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 1331762842 ps |
CPU time | 25.06 seconds |
Started | May 23 12:34:52 PM PDT 24 |
Finished | May 23 12:35:18 PM PDT 24 |
Peak memory | 311116 kb |
Host | smart-8331cf3e-4884-426e-9b54-fb173454dc12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383997327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.383997327 |
Directory | /workspace/24.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/24.i2c_host_stretch_timeout.3184447988 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 530977555 ps |
CPU time | 9.16 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:01 PM PDT 24 |
Peak memory | 213092 kb |
Host | smart-a6844f69-5ea4-4b5e-a843-bc28343280ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184447988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3184447988 |
Directory | /workspace/24.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3978606454 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 10044895142 ps |
CPU time | 75.66 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:36:10 PM PDT 24 |
Peak memory | 446788 kb |
Host | smart-d5d0a424-3d07-4a05-b0b9-4d8cd995403c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978606454 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.3978606454 |
Directory | /workspace/24.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3634821184 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 10377732296 ps |
CPU time | 12.31 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:35:08 PM PDT 24 |
Peak memory | 254532 kb |
Host | smart-706e7641-62d8-40e1-b2ff-7f8a6f90a4b3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634821184 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 24.i2c_target_fifo_reset_tx.3634821184 |
Directory | /workspace/24.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/24.i2c_target_hrst.1536126398 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 1204246305 ps |
CPU time | 2.31 seconds |
Started | May 23 12:34:55 PM PDT 24 |
Finished | May 23 12:34:59 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-b82cdd5a-c3ed-4a25-a29b-9e1ebd60773c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536126398 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_hrst.1536126398 |
Directory | /workspace/24.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/24.i2c_target_intr_smoke.2482625412 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 637310710 ps |
CPU time | 3.6 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:34:58 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-7ae2a01a-3f04-4e3b-94ca-8b38e3a94ffc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482625412 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.i2c_target_intr_smoke.2482625412 |
Directory | /workspace/24.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/24.i2c_target_intr_stress_wr.2554084270 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 12516340701 ps |
CPU time | 133.88 seconds |
Started | May 23 12:34:55 PM PDT 24 |
Finished | May 23 12:37:10 PM PDT 24 |
Peak memory | 2243684 kb |
Host | smart-9be04289-8e8a-4929-aa75-b94547447512 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554084270 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2554084270 |
Directory | /workspace/24.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/24.i2c_target_smoke.4248664530 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 1038730442 ps |
CPU time | 41.74 seconds |
Started | May 23 12:34:51 PM PDT 24 |
Finished | May 23 12:35:34 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-787c2eac-3103-4a0d-a9cc-b5712a5bf388 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248664530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta rget_smoke.4248664530 |
Directory | /workspace/24.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/24.i2c_target_stress_rd.1105946240 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 3018987922 ps |
CPU time | 40.49 seconds |
Started | May 23 12:34:58 PM PDT 24 |
Finished | May 23 12:35:40 PM PDT 24 |
Peak memory | 206064 kb |
Host | smart-bda46329-386c-457e-aa08-e83039bba483 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105946240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2 c_target_stress_rd.1105946240 |
Directory | /workspace/24.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/24.i2c_target_stress_wr.1469940230 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 56671226804 ps |
CPU time | 680.55 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:46:15 PM PDT 24 |
Peak memory | 5437816 kb |
Host | smart-397cdfa9-f4e6-414a-b88b-33c477d34909 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469940230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2 c_target_stress_wr.1469940230 |
Directory | /workspace/24.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/24.i2c_target_stretch.1491035816 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 31795110064 ps |
CPU time | 2334.42 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 01:13:50 PM PDT 24 |
Peak memory | 7604812 kb |
Host | smart-68b44fc6-65a1-4130-a0e7-30e86e78d3bd |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491035816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ target_stretch.1491035816 |
Directory | /workspace/24.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/24.i2c_target_timeout.434394223 |
Short name | T1166 |
Test name | |
Test status | |
Simulation time | 4003909633 ps |
CPU time | 6.15 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:35:02 PM PDT 24 |
Peak memory | 221168 kb |
Host | smart-90d15773-369f-44f0-b5b4-9d288ac382ef |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434394223 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.i2c_target_timeout.434394223 |
Directory | /workspace/24.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/25.i2c_alert_test.746746798 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 19717012 ps |
CPU time | 0.61 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:06 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-3b108e91-5f15-4eae-8415-19898daf2852 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746746798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.746746798 |
Directory | /workspace/25.i2c_alert_test/latest |
Test location | /workspace/coverage/default/25.i2c_host_error_intr.3326184666 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 538014195 ps |
CPU time | 2.02 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:35:00 PM PDT 24 |
Peak memory | 213100 kb |
Host | smart-2eb67e79-efc7-4c29-b95c-1e3d9641dafa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326184666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3326184666 |
Directory | /workspace/25.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1281424397 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 683975983 ps |
CPU time | 7.85 seconds |
Started | May 23 12:34:59 PM PDT 24 |
Finished | May 23 12:35:08 PM PDT 24 |
Peak memory | 272180 kb |
Host | smart-fbd587c4-4b3b-48fe-898c-6266f07afefa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281424397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp ty.1281424397 |
Directory | /workspace/25.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_full.699532087 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 8874051671 ps |
CPU time | 163.79 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:37:41 PM PDT 24 |
Peak memory | 758836 kb |
Host | smart-d69377cb-7813-48ce-8124-c8e98b43e2ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699532087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.699532087 |
Directory | /workspace/25.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_overflow.456981910 |
Short name | T1163 |
Test name | |
Test status | |
Simulation time | 8398502320 ps |
CPU time | 157.78 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:37:35 PM PDT 24 |
Peak memory | 708004 kb |
Host | smart-27bd3460-0040-4407-9544-88725bde2222 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456981910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.456981910 |
Directory | /workspace/25.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3481264219 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 89536536 ps |
CPU time | 0.88 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:02 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-b094da13-1b4f-4651-8528-fa326778fa66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481264219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f mt.3481264219 |
Directory | /workspace/25.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1263429394 |
Short name | T1092 |
Test name | |
Test status | |
Simulation time | 171045722 ps |
CPU time | 9.57 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 234620 kb |
Host | smart-a2cbc543-8f44-4d75-a390-0d2c201bdcf8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263429394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx .1263429394 |
Directory | /workspace/25.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/25.i2c_host_fifo_watermark.3834150652 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 7988252642 ps |
CPU time | 120.53 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 1179860 kb |
Host | smart-63c3027b-4303-4cf8-ab87-30f9a05af119 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834150652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3834150652 |
Directory | /workspace/25.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/25.i2c_host_may_nack.1282619508 |
Short name | T1132 |
Test name | |
Test status | |
Simulation time | 1128711859 ps |
CPU time | 12.11 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:17 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-6f7e8320-7cc8-44d5-871c-90d6d6bce5ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282619508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1282619508 |
Directory | /workspace/25.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/25.i2c_host_mode_toggle.1191017205 |
Short name | T1209 |
Test name | |
Test status | |
Simulation time | 4089988840 ps |
CPU time | 32.03 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:35:36 PM PDT 24 |
Peak memory | 385832 kb |
Host | smart-54d1665a-f91f-4a37-bd45-9d502108f993 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191017205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1191017205 |
Directory | /workspace/25.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/25.i2c_host_override.950026421 |
Short name | T1249 |
Test name | |
Test status | |
Simulation time | 44664062 ps |
CPU time | 0.65 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:03 PM PDT 24 |
Peak memory | 204476 kb |
Host | smart-f7838996-2882-4985-b134-bd828badb9c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950026421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.950026421 |
Directory | /workspace/25.i2c_host_override/latest |
Test location | /workspace/coverage/default/25.i2c_host_perf.1228175428 |
Short name | T1098 |
Test name | |
Test status | |
Simulation time | 3344836485 ps |
CPU time | 14.04 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:35:12 PM PDT 24 |
Peak memory | 356328 kb |
Host | smart-d1df1c6a-6dec-41b0-aafb-ad4f2f5c0005 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228175428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1228175428 |
Directory | /workspace/25.i2c_host_perf/latest |
Test location | /workspace/coverage/default/25.i2c_host_smoke.325616949 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 1055856856 ps |
CPU time | 17.95 seconds |
Started | May 23 12:34:56 PM PDT 24 |
Finished | May 23 12:35:16 PM PDT 24 |
Peak memory | 285636 kb |
Host | smart-88feb1d1-154e-464a-b905-ca9501d00ee6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325616949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.325616949 |
Directory | /workspace/25.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/25.i2c_host_stress_all.1916994420 |
Short name | T1268 |
Test name | |
Test status | |
Simulation time | 17289881681 ps |
CPU time | 2066.15 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 01:09:22 PM PDT 24 |
Peak memory | 3278648 kb |
Host | smart-879cdba0-399a-4f04-9be4-9e04a2b7020a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916994420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1916994420 |
Directory | /workspace/25.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/25.i2c_host_stretch_timeout.3746783666 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1363425881 ps |
CPU time | 10.02 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 221068 kb |
Host | smart-6d0485c5-1b0f-42ce-9ac9-95145b641725 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746783666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3746783666 |
Directory | /workspace/25.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/25.i2c_target_bad_addr.613838972 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 901104861 ps |
CPU time | 4.05 seconds |
Started | May 23 12:35:05 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 212980 kb |
Host | smart-2645e5a2-d17f-4162-9f4e-1693c084a797 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613838972 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.613838972 |
Directory | /workspace/25.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4079222119 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 10034176476 ps |
CPU time | 73.84 seconds |
Started | May 23 12:35:06 PM PDT 24 |
Finished | May 23 12:36:21 PM PDT 24 |
Peak memory | 457384 kb |
Host | smart-a076ff4f-9d11-465c-8b61-5e9f7b6d090d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079222119 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.4079222119 |
Directory | /workspace/25.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2425092572 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 10313628379 ps |
CPU time | 14.19 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:35:18 PM PDT 24 |
Peak memory | 303464 kb |
Host | smart-11cb9be7-edbc-4582-a910-3bcb13c70984 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425092572 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 25.i2c_target_fifo_reset_tx.2425092572 |
Directory | /workspace/25.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/25.i2c_target_hrst.3314018883 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 1722935923 ps |
CPU time | 2.63 seconds |
Started | May 23 12:35:04 PM PDT 24 |
Finished | May 23 12:35:09 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-0652fac7-9f14-481d-b5bd-c6b2d9c32263 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314018883 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.3314018883 |
Directory | /workspace/25.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/25.i2c_target_intr_smoke.2417037180 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 820384787 ps |
CPU time | 4.71 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:09 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-6848b201-d2e9-4823-9c4a-3da058ba1079 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417037180 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 25.i2c_target_intr_smoke.2417037180 |
Directory | /workspace/25.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/25.i2c_target_intr_stress_wr.2430764561 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 12045756360 ps |
CPU time | 76.75 seconds |
Started | May 23 12:35:05 PM PDT 24 |
Finished | May 23 12:36:23 PM PDT 24 |
Peak memory | 1283640 kb |
Host | smart-66de4175-f965-4c74-a971-111c8f7d2a17 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430764561 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2430764561 |
Directory | /workspace/25.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/25.i2c_target_smoke.1350992 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 2690296583 ps |
CPU time | 11.43 seconds |
Started | May 23 12:34:53 PM PDT 24 |
Finished | May 23 12:35:07 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-2d328ae1-3ac9-493f-8ba2-c5ee541e7d91 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i 2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_targe t_smoke.1350992 |
Directory | /workspace/25.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/25.i2c_target_stress_rd.1803236354 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 2991807253 ps |
CPU time | 9.64 seconds |
Started | May 23 12:34:54 PM PDT 24 |
Finished | May 23 12:35:05 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-1bff98a2-9af6-46a5-a782-e1ad065f91da |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803236354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2 c_target_stress_rd.1803236354 |
Directory | /workspace/25.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/25.i2c_target_stress_wr.3447232696 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 22176302844 ps |
CPU time | 13.38 seconds |
Started | May 23 12:34:52 PM PDT 24 |
Finished | May 23 12:35:07 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-97ff3e29-ba9f-4e23-9a16-44885065abc2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447232696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2 c_target_stress_wr.3447232696 |
Directory | /workspace/25.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/25.i2c_target_stretch.899778678 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 19620551573 ps |
CPU time | 351.53 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:40:55 PM PDT 24 |
Peak memory | 2558812 kb |
Host | smart-1a5ac7b8-4b60-438b-9aeb-f2f64242f92e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899778678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t arget_stretch.899778678 |
Directory | /workspace/25.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/25.i2c_target_timeout.2647759932 |
Short name | T1039 |
Test name | |
Test status | |
Simulation time | 1177376779 ps |
CPU time | 6.84 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-4cafb47c-376f-4986-98dd-677a29fa3ad6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647759932 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.i2c_target_timeout.2647759932 |
Directory | /workspace/25.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/26.i2c_alert_test.524438430 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 68298412 ps |
CPU time | 0.66 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:05 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-021a31ff-fc24-4e4b-8920-eecf2bda4247 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524438430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.524438430 |
Directory | /workspace/26.i2c_alert_test/latest |
Test location | /workspace/coverage/default/26.i2c_host_error_intr.1120952495 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 173784500 ps |
CPU time | 6.25 seconds |
Started | May 23 12:35:04 PM PDT 24 |
Finished | May 23 12:35:12 PM PDT 24 |
Peak memory | 234312 kb |
Host | smart-cc0d51dc-0205-45cb-88a4-e369631c10a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120952495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1120952495 |
Directory | /workspace/26.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2322031786 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 1465465280 ps |
CPU time | 8.66 seconds |
Started | May 23 12:35:04 PM PDT 24 |
Finished | May 23 12:35:14 PM PDT 24 |
Peak memory | 307100 kb |
Host | smart-738e44ad-88e5-4424-bb84-1b84f3cd89d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322031786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp ty.2322031786 |
Directory | /workspace/26.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_full.3881702678 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 2267651488 ps |
CPU time | 146.48 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:37:31 PM PDT 24 |
Peak memory | 652796 kb |
Host | smart-2ac21a15-29bb-47ad-b06c-b311f59e7721 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881702678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3881702678 |
Directory | /workspace/26.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_overflow.2165397085 |
Short name | T1143 |
Test name | |
Test status | |
Simulation time | 2081954171 ps |
CPU time | 61.87 seconds |
Started | May 23 12:35:04 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 593540 kb |
Host | smart-fa88359b-117f-454e-95d0-024309aa7233 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165397085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2165397085 |
Directory | /workspace/26.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3334482031 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 306877968 ps |
CPU time | 0.95 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:06 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-5f150924-07ca-4b88-b539-f2d1390582bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334482031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f mt.3334482031 |
Directory | /workspace/26.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3268203317 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 236789673 ps |
CPU time | 9.05 seconds |
Started | May 23 12:35:07 PM PDT 24 |
Finished | May 23 12:35:17 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-976baadf-6d7e-49a7-a1e2-0b0d793b11a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268203317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx .3268203317 |
Directory | /workspace/26.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/26.i2c_host_fifo_watermark.2896409108 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 4303422281 ps |
CPU time | 107.47 seconds |
Started | May 23 12:35:04 PM PDT 24 |
Finished | May 23 12:36:53 PM PDT 24 |
Peak memory | 1243596 kb |
Host | smart-125ceb0f-e497-4c41-8d0b-7f407cd967b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896409108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2896409108 |
Directory | /workspace/26.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/26.i2c_host_may_nack.2262704120 |
Short name | T1075 |
Test name | |
Test status | |
Simulation time | 2282421712 ps |
CPU time | 22.67 seconds |
Started | May 23 12:35:13 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-5a57ed98-e575-42d0-b2bc-46f407f283f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262704120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2262704120 |
Directory | /workspace/26.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/26.i2c_host_mode_toggle.255167544 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 4817205791 ps |
CPU time | 121.86 seconds |
Started | May 23 12:35:13 PM PDT 24 |
Finished | May 23 12:37:16 PM PDT 24 |
Peak memory | 479340 kb |
Host | smart-485d33d2-c96b-4b7f-ae26-989b3e111d3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255167544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.255167544 |
Directory | /workspace/26.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/26.i2c_host_override.1435877565 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 27644470 ps |
CPU time | 0.7 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:06 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-fc90f77b-1958-4d60-9bd6-828618c90a2c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435877565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1435877565 |
Directory | /workspace/26.i2c_host_override/latest |
Test location | /workspace/coverage/default/26.i2c_host_perf.2752497797 |
Short name | T1058 |
Test name | |
Test status | |
Simulation time | 7544136315 ps |
CPU time | 199.25 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:38:24 PM PDT 24 |
Peak memory | 992464 kb |
Host | smart-133cca7e-57c2-4b97-9012-eb3cde5cf6f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752497797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2752497797 |
Directory | /workspace/26.i2c_host_perf/latest |
Test location | /workspace/coverage/default/26.i2c_host_smoke.1167383022 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 5648986120 ps |
CPU time | 26.94 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:29 PM PDT 24 |
Peak memory | 311760 kb |
Host | smart-9da7ac1f-97a3-4e1f-aa41-bb988df86d72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167383022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1167383022 |
Directory | /workspace/26.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/26.i2c_host_stretch_timeout.3068985588 |
Short name | T1177 |
Test name | |
Test status | |
Simulation time | 1621889683 ps |
CPU time | 18.76 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 12:35:23 PM PDT 24 |
Peak memory | 212988 kb |
Host | smart-1732a5bf-92ea-4aad-ab6d-86127e969cf5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068985588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3068985588 |
Directory | /workspace/26.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/26.i2c_target_bad_addr.326985214 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 713509611 ps |
CPU time | 3.81 seconds |
Started | May 23 12:35:12 PM PDT 24 |
Finished | May 23 12:35:17 PM PDT 24 |
Peak memory | 212924 kb |
Host | smart-8b77ccd2-0d76-476a-8b84-6b6919b4125d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326985214 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.326985214 |
Directory | /workspace/26.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2243447650 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 10051839357 ps |
CPU time | 71.35 seconds |
Started | May 23 12:35:13 PM PDT 24 |
Finished | May 23 12:36:25 PM PDT 24 |
Peak memory | 407684 kb |
Host | smart-0e33d4bf-1f1f-4561-805a-d6b8e661e949 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243447650 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.2243447650 |
Directory | /workspace/26.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3964179892 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 10643621758 ps |
CPU time | 17.15 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:22 PM PDT 24 |
Peak memory | 326396 kb |
Host | smart-23f99335-86b7-4321-81fe-5120a4fc920c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964179892 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 26.i2c_target_fifo_reset_tx.3964179892 |
Directory | /workspace/26.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/26.i2c_target_hrst.2883332548 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 5068609222 ps |
CPU time | 2.72 seconds |
Started | May 23 12:35:13 PM PDT 24 |
Finished | May 23 12:35:16 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-48aecf08-0995-4156-8b01-a5c06ccdba87 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883332548 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_hrst.2883332548 |
Directory | /workspace/26.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/26.i2c_target_intr_smoke.2270445606 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 736853182 ps |
CPU time | 4.02 seconds |
Started | May 23 12:35:07 PM PDT 24 |
Finished | May 23 12:35:12 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-9c6d3783-c474-4851-bf98-8ca50da03817 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270445606 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.i2c_target_intr_smoke.2270445606 |
Directory | /workspace/26.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/26.i2c_target_intr_stress_wr.2718277656 |
Short name | T1220 |
Test name | |
Test status | |
Simulation time | 13404883344 ps |
CPU time | 103.14 seconds |
Started | May 23 12:35:01 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 1718080 kb |
Host | smart-0c1425c9-a55e-4779-8744-f149aefe853f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718277656 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2718277656 |
Directory | /workspace/26.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/26.i2c_target_smoke.2066895473 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2526430207 ps |
CPU time | 8.29 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:13 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-31544aca-532f-42ed-b055-e0181ffefaec |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066895473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta rget_smoke.2066895473 |
Directory | /workspace/26.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/26.i2c_target_stress_rd.101324683 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 4900433280 ps |
CPU time | 50.96 seconds |
Started | May 23 12:35:07 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 208336 kb |
Host | smart-f1f203c3-dc51-475c-b918-bd7aad69d754 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101324683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c _target_stress_rd.101324683 |
Directory | /workspace/26.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/26.i2c_target_stress_wr.3859710405 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 19004341447 ps |
CPU time | 20.54 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:35:26 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-084d7331-b0b1-4ede-bcea-721093e25dca |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859710405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2 c_target_stress_wr.3859710405 |
Directory | /workspace/26.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/26.i2c_target_stretch.1590155696 |
Short name | T1272 |
Test name | |
Test status | |
Simulation time | 41793342978 ps |
CPU time | 2934.71 seconds |
Started | May 23 12:35:02 PM PDT 24 |
Finished | May 23 01:23:59 PM PDT 24 |
Peak memory | 4671736 kb |
Host | smart-48a376fa-eb2c-4d08-8e41-2065d64c71dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590155696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ target_stretch.1590155696 |
Directory | /workspace/26.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/26.i2c_target_timeout.3546745422 |
Short name | T1230 |
Test name | |
Test status | |
Simulation time | 1359350610 ps |
CPU time | 7.37 seconds |
Started | May 23 12:35:01 PM PDT 24 |
Finished | May 23 12:35:10 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-b1a67846-90eb-4738-81cd-e1bf835b1b3e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546745422 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.i2c_target_timeout.3546745422 |
Directory | /workspace/26.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/27.i2c_alert_test.411017822 |
Short name | T1120 |
Test name | |
Test status | |
Simulation time | 22507976 ps |
CPU time | 0.62 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:35:19 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-ed3ee682-98ab-4068-9a49-ae85989353b1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411017822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.411017822 |
Directory | /workspace/27.i2c_alert_test/latest |
Test location | /workspace/coverage/default/27.i2c_host_error_intr.3721364350 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 199866550 ps |
CPU time | 2.92 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:35:21 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-b0be4bdc-7cb2-4d8c-8e97-450f02fb5ad7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721364350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3721364350 |
Directory | /workspace/27.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1536304376 |
Short name | T1204 |
Test name | |
Test status | |
Simulation time | 471810993 ps |
CPU time | 2.86 seconds |
Started | May 23 12:35:00 PM PDT 24 |
Finished | May 23 12:35:05 PM PDT 24 |
Peak memory | 225372 kb |
Host | smart-81d052f3-06e6-4754-ac52-f72fe0434fc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536304376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp ty.1536304376 |
Directory | /workspace/27.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_full.806095353 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 10493107379 ps |
CPU time | 92.97 seconds |
Started | May 23 12:35:09 PM PDT 24 |
Finished | May 23 12:36:43 PM PDT 24 |
Peak memory | 831920 kb |
Host | smart-244f4d4f-68f0-4cd7-b805-f9bbada9f744 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806095353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.806095353 |
Directory | /workspace/27.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_overflow.2056817348 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 2216041630 ps |
CPU time | 153.4 seconds |
Started | May 23 12:35:10 PM PDT 24 |
Finished | May 23 12:37:44 PM PDT 24 |
Peak memory | 693748 kb |
Host | smart-539d98ea-d552-42b5-8bbf-c3a8bd4dade0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056817348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2056817348 |
Directory | /workspace/27.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2552421302 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 97773322 ps |
CPU time | 0.89 seconds |
Started | May 23 12:35:12 PM PDT 24 |
Finished | May 23 12:35:14 PM PDT 24 |
Peak memory | 204552 kb |
Host | smart-bab4f5d6-f064-4a61-a263-4250a1692cc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552421302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f mt.2552421302 |
Directory | /workspace/27.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3875223529 |
Short name | T1273 |
Test name | |
Test status | |
Simulation time | 761532559 ps |
CPU time | 10.69 seconds |
Started | May 23 12:35:09 PM PDT 24 |
Finished | May 23 12:35:21 PM PDT 24 |
Peak memory | 241592 kb |
Host | smart-fc987e01-71cf-4c24-b6ab-39cdacb1ec04 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875223529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx .3875223529 |
Directory | /workspace/27.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/27.i2c_host_fifo_watermark.369444377 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 5007347745 ps |
CPU time | 170.77 seconds |
Started | May 23 12:35:05 PM PDT 24 |
Finished | May 23 12:37:57 PM PDT 24 |
Peak memory | 1467736 kb |
Host | smart-78ee6afd-6e38-4e25-b6d5-38c2d13ea470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369444377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.369444377 |
Directory | /workspace/27.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/27.i2c_host_may_nack.1814320382 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 672935294 ps |
CPU time | 8.58 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:35:24 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-419c355b-eaa8-4db0-9572-c8777e058753 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814320382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1814320382 |
Directory | /workspace/27.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/27.i2c_host_mode_toggle.2178486198 |
Short name | T1202 |
Test name | |
Test status | |
Simulation time | 1572559413 ps |
CPU time | 69.26 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:36:29 PM PDT 24 |
Peak memory | 361192 kb |
Host | smart-c151d74c-2f40-4f4c-aa55-452810efb109 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178486198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2178486198 |
Directory | /workspace/27.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/27.i2c_host_override.3222643753 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 126285539 ps |
CPU time | 0.67 seconds |
Started | May 23 12:35:01 PM PDT 24 |
Finished | May 23 12:35:04 PM PDT 24 |
Peak memory | 203716 kb |
Host | smart-2578ae8a-f126-40d4-89b5-aa5af9eebb8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222643753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3222643753 |
Directory | /workspace/27.i2c_host_override/latest |
Test location | /workspace/coverage/default/27.i2c_host_perf.728800671 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 6882254312 ps |
CPU time | 624.71 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:45:42 PM PDT 24 |
Peak memory | 1659752 kb |
Host | smart-2301d43e-222f-47f2-9471-9bcde6f87d82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728800671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.728800671 |
Directory | /workspace/27.i2c_host_perf/latest |
Test location | /workspace/coverage/default/27.i2c_host_smoke.4012319856 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 4656304969 ps |
CPU time | 115.81 seconds |
Started | May 23 12:35:03 PM PDT 24 |
Finished | May 23 12:37:00 PM PDT 24 |
Peak memory | 450816 kb |
Host | smart-d6e3fed9-c98f-49d8-8044-2f8d5f5901ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012319856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4012319856 |
Directory | /workspace/27.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/27.i2c_host_stretch_timeout.2048766454 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 533357730 ps |
CPU time | 9.76 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:35:29 PM PDT 24 |
Peak memory | 212944 kb |
Host | smart-b10e591b-db3d-495e-a21f-bad5b80c33bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048766454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2048766454 |
Directory | /workspace/27.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/27.i2c_target_bad_addr.1029501160 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1234527404 ps |
CPU time | 5.79 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:35:21 PM PDT 24 |
Peak memory | 212936 kb |
Host | smart-6757928a-10e7-4315-88b4-d5d976f3a2a8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029501160 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1029501160 |
Directory | /workspace/27.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2059848666 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 10137788748 ps |
CPU time | 27.51 seconds |
Started | May 23 12:35:19 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 299788 kb |
Host | smart-faf6bc49-c91c-46d1-bfb0-92b928bde4a4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059848666 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.2059848666 |
Directory | /workspace/27.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1194425999 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 10515393846 ps |
CPU time | 15.19 seconds |
Started | May 23 12:35:15 PM PDT 24 |
Finished | May 23 12:35:31 PM PDT 24 |
Peak memory | 308236 kb |
Host | smart-0443f3e7-1f5e-44de-9c3d-9e95867ce6f8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194425999 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 27.i2c_target_fifo_reset_tx.1194425999 |
Directory | /workspace/27.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/27.i2c_target_hrst.2563803561 |
Short name | T1159 |
Test name | |
Test status | |
Simulation time | 811077497 ps |
CPU time | 2.72 seconds |
Started | May 23 12:35:20 PM PDT 24 |
Finished | May 23 12:35:23 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-665c8445-1e67-4d71-b812-e30a46ab0be6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563803561 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.2563803561 |
Directory | /workspace/27.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/27.i2c_target_intr_smoke.1649730515 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 3564691740 ps |
CPU time | 4.76 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:35:22 PM PDT 24 |
Peak memory | 208080 kb |
Host | smart-c0ac9d39-2f86-4e5d-bfaf-4cf7b21aac45 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649730515 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 27.i2c_target_intr_smoke.1649730515 |
Directory | /workspace/27.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/27.i2c_target_intr_stress_wr.2796016058 |
Short name | T1297 |
Test name | |
Test status | |
Simulation time | 23207603361 ps |
CPU time | 60.64 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:36:19 PM PDT 24 |
Peak memory | 949956 kb |
Host | smart-4abfc438-1b85-48b7-a882-5d391eafa29b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796016058 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2796016058 |
Directory | /workspace/27.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/27.i2c_target_smoke.1752849167 |
Short name | T1135 |
Test name | |
Test status | |
Simulation time | 4437514199 ps |
CPU time | 16.64 seconds |
Started | May 23 12:35:19 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-08caf24b-e9f1-4512-85f1-1b00bc6e5aa3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752849167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta rget_smoke.1752849167 |
Directory | /workspace/27.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/27.i2c_target_stress_rd.2877540020 |
Short name | T1173 |
Test name | |
Test status | |
Simulation time | 11493555082 ps |
CPU time | 11.19 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:35:31 PM PDT 24 |
Peak memory | 213864 kb |
Host | smart-8e9e768a-4066-4d07-a286-ee646825410d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877540020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2 c_target_stress_rd.2877540020 |
Directory | /workspace/27.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/27.i2c_target_stress_wr.2571696829 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 34858617772 ps |
CPU time | 349.23 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:41:07 PM PDT 24 |
Peak memory | 3609940 kb |
Host | smart-f5c337b3-97df-47e9-b82a-7e786188fe09 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571696829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2 c_target_stress_wr.2571696829 |
Directory | /workspace/27.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/27.i2c_target_stretch.1113522249 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 39725838252 ps |
CPU time | 914.38 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:50:33 PM PDT 24 |
Peak memory | 2372492 kb |
Host | smart-8d420a51-8110-426f-93cf-4f572ede0644 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113522249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ target_stretch.1113522249 |
Directory | /workspace/27.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/27.i2c_target_timeout.2631469264 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 5230795240 ps |
CPU time | 6.67 seconds |
Started | May 23 12:35:15 PM PDT 24 |
Finished | May 23 12:35:23 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-f7d3d898-1bdf-4171-b518-c73cc3af78f8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631469264 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.i2c_target_timeout.2631469264 |
Directory | /workspace/27.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/28.i2c_alert_test.3767024416 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 15035280 ps |
CPU time | 0.61 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:35:30 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-d5fc63e2-2eb8-4ea3-9933-269bfa4a039c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767024416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3767024416 |
Directory | /workspace/28.i2c_alert_test/latest |
Test location | /workspace/coverage/default/28.i2c_host_error_intr.2713988840 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 87856302 ps |
CPU time | 1.21 seconds |
Started | May 23 12:35:19 PM PDT 24 |
Finished | May 23 12:35:21 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-7feb76d3-b76b-4f7d-9408-a295b9ecf960 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713988840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2713988840 |
Directory | /workspace/28.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.149617034 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2616249668 ps |
CPU time | 20.73 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:35:38 PM PDT 24 |
Peak memory | 291800 kb |
Host | smart-e013f73e-5521-4bf6-b6ff-c466ca548694 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149617034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt y.149617034 |
Directory | /workspace/28.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_full.2097892714 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 4543917504 ps |
CPU time | 65.11 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:36:20 PM PDT 24 |
Peak memory | 653196 kb |
Host | smart-0d431c14-11e0-4010-80fc-59f8c5e5f63b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097892714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2097892714 |
Directory | /workspace/28.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_overflow.4038281533 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 2042851460 ps |
CPU time | 158.47 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:37:57 PM PDT 24 |
Peak memory | 712660 kb |
Host | smart-202dcd75-c37d-4e13-8922-9e05bd237bf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038281533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4038281533 |
Directory | /workspace/28.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.4079138099 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 170620086 ps |
CPU time | 0.78 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:35:19 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-78c1859c-15c6-4ce7-ac05-605275491f3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079138099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f mt.4079138099 |
Directory | /workspace/28.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_reset_rx.383732376 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 348779014 ps |
CPU time | 4.18 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:35:22 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-b67473f5-3d61-4fd3-9e36-340fc0bd5164 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383732376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx. 383732376 |
Directory | /workspace/28.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/28.i2c_host_fifo_watermark.1409488358 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 4984895032 ps |
CPU time | 119.69 seconds |
Started | May 23 12:35:15 PM PDT 24 |
Finished | May 23 12:37:16 PM PDT 24 |
Peak memory | 1381276 kb |
Host | smart-9fe7535c-829b-40a6-991e-488d0c2dde94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409488358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1409488358 |
Directory | /workspace/28.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/28.i2c_host_may_nack.4247260083 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 475239205 ps |
CPU time | 6.6 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-9079142e-4e25-4555-9690-a042e936aac2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247260083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.4247260083 |
Directory | /workspace/28.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/28.i2c_host_mode_toggle.3282241347 |
Short name | T1176 |
Test name | |
Test status | |
Simulation time | 11668156850 ps |
CPU time | 33.37 seconds |
Started | May 23 12:35:33 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 344520 kb |
Host | smart-595160e1-ba36-44af-b22d-08e5b78435db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282241347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3282241347 |
Directory | /workspace/28.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/28.i2c_host_override.3909043394 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 170961557 ps |
CPU time | 0.71 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:35:16 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-5e6f6997-8c9c-4beb-874a-b99393d950bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909043394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3909043394 |
Directory | /workspace/28.i2c_host_override/latest |
Test location | /workspace/coverage/default/28.i2c_host_perf.4028913276 |
Short name | T1306 |
Test name | |
Test status | |
Simulation time | 15633272517 ps |
CPU time | 34.33 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:35:50 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-30bdfdc2-38b0-493a-85c1-47289c79129e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028913276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4028913276 |
Directory | /workspace/28.i2c_host_perf/latest |
Test location | /workspace/coverage/default/28.i2c_host_smoke.3134326793 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 4028095926 ps |
CPU time | 50.84 seconds |
Started | May 23 12:35:14 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 310480 kb |
Host | smart-ebe7ca15-b1d1-4930-a985-ba9c34e855e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134326793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3134326793 |
Directory | /workspace/28.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/28.i2c_host_stretch_timeout.2748522546 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 973887541 ps |
CPU time | 18.72 seconds |
Started | May 23 12:35:19 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 228764 kb |
Host | smart-240a5f10-7e82-408b-ba57-b8788ba09069 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748522546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2748522546 |
Directory | /workspace/28.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/28.i2c_target_bad_addr.958869670 |
Short name | T1254 |
Test name | |
Test status | |
Simulation time | 1187113967 ps |
CPU time | 3.98 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:36 PM PDT 24 |
Peak memory | 213016 kb |
Host | smart-3aea9741-13b3-43b3-8ea8-f72c08014aa6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958869670 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.958869670 |
Directory | /workspace/28.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2899011177 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 11952695191 ps |
CPU time | 4.01 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:35:23 PM PDT 24 |
Peak memory | 214120 kb |
Host | smart-04a6a9f3-db8b-4aa5-b750-19c15fa85aa2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899011177 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.2899011177 |
Directory | /workspace/28.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/28.i2c_target_fifo_reset_tx.4236738369 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 11107249809 ps |
CPU time | 5.7 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 233756 kb |
Host | smart-dab900c2-910b-4cef-8a5e-e58ae8ceef3e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236738369 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 28.i2c_target_fifo_reset_tx.4236738369 |
Directory | /workspace/28.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/28.i2c_target_hrst.373353288 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 3408942365 ps |
CPU time | 2.94 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-35625d21-7c53-4d1c-ab0c-4ee293f9d42c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373353288 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.i2c_target_hrst.373353288 |
Directory | /workspace/28.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/28.i2c_target_intr_smoke.2749392818 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 3412421935 ps |
CPU time | 4.77 seconds |
Started | May 23 12:35:17 PM PDT 24 |
Finished | May 23 12:35:24 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-5a4beb42-d2df-4758-8e28-5e2bda746d41 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749392818 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 28.i2c_target_intr_smoke.2749392818 |
Directory | /workspace/28.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/28.i2c_target_intr_stress_wr.426756898 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 24213176176 ps |
CPU time | 583.38 seconds |
Started | May 23 12:35:15 PM PDT 24 |
Finished | May 23 12:45:00 PM PDT 24 |
Peak memory | 5900492 kb |
Host | smart-fc1314a5-32b8-42af-92e6-bfda9ba15884 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426756898 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.426756898 |
Directory | /workspace/28.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/28.i2c_target_smoke.2126873926 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 1155553855 ps |
CPU time | 51.6 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-35dabbc8-13b5-4607-8f42-84d7d34a35c0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126873926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta rget_smoke.2126873926 |
Directory | /workspace/28.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/28.i2c_target_stress_rd.2020466745 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 563360797 ps |
CPU time | 10.44 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:35:30 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-7a245239-e703-4327-b458-ce5eddfa9120 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020466745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2 c_target_stress_rd.2020466745 |
Directory | /workspace/28.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/28.i2c_target_stress_wr.3172474024 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 41556416083 ps |
CPU time | 625.75 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:45:45 PM PDT 24 |
Peak memory | 5264028 kb |
Host | smart-952e3c45-cb7a-4fab-ba33-e7ae4d21ad24 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172474024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2 c_target_stress_wr.3172474024 |
Directory | /workspace/28.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/28.i2c_target_stretch.246263609 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 7381492335 ps |
CPU time | 33.38 seconds |
Started | May 23 12:35:18 PM PDT 24 |
Finished | May 23 12:35:53 PM PDT 24 |
Peak memory | 597868 kb |
Host | smart-1ab69a77-f013-4aa7-8990-d586bd0ea7da |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246263609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t arget_stretch.246263609 |
Directory | /workspace/28.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/28.i2c_target_timeout.4166463064 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 7063311824 ps |
CPU time | 7.08 seconds |
Started | May 23 12:35:16 PM PDT 24 |
Finished | May 23 12:35:25 PM PDT 24 |
Peak memory | 219688 kb |
Host | smart-304b821f-a52e-4272-a8aa-4abd0f620d08 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166463064 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 28.i2c_target_timeout.4166463064 |
Directory | /workspace/28.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/29.i2c_alert_test.2898834765 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 16989573 ps |
CPU time | 0.63 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 204408 kb |
Host | smart-6d72e0dd-7062-4166-8546-ee36d71cca54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898834765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2898834765 |
Directory | /workspace/29.i2c_alert_test/latest |
Test location | /workspace/coverage/default/29.i2c_host_error_intr.1870830642 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 54392612 ps |
CPU time | 2.18 seconds |
Started | May 23 12:35:28 PM PDT 24 |
Finished | May 23 12:35:31 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-1157cbc0-be53-445e-81ec-d52ca75b41a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870830642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1870830642 |
Directory | /workspace/29.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1984168676 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 1731631962 ps |
CPU time | 12.5 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:35:45 PM PDT 24 |
Peak memory | 242580 kb |
Host | smart-8c560812-1da6-4dc2-bfd9-9b47b0a1f1d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984168676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp ty.1984168676 |
Directory | /workspace/29.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_full.3426045172 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 6115470878 ps |
CPU time | 51.6 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:36:22 PM PDT 24 |
Peak memory | 517232 kb |
Host | smart-a168ed53-b863-419f-b415-51db7745fd00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426045172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3426045172 |
Directory | /workspace/29.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_overflow.1402263519 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 3535835335 ps |
CPU time | 69.8 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 667960 kb |
Host | smart-fa28f75e-fd87-4bc7-b52e-e746243284ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402263519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1402263519 |
Directory | /workspace/29.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1161391125 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 424130549 ps |
CPU time | 0.95 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-2692defa-ab4e-4717-bc9e-218a09a6a1cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161391125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f mt.1161391125 |
Directory | /workspace/29.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_reset_rx.4147141647 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 2445426399 ps |
CPU time | 3.68 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-5fa4e73f-9154-4a9a-86d4-cc51d7fd0284 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147141647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx .4147141647 |
Directory | /workspace/29.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/29.i2c_host_fifo_watermark.1423558958 |
Short name | T1114 |
Test name | |
Test status | |
Simulation time | 12122946682 ps |
CPU time | 217.99 seconds |
Started | May 23 12:35:33 PM PDT 24 |
Finished | May 23 12:39:13 PM PDT 24 |
Peak memory | 957848 kb |
Host | smart-69711031-8723-4a93-8f30-fb633541b9bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423558958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1423558958 |
Directory | /workspace/29.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/29.i2c_host_may_nack.576302678 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 1103347989 ps |
CPU time | 4.57 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-f0189ac5-d43b-4203-a5fc-9a9991c71072 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576302678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.576302678 |
Directory | /workspace/29.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/29.i2c_host_mode_toggle.80551192 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 7268122099 ps |
CPU time | 89.82 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 453216 kb |
Host | smart-b2bcfd3f-1830-4710-b3a5-7b92a88e44dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80551192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.80551192 |
Directory | /workspace/29.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/29.i2c_host_override.4236130744 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 26348213 ps |
CPU time | 0.67 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:34 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-a516d7f1-07c9-4557-9c90-5a2ecbe875ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236130744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4236130744 |
Directory | /workspace/29.i2c_host_override/latest |
Test location | /workspace/coverage/default/29.i2c_host_perf.1478028772 |
Short name | T1119 |
Test name | |
Test status | |
Simulation time | 12847521019 ps |
CPU time | 131.51 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:37:45 PM PDT 24 |
Peak memory | 239168 kb |
Host | smart-897d8b20-5f0c-4649-82a9-ab985e0a0f19 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478028772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1478028772 |
Directory | /workspace/29.i2c_host_perf/latest |
Test location | /workspace/coverage/default/29.i2c_host_smoke.2830256241 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 7011572823 ps |
CPU time | 76.92 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 347476 kb |
Host | smart-bf5a35e2-d146-4bd1-bb5d-ab57f9a22170 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830256241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2830256241 |
Directory | /workspace/29.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/29.i2c_host_stretch_timeout.4053041564 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 782398385 ps |
CPU time | 14.78 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:47 PM PDT 24 |
Peak memory | 216052 kb |
Host | smart-a67809c1-bbaa-454b-b451-9b39871d5e99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053041564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4053041564 |
Directory | /workspace/29.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/29.i2c_target_bad_addr.3436011500 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 2295989582 ps |
CPU time | 5.49 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:37 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-8db03aab-9cfb-4126-9e2f-9fcd39851f51 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436011500 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3436011500 |
Directory | /workspace/29.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/29.i2c_target_fifo_reset_acq.847978901 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 10448526278 ps |
CPU time | 12.64 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:44 PM PDT 24 |
Peak memory | 266476 kb |
Host | smart-bf5b8435-f1f7-4c78-97c1-b9a906298179 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847978901 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 29.i2c_target_fifo_reset_acq.847978901 |
Directory | /workspace/29.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/29.i2c_target_fifo_reset_tx.360895158 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 10071042855 ps |
CPU time | 64.61 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 546420 kb |
Host | smart-726151b1-d9df-498a-a764-b743e259b045 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360895158 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.i2c_target_fifo_reset_tx.360895158 |
Directory | /workspace/29.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/29.i2c_target_hrst.638457050 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 383097386 ps |
CPU time | 2.36 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:35:33 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-378147b4-83b8-4dd2-be4e-25bc4af86d8b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638457050 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.i2c_target_hrst.638457050 |
Directory | /workspace/29.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/29.i2c_target_intr_smoke.679169532 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 1200699009 ps |
CPU time | 6.03 seconds |
Started | May 23 12:35:28 PM PDT 24 |
Finished | May 23 12:35:35 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-a4b1cada-d52c-4ed9-963b-9b019f5714a6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679169532 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.679169532 |
Directory | /workspace/29.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/29.i2c_target_intr_stress_wr.2084477358 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 17263635680 ps |
CPU time | 5.57 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-b04aabe0-567d-41fc-a9b0-ca84d751e82b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084477358 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2084477358 |
Directory | /workspace/29.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/29.i2c_target_smoke.1058603964 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 5598531164 ps |
CPU time | 18.98 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:35:50 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-1a1bd5fd-1070-4e56-84fa-2994551630c4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058603964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta rget_smoke.1058603964 |
Directory | /workspace/29.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/29.i2c_target_stress_rd.319476620 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 2981069593 ps |
CPU time | 14.3 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 209132 kb |
Host | smart-085f8f84-2c03-466b-ae74-b2d1b35ef3d2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319476620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c _target_stress_rd.319476620 |
Directory | /workspace/29.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/29.i2c_target_stress_wr.3843276798 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 17682310743 ps |
CPU time | 9.89 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:35:41 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-a716d797-4d34-45cf-9435-f3992de0f7bb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843276798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2 c_target_stress_wr.3843276798 |
Directory | /workspace/29.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/29.i2c_target_stretch.1733533470 |
Short name | T1339 |
Test name | |
Test status | |
Simulation time | 18159630299 ps |
CPU time | 282.03 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:40:15 PM PDT 24 |
Peak memory | 2114764 kb |
Host | smart-76ebcb7b-63bd-4f14-bb12-a34cd1d0ad55 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733533470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ target_stretch.1733533470 |
Directory | /workspace/29.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/29.i2c_target_timeout.3318459678 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 4120133058 ps |
CPU time | 7.1 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 221204 kb |
Host | smart-05c09ea6-43a8-461d-8ce8-e35215725fa0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318459678 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.i2c_target_timeout.3318459678 |
Directory | /workspace/29.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/3.i2c_alert_test.1077165580 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 45201302 ps |
CPU time | 0.59 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:49 PM PDT 24 |
Peak memory | 204468 kb |
Host | smart-04fa79c9-9021-4db9-9750-84d141a65bc1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077165580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1077165580 |
Directory | /workspace/3.i2c_alert_test/latest |
Test location | /workspace/coverage/default/3.i2c_host_error_intr.152766740 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 362145237 ps |
CPU time | 14 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:33:03 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-363c0284-a5f6-4eff-8dba-3d3c0b476e6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152766740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.152766740 |
Directory | /workspace/3.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1177858602 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 533967311 ps |
CPU time | 2.5 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 221472 kb |
Host | smart-9c18aec3-d6d0-4987-8269-09a3702fdf4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177858602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt y.1177858602 |
Directory | /workspace/3.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_full.1657551437 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 5041770655 ps |
CPU time | 76.04 seconds |
Started | May 23 12:32:49 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 769960 kb |
Host | smart-7c052281-03f6-4079-a560-096ee1490268 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657551437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1657551437 |
Directory | /workspace/3.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_overflow.1807275364 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3305983535 ps |
CPU time | 41.84 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:33:33 PM PDT 24 |
Peak memory | 535252 kb |
Host | smart-449a78cf-54b3-4edf-8c4e-b6fad7b0633b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807275364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1807275364 |
Directory | /workspace/3.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3198656514 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 541544435 ps |
CPU time | 1.03 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204588 kb |
Host | smart-b7c996a0-64b2-4e61-9eb6-5455cb674f5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198656514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm t.3198656514 |
Directory | /workspace/3.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1627270191 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 196205637 ps |
CPU time | 5.29 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:54 PM PDT 24 |
Peak memory | 238176 kb |
Host | smart-ef880981-b3aa-4d89-976c-691fc64bbc87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627270191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx. 1627270191 |
Directory | /workspace/3.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/3.i2c_host_fifo_watermark.199443552 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 14668177521 ps |
CPU time | 264.67 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:37:13 PM PDT 24 |
Peak memory | 1118548 kb |
Host | smart-c4adbd46-0d0b-4f5a-a297-20bd85357944 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199443552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.199443552 |
Directory | /workspace/3.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/3.i2c_host_may_nack.2233282115 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 280684645 ps |
CPU time | 11.62 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:33:00 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-2a5991c0-0c61-4a5e-9a97-e8b2dde59e3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233282115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2233282115 |
Directory | /workspace/3.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/3.i2c_host_mode_toggle.3061783989 |
Short name | T1289 |
Test name | |
Test status | |
Simulation time | 32775546094 ps |
CPU time | 38.98 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:33:28 PM PDT 24 |
Peak memory | 342912 kb |
Host | smart-0384e429-95ef-4f17-a9cf-b3930b365f16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061783989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3061783989 |
Directory | /workspace/3.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/3.i2c_host_override.242386958 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 30957344 ps |
CPU time | 0.67 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204536 kb |
Host | smart-68bd59b3-b4ce-4dd2-8c10-cb7ae35b3e38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242386958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.242386958 |
Directory | /workspace/3.i2c_host_override/latest |
Test location | /workspace/coverage/default/3.i2c_host_perf.2708961686 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1805920189 ps |
CPU time | 5.47 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:32:56 PM PDT 24 |
Peak memory | 213088 kb |
Host | smart-e4e8ef49-2de8-4f44-bac4-9120097ca93b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708961686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2708961686 |
Directory | /workspace/3.i2c_host_perf/latest |
Test location | /workspace/coverage/default/3.i2c_host_smoke.4077779676 |
Short name | T1137 |
Test name | |
Test status | |
Simulation time | 809500915 ps |
CPU time | 16.06 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:33:03 PM PDT 24 |
Peak memory | 284724 kb |
Host | smart-b454de83-fb66-4c9a-ad52-a66f52f03efe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077779676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.4077779676 |
Directory | /workspace/3.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/3.i2c_host_stress_all.827857962 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 9868418271 ps |
CPU time | 980.03 seconds |
Started | May 23 12:32:45 PM PDT 24 |
Finished | May 23 12:49:06 PM PDT 24 |
Peak memory | 2038024 kb |
Host | smart-c2219e73-6ea3-4567-b063-7bc55864d9ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827857962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.827857962 |
Directory | /workspace/3.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/3.i2c_host_stretch_timeout.305559499 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 2887165478 ps |
CPU time | 22.9 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:33:13 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-4fccf3a8-4cbf-4e67-873e-aa7a8a9db2cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305559499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.305559499 |
Directory | /workspace/3.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/3.i2c_sec_cm.1293456297 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 475775817 ps |
CPU time | 1.01 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:50 PM PDT 24 |
Peak memory | 222976 kb |
Host | smart-c2d68f93-eb62-4872-95de-009e8931b949 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293456297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1293456297 |
Directory | /workspace/3.i2c_sec_cm/latest |
Test location | /workspace/coverage/default/3.i2c_target_bad_addr.763044349 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 554827001 ps |
CPU time | 3.04 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-cdff0814-4cf5-47af-bf40-143fa908e562 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763044349 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.763044349 |
Directory | /workspace/3.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2173845939 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 10153345989 ps |
CPU time | 15.54 seconds |
Started | May 23 12:32:45 PM PDT 24 |
Finished | May 23 12:33:02 PM PDT 24 |
Peak memory | 279196 kb |
Host | smart-a8bde958-c492-4d7f-b705-2c965994b71d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173845939 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.2173845939 |
Directory | /workspace/3.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/3.i2c_target_fifo_reset_tx.4044237623 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 10090966390 ps |
CPU time | 68.24 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:33:56 PM PDT 24 |
Peak memory | 461512 kb |
Host | smart-c59d6199-6a86-45e8-959a-3e5002f03ba1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044237623 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.i2c_target_fifo_reset_tx.4044237623 |
Directory | /workspace/3.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/3.i2c_target_hrst.1938998433 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 1151040725 ps |
CPU time | 2.44 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:32:52 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-9d30d259-536f-4867-b119-2c8a0d63e994 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938998433 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.1938998433 |
Directory | /workspace/3.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/3.i2c_target_intr_smoke.453365828 |
Short name | T1055 |
Test name | |
Test status | |
Simulation time | 2098607035 ps |
CPU time | 4.47 seconds |
Started | May 23 12:32:45 PM PDT 24 |
Finished | May 23 12:32:50 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-5d8983aa-3ed2-4669-a8ee-500b311a6276 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453365828 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.453365828 |
Directory | /workspace/3.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/3.i2c_target_intr_stress_wr.229556523 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 7107738636 ps |
CPU time | 85.96 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:34:16 PM PDT 24 |
Peak memory | 1836292 kb |
Host | smart-e8efa409-63d0-402b-8004-13af95016d2c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229556523 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.229556523 |
Directory | /workspace/3.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/3.i2c_target_smoke.517893434 |
Short name | T1195 |
Test name | |
Test status | |
Simulation time | 2039369070 ps |
CPU time | 14.53 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-152f4f6b-4b66-4295-bf06-04ea3714b725 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517893434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ et_smoke.517893434 |
Directory | /workspace/3.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/3.i2c_target_stress_rd.366036085 |
Short name | T1158 |
Test name | |
Test status | |
Simulation time | 819152243 ps |
CPU time | 10.35 seconds |
Started | May 23 12:32:50 PM PDT 24 |
Finished | May 23 12:33:02 PM PDT 24 |
Peak memory | 207156 kb |
Host | smart-9280aefb-9017-448a-866a-60869110a8a1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366036085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ target_stress_rd.366036085 |
Directory | /workspace/3.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/3.i2c_target_stress_wr.1952552898 |
Short name | T1085 |
Test name | |
Test status | |
Simulation time | 31049783769 ps |
CPU time | 244.25 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:36:54 PM PDT 24 |
Peak memory | 2791156 kb |
Host | smart-eaa0e7c1-76e4-4c5a-8dd6-e03e0212b74b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952552898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c _target_stress_wr.1952552898 |
Directory | /workspace/3.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/3.i2c_target_timeout.216599692 |
Short name | T1304 |
Test name | |
Test status | |
Simulation time | 1485900418 ps |
CPU time | 7.65 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:55 PM PDT 24 |
Peak memory | 221128 kb |
Host | smart-f34e0ee5-10d7-4180-b4ce-e25a51005fcb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216599692 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.i2c_target_timeout.216599692 |
Directory | /workspace/3.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/30.i2c_alert_test.3776991888 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 90710738 ps |
CPU time | 0.64 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:45 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-5d6f41aa-939e-4c0e-a92b-f18c746d82df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776991888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3776991888 |
Directory | /workspace/30.i2c_alert_test/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1853047988 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 796283467 ps |
CPU time | 11.64 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:43 PM PDT 24 |
Peak memory | 251720 kb |
Host | smart-f3a72037-bee5-4a59-8f81-5c9212b4686a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853047988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp ty.1853047988 |
Directory | /workspace/30.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_full.3106831821 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 3995500979 ps |
CPU time | 222.72 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:39:17 PM PDT 24 |
Peak memory | 901892 kb |
Host | smart-6b35dc81-763c-4a3b-b44f-fc05ccb39267 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106831821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3106831821 |
Directory | /workspace/30.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_overflow.1436648103 |
Short name | T1276 |
Test name | |
Test status | |
Simulation time | 9147665994 ps |
CPU time | 69.74 seconds |
Started | May 23 12:35:28 PM PDT 24 |
Finished | May 23 12:36:38 PM PDT 24 |
Peak memory | 751208 kb |
Host | smart-5d023fd0-b115-499a-864f-7a3b2e46883c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436648103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1436648103 |
Directory | /workspace/30.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1075363253 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 114523165 ps |
CPU time | 0.83 seconds |
Started | May 23 12:35:28 PM PDT 24 |
Finished | May 23 12:35:30 PM PDT 24 |
Peak memory | 204588 kb |
Host | smart-6a7357cb-bd14-4b0e-b195-c2590f611aec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075363253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f mt.1075363253 |
Directory | /workspace/30.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2800038277 |
Short name | T1332 |
Test name | |
Test status | |
Simulation time | 190122534 ps |
CPU time | 5.36 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:39 PM PDT 24 |
Peak memory | 239752 kb |
Host | smart-1541bbdf-600f-47c9-bf0f-88c1baa81fa1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800038277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx .2800038277 |
Directory | /workspace/30.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/30.i2c_host_fifo_watermark.1595534094 |
Short name | T1117 |
Test name | |
Test status | |
Simulation time | 15452227980 ps |
CPU time | 370.26 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:41:44 PM PDT 24 |
Peak memory | 1324576 kb |
Host | smart-f1f17ca3-ffb3-45c7-bdcc-a8bca8e3884e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595534094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1595534094 |
Directory | /workspace/30.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/30.i2c_host_may_nack.1537193463 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 1063466889 ps |
CPU time | 3.42 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:49 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-be1f5214-677e-40c7-bea5-118e44959f57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537193463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1537193463 |
Directory | /workspace/30.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/30.i2c_host_mode_toggle.75694900 |
Short name | T1161 |
Test name | |
Test status | |
Simulation time | 4274059895 ps |
CPU time | 109.36 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:37:32 PM PDT 24 |
Peak memory | 445652 kb |
Host | smart-9f6db36b-0d96-421f-8839-12f9f8bced6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75694900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.75694900 |
Directory | /workspace/30.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/30.i2c_host_override.1341894702 |
Short name | T1235 |
Test name | |
Test status | |
Simulation time | 43191371 ps |
CPU time | 0.66 seconds |
Started | May 23 12:35:30 PM PDT 24 |
Finished | May 23 12:35:33 PM PDT 24 |
Peak memory | 204456 kb |
Host | smart-52ffa907-c82c-4665-8f4d-f935f6962fe0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341894702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1341894702 |
Directory | /workspace/30.i2c_host_override/latest |
Test location | /workspace/coverage/default/30.i2c_host_perf.2748467396 |
Short name | T1255 |
Test name | |
Test status | |
Simulation time | 2738765655 ps |
CPU time | 57.08 seconds |
Started | May 23 12:35:33 PM PDT 24 |
Finished | May 23 12:36:32 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-03845878-e65c-4f57-96fa-b16f520aef13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748467396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2748467396 |
Directory | /workspace/30.i2c_host_perf/latest |
Test location | /workspace/coverage/default/30.i2c_host_smoke.3334918239 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 1134257811 ps |
CPU time | 23.09 seconds |
Started | May 23 12:35:28 PM PDT 24 |
Finished | May 23 12:35:52 PM PDT 24 |
Peak memory | 316416 kb |
Host | smart-73bb2f5e-06d4-4faa-afb9-a180e53f4b4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334918239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3334918239 |
Directory | /workspace/30.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/30.i2c_host_stress_all.2767781063 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 12843013406 ps |
CPU time | 1016.47 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:52:31 PM PDT 24 |
Peak memory | 1162060 kb |
Host | smart-1fca5793-f7b1-4e39-8670-188eec2602aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767781063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2767781063 |
Directory | /workspace/30.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/30.i2c_host_stretch_timeout.3560705857 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 691096413 ps |
CPU time | 30.67 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:36:05 PM PDT 24 |
Peak memory | 213008 kb |
Host | smart-93555c68-ccd2-4943-b8a5-6ef981405891 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560705857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3560705857 |
Directory | /workspace/30.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/30.i2c_target_bad_addr.1212008880 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 2894908543 ps |
CPU time | 3.96 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:49 PM PDT 24 |
Peak memory | 206056 kb |
Host | smart-fa70a7de-75a7-43fb-956c-2a6cffeb9efb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212008880 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1212008880 |
Directory | /workspace/30.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1992169839 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 10166820766 ps |
CPU time | 28.4 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:36:01 PM PDT 24 |
Peak memory | 283268 kb |
Host | smart-10ab86dc-cabf-4212-bac7-c1b54a9dffe8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992169839 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.1992169839 |
Directory | /workspace/30.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/30.i2c_target_fifo_reset_tx.4279605065 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 10959326027 ps |
CPU time | 8.2 seconds |
Started | May 23 12:35:29 PM PDT 24 |
Finished | May 23 12:35:38 PM PDT 24 |
Peak memory | 258704 kb |
Host | smart-fbf4d924-d608-444b-8349-849ecb27a192 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279605065 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 30.i2c_target_fifo_reset_tx.4279605065 |
Directory | /workspace/30.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/30.i2c_target_hrst.1300889792 |
Short name | T1074 |
Test name | |
Test status | |
Simulation time | 300213346 ps |
CPU time | 2.21 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:49 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-8c4f1466-4bd8-4f02-874e-1ba05939b457 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300889792 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.1300889792 |
Directory | /workspace/30.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/30.i2c_target_intr_smoke.392833651 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 1322965507 ps |
CPU time | 6.98 seconds |
Started | May 23 12:35:33 PM PDT 24 |
Finished | May 23 12:35:42 PM PDT 24 |
Peak memory | 213132 kb |
Host | smart-5a8b2d2e-6c76-4e89-b31c-5f8ff5a6704b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392833651 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.392833651 |
Directory | /workspace/30.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/30.i2c_target_smoke.1584213285 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 3747360622 ps |
CPU time | 10.32 seconds |
Started | May 23 12:35:35 PM PDT 24 |
Finished | May 23 12:35:46 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-fa391314-4b16-4ab2-9117-cae2be91d29f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584213285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta rget_smoke.1584213285 |
Directory | /workspace/30.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/30.i2c_target_stress_rd.3060597240 |
Short name | T1180 |
Test name | |
Test status | |
Simulation time | 730196622 ps |
CPU time | 5.75 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:40 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-c9408cb8-e724-4db8-8a93-c55ff1550f27 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060597240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2 c_target_stress_rd.3060597240 |
Directory | /workspace/30.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/30.i2c_target_stress_wr.1694455704 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 13563464650 ps |
CPU time | 7.84 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:35:42 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-33d44709-bcbc-4920-a0ed-763fdcde95dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694455704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2 c_target_stress_wr.1694455704 |
Directory | /workspace/30.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/30.i2c_target_stretch.1805058104 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 36215200661 ps |
CPU time | 917.81 seconds |
Started | May 23 12:35:32 PM PDT 24 |
Finished | May 23 12:50:52 PM PDT 24 |
Peak memory | 4472772 kb |
Host | smart-dbf2bcee-41b0-4a99-a80c-eea8bf825124 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805058104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ target_stretch.1805058104 |
Directory | /workspace/30.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/30.i2c_target_timeout.2225345798 |
Short name | T1206 |
Test name | |
Test status | |
Simulation time | 1459494466 ps |
CPU time | 7.77 seconds |
Started | May 23 12:35:31 PM PDT 24 |
Finished | May 23 12:35:41 PM PDT 24 |
Peak memory | 214412 kb |
Host | smart-5c06f1cc-b866-4b0a-bd38-3228575a1023 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225345798 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.i2c_target_timeout.2225345798 |
Directory | /workspace/30.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/31.i2c_alert_test.1630599937 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 25523248 ps |
CPU time | 0.62 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 204460 kb |
Host | smart-3f5be5d2-2c08-48d1-b9de-434f86e73dd2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630599937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1630599937 |
Directory | /workspace/31.i2c_alert_test/latest |
Test location | /workspace/coverage/default/31.i2c_host_error_intr.3205547086 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 263089811 ps |
CPU time | 10.9 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:57 PM PDT 24 |
Peak memory | 238088 kb |
Host | smart-127113f9-63a9-4129-a89f-ff74402011d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205547086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3205547086 |
Directory | /workspace/31.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2033311845 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 680001794 ps |
CPU time | 6.15 seconds |
Started | May 23 12:35:41 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 279712 kb |
Host | smart-fc5e0199-d670-4227-adcc-6117338c370f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033311845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp ty.2033311845 |
Directory | /workspace/31.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_full.319881476 |
Short name | T1301 |
Test name | |
Test status | |
Simulation time | 13320578041 ps |
CPU time | 63.05 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 642988 kb |
Host | smart-a5cecbc1-9bd8-4104-9e94-f9b4ca99a668 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319881476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.319881476 |
Directory | /workspace/31.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_overflow.4139174280 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 3143887219 ps |
CPU time | 50.8 seconds |
Started | May 23 12:35:41 PM PDT 24 |
Finished | May 23 12:36:32 PM PDT 24 |
Peak memory | 575840 kb |
Host | smart-0859fb5b-c7df-4427-be6c-a4594ac0e0be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139174280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.4139174280 |
Directory | /workspace/31.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1165771039 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 183093611 ps |
CPU time | 0.95 seconds |
Started | May 23 12:35:41 PM PDT 24 |
Finished | May 23 12:35:44 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-83ac4046-46de-4acf-a0d9-0ea0792e7ddc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165771039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f mt.1165771039 |
Directory | /workspace/31.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_reset_rx.18392117 |
Short name | T1084 |
Test name | |
Test status | |
Simulation time | 805324755 ps |
CPU time | 7.57 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 226344 kb |
Host | smart-28547978-0307-456e-8673-7bae7b6284bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18392117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.18392117 |
Directory | /workspace/31.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/31.i2c_host_fifo_watermark.2329601857 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 21943693502 ps |
CPU time | 133.98 seconds |
Started | May 23 12:35:41 PM PDT 24 |
Finished | May 23 12:37:56 PM PDT 24 |
Peak memory | 1491424 kb |
Host | smart-23223096-d008-4da5-b622-0a8625eacb37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329601857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2329601857 |
Directory | /workspace/31.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/31.i2c_host_may_nack.2630311307 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 364246100 ps |
CPU time | 14.44 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-983491d1-bafe-45f6-b908-ee977237db6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630311307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2630311307 |
Directory | /workspace/31.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/31.i2c_host_mode_toggle.2388693937 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 3799987884 ps |
CPU time | 35.16 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:36:22 PM PDT 24 |
Peak memory | 347184 kb |
Host | smart-838558f0-c2f2-4b2a-b645-a601f93f2a07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388693937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2388693937 |
Directory | /workspace/31.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/31.i2c_host_override.1904861855 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 82736643 ps |
CPU time | 0.65 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:45 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-aaa81ba7-5952-4f36-b191-39f54583b1e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904861855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1904861855 |
Directory | /workspace/31.i2c_host_override/latest |
Test location | /workspace/coverage/default/31.i2c_host_perf.3169318066 |
Short name | T1182 |
Test name | |
Test status | |
Simulation time | 7032635087 ps |
CPU time | 131.3 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:37:55 PM PDT 24 |
Peak memory | 280548 kb |
Host | smart-8a40e36b-3cf5-4002-9845-52aaf06e34b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169318066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3169318066 |
Directory | /workspace/31.i2c_host_perf/latest |
Test location | /workspace/coverage/default/31.i2c_host_smoke.899887755 |
Short name | T1226 |
Test name | |
Test status | |
Simulation time | 1750823939 ps |
CPU time | 84.59 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 414180 kb |
Host | smart-8390fb84-f327-4a3e-b1c0-68815ffc0048 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899887755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.899887755 |
Directory | /workspace/31.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/31.i2c_host_stress_all.986450826 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 42958566758 ps |
CPU time | 421.74 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:42:48 PM PDT 24 |
Peak memory | 1863272 kb |
Host | smart-b1260f63-6c0e-4e69-b653-ec7590eae7d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986450826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.986450826 |
Directory | /workspace/31.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/31.i2c_host_stretch_timeout.1952683574 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 708725607 ps |
CPU time | 10.82 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 217860 kb |
Host | smart-bd212de1-b268-48b3-9ffd-d61f64bca2aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952683574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1952683574 |
Directory | /workspace/31.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/31.i2c_target_bad_addr.825385874 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 1021848844 ps |
CPU time | 3.03 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:47 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-b0a76860-7566-4eb5-a07f-36fa5d93ad68 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825385874 -assert nopostproc +U VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.825385874 |
Directory | /workspace/31.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3974799866 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 10180796945 ps |
CPU time | 15.1 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 265824 kb |
Host | smart-54ede886-ef7c-4671-b777-049b193f545b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974799866 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.3974799866 |
Directory | /workspace/31.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/31.i2c_target_fifo_reset_tx.286425786 |
Short name | T1248 |
Test name | |
Test status | |
Simulation time | 10326523207 ps |
CPU time | 12.23 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 274532 kb |
Host | smart-f944d97e-ac4a-478e-8a69-863c42838aa4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286425786 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.i2c_target_fifo_reset_tx.286425786 |
Directory | /workspace/31.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/31.i2c_target_hrst.292933861 |
Short name | T1344 |
Test name | |
Test status | |
Simulation time | 407567946 ps |
CPU time | 2.61 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-05651ead-1c31-4a03-8d06-2f05fff0cdce |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292933861 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.i2c_target_hrst.292933861 |
Directory | /workspace/31.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/31.i2c_target_intr_smoke.976087952 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 7778896649 ps |
CPU time | 5.85 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:35:54 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-857b9aed-b300-4fd6-8ca2-8d83be890315 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976087952 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.976087952 |
Directory | /workspace/31.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/31.i2c_target_intr_stress_wr.1232763195 |
Short name | T1318 |
Test name | |
Test status | |
Simulation time | 9880345203 ps |
CPU time | 7.58 seconds |
Started | May 23 12:35:41 PM PDT 24 |
Finished | May 23 12:35:49 PM PDT 24 |
Peak memory | 229036 kb |
Host | smart-01c13707-9bb1-46b7-b3af-ce8c514113a5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232763195 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1232763195 |
Directory | /workspace/31.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/31.i2c_target_smoke.2771753755 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 2597239266 ps |
CPU time | 10.07 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:56 PM PDT 24 |
Peak memory | 204288 kb |
Host | smart-feac5b82-caef-4d9e-b667-f9870cf5bb71 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771753755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta rget_smoke.2771753755 |
Directory | /workspace/31.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/31.i2c_target_stress_rd.1983448765 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 411207144 ps |
CPU time | 7.68 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:52 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-e0167b77-2166-40e9-bd8a-2e731aa83a51 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983448765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2 c_target_stress_rd.1983448765 |
Directory | /workspace/31.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/31.i2c_target_stress_wr.2318844805 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 15148142811 ps |
CPU time | 6.52 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:35:54 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-6039cac7-492e-4dd6-a60e-b010c1adc860 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318844805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2 c_target_stress_wr.2318844805 |
Directory | /workspace/31.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/31.i2c_target_stretch.1939607968 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 35228618464 ps |
CPU time | 579.42 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:45:23 PM PDT 24 |
Peak memory | 1714780 kb |
Host | smart-563d56bd-3d3d-427f-8762-26fcec7a2314 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939607968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ target_stretch.1939607968 |
Directory | /workspace/31.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/31.i2c_target_timeout.127465670 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 2296231362 ps |
CPU time | 6.37 seconds |
Started | May 23 12:35:42 PM PDT 24 |
Finished | May 23 12:35:50 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-bea72cb9-8940-48ec-8145-90e1f3387d1e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127465670 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.i2c_target_timeout.127465670 |
Directory | /workspace/31.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/32.i2c_alert_test.966804969 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 18123942 ps |
CPU time | 0.64 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-3ed54b78-a313-46a7-b46a-026ef839aa8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966804969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.966804969 |
Directory | /workspace/32.i2c_alert_test/latest |
Test location | /workspace/coverage/default/32.i2c_host_error_intr.882047142 |
Short name | T1211 |
Test name | |
Test status | |
Simulation time | 334451611 ps |
CPU time | 4.31 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 221312 kb |
Host | smart-44c02eac-7193-4cc5-b02f-a2ba6ee39e23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882047142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.882047142 |
Directory | /workspace/32.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1734112512 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 1746088450 ps |
CPU time | 6.8 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:35:52 PM PDT 24 |
Peak memory | 287276 kb |
Host | smart-639fe635-74a2-40ca-a500-b893bd0c7f01 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734112512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp ty.1734112512 |
Directory | /workspace/32.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_full.2354448751 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 1601314085 ps |
CPU time | 46.7 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:36:32 PM PDT 24 |
Peak memory | 486676 kb |
Host | smart-fac1db8b-a15c-443c-8e5c-17b411b51896 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354448751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2354448751 |
Directory | /workspace/32.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_overflow.90597128 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 2387348290 ps |
CPU time | 171.64 seconds |
Started | May 23 12:35:43 PM PDT 24 |
Finished | May 23 12:38:37 PM PDT 24 |
Peak memory | 733852 kb |
Host | smart-0093159f-e50f-4902-9e4c-c94e15e1675d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90597128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.90597128 |
Directory | /workspace/32.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.94767743 |
Short name | T1079 |
Test name | |
Test status | |
Simulation time | 81162713 ps |
CPU time | 0.87 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:47 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-d03228da-dd8d-425a-808d-792109d5cc93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94767743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt .94767743 |
Directory | /workspace/32.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1185067543 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 495714049 ps |
CPU time | 6.59 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:53 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-9ebb30f6-6227-4544-a12a-bf2d53272232 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185067543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx .1185067543 |
Directory | /workspace/32.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/32.i2c_host_fifo_watermark.660356333 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 11987397197 ps |
CPU time | 190.7 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:38:59 PM PDT 24 |
Peak memory | 889484 kb |
Host | smart-e76f06ba-3f03-447f-8e62-09cbddd3c641 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660356333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.660356333 |
Directory | /workspace/32.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/32.i2c_host_may_nack.3391745101 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 765972966 ps |
CPU time | 12.15 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-6411f62b-e669-487d-8b2a-fff02dc125fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391745101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3391745101 |
Directory | /workspace/32.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/32.i2c_host_mode_toggle.2382594741 |
Short name | T1322 |
Test name | |
Test status | |
Simulation time | 1970458129 ps |
CPU time | 87.91 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:37:15 PM PDT 24 |
Peak memory | 307040 kb |
Host | smart-f8ae1608-2a2e-43a5-a896-987ee0e501f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382594741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2382594741 |
Directory | /workspace/32.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/32.i2c_host_override.989817338 |
Short name | T1175 |
Test name | |
Test status | |
Simulation time | 34489383 ps |
CPU time | 0.61 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:47 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-e15ced06-dbfb-4885-88c2-045d23023143 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989817338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.989817338 |
Directory | /workspace/32.i2c_host_override/latest |
Test location | /workspace/coverage/default/32.i2c_host_smoke.1832267068 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 2916426940 ps |
CPU time | 22.65 seconds |
Started | May 23 12:35:47 PM PDT 24 |
Finished | May 23 12:36:11 PM PDT 24 |
Peak memory | 326444 kb |
Host | smart-d9920a18-c382-4b0c-90b9-e3f55f3e997f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832267068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1832267068 |
Directory | /workspace/32.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/32.i2c_host_stress_all.2777634123 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 39284168522 ps |
CPU time | 3321.23 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 01:31:10 PM PDT 24 |
Peak memory | 3808548 kb |
Host | smart-0cae745d-cb7a-4a0b-a8ee-d433d4be95df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777634123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2777634123 |
Directory | /workspace/32.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/32.i2c_host_stretch_timeout.3705683540 |
Short name | T1319 |
Test name | |
Test status | |
Simulation time | 520018818 ps |
CPU time | 22.4 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:36:09 PM PDT 24 |
Peak memory | 212960 kb |
Host | smart-7fe01aa2-5159-48f6-aaf2-266331e6cdb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705683540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3705683540 |
Directory | /workspace/32.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/32.i2c_target_bad_addr.4124859958 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 2622533747 ps |
CPU time | 3.7 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:35:52 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-58a1779e-d58b-4b27-98a5-7a08c361dded |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124859958 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.4124859958 |
Directory | /workspace/32.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4065084197 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 10438390813 ps |
CPU time | 13.75 seconds |
Started | May 23 12:35:47 PM PDT 24 |
Finished | May 23 12:36:03 PM PDT 24 |
Peak memory | 267456 kb |
Host | smart-bed7e56d-0eb9-44ec-b3b1-e8f7ca375a86 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065084197 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.4065084197 |
Directory | /workspace/32.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1753972795 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 10333519243 ps |
CPU time | 14.25 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 265772 kb |
Host | smart-ca870f31-e948-4602-9d8c-f034067081a1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753972795 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 32.i2c_target_fifo_reset_tx.1753972795 |
Directory | /workspace/32.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/32.i2c_target_hrst.3750277689 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 2819023936 ps |
CPU time | 2.78 seconds |
Started | May 23 12:35:46 PM PDT 24 |
Finished | May 23 12:35:51 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-4d3f0604-8d0f-4ec5-9434-b1e73e2f00df |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750277689 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.3750277689 |
Directory | /workspace/32.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/32.i2c_target_intr_smoke.2874437920 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1119526198 ps |
CPU time | 6.33 seconds |
Started | May 23 12:35:45 PM PDT 24 |
Finished | May 23 12:35:53 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-b8e73d38-41aa-4757-8511-962ab5163981 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874437920 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.i2c_target_intr_smoke.2874437920 |
Directory | /workspace/32.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/32.i2c_target_intr_stress_wr.413303545 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 10033778873 ps |
CPU time | 8.49 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 291960 kb |
Host | smart-48839f0f-3ec8-4280-9c0c-37772845826b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413303545 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.413303545 |
Directory | /workspace/32.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/32.i2c_target_smoke.4158375200 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 4873600002 ps |
CPU time | 51.5 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:36:38 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-3b2d9c77-825e-4409-9239-7a6df3e6252f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158375200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta rget_smoke.4158375200 |
Directory | /workspace/32.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/32.i2c_target_stress_rd.3454058565 |
Short name | T1190 |
Test name | |
Test status | |
Simulation time | 8095996535 ps |
CPU time | 27.24 seconds |
Started | May 23 12:35:47 PM PDT 24 |
Finished | May 23 12:36:16 PM PDT 24 |
Peak memory | 235212 kb |
Host | smart-6fdaf689-e0a4-4c00-800d-68b6211b22c8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454058565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2 c_target_stress_rd.3454058565 |
Directory | /workspace/32.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/32.i2c_target_stress_wr.1853524003 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 12058971263 ps |
CPU time | 12.29 seconds |
Started | May 23 12:35:44 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-477aacf5-5e86-4f3a-a0d0-214a1ee3bd04 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853524003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2 c_target_stress_wr.1853524003 |
Directory | /workspace/32.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/32.i2c_target_stretch.3570212331 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 26837317826 ps |
CPU time | 172.8 seconds |
Started | May 23 12:35:47 PM PDT 24 |
Finished | May 23 12:38:42 PM PDT 24 |
Peak memory | 1617792 kb |
Host | smart-d2853b83-8e2b-42ed-953e-2a77867c2fa8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570212331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ target_stretch.3570212331 |
Directory | /workspace/32.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/32.i2c_target_timeout.1162149562 |
Short name | T1244 |
Test name | |
Test status | |
Simulation time | 2782991048 ps |
CPU time | 7.07 seconds |
Started | May 23 12:35:48 PM PDT 24 |
Finished | May 23 12:35:57 PM PDT 24 |
Peak memory | 218672 kb |
Host | smart-5a807735-5435-42d5-893f-948ff5fd205e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162149562 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 32.i2c_target_timeout.1162149562 |
Directory | /workspace/32.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/33.i2c_alert_test.2927547686 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 16764649 ps |
CPU time | 0.62 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:35:55 PM PDT 24 |
Peak memory | 204564 kb |
Host | smart-d938774a-9738-49b0-b5d1-f205d345c169 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927547686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2927547686 |
Directory | /workspace/33.i2c_alert_test/latest |
Test location | /workspace/coverage/default/33.i2c_host_error_intr.201833393 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 206108464 ps |
CPU time | 1.28 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:36:01 PM PDT 24 |
Peak memory | 213092 kb |
Host | smart-5dddf376-832c-4c2f-b901-731fce506112 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201833393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.201833393 |
Directory | /workspace/33.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.827334616 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 818467803 ps |
CPU time | 9.08 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 294656 kb |
Host | smart-b32adf3f-391f-4acb-b892-62c25ad9c02e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827334616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt y.827334616 |
Directory | /workspace/33.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_full.3226378724 |
Short name | T1139 |
Test name | |
Test status | |
Simulation time | 6568783398 ps |
CPU time | 64.37 seconds |
Started | May 23 12:35:52 PM PDT 24 |
Finished | May 23 12:36:58 PM PDT 24 |
Peak memory | 681008 kb |
Host | smart-c88e8ef3-8cc1-4076-acac-f62a9f45fcd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226378724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3226378724 |
Directory | /workspace/33.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_overflow.914262472 |
Short name | T1102 |
Test name | |
Test status | |
Simulation time | 21435760232 ps |
CPU time | 84.13 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 753980 kb |
Host | smart-a9cc2684-6f99-47ce-915d-c6087589e1f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914262472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.914262472 |
Directory | /workspace/33.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3052423965 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 935901945 ps |
CPU time | 1.05 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-be055f86-95f1-4d92-ae13-26d01b203d2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052423965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f mt.3052423965 |
Directory | /workspace/33.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1278121508 |
Short name | T1047 |
Test name | |
Test status | |
Simulation time | 175956056 ps |
CPU time | 4.41 seconds |
Started | May 23 12:35:51 PM PDT 24 |
Finished | May 23 12:35:57 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-d22ed9b6-a252-4192-aa5f-6307c2591823 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278121508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx .1278121508 |
Directory | /workspace/33.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/33.i2c_host_fifo_watermark.1296596493 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 19653038883 ps |
CPU time | 126.47 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:38:01 PM PDT 24 |
Peak memory | 1403196 kb |
Host | smart-c3a6cabb-cac8-4478-aafd-7f2350bf9579 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296596493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1296596493 |
Directory | /workspace/33.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/33.i2c_host_may_nack.2656205684 |
Short name | T1188 |
Test name | |
Test status | |
Simulation time | 328588334 ps |
CPU time | 5.24 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:36:10 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-574588ba-696c-49c7-b730-c00c24e65147 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656205684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2656205684 |
Directory | /workspace/33.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/33.i2c_host_mode_toggle.3130864970 |
Short name | T1144 |
Test name | |
Test status | |
Simulation time | 2013310398 ps |
CPU time | 30.37 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:36:31 PM PDT 24 |
Peak memory | 354508 kb |
Host | smart-fa79f96b-83a0-435b-a122-16b387caf74f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130864970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.3130864970 |
Directory | /workspace/33.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/33.i2c_host_override.4080478620 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 108550692 ps |
CPU time | 0.68 seconds |
Started | May 23 12:35:55 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-78bab314-5425-4d1f-842f-ef9a5d6516bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080478620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4080478620 |
Directory | /workspace/33.i2c_host_override/latest |
Test location | /workspace/coverage/default/33.i2c_host_perf.2575499777 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 1643259592 ps |
CPU time | 3.82 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-68b0aad6-44f0-416c-b798-ddfcdd6130bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575499777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2575499777 |
Directory | /workspace/33.i2c_host_perf/latest |
Test location | /workspace/coverage/default/33.i2c_host_smoke.3333499929 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 5327959969 ps |
CPU time | 26.08 seconds |
Started | May 23 12:35:54 PM PDT 24 |
Finished | May 23 12:36:21 PM PDT 24 |
Peak memory | 285992 kb |
Host | smart-544db524-b84b-4514-9d11-f6326d524b97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333499929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3333499929 |
Directory | /workspace/33.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/33.i2c_host_stress_all.1524902512 |
Short name | T1121 |
Test name | |
Test status | |
Simulation time | 33851305628 ps |
CPU time | 1065.29 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:53:40 PM PDT 24 |
Peak memory | 2062520 kb |
Host | smart-d855674c-84bf-4254-97bb-24724560b7a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524902512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1524902512 |
Directory | /workspace/33.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/33.i2c_host_stretch_timeout.3017079353 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 1489218411 ps |
CPU time | 12.14 seconds |
Started | May 23 12:35:55 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 220628 kb |
Host | smart-4df2e33f-c5ba-4a71-bda4-b2746bfc603a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017079353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3017079353 |
Directory | /workspace/33.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/33.i2c_target_bad_addr.1447459670 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 4223452233 ps |
CPU time | 4.59 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:36:03 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-0e7867fa-12cc-4203-8698-1fa53535be78 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447459670 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1447459670 |
Directory | /workspace/33.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/33.i2c_target_fifo_reset_acq.321809763 |
Short name | T1086 |
Test name | |
Test status | |
Simulation time | 10222276643 ps |
CPU time | 9.21 seconds |
Started | May 23 12:35:55 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 236696 kb |
Host | smart-0369bb4e-6bb0-4ff1-844d-fb0cba68994e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321809763 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 33.i2c_target_fifo_reset_acq.321809763 |
Directory | /workspace/33.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3762296964 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 10094870095 ps |
CPU time | 82.46 seconds |
Started | May 23 12:35:55 PM PDT 24 |
Finished | May 23 12:37:19 PM PDT 24 |
Peak memory | 503476 kb |
Host | smart-23afe75c-da8f-4672-8ee3-e4d776c0befd |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762296964 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 33.i2c_target_fifo_reset_tx.3762296964 |
Directory | /workspace/33.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/33.i2c_target_hrst.294600928 |
Short name | T1109 |
Test name | |
Test status | |
Simulation time | 1403244798 ps |
CPU time | 2.39 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-9d68b1f4-db70-4cba-a635-314a0ac37690 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294600928 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.i2c_target_hrst.294600928 |
Directory | /workspace/33.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/33.i2c_target_intr_smoke.4109366318 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 1283639973 ps |
CPU time | 6.83 seconds |
Started | May 23 12:35:54 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 219592 kb |
Host | smart-db0dfe1a-44ab-4f81-a4c1-9bb263068f25 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109366318 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.i2c_target_intr_smoke.4109366318 |
Directory | /workspace/33.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/33.i2c_target_intr_stress_wr.4077973986 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 4829125431 ps |
CPU time | 4.33 seconds |
Started | May 23 12:36:03 PM PDT 24 |
Finished | May 23 12:36:09 PM PDT 24 |
Peak memory | 291972 kb |
Host | smart-7512eab3-d23a-48bc-872c-9d991f5ab9b0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077973986 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.4077973986 |
Directory | /workspace/33.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/33.i2c_target_smoke.2990684142 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1022951440 ps |
CPU time | 16.51 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:36:11 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-148f568f-41a5-4641-b635-176be8d98248 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990684142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta rget_smoke.2990684142 |
Directory | /workspace/33.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/33.i2c_target_stress_wr.2746355841 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 45870269695 ps |
CPU time | 113.87 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:37:53 PM PDT 24 |
Peak memory | 1707216 kb |
Host | smart-0ab7b60c-365f-4c4c-a425-74f8624f0e19 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746355841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2 c_target_stress_wr.2746355841 |
Directory | /workspace/33.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/33.i2c_target_timeout.2875327875 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 1278444978 ps |
CPU time | 8.04 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:36:06 PM PDT 24 |
Peak memory | 221232 kb |
Host | smart-da4f15b9-5a96-4134-8030-2ad1fee16357 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875327875 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.i2c_target_timeout.2875327875 |
Directory | /workspace/33.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/34.i2c_alert_test.4220997508 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 16471899 ps |
CPU time | 0.63 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 204464 kb |
Host | smart-9492749c-9ef9-435b-a769-43c0ef16e6f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220997508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.4220997508 |
Directory | /workspace/34.i2c_alert_test/latest |
Test location | /workspace/coverage/default/34.i2c_host_error_intr.2778121225 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 502102465 ps |
CPU time | 4.79 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:36:03 PM PDT 24 |
Peak memory | 230664 kb |
Host | smart-d3ac77da-9ae1-4849-8fe2-dc12f9de25a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778121225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2778121225 |
Directory | /workspace/34.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.502060282 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 353715256 ps |
CPU time | 12.34 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:36:12 PM PDT 24 |
Peak memory | 234624 kb |
Host | smart-41d99527-088b-4482-bbbd-180d7af1e29d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502060282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt y.502060282 |
Directory | /workspace/34.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_full.233219073 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 8956256346 ps |
CPU time | 73.76 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 698980 kb |
Host | smart-155fbd43-8341-47cb-ba3d-7fc8cef8704d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233219073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.233219073 |
Directory | /workspace/34.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_overflow.3405878454 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 21424314729 ps |
CPU time | 50.43 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:36:45 PM PDT 24 |
Peak memory | 630776 kb |
Host | smart-746f9013-7b15-4dea-a282-24c9a754e8fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405878454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3405878454 |
Directory | /workspace/34.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2122345458 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 120186040 ps |
CPU time | 1.02 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-fcd93354-1358-40a7-a2fe-4eb57bfb2686 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122345458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f mt.2122345458 |
Directory | /workspace/34.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1199299965 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 352345062 ps |
CPU time | 3.64 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-f2229e28-dfc2-49d2-afce-4fcc62705c4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199299965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx .1199299965 |
Directory | /workspace/34.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/34.i2c_host_fifo_watermark.661129651 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 7423952865 ps |
CPU time | 150.92 seconds |
Started | May 23 12:35:52 PM PDT 24 |
Finished | May 23 12:38:24 PM PDT 24 |
Peak memory | 1342376 kb |
Host | smart-6d17d50d-7cf8-433d-885b-158f79c8dfcc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661129651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.661129651 |
Directory | /workspace/34.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/34.i2c_host_may_nack.3933166105 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 247260881 ps |
CPU time | 3.91 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:35:58 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-6083ee70-2ece-4761-a74e-e9c647b2f5fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933166105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3933166105 |
Directory | /workspace/34.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/34.i2c_host_mode_toggle.1117026149 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 12989733181 ps |
CPU time | 23.83 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:36:29 PM PDT 24 |
Peak memory | 365808 kb |
Host | smart-d45bc4e5-bee3-4f10-a30f-cc6e85e2ca85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117026149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1117026149 |
Directory | /workspace/34.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/34.i2c_host_override.125353280 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 47689691 ps |
CPU time | 0.69 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:35:59 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-f5be2b4a-1f85-4df7-af52-e592853ef780 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125353280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.125353280 |
Directory | /workspace/34.i2c_host_override/latest |
Test location | /workspace/coverage/default/34.i2c_host_perf.3959571681 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 2885561095 ps |
CPU time | 121.71 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:38:00 PM PDT 24 |
Peak memory | 270128 kb |
Host | smart-337a981d-4acf-4dd5-89cd-c218a7db2ee3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959571681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3959571681 |
Directory | /workspace/34.i2c_host_perf/latest |
Test location | /workspace/coverage/default/34.i2c_host_smoke.205323222 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 1668586075 ps |
CPU time | 74.01 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:37:14 PM PDT 24 |
Peak memory | 287608 kb |
Host | smart-c71a4eae-4261-49d3-8cfb-ff4aa609ac43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205323222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.205323222 |
Directory | /workspace/34.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/34.i2c_host_stress_all.1415829418 |
Short name | T1153 |
Test name | |
Test status | |
Simulation time | 8030665843 ps |
CPU time | 680.98 seconds |
Started | May 23 12:36:03 PM PDT 24 |
Finished | May 23 12:47:25 PM PDT 24 |
Peak memory | 1231720 kb |
Host | smart-f84f03c9-4c00-4759-92f6-55a442a25c6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415829418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1415829418 |
Directory | /workspace/34.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/34.i2c_host_stretch_timeout.1524454251 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 662209225 ps |
CPU time | 12.64 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:36:13 PM PDT 24 |
Peak memory | 220848 kb |
Host | smart-cb273e50-6448-4631-ab6f-17e958999ef3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524454251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1524454251 |
Directory | /workspace/34.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/34.i2c_target_bad_addr.2840569431 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 524444984 ps |
CPU time | 2.68 seconds |
Started | May 23 12:36:03 PM PDT 24 |
Finished | May 23 12:36:07 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-eee21063-6787-4138-822d-63a9e47ac5ae |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840569431 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2840569431 |
Directory | /workspace/34.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1386664436 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 10158673919 ps |
CPU time | 45.04 seconds |
Started | May 23 12:35:54 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 438244 kb |
Host | smart-552e022e-91f7-4e65-bac8-354050da1328 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386664436 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.1386664436 |
Directory | /workspace/34.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/34.i2c_target_fifo_reset_tx.538100845 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 10046917584 ps |
CPU time | 83 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 560004 kb |
Host | smart-5747d5ca-2612-4dd2-9fc6-69fba601e3f3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538100845 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.i2c_target_fifo_reset_tx.538100845 |
Directory | /workspace/34.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/34.i2c_target_hrst.1453064239 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 750382287 ps |
CPU time | 2.5 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:36:08 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-f758442c-807e-4e2f-b2a3-992001da268b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453064239 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_hrst.1453064239 |
Directory | /workspace/34.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/34.i2c_target_intr_smoke.216266442 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 1011800670 ps |
CPU time | 5.19 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:36:00 PM PDT 24 |
Peak memory | 208364 kb |
Host | smart-600cea13-7cb8-453e-98c6-ca27e703d15a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216266442 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.216266442 |
Directory | /workspace/34.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/34.i2c_target_intr_stress_wr.3543876285 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 5626571473 ps |
CPU time | 7.14 seconds |
Started | May 23 12:36:03 PM PDT 24 |
Finished | May 23 12:36:12 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-0359229e-5a5a-4e15-8a32-8b5b5d4e75c4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543876285 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3543876285 |
Directory | /workspace/34.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/34.i2c_target_smoke.2851054317 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 930986757 ps |
CPU time | 13.88 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:36:12 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-71c7530f-7023-4771-a9d1-ef00a60f9486 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851054317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta rget_smoke.2851054317 |
Directory | /workspace/34.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/34.i2c_target_stress_rd.1916471404 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 6428517360 ps |
CPU time | 24.21 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:36:24 PM PDT 24 |
Peak memory | 232720 kb |
Host | smart-a90bcaf4-d115-4349-b4dc-2982152267f5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916471404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2 c_target_stress_rd.1916471404 |
Directory | /workspace/34.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/34.i2c_target_stress_wr.1222038620 |
Short name | T1309 |
Test name | |
Test status | |
Simulation time | 23711084638 ps |
CPU time | 31.27 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 522480 kb |
Host | smart-d1e9b0c7-b77e-4111-8dfe-3c0e6aa1d838 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222038620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2 c_target_stress_wr.1222038620 |
Directory | /workspace/34.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/34.i2c_target_stretch.2369538548 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 21198800280 ps |
CPU time | 164.3 seconds |
Started | May 23 12:36:04 PM PDT 24 |
Finished | May 23 12:38:49 PM PDT 24 |
Peak memory | 1357212 kb |
Host | smart-f99c92ec-031f-41f8-b705-db96c011273a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369538548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ target_stretch.2369538548 |
Directory | /workspace/34.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/34.i2c_target_timeout.151572908 |
Short name | T1048 |
Test name | |
Test status | |
Simulation time | 7362946927 ps |
CPU time | 6.96 seconds |
Started | May 23 12:35:55 PM PDT 24 |
Finished | May 23 12:36:03 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-298f33fe-dc04-4658-9e87-4e76de4969d2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151572908 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 34.i2c_target_timeout.151572908 |
Directory | /workspace/34.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/35.i2c_alert_test.182146630 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 16410781 ps |
CPU time | 0.63 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:36:14 PM PDT 24 |
Peak memory | 204444 kb |
Host | smart-e82a4ddb-78ef-4281-aba6-c042ccafca23 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182146630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.182146630 |
Directory | /workspace/35.i2c_alert_test/latest |
Test location | /workspace/coverage/default/35.i2c_host_error_intr.1606026968 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 84128069 ps |
CPU time | 1.33 seconds |
Started | May 23 12:36:07 PM PDT 24 |
Finished | May 23 12:36:10 PM PDT 24 |
Peak memory | 213120 kb |
Host | smart-05e6bab5-c5bc-4fef-b1a2-af90b2a56c5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606026968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1606026968 |
Directory | /workspace/35.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.577704494 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 1334629240 ps |
CPU time | 14.52 seconds |
Started | May 23 12:35:53 PM PDT 24 |
Finished | May 23 12:36:09 PM PDT 24 |
Peak memory | 262920 kb |
Host | smart-13ee046b-9fbc-4559-9c28-a6239be1c9a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577704494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt y.577704494 |
Directory | /workspace/35.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_full.2296838180 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 12048018880 ps |
CPU time | 165.53 seconds |
Started | May 23 12:35:56 PM PDT 24 |
Finished | May 23 12:38:43 PM PDT 24 |
Peak memory | 726948 kb |
Host | smart-e73895c3-c694-4e12-878d-e17ee3e500cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296838180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2296838180 |
Directory | /workspace/35.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_overflow.2656113305 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 3376145896 ps |
CPU time | 51.98 seconds |
Started | May 23 12:35:58 PM PDT 24 |
Finished | May 23 12:36:52 PM PDT 24 |
Peak memory | 552880 kb |
Host | smart-ca82a65e-ad94-4e6c-a5d1-f875292a9bb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656113305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2656113305 |
Directory | /workspace/35.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.894575699 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 75961238 ps |
CPU time | 0.87 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-61fb9d15-3a99-4792-b5e2-7f0284611812 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894575699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm t.894575699 |
Directory | /workspace/35.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2774876653 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 1124319666 ps |
CPU time | 3.81 seconds |
Started | May 23 12:35:52 PM PDT 24 |
Finished | May 23 12:35:57 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-f18ecdf5-3bca-4777-b549-58454c589447 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774876653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx .2774876653 |
Directory | /workspace/35.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/35.i2c_host_fifo_watermark.1254190180 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 22643709672 ps |
CPU time | 152.37 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:38:34 PM PDT 24 |
Peak memory | 1588180 kb |
Host | smart-d231fafc-01c3-4dd1-a0ba-326d17157e6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254190180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1254190180 |
Directory | /workspace/35.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/35.i2c_host_may_nack.2559385064 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 2065570187 ps |
CPU time | 19.92 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:31 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-56907052-e4ef-4220-8162-938f868632ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559385064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2559385064 |
Directory | /workspace/35.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/35.i2c_host_mode_toggle.2585646601 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 3920195612 ps |
CPU time | 82.66 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:37:36 PM PDT 24 |
Peak memory | 306640 kb |
Host | smart-202c9159-da42-4470-8b59-2f48980062c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585646601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2585646601 |
Directory | /workspace/35.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/35.i2c_host_override.1630018316 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 28204516 ps |
CPU time | 0.66 seconds |
Started | May 23 12:35:59 PM PDT 24 |
Finished | May 23 12:36:02 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-8be40fba-727d-4968-b346-39f151a9860f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630018316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1630018316 |
Directory | /workspace/35.i2c_host_override/latest |
Test location | /workspace/coverage/default/35.i2c_host_perf.4139364061 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 594670724 ps |
CPU time | 27.21 seconds |
Started | May 23 12:35:52 PM PDT 24 |
Finished | May 23 12:36:20 PM PDT 24 |
Peak memory | 277416 kb |
Host | smart-7f33c208-b8cf-4cb0-8784-d256390e5b25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139364061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4139364061 |
Directory | /workspace/35.i2c_host_perf/latest |
Test location | /workspace/coverage/default/35.i2c_host_smoke.2984883540 |
Short name | T1080 |
Test name | |
Test status | |
Simulation time | 1926890173 ps |
CPU time | 92.91 seconds |
Started | May 23 12:35:57 PM PDT 24 |
Finished | May 23 12:37:32 PM PDT 24 |
Peak memory | 354072 kb |
Host | smart-f0ea74c9-2b07-440c-a752-3e8db948eb08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984883540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2984883540 |
Directory | /workspace/35.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/35.i2c_host_stretch_timeout.1170959459 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 635098678 ps |
CPU time | 27.96 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 212936 kb |
Host | smart-892aa77b-7508-48ea-90b2-232f1a806981 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170959459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1170959459 |
Directory | /workspace/35.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/35.i2c_target_bad_addr.1312640627 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 745885201 ps |
CPU time | 3.77 seconds |
Started | May 23 12:36:07 PM PDT 24 |
Finished | May 23 12:36:13 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-5cf08e1d-3304-4275-ac86-3bf6231ce87f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312640627 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1312640627 |
Directory | /workspace/35.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/35.i2c_target_fifo_reset_acq.64161504 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 10133003164 ps |
CPU time | 16.36 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:26 PM PDT 24 |
Peak memory | 280612 kb |
Host | smart-b41a80dc-f1a6-48a8-a18b-2fd4e9830778 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64161504 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.i2c_target_fifo_reset_acq.64161504 |
Directory | /workspace/35.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1330009027 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 10047053636 ps |
CPU time | 75.29 seconds |
Started | May 23 12:36:07 PM PDT 24 |
Finished | May 23 12:37:24 PM PDT 24 |
Peak memory | 482292 kb |
Host | smart-a4090c2e-c245-446b-b382-cb7afae9a94b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330009027 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 35.i2c_target_fifo_reset_tx.1330009027 |
Directory | /workspace/35.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/35.i2c_target_hrst.822441644 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 852227258 ps |
CPU time | 3.11 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:15 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-8a656483-28da-495e-a6a1-ae854b3df1d9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822441644 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.i2c_target_hrst.822441644 |
Directory | /workspace/35.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/35.i2c_target_intr_smoke.985691770 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 9550427885 ps |
CPU time | 4.96 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:16 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-3faffd03-83af-41d0-8d1e-5cde953106ef |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985691770 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.985691770 |
Directory | /workspace/35.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/35.i2c_target_intr_stress_wr.1113904530 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 3165352742 ps |
CPU time | 3.98 seconds |
Started | May 23 12:36:07 PM PDT 24 |
Finished | May 23 12:36:13 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-b7bdbb70-f816-40e2-9cce-172cc3b5c2df |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113904530 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1113904530 |
Directory | /workspace/35.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/35.i2c_target_smoke.2220299644 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 3956364082 ps |
CPU time | 27.64 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:40 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-27bd1019-8992-42ed-909e-6d18c061bdd4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220299644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta rget_smoke.2220299644 |
Directory | /workspace/35.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/35.i2c_target_stress_rd.277680275 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 981556019 ps |
CPU time | 38.95 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:49 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-42bdb971-e671-4d5d-adef-fb417133c602 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277680275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c _target_stress_rd.277680275 |
Directory | /workspace/35.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/35.i2c_target_stress_wr.2644486768 |
Short name | T1345 |
Test name | |
Test status | |
Simulation time | 62551393624 ps |
CPU time | 47.04 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 776152 kb |
Host | smart-08f790b6-82a1-414f-80f8-0e889683656a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644486768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2 c_target_stress_wr.2644486768 |
Directory | /workspace/35.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/35.i2c_target_stretch.1249025922 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 8918151135 ps |
CPU time | 271.04 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:40:45 PM PDT 24 |
Peak memory | 2318812 kb |
Host | smart-90649a6e-b21e-430e-bf64-8a923bfd102d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249025922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ target_stretch.1249025922 |
Directory | /workspace/35.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/35.i2c_target_timeout.2239559988 |
Short name | T1072 |
Test name | |
Test status | |
Simulation time | 7002970956 ps |
CPU time | 7.17 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:36:21 PM PDT 24 |
Peak memory | 219200 kb |
Host | smart-04984664-56fb-4638-8603-0bfb442a0d4e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239559988 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 35.i2c_target_timeout.2239559988 |
Directory | /workspace/35.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/36.i2c_alert_test.4081963282 |
Short name | T1065 |
Test name | |
Test status | |
Simulation time | 45549253 ps |
CPU time | 0.62 seconds |
Started | May 23 12:36:13 PM PDT 24 |
Finished | May 23 12:36:17 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-1efa51d4-5a6d-4890-9b69-04a421eb63bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081963282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.4081963282 |
Directory | /workspace/36.i2c_alert_test/latest |
Test location | /workspace/coverage/default/36.i2c_host_error_intr.3949197203 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 196768583 ps |
CPU time | 1.63 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:36:16 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-5165f6f8-11f2-4c48-8dac-0a99a29465a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949197203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3949197203 |
Directory | /workspace/36.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2084412109 |
Short name | T1126 |
Test name | |
Test status | |
Simulation time | 2089406236 ps |
CPU time | 8.36 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:22 PM PDT 24 |
Peak memory | 274348 kb |
Host | smart-ff5c8d7e-e82f-42f2-bcb2-ef35f3263d50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084412109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp ty.2084412109 |
Directory | /workspace/36.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_full.1365417494 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 1807034906 ps |
CPU time | 40.78 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:52 PM PDT 24 |
Peak memory | 358992 kb |
Host | smart-c0719944-ab50-419e-94d4-6cb36e93b9ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365417494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1365417494 |
Directory | /workspace/36.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_overflow.450392389 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 8746974932 ps |
CPU time | 175.84 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:39:09 PM PDT 24 |
Peak memory | 748124 kb |
Host | smart-35f802cb-2aa7-4d96-b2dd-4443e5029840 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450392389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.450392389 |
Directory | /workspace/36.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.4113875881 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 368908422 ps |
CPU time | 0.9 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:13 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-948eab92-bdf0-45ef-96dc-e8c902f21735 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113875881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f mt.4113875881 |
Directory | /workspace/36.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2558561297 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 167413067 ps |
CPU time | 9.31 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:20 PM PDT 24 |
Peak memory | 233684 kb |
Host | smart-6568fb52-ef9e-449d-bbc6-a4f806d57ad6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558561297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx .2558561297 |
Directory | /workspace/36.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/36.i2c_host_fifo_watermark.210262332 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 4667899897 ps |
CPU time | 338.71 seconds |
Started | May 23 12:36:12 PM PDT 24 |
Finished | May 23 12:41:54 PM PDT 24 |
Peak memory | 1234016 kb |
Host | smart-82359415-0284-4648-8b36-0a51dc9dd72c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210262332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.210262332 |
Directory | /workspace/36.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/36.i2c_host_mode_toggle.1568796842 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 3349222057 ps |
CPU time | 26.06 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 374748 kb |
Host | smart-03004e98-ae43-4a67-aa47-9e32df70e06c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568796842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1568796842 |
Directory | /workspace/36.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/36.i2c_host_override.3312653131 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 29216796 ps |
CPU time | 0.68 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:13 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-97deb7c8-9213-4223-aafa-b54f11f8058a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312653131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3312653131 |
Directory | /workspace/36.i2c_host_override/latest |
Test location | /workspace/coverage/default/36.i2c_host_perf.313069471 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 53048134971 ps |
CPU time | 406.71 seconds |
Started | May 23 12:36:16 PM PDT 24 |
Finished | May 23 12:43:05 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-89df991b-bc5e-4ebe-b594-c5efe42146c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313069471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.313069471 |
Directory | /workspace/36.i2c_host_perf/latest |
Test location | /workspace/coverage/default/36.i2c_host_smoke.2346395708 |
Short name | T1184 |
Test name | |
Test status | |
Simulation time | 2979608357 ps |
CPU time | 25.11 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:37 PM PDT 24 |
Peak memory | 328280 kb |
Host | smart-196dccb3-081a-40c0-b9ef-493300b37515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346395708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2346395708 |
Directory | /workspace/36.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/36.i2c_host_stress_all.645100024 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 21272773673 ps |
CPU time | 3447.87 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 01:33:42 PM PDT 24 |
Peak memory | 3518684 kb |
Host | smart-b40ed0e5-39d1-4cb1-ae27-b9b9027d354c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645100024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.645100024 |
Directory | /workspace/36.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/36.i2c_host_stretch_timeout.1860040192 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 492111209 ps |
CPU time | 9.15 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:21 PM PDT 24 |
Peak memory | 214100 kb |
Host | smart-f20b25de-e0be-4d3a-b9d9-2f8501f79af9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860040192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1860040192 |
Directory | /workspace/36.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/36.i2c_target_bad_addr.2414374320 |
Short name | T1232 |
Test name | |
Test status | |
Simulation time | 942425063 ps |
CPU time | 4.72 seconds |
Started | May 23 12:36:15 PM PDT 24 |
Finished | May 23 12:36:22 PM PDT 24 |
Peak memory | 213052 kb |
Host | smart-4e62a236-9394-4bb7-bb5a-cdb83ce2e663 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414374320 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2414374320 |
Directory | /workspace/36.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/36.i2c_target_fifo_reset_acq.4280200354 |
Short name | T1046 |
Test name | |
Test status | |
Simulation time | 10309707579 ps |
CPU time | 11.94 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:23 PM PDT 24 |
Peak memory | 257000 kb |
Host | smart-d7527489-2a94-4e7e-913c-023be780b278 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280200354 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.4280200354 |
Directory | /workspace/36.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/36.i2c_target_fifo_reset_tx.7284364 |
Short name | T1253 |
Test name | |
Test status | |
Simulation time | 10132642428 ps |
CPU time | 66.27 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:37:19 PM PDT 24 |
Peak memory | 557392 kb |
Host | smart-393990be-3ddc-4125-b1f1-8d15c2b97283 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7284364 -assert nopostproc +UVM_TESTNAME=i2c_base_t est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.i2c_target_fifo_reset_tx.7284364 |
Directory | /workspace/36.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/36.i2c_target_hrst.302768434 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 458878042 ps |
CPU time | 2.71 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:36:17 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-16ec91e1-a611-4832-b191-6d0cddbc8a51 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302768434 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.i2c_target_hrst.302768434 |
Directory | /workspace/36.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/36.i2c_target_intr_smoke.1726011336 |
Short name | T1107 |
Test name | |
Test status | |
Simulation time | 5272880025 ps |
CPU time | 5.63 seconds |
Started | May 23 12:36:09 PM PDT 24 |
Finished | May 23 12:36:18 PM PDT 24 |
Peak memory | 210024 kb |
Host | smart-d468850a-d37e-4c54-a4a3-b2023df300a8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726011336 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 36.i2c_target_intr_smoke.1726011336 |
Directory | /workspace/36.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/36.i2c_target_intr_stress_wr.2781051622 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 8004031732 ps |
CPU time | 18.58 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 298888 kb |
Host | smart-d1f81399-410d-4845-9f81-b208bce909a0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781051622 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2781051622 |
Directory | /workspace/36.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/36.i2c_target_smoke.3372337957 |
Short name | T1343 |
Test name | |
Test status | |
Simulation time | 3024657620 ps |
CPU time | 27.67 seconds |
Started | May 23 12:36:08 PM PDT 24 |
Finished | May 23 12:36:39 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-7ca5ab6d-da19-4e9e-bcd0-51c0c1ac4159 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372337957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta rget_smoke.3372337957 |
Directory | /workspace/36.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/36.i2c_target_stress_rd.560476610 |
Short name | T1108 |
Test name | |
Test status | |
Simulation time | 24537406802 ps |
CPU time | 66.22 seconds |
Started | May 23 12:36:12 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-b6d95601-92ee-4a7a-86a1-66e104768313 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560476610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c _target_stress_rd.560476610 |
Directory | /workspace/36.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/36.i2c_target_stress_wr.2530457934 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 50526152806 ps |
CPU time | 159.45 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:38:53 PM PDT 24 |
Peak memory | 1955736 kb |
Host | smart-5722f5d7-9792-4590-aa0b-b95899cbbfcb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530457934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2 c_target_stress_wr.2530457934 |
Directory | /workspace/36.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/36.i2c_target_stretch.3155505878 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 18267184974 ps |
CPU time | 1180.51 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:55:55 PM PDT 24 |
Peak memory | 4577848 kb |
Host | smart-bbe1d348-6334-45dd-aeec-8edb9b9a1992 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155505878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ target_stretch.3155505878 |
Directory | /workspace/36.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/36.i2c_target_timeout.4069586495 |
Short name | T1070 |
Test name | |
Test status | |
Simulation time | 4583465937 ps |
CPU time | 6.35 seconds |
Started | May 23 12:36:06 PM PDT 24 |
Finished | May 23 12:36:14 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-a1a973fb-fd72-4fa1-bc27-ce69ba276673 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069586495 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 36.i2c_target_timeout.4069586495 |
Directory | /workspace/36.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/37.i2c_alert_test.3376520578 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 66755291 ps |
CPU time | 0.61 seconds |
Started | May 23 12:36:24 PM PDT 24 |
Finished | May 23 12:36:27 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-ad3a9533-969a-49e8-9999-82c7974dc2d1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376520578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3376520578 |
Directory | /workspace/37.i2c_alert_test/latest |
Test location | /workspace/coverage/default/37.i2c_host_error_intr.1553866797 |
Short name | T1267 |
Test name | |
Test status | |
Simulation time | 214174620 ps |
CPU time | 7.9 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:38 PM PDT 24 |
Peak memory | 231768 kb |
Host | smart-19cfffc2-f073-4d4b-a12d-16cef7b6b3cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553866797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1553866797 |
Directory | /workspace/37.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1237717293 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 935951625 ps |
CPU time | 9.3 seconds |
Started | May 23 12:36:12 PM PDT 24 |
Finished | May 23 12:36:25 PM PDT 24 |
Peak memory | 291400 kb |
Host | smart-3cc4dee3-e1d1-4565-b51a-a6f603a0e171 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237717293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp ty.1237717293 |
Directory | /workspace/37.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_full.4215848293 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 6206774723 ps |
CPU time | 120.1 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:38:31 PM PDT 24 |
Peak memory | 623544 kb |
Host | smart-39cca184-f350-4ba9-9744-be98e99d7066 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215848293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4215848293 |
Directory | /workspace/37.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_overflow.720960785 |
Short name | T1281 |
Test name | |
Test status | |
Simulation time | 2294575035 ps |
CPU time | 69.79 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:37:25 PM PDT 24 |
Peak memory | 751044 kb |
Host | smart-d462fadd-3bd3-49e1-8652-38035736ae58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720960785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.720960785 |
Directory | /workspace/37.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2053451494 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 147023217 ps |
CPU time | 1.05 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:36:16 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-ef4f6689-4d77-4c5e-a6c4-f397a43b53cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053451494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f mt.2053451494 |
Directory | /workspace/37.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_reset_rx.4168190654 |
Short name | T1110 |
Test name | |
Test status | |
Simulation time | 207596632 ps |
CPU time | 4.23 seconds |
Started | May 23 12:36:13 PM PDT 24 |
Finished | May 23 12:36:20 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-f1448b75-b8cc-442f-8b73-61359312f414 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168190654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx .4168190654 |
Directory | /workspace/37.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/37.i2c_host_fifo_watermark.540888110 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 17996659554 ps |
CPU time | 77.42 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:37:32 PM PDT 24 |
Peak memory | 967728 kb |
Host | smart-c00a3f59-7ce9-45e9-b85e-acdf64003a43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540888110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.540888110 |
Directory | /workspace/37.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/37.i2c_host_may_nack.3190034138 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 476939912 ps |
CPU time | 19.13 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-2fa49b3f-9b92-43b7-8574-3789ed36d866 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190034138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3190034138 |
Directory | /workspace/37.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/37.i2c_host_mode_toggle.2671203335 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 2290243641 ps |
CPU time | 42.31 seconds |
Started | May 23 12:36:23 PM PDT 24 |
Finished | May 23 12:37:06 PM PDT 24 |
Peak memory | 400444 kb |
Host | smart-d2953650-c6ef-49dd-8103-bee64fe9a2cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671203335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2671203335 |
Directory | /workspace/37.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/37.i2c_host_override.3419740388 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 28078259 ps |
CPU time | 0.68 seconds |
Started | May 23 12:36:10 PM PDT 24 |
Finished | May 23 12:36:15 PM PDT 24 |
Peak memory | 204536 kb |
Host | smart-ee6a2446-f15f-4915-972b-b5730c7f78a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419740388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3419740388 |
Directory | /workspace/37.i2c_host_override/latest |
Test location | /workspace/coverage/default/37.i2c_host_perf.4201893282 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 27450774297 ps |
CPU time | 73 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:41 PM PDT 24 |
Peak memory | 291860 kb |
Host | smart-731a3e40-2aeb-4162-8969-f1ac527677c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201893282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.4201893282 |
Directory | /workspace/37.i2c_host_perf/latest |
Test location | /workspace/coverage/default/37.i2c_host_smoke.3149847173 |
Short name | T1279 |
Test name | |
Test status | |
Simulation time | 5596161686 ps |
CPU time | 23.27 seconds |
Started | May 23 12:36:11 PM PDT 24 |
Finished | May 23 12:36:38 PM PDT 24 |
Peak memory | 268944 kb |
Host | smart-f634d399-5b4b-4c84-a1fd-9b29aea7056a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149847173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3149847173 |
Directory | /workspace/37.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/37.i2c_host_stress_all.2173232778 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 28753663197 ps |
CPU time | 1967.6 seconds |
Started | May 23 12:36:23 PM PDT 24 |
Finished | May 23 01:09:12 PM PDT 24 |
Peak memory | 3919696 kb |
Host | smart-b48ef7cb-e738-43b1-8c6a-4c0e51a1f10e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173232778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2173232778 |
Directory | /workspace/37.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/37.i2c_host_stretch_timeout.272475446 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 6637615598 ps |
CPU time | 15.15 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 229272 kb |
Host | smart-8b15d548-b906-4000-8d91-08179c0c4f97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272475446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.272475446 |
Directory | /workspace/37.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/37.i2c_target_bad_addr.2969343179 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 2802488122 ps |
CPU time | 3.81 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:33 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-ed76e980-7f42-4fd2-bc5d-c8438ae42bf8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969343179 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2969343179 |
Directory | /workspace/37.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2449985641 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 10092077510 ps |
CPU time | 32.69 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:01 PM PDT 24 |
Peak memory | 387452 kb |
Host | smart-83d2ad81-a0e2-4a4e-b63c-daa800b3ac8b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449985641 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.2449985641 |
Directory | /workspace/37.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3394544587 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 10185527121 ps |
CPU time | 32.5 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:01 PM PDT 24 |
Peak memory | 332272 kb |
Host | smart-660993f6-f746-430b-a680-033ddf17d68f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394544587 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 37.i2c_target_fifo_reset_tx.3394544587 |
Directory | /workspace/37.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/37.i2c_target_hrst.3531836437 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 284388539 ps |
CPU time | 1.99 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:33 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-8d68b0d3-0c25-4786-b605-9c459764f2ac |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531836437 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.3531836437 |
Directory | /workspace/37.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/37.i2c_target_intr_smoke.3906883380 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 4205524925 ps |
CPU time | 4.69 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:31 PM PDT 24 |
Peak memory | 206072 kb |
Host | smart-03cbd9bd-6514-40e9-876b-2be3aebb2837 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906883380 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.i2c_target_intr_smoke.3906883380 |
Directory | /workspace/37.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/37.i2c_target_intr_stress_wr.1388843242 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 4918752755 ps |
CPU time | 10.07 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:37 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-a077de55-8455-4d78-a86a-7fd746e846b8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388843242 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1388843242 |
Directory | /workspace/37.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/37.i2c_target_smoke.2102499013 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 714195286 ps |
CPU time | 8.68 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:40 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-690f2628-d6bd-4801-9279-0ffeeac8a15b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102499013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta rget_smoke.2102499013 |
Directory | /workspace/37.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/37.i2c_target_stress_rd.2952645486 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 7641734615 ps |
CPU time | 25.98 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:57 PM PDT 24 |
Peak memory | 220216 kb |
Host | smart-4130be48-c514-4430-b9fb-4d6f61da43f2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952645486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2 c_target_stress_rd.2952645486 |
Directory | /workspace/37.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/37.i2c_target_stress_wr.3838527662 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 39619610372 ps |
CPU time | 194.54 seconds |
Started | May 23 12:36:24 PM PDT 24 |
Finished | May 23 12:39:41 PM PDT 24 |
Peak memory | 2516328 kb |
Host | smart-5b98f027-50ac-420c-87ae-2f67e3e41727 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838527662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2 c_target_stress_wr.3838527662 |
Directory | /workspace/37.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/37.i2c_target_stretch.901044327 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 7528357380 ps |
CPU time | 185.37 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:39:32 PM PDT 24 |
Peak memory | 1762532 kb |
Host | smart-33707d7b-95db-4da2-87f1-744ac7fe2e6b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901044327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t arget_stretch.901044327 |
Directory | /workspace/37.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/37.i2c_target_timeout.233255992 |
Short name | T1334 |
Test name | |
Test status | |
Simulation time | 1367442641 ps |
CPU time | 8.15 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 221084 kb |
Host | smart-c099ac09-b4e4-49d7-b631-25c8befbb260 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233255992 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.i2c_target_timeout.233255992 |
Directory | /workspace/37.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/38.i2c_alert_test.2937861911 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 32441353 ps |
CPU time | 0.6 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 204412 kb |
Host | smart-4137667e-bd0c-45d4-b322-7ab09454bfb9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937861911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2937861911 |
Directory | /workspace/38.i2c_alert_test/latest |
Test location | /workspace/coverage/default/38.i2c_host_error_intr.1675649592 |
Short name | T1071 |
Test name | |
Test status | |
Simulation time | 197486941 ps |
CPU time | 1.4 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-5a4fb54e-14c4-4cd9-bd1b-4e7f22c7b8de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675649592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1675649592 |
Directory | /workspace/38.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1524017764 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 2029903274 ps |
CPU time | 9.63 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 303484 kb |
Host | smart-b96c32d3-a32b-4cb1-8a31-4fc32ab7f728 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524017764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp ty.1524017764 |
Directory | /workspace/38.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_full.4113209011 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 2839460816 ps |
CPU time | 167.98 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:39:15 PM PDT 24 |
Peak memory | 616732 kb |
Host | smart-e2f3d2db-1f21-4fb6-8756-15c3d198566e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113209011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4113209011 |
Directory | /workspace/38.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_overflow.3402940472 |
Short name | T1167 |
Test name | |
Test status | |
Simulation time | 5630781343 ps |
CPU time | 41.38 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:10 PM PDT 24 |
Peak memory | 471024 kb |
Host | smart-1beecb6f-ca4d-4d3a-9bd8-b0f52d0ac95e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402940472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3402940472 |
Directory | /workspace/38.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.227446644 |
Short name | T1160 |
Test name | |
Test status | |
Simulation time | 149947021 ps |
CPU time | 1.06 seconds |
Started | May 23 12:36:22 PM PDT 24 |
Finished | May 23 12:36:24 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-5109dcfe-bc3e-4591-8cac-ab2ee89ce602 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227446644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm t.227446644 |
Directory | /workspace/38.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2684902759 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 197359270 ps |
CPU time | 10.54 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:39 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-ac066742-c7ae-4f5b-8f4b-77e3f36091c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684902759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx .2684902759 |
Directory | /workspace/38.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/38.i2c_host_fifo_watermark.917607418 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 18683865056 ps |
CPU time | 113.98 seconds |
Started | May 23 12:36:29 PM PDT 24 |
Finished | May 23 12:38:26 PM PDT 24 |
Peak memory | 1334168 kb |
Host | smart-b757eafb-98a4-4593-82bf-42932d462e3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917607418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.917607418 |
Directory | /workspace/38.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/38.i2c_host_may_nack.3038353348 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 554356592 ps |
CPU time | 7.3 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:34 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-c216a63d-6e21-42ec-8f2e-75b66f13946c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038353348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3038353348 |
Directory | /workspace/38.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/38.i2c_host_mode_toggle.1736243579 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 1310845117 ps |
CPU time | 61 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 380636 kb |
Host | smart-546ac4e2-3f2c-416b-81c9-3bce24b9e1ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736243579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1736243579 |
Directory | /workspace/38.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/38.i2c_host_override.2029093329 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 52719787 ps |
CPU time | 0.63 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-8f20e570-a917-460d-9545-60153a67d190 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029093329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2029093329 |
Directory | /workspace/38.i2c_host_override/latest |
Test location | /workspace/coverage/default/38.i2c_host_perf.1818250219 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 3373315297 ps |
CPU time | 11.63 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:39 PM PDT 24 |
Peak memory | 229532 kb |
Host | smart-c2fc2250-4d19-4846-b04c-34233ebf6a60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818250219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1818250219 |
Directory | /workspace/38.i2c_host_perf/latest |
Test location | /workspace/coverage/default/38.i2c_host_smoke.313689741 |
Short name | T1060 |
Test name | |
Test status | |
Simulation time | 20982410064 ps |
CPU time | 22.19 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:53 PM PDT 24 |
Peak memory | 284216 kb |
Host | smart-677428d1-3580-4ad2-acd3-7fc418a755c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313689741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.313689741 |
Directory | /workspace/38.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/38.i2c_host_stress_all.2058248357 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 56192901106 ps |
CPU time | 916.24 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:51:45 PM PDT 24 |
Peak memory | 3080004 kb |
Host | smart-778dc95b-4e55-4a1b-955d-765adb79099f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058248357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2058248357 |
Directory | /workspace/38.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/38.i2c_host_stretch_timeout.2291089593 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 7217221224 ps |
CPU time | 10.13 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:37 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-e6c28b91-bf29-44cb-9d5e-c0776e879f9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291089593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2291089593 |
Directory | /workspace/38.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/38.i2c_target_bad_addr.2514726839 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 666821094 ps |
CPU time | 3.69 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:33 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-45520407-e199-49c4-aa1f-ad044a2fc288 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514726839 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2514726839 |
Directory | /workspace/38.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3485929486 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 10022092287 ps |
CPU time | 62.24 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:31 PM PDT 24 |
Peak memory | 402572 kb |
Host | smart-8f67d1ab-f92d-4911-b62d-5d7b311307a9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485929486 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.3485929486 |
Directory | /workspace/38.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3597779643 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 10034908842 ps |
CPU time | 72.92 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:37:40 PM PDT 24 |
Peak memory | 527592 kb |
Host | smart-e4fe5eaf-3727-4dc9-8408-7ad6e62a1132 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597779643 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 38.i2c_target_fifo_reset_tx.3597779643 |
Directory | /workspace/38.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/38.i2c_target_hrst.999346773 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 426339987 ps |
CPU time | 2.66 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-ff03fd1c-2135-47ab-9575-279a3203398e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999346773 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.i2c_target_hrst.999346773 |
Directory | /workspace/38.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/38.i2c_target_intr_smoke.407054911 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 2203389083 ps |
CPU time | 5.93 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:35 PM PDT 24 |
Peak memory | 221260 kb |
Host | smart-f8e8d027-e791-4b68-9ae3-d9f2c282790a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407054911 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.407054911 |
Directory | /workspace/38.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/38.i2c_target_intr_stress_wr.2379762283 |
Short name | T1225 |
Test name | |
Test status | |
Simulation time | 7623859876 ps |
CPU time | 31.59 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:37:03 PM PDT 24 |
Peak memory | 1018824 kb |
Host | smart-430c8a78-ea03-45ce-a191-4248234f6eac |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379762283 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2379762283 |
Directory | /workspace/38.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/38.i2c_target_smoke.2576188302 |
Short name | T1229 |
Test name | |
Test status | |
Simulation time | 4688316506 ps |
CPU time | 17.96 seconds |
Started | May 23 12:36:30 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-2c320b70-6b8c-40f5-93cc-5662c02e2b08 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576188302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta rget_smoke.2576188302 |
Directory | /workspace/38.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/38.i2c_target_stress_rd.220423414 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 1465635892 ps |
CPU time | 11.46 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:39 PM PDT 24 |
Peak memory | 209692 kb |
Host | smart-7824f3f9-0b5d-4800-9f7d-470de4417ea0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220423414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c _target_stress_rd.220423414 |
Directory | /workspace/38.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/38.i2c_target_stress_wr.261314597 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 27769149921 ps |
CPU time | 13.21 seconds |
Started | May 23 12:36:29 PM PDT 24 |
Finished | May 23 12:36:45 PM PDT 24 |
Peak memory | 368848 kb |
Host | smart-d8ffe839-89a2-4152-884d-3231ec2de8a7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261314597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c _target_stress_wr.261314597 |
Directory | /workspace/38.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/38.i2c_target_stretch.2676894288 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 17585656124 ps |
CPU time | 1028.23 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:53:36 PM PDT 24 |
Peak memory | 4403992 kb |
Host | smart-04b1cc96-f2d9-4b3f-8133-0f7fc84ecd2b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676894288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ target_stretch.2676894288 |
Directory | /workspace/38.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/38.i2c_target_timeout.4037577883 |
Short name | T1090 |
Test name | |
Test status | |
Simulation time | 1623059161 ps |
CPU time | 8.7 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 210552 kb |
Host | smart-2c734c4d-eccf-4ff2-949f-9e29482e65dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037577883 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.i2c_target_timeout.4037577883 |
Directory | /workspace/38.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/39.i2c_alert_test.2241603656 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 36191942 ps |
CPU time | 0.61 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-48e186a0-a4dd-4329-9333-8870cd7e5cba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241603656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2241603656 |
Directory | /workspace/39.i2c_alert_test/latest |
Test location | /workspace/coverage/default/39.i2c_host_error_intr.1040263100 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 318522436 ps |
CPU time | 5.76 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:34 PM PDT 24 |
Peak memory | 269184 kb |
Host | smart-93df7dad-9a47-4b55-939b-7a4c531ed8c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040263100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1040263100 |
Directory | /workspace/39.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3741149585 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 412236001 ps |
CPU time | 4.84 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:35 PM PDT 24 |
Peak memory | 247040 kb |
Host | smart-f0fd8a29-4a94-474b-8b29-496ca4bb2a3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741149585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp ty.3741149585 |
Directory | /workspace/39.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_full.3308959333 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 2927072713 ps |
CPU time | 100.38 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:38:11 PM PDT 24 |
Peak memory | 899144 kb |
Host | smart-fef8c89c-7095-4577-ac6a-c3db9f65f1ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308959333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3308959333 |
Directory | /workspace/39.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_overflow.262257461 |
Short name | T1308 |
Test name | |
Test status | |
Simulation time | 4302618078 ps |
CPU time | 59.84 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:37:27 PM PDT 24 |
Peak memory | 680704 kb |
Host | smart-20281e8f-e458-4108-a83b-0ac513c774a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262257461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.262257461 |
Directory | /workspace/39.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3283567647 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 385962015 ps |
CPU time | 1 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:32 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-1d30b06c-da78-4f4f-afc4-6cf58cece47c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283567647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f mt.3283567647 |
Directory | /workspace/39.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2629264069 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 202321295 ps |
CPU time | 4.69 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 240424 kb |
Host | smart-66c0becf-42d3-4bb0-9525-ae2ebad9b69a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629264069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx .2629264069 |
Directory | /workspace/39.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/39.i2c_host_fifo_watermark.3547198042 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 4016660236 ps |
CPU time | 116.98 seconds |
Started | May 23 12:36:25 PM PDT 24 |
Finished | May 23 12:38:24 PM PDT 24 |
Peak memory | 1204392 kb |
Host | smart-4f7a8e8b-f83b-4ec4-b2d6-ea264ec7705e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547198042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3547198042 |
Directory | /workspace/39.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/39.i2c_host_may_nack.2863688297 |
Short name | T1066 |
Test name | |
Test status | |
Simulation time | 1535205157 ps |
CPU time | 5.49 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:36:49 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-2ecfe2a9-4f92-4881-a346-cc443cc6e34e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863688297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2863688297 |
Directory | /workspace/39.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/39.i2c_host_mode_toggle.1751992774 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 8149730323 ps |
CPU time | 22.91 seconds |
Started | May 23 12:36:38 PM PDT 24 |
Finished | May 23 12:37:01 PM PDT 24 |
Peak memory | 366404 kb |
Host | smart-17d1865b-cb35-4c51-9bf8-2c62a74ecb41 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751992774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1751992774 |
Directory | /workspace/39.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/39.i2c_host_override.2832589467 |
Short name | T1112 |
Test name | |
Test status | |
Simulation time | 28609543 ps |
CPU time | 0.67 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:30 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-2bef9f8e-141c-46f0-ab4f-9b24fabe46df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832589467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2832589467 |
Directory | /workspace/39.i2c_host_override/latest |
Test location | /workspace/coverage/default/39.i2c_host_perf.337088883 |
Short name | T1262 |
Test name | |
Test status | |
Simulation time | 48559781731 ps |
CPU time | 2763.4 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 01:22:34 PM PDT 24 |
Peak memory | 3137240 kb |
Host | smart-0c1fd159-c8b8-454e-9423-9dacce04d438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337088883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.337088883 |
Directory | /workspace/39.i2c_host_perf/latest |
Test location | /workspace/coverage/default/39.i2c_host_smoke.3150947139 |
Short name | T1101 |
Test name | |
Test status | |
Simulation time | 1182532007 ps |
CPU time | 53.06 seconds |
Started | May 23 12:36:29 PM PDT 24 |
Finished | May 23 12:37:25 PM PDT 24 |
Peak memory | 309040 kb |
Host | smart-c8c659c3-b2c2-4a7a-a379-a7c8f03863db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150947139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3150947139 |
Directory | /workspace/39.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/39.i2c_host_stress_all.2288756950 |
Short name | T1258 |
Test name | |
Test status | |
Simulation time | 37153697455 ps |
CPU time | 438.43 seconds |
Started | May 23 12:36:29 PM PDT 24 |
Finished | May 23 12:43:51 PM PDT 24 |
Peak memory | 2044636 kb |
Host | smart-e96b00ee-1a00-44a0-a524-fb4340a122c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288756950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.2288756950 |
Directory | /workspace/39.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/39.i2c_host_stretch_timeout.1823104483 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 2431178668 ps |
CPU time | 21.75 seconds |
Started | May 23 12:36:28 PM PDT 24 |
Finished | May 23 12:36:53 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-3295c378-3b16-480a-b103-471a6058b878 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823104483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1823104483 |
Directory | /workspace/39.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/39.i2c_target_bad_addr.1806971623 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 14310845186 ps |
CPU time | 5.71 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:36 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-7296f9ff-99fd-40a1-9a19-0b62ccf04971 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806971623 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1806971623 |
Directory | /workspace/39.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2214690715 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 10044022736 ps |
CPU time | 72.2 seconds |
Started | May 23 12:36:29 PM PDT 24 |
Finished | May 23 12:37:44 PM PDT 24 |
Peak memory | 447248 kb |
Host | smart-12ba3965-5bf4-419b-a401-9034a65bb70d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214690715 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.2214690715 |
Directory | /workspace/39.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/39.i2c_target_fifo_reset_tx.594785138 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 10079738857 ps |
CPU time | 71.38 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:37:41 PM PDT 24 |
Peak memory | 531148 kb |
Host | smart-12403675-ee90-4360-bd5b-fd6dba448881 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594785138 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.i2c_target_fifo_reset_tx.594785138 |
Directory | /workspace/39.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/39.i2c_target_hrst.735063486 |
Short name | T1172 |
Test name | |
Test status | |
Simulation time | 427659647 ps |
CPU time | 2.63 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:32 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-6db6052b-02ff-4d4c-b5dc-7a02a9eac7c9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735063486 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.i2c_target_hrst.735063486 |
Directory | /workspace/39.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/39.i2c_target_intr_smoke.2572030706 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 4501514566 ps |
CPU time | 5.39 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:34 PM PDT 24 |
Peak memory | 216324 kb |
Host | smart-f7e650f4-2d94-4b39-8302-6830aad12492 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572030706 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 39.i2c_target_intr_smoke.2572030706 |
Directory | /workspace/39.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/39.i2c_target_intr_stress_wr.665779812 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 5044455670 ps |
CPU time | 6.57 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:36:35 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-ab2f5a33-ea9c-49f9-b51b-9e3c87182ba9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665779812 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.665779812 |
Directory | /workspace/39.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/39.i2c_target_smoke.57489153 |
Short name | T1210 |
Test name | |
Test status | |
Simulation time | 1531132972 ps |
CPU time | 16.37 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:47 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-81a7dff2-4ab9-4eb5-82c6-3ea200186adf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57489153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ= i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_targ et_smoke.57489153 |
Directory | /workspace/39.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/39.i2c_target_stress_rd.4281654501 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 639472634 ps |
CPU time | 11.38 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:42 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-a0297c3c-3386-4b76-853e-962526b45fac |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281654501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2 c_target_stress_rd.4281654501 |
Directory | /workspace/39.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/39.i2c_target_stress_wr.3196733649 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 27890252251 ps |
CPU time | 56.58 seconds |
Started | May 23 12:36:26 PM PDT 24 |
Finished | May 23 12:37:25 PM PDT 24 |
Peak memory | 1000284 kb |
Host | smart-cc962d7c-4d81-4696-af93-a9161d360cf0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196733649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2 c_target_stress_wr.3196733649 |
Directory | /workspace/39.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/39.i2c_target_stretch.293364125 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 8114946711 ps |
CPU time | 253.28 seconds |
Started | May 23 12:36:30 PM PDT 24 |
Finished | May 23 12:40:46 PM PDT 24 |
Peak memory | 1047152 kb |
Host | smart-5e6f678d-c70a-4898-8ff9-b863c648b661 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293364125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t arget_stretch.293364125 |
Directory | /workspace/39.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/39.i2c_target_timeout.1494006532 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1280747088 ps |
CPU time | 6.3 seconds |
Started | May 23 12:36:27 PM PDT 24 |
Finished | May 23 12:36:37 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-8a83e669-a234-44b4-bb3d-4ce8439d3bde |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494006532 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.i2c_target_timeout.1494006532 |
Directory | /workspace/39.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/4.i2c_alert_test.1820895903 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 48570990 ps |
CPU time | 0.58 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:04 PM PDT 24 |
Peak memory | 204448 kb |
Host | smart-cc0aa86d-621e-4cc5-b534-25aac8b14252 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820895903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1820895903 |
Directory | /workspace/4.i2c_alert_test/latest |
Test location | /workspace/coverage/default/4.i2c_host_error_intr.1119452014 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 1326299350 ps |
CPU time | 3.04 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 215232 kb |
Host | smart-bcfcc8df-d403-4fae-8d6d-5658e2263aa9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119452014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1119452014 |
Directory | /workspace/4.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.918576299 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 341021606 ps |
CPU time | 5.7 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:06 PM PDT 24 |
Peak memory | 269480 kb |
Host | smart-3c142675-f6da-41f1-9413-98331d102ae0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918576299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty .918576299 |
Directory | /workspace/4.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_full.3191203825 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 11315903275 ps |
CPU time | 223.34 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:36:49 PM PDT 24 |
Peak memory | 882852 kb |
Host | smart-dec22254-e5e1-47aa-a66b-381e0dc58001 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191203825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3191203825 |
Directory | /workspace/4.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_overflow.967629599 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 3126319534 ps |
CPU time | 41.77 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 576176 kb |
Host | smart-9555f781-3970-4444-aa99-011358bad86d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967629599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.967629599 |
Directory | /workspace/4.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3172241113 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 128036138 ps |
CPU time | 1.07 seconds |
Started | May 23 12:32:46 PM PDT 24 |
Finished | May 23 12:32:48 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-1a14f5fb-f413-4c42-a480-71c16e0a6f79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172241113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm t.3172241113 |
Directory | /workspace/4.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_reset_rx.438643177 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 227602315 ps |
CPU time | 12.11 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-c0235b28-620f-4fb8-8380-e78047ea7008 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438643177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.438643177 |
Directory | /workspace/4.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/4.i2c_host_fifo_watermark.2057667692 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 63055180118 ps |
CPU time | 416.49 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:39:47 PM PDT 24 |
Peak memory | 1488816 kb |
Host | smart-62c8c30b-e16d-4fb0-b9b2-87c134dd98fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057667692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2057667692 |
Directory | /workspace/4.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/4.i2c_host_may_nack.148168350 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 5915230122 ps |
CPU time | 8.54 seconds |
Started | May 23 12:32:57 PM PDT 24 |
Finished | May 23 12:33:08 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-df83da06-f34a-4695-a8f2-edb73cc05ea1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148168350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.148168350 |
Directory | /workspace/4.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/4.i2c_host_mode_toggle.2183837976 |
Short name | T1049 |
Test name | |
Test status | |
Simulation time | 8742285487 ps |
CPU time | 42.04 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:44 PM PDT 24 |
Peak memory | 340484 kb |
Host | smart-bf8c5469-0728-44b1-ad32-ef165ce8b5b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183837976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2183837976 |
Directory | /workspace/4.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/4.i2c_host_override.3134177289 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 34321550 ps |
CPU time | 0.62 seconds |
Started | May 23 12:32:48 PM PDT 24 |
Finished | May 23 12:32:51 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-903346e1-ccaa-4cb1-954f-a725122b092e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134177289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3134177289 |
Directory | /workspace/4.i2c_host_override/latest |
Test location | /workspace/coverage/default/4.i2c_host_perf.2742042965 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 12802465638 ps |
CPU time | 127.33 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:35:11 PM PDT 24 |
Peak memory | 221248 kb |
Host | smart-a28ca26c-8371-49e4-9c0b-be28142506fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742042965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2742042965 |
Directory | /workspace/4.i2c_host_perf/latest |
Test location | /workspace/coverage/default/4.i2c_host_smoke.2973109854 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 2452511411 ps |
CPU time | 22.71 seconds |
Started | May 23 12:32:47 PM PDT 24 |
Finished | May 23 12:33:12 PM PDT 24 |
Peak memory | 374920 kb |
Host | smart-29c52735-a504-44bf-a3f5-ae16f8c3127a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973109854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2973109854 |
Directory | /workspace/4.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/4.i2c_host_stress_all.62319625 |
Short name | T1097 |
Test name | |
Test status | |
Simulation time | 80287682893 ps |
CPU time | 1470.44 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:57:32 PM PDT 24 |
Peak memory | 4678224 kb |
Host | smart-cd3ca00c-659c-4048-90db-dba76b51bd33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62319625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.62319625 |
Directory | /workspace/4.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/4.i2c_host_stretch_timeout.3283480885 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 1165263149 ps |
CPU time | 10.95 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:15 PM PDT 24 |
Peak memory | 214180 kb |
Host | smart-530c8a78-47d0-47ae-ab0f-9962c511d0e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283480885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3283480885 |
Directory | /workspace/4.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/4.i2c_target_bad_addr.3705127216 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 3493694997 ps |
CPU time | 4.78 seconds |
Started | May 23 12:32:57 PM PDT 24 |
Finished | May 23 12:33:04 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-6da2b007-5883-4065-b00c-1f138eaf3f2e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705127216 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3705127216 |
Directory | /workspace/4.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3206111014 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 10225709138 ps |
CPU time | 9.2 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:13 PM PDT 24 |
Peak memory | 257520 kb |
Host | smart-eea87693-05cc-4676-973b-9bdf5e9039c6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206111014 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.3206111014 |
Directory | /workspace/4.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2951144653 |
Short name | T1187 |
Test name | |
Test status | |
Simulation time | 10058752312 ps |
CPU time | 67.36 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:34:10 PM PDT 24 |
Peak memory | 442564 kb |
Host | smart-7f3d47a6-57bc-48b3-b45b-fe8f88c937c4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951144653 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.i2c_target_fifo_reset_tx.2951144653 |
Directory | /workspace/4.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/4.i2c_target_hrst.4003218901 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1349044625 ps |
CPU time | 2.49 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:02 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-3cca06f3-2ff3-4978-90e4-5fc47e9584a8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003218901 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.4003218901 |
Directory | /workspace/4.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/4.i2c_target_intr_smoke.3796956804 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 3649524395 ps |
CPU time | 4.72 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:08 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-f8b5f774-a52f-4ea7-ac05-5ed805c29da1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796956804 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.i2c_target_intr_smoke.3796956804 |
Directory | /workspace/4.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/4.i2c_target_intr_stress_wr.2506086563 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 8542324162 ps |
CPU time | 28.73 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 595212 kb |
Host | smart-914c403c-7d8d-4b94-ae91-4317095a803e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506086563 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2506086563 |
Directory | /workspace/4.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/4.i2c_target_smoke.1370170228 |
Short name | T1099 |
Test name | |
Test status | |
Simulation time | 6860192470 ps |
CPU time | 13.76 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-7b71d7ba-e4c1-4e3e-95fd-1bd037f8e91b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370170228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar get_smoke.1370170228 |
Directory | /workspace/4.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/4.i2c_target_stress_rd.1026143025 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 1300789612 ps |
CPU time | 20.66 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:25 PM PDT 24 |
Peak memory | 222204 kb |
Host | smart-e35096c4-7f77-493d-84ad-fc2d3f00da07 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026143025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c _target_stress_rd.1026143025 |
Directory | /workspace/4.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/4.i2c_target_stress_wr.4044206124 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 10341474074 ps |
CPU time | 21.71 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-b23a8453-1ea2-4d6e-a0ec-976d5cf55bb5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044206124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c _target_stress_wr.4044206124 |
Directory | /workspace/4.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/4.i2c_target_timeout.499302245 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 4112884351 ps |
CPU time | 6.1 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:10 PM PDT 24 |
Peak memory | 213120 kb |
Host | smart-e138173e-d0e2-49eb-bea8-7a7fe93d273b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499302245 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.i2c_target_timeout.499302245 |
Directory | /workspace/4.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/40.i2c_alert_test.1038789827 |
Short name | T1179 |
Test name | |
Test status | |
Simulation time | 53376638 ps |
CPU time | 0.65 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:36:48 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-b54952a8-6a73-4954-a4b7-411cf7039bb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038789827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1038789827 |
Directory | /workspace/40.i2c_alert_test/latest |
Test location | /workspace/coverage/default/40.i2c_host_error_intr.3495102436 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 290430887 ps |
CPU time | 1.96 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-9f1656a2-fdd7-4435-bbde-d997a63caaa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495102436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3495102436 |
Directory | /workspace/40.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1157999699 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 285216201 ps |
CPU time | 5.85 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 243792 kb |
Host | smart-a92bc2a0-3e8b-47c6-81c5-64e2c1521753 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157999699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp ty.1157999699 |
Directory | /workspace/40.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_full.3287007023 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3943795467 ps |
CPU time | 89.81 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:38:15 PM PDT 24 |
Peak memory | 893904 kb |
Host | smart-1a72bfc4-c235-4575-8a3e-1e18061861d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287007023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3287007023 |
Directory | /workspace/40.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_overflow.1552948927 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 3241546970 ps |
CPU time | 49 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 591064 kb |
Host | smart-0986ba17-4d7e-4724-add0-2d7975775262 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552948927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1552948927 |
Directory | /workspace/40.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1228343670 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 457665380 ps |
CPU time | 0.94 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-175f05d3-d62d-4561-9e17-6d43e1a584bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228343670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f mt.1228343670 |
Directory | /workspace/40.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2145255652 |
Short name | T1239 |
Test name | |
Test status | |
Simulation time | 517637080 ps |
CPU time | 6.59 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-f1b09b3f-acf6-4286-9c98-1e7874cae859 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145255652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx .2145255652 |
Directory | /workspace/40.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/40.i2c_host_fifo_watermark.3505603186 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 13174097257 ps |
CPU time | 214.86 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:40:17 PM PDT 24 |
Peak memory | 960024 kb |
Host | smart-5c197017-2a0c-4135-a692-785423ac2220 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505603186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3505603186 |
Directory | /workspace/40.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/40.i2c_host_may_nack.3463534305 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 822716478 ps |
CPU time | 6.52 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c719cd94-ddf0-40c3-97c6-eb8c7a075276 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463534305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3463534305 |
Directory | /workspace/40.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/40.i2c_host_mode_toggle.618492861 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 5328566251 ps |
CPU time | 68.83 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:37:50 PM PDT 24 |
Peak memory | 388424 kb |
Host | smart-e442591d-933a-456c-ba8d-4b1727ff83ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618492861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.618492861 |
Directory | /workspace/40.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/40.i2c_host_override.3517916106 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 28212079 ps |
CPU time | 0.69 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-b24dc189-d9fc-435d-a34a-9ae2b4639760 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517916106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3517916106 |
Directory | /workspace/40.i2c_host_override/latest |
Test location | /workspace/coverage/default/40.i2c_host_perf.3995848617 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 18594056387 ps |
CPU time | 355.36 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:42:39 PM PDT 24 |
Peak memory | 2085384 kb |
Host | smart-46cc31b2-5898-4d9d-9972-20b5a10ead81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995848617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3995848617 |
Directory | /workspace/40.i2c_host_perf/latest |
Test location | /workspace/coverage/default/40.i2c_host_smoke.2998319745 |
Short name | T1250 |
Test name | |
Test status | |
Simulation time | 9232419283 ps |
CPU time | 37.73 seconds |
Started | May 23 12:36:39 PM PDT 24 |
Finished | May 23 12:37:19 PM PDT 24 |
Peak memory | 318760 kb |
Host | smart-32474d40-553e-4c01-9905-6a6470c587f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998319745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2998319745 |
Directory | /workspace/40.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/40.i2c_host_stretch_timeout.3383815264 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 2312508274 ps |
CPU time | 25.2 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 213120 kb |
Host | smart-8aa57879-d4a9-4cbe-bc87-de4364708b6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383815264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3383815264 |
Directory | /workspace/40.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/40.i2c_target_bad_addr.2590042270 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 2478430568 ps |
CPU time | 3.3 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:36:49 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-28683643-cc0c-4361-90b0-bfbed6958332 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590042270 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2590042270 |
Directory | /workspace/40.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/40.i2c_target_fifo_reset_acq.4115668167 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 10157996438 ps |
CPU time | 15.57 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:37:00 PM PDT 24 |
Peak memory | 283884 kb |
Host | smart-a3f327a2-6cd3-47cf-8d60-83435834cc12 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115668167 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.4115668167 |
Directory | /workspace/40.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1804381096 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 10132921996 ps |
CPU time | 36.44 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 361836 kb |
Host | smart-cdbde1f3-004c-4a69-8028-aa1f0d36839c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804381096 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 40.i2c_target_fifo_reset_tx.1804381096 |
Directory | /workspace/40.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/40.i2c_target_hrst.2191183726 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 497237169 ps |
CPU time | 2.79 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:36:47 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-300505ae-df89-48d6-83ae-1c67b173df9a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191183726 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_hrst.2191183726 |
Directory | /workspace/40.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/40.i2c_target_intr_smoke.1232194953 |
Short name | T1042 |
Test name | |
Test status | |
Simulation time | 688387105 ps |
CPU time | 3.87 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:36:48 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-b5b7c159-103b-4fdf-9293-def9041706c1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232194953 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 40.i2c_target_intr_smoke.1232194953 |
Directory | /workspace/40.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/40.i2c_target_intr_stress_wr.3960282047 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 16209981448 ps |
CPU time | 326.67 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:42:12 PM PDT 24 |
Peak memory | 4019720 kb |
Host | smart-be5d9dfb-57dd-43a7-9e2c-1372753f9959 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960282047 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3960282047 |
Directory | /workspace/40.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/40.i2c_target_smoke.1543749734 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1404588958 ps |
CPU time | 11 seconds |
Started | May 23 12:36:43 PM PDT 24 |
Finished | May 23 12:36:57 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-d1d5e2ae-adb0-45d8-b9b7-7b26f363e674 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543749734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta rget_smoke.1543749734 |
Directory | /workspace/40.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/40.i2c_target_stress_rd.1425741523 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 5032470120 ps |
CPU time | 52.47 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:37:38 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-cc99cc8a-4a0b-451c-8691-56aef827021f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425741523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2 c_target_stress_rd.1425741523 |
Directory | /workspace/40.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/40.i2c_target_stress_wr.1541060951 |
Short name | T1320 |
Test name | |
Test status | |
Simulation time | 35708501803 ps |
CPU time | 405.06 seconds |
Started | May 23 12:36:45 PM PDT 24 |
Finished | May 23 12:43:33 PM PDT 24 |
Peak memory | 3946048 kb |
Host | smart-e1afdc49-df0b-48f6-add8-1a5965829a6f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541060951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2 c_target_stress_wr.1541060951 |
Directory | /workspace/40.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/40.i2c_target_stretch.470121570 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 1261354029 ps |
CPU time | 16.5 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 404296 kb |
Host | smart-7d457bc5-468e-4c9f-aabb-fb2e0d72b8f7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470121570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t arget_stretch.470121570 |
Directory | /workspace/40.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/40.i2c_target_timeout.1718402794 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 2762681388 ps |
CPU time | 7.66 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:36:52 PM PDT 24 |
Peak memory | 221260 kb |
Host | smart-53868567-472e-4c17-ab44-3a2e8fcbedab |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718402794 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.i2c_target_timeout.1718402794 |
Directory | /workspace/40.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/41.i2c_alert_test.3399005684 |
Short name | T1045 |
Test name | |
Test status | |
Simulation time | 48896112 ps |
CPU time | 0.62 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:36:46 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-4e2a1140-8fc5-44c1-9b6d-b4c744f82b27 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399005684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3399005684 |
Directory | /workspace/41.i2c_alert_test/latest |
Test location | /workspace/coverage/default/41.i2c_host_error_intr.1097275852 |
Short name | T1116 |
Test name | |
Test status | |
Simulation time | 1382605846 ps |
CPU time | 14.28 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 234912 kb |
Host | smart-ee80792d-d559-41f3-bbc2-81853029b30d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097275852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1097275852 |
Directory | /workspace/41.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1033547003 |
Short name | T1083 |
Test name | |
Test status | |
Simulation time | 560075529 ps |
CPU time | 28.71 seconds |
Started | May 23 12:36:43 PM PDT 24 |
Finished | May 23 12:37:15 PM PDT 24 |
Peak memory | 325320 kb |
Host | smart-2320b4df-16fe-4f91-8c0a-4cdff235b587 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033547003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp ty.1033547003 |
Directory | /workspace/41.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_full.3775882088 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 31408779453 ps |
CPU time | 95.6 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:38:24 PM PDT 24 |
Peak memory | 888008 kb |
Host | smart-1b0ef470-c55c-43e2-b6ae-21803ce30d5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775882088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3775882088 |
Directory | /workspace/41.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_overflow.4265582566 |
Short name | T1269 |
Test name | |
Test status | |
Simulation time | 2207697217 ps |
CPU time | 68.98 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:37:56 PM PDT 24 |
Peak memory | 659812 kb |
Host | smart-4bfbe45e-7e5d-4991-b3c7-3f374e5bef5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265582566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.4265582566 |
Directory | /workspace/41.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2858491826 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 352148837 ps |
CPU time | 0.85 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:36:48 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-2ac97190-6ce8-4cd2-8e7d-5254092414f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858491826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f mt.2858491826 |
Directory | /workspace/41.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3334458007 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 517452322 ps |
CPU time | 6.54 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:36:54 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-7b711826-0641-4f93-8054-1f4063d63027 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334458007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx .3334458007 |
Directory | /workspace/41.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/41.i2c_host_fifo_watermark.918916980 |
Short name | T1223 |
Test name | |
Test status | |
Simulation time | 17450684066 ps |
CPU time | 339.61 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:42:28 PM PDT 24 |
Peak memory | 1260624 kb |
Host | smart-acbb6211-8eed-467b-ba17-b37733858d91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918916980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.918916980 |
Directory | /workspace/41.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/41.i2c_host_may_nack.1417904586 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 226039959 ps |
CPU time | 3.56 seconds |
Started | May 23 12:36:43 PM PDT 24 |
Finished | May 23 12:36:49 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-dfc93d1a-4a85-43b0-b81d-9197c2e89034 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417904586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1417904586 |
Directory | /workspace/41.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/41.i2c_host_mode_toggle.1000486478 |
Short name | T1067 |
Test name | |
Test status | |
Simulation time | 19174066673 ps |
CPU time | 36.21 seconds |
Started | May 23 12:36:41 PM PDT 24 |
Finished | May 23 12:37:21 PM PDT 24 |
Peak memory | 370544 kb |
Host | smart-402d517c-daf3-4bd5-8e30-9b20dea9d537 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000486478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1000486478 |
Directory | /workspace/41.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/41.i2c_host_override.429012262 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 155209275 ps |
CPU time | 0.65 seconds |
Started | May 23 12:36:45 PM PDT 24 |
Finished | May 23 12:36:48 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-8dc52078-42b6-42ce-8446-209990e72cda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429012262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.429012262 |
Directory | /workspace/41.i2c_host_override/latest |
Test location | /workspace/coverage/default/41.i2c_host_perf.2199764620 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 1131224028 ps |
CPU time | 9.83 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:36:58 PM PDT 24 |
Peak memory | 326796 kb |
Host | smart-d300128c-3bcd-4267-8b37-4cc8f6191c7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199764620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2199764620 |
Directory | /workspace/41.i2c_host_perf/latest |
Test location | /workspace/coverage/default/41.i2c_host_smoke.1015054603 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 11983946813 ps |
CPU time | 25.82 seconds |
Started | May 23 12:36:43 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 278412 kb |
Host | smart-da4104aa-6473-4b7a-9324-2b1f42dfd8f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015054603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1015054603 |
Directory | /workspace/41.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/41.i2c_host_stretch_timeout.1262968472 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 2149412269 ps |
CPU time | 24.31 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:37:13 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-5d23fbde-0dd0-489b-87a9-14a405c5f15e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262968472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1262968472 |
Directory | /workspace/41.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/41.i2c_target_bad_addr.3992078862 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 3298521451 ps |
CPU time | 4.36 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:36:47 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-c047567e-f711-4b6b-a01e-8914ccb24c62 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992078862 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3992078862 |
Directory | /workspace/41.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/41.i2c_target_fifo_reset_acq.159380475 |
Short name | T1157 |
Test name | |
Test status | |
Simulation time | 10247898631 ps |
CPU time | 14.22 seconds |
Started | May 23 12:36:37 PM PDT 24 |
Finished | May 23 12:36:52 PM PDT 24 |
Peak memory | 282408 kb |
Host | smart-894b69df-f6ea-47ed-857d-bca816e124b0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159380475 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 41.i2c_target_fifo_reset_acq.159380475 |
Directory | /workspace/41.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/41.i2c_target_fifo_reset_tx.4047194306 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 10088878851 ps |
CPU time | 16.25 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:37:00 PM PDT 24 |
Peak memory | 278684 kb |
Host | smart-6534cae4-6a31-4dae-a4a2-75baf983ea1c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047194306 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 41.i2c_target_fifo_reset_tx.4047194306 |
Directory | /workspace/41.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/41.i2c_target_hrst.3085605892 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 3469104393 ps |
CPU time | 2.88 seconds |
Started | May 23 12:36:37 PM PDT 24 |
Finished | May 23 12:36:41 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-9cceb28b-4990-4818-80f6-36e078f08d5c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085605892 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.3085605892 |
Directory | /workspace/41.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/41.i2c_target_intr_smoke.3529792773 |
Short name | T1174 |
Test name | |
Test status | |
Simulation time | 4092907627 ps |
CPU time | 4.52 seconds |
Started | May 23 12:36:37 PM PDT 24 |
Finished | May 23 12:36:42 PM PDT 24 |
Peak memory | 207024 kb |
Host | smart-db2b4563-ed9f-437f-b03a-d04272b5ab94 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529792773 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 41.i2c_target_intr_smoke.3529792773 |
Directory | /workspace/41.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/41.i2c_target_intr_stress_wr.2092646319 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 22093671124 ps |
CPU time | 36.5 seconds |
Started | May 23 12:36:38 PM PDT 24 |
Finished | May 23 12:37:16 PM PDT 24 |
Peak memory | 633012 kb |
Host | smart-9e676249-bd8d-470f-b05c-f6663db1068d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092646319 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2092646319 |
Directory | /workspace/41.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/41.i2c_target_smoke.2650041047 |
Short name | T1064 |
Test name | |
Test status | |
Simulation time | 1398755265 ps |
CPU time | 11.66 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:36:59 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-9100f282-05b8-4aec-9e97-429efac95ae0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650041047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta rget_smoke.2650041047 |
Directory | /workspace/41.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/41.i2c_target_stress_rd.2316436400 |
Short name | T1096 |
Test name | |
Test status | |
Simulation time | 5024451784 ps |
CPU time | 56.79 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:37:44 PM PDT 24 |
Peak memory | 209144 kb |
Host | smart-916caa4d-9d6d-46b9-a861-83af1492ff19 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316436400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2 c_target_stress_rd.2316436400 |
Directory | /workspace/41.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/41.i2c_target_stress_wr.1815039823 |
Short name | T1056 |
Test name | |
Test status | |
Simulation time | 11250569159 ps |
CPU time | 17.73 seconds |
Started | May 23 12:36:46 PM PDT 24 |
Finished | May 23 12:37:06 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-bb2decf9-a1ef-484c-af64-e6f30b13751e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815039823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2 c_target_stress_wr.1815039823 |
Directory | /workspace/41.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/41.i2c_target_timeout.1140787130 |
Short name | T1133 |
Test name | |
Test status | |
Simulation time | 6586482620 ps |
CPU time | 7.27 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:36:50 PM PDT 24 |
Peak memory | 221264 kb |
Host | smart-0433fab1-c588-430d-8bcd-bade1a4b70cc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140787130 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.i2c_target_timeout.1140787130 |
Directory | /workspace/41.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/42.i2c_alert_test.3677260215 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 44772880 ps |
CPU time | 0.65 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:36:59 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-b6b06802-dc12-4144-b91d-de6a99358f86 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677260215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3677260215 |
Directory | /workspace/42.i2c_alert_test/latest |
Test location | /workspace/coverage/default/42.i2c_host_error_intr.2667000585 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1616276435 ps |
CPU time | 8.39 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:37:04 PM PDT 24 |
Peak memory | 276600 kb |
Host | smart-04d32354-19bb-4d2d-a721-d74c636ad5cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667000585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2667000585 |
Directory | /workspace/42.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.267980442 |
Short name | T1302 |
Test name | |
Test status | |
Simulation time | 405172116 ps |
CPU time | 20.7 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:37:17 PM PDT 24 |
Peak memory | 287760 kb |
Host | smart-7dc0e10e-49ce-478f-b69d-3b6c88c59384 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267980442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt y.267980442 |
Directory | /workspace/42.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_full.3514860859 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 5466467083 ps |
CPU time | 211.19 seconds |
Started | May 23 12:36:59 PM PDT 24 |
Finished | May 23 12:40:33 PM PDT 24 |
Peak memory | 857296 kb |
Host | smart-46c036e2-4e18-4aeb-98fe-0865b5558d9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514860859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3514860859 |
Directory | /workspace/42.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_overflow.1392473412 |
Short name | T1299 |
Test name | |
Test status | |
Simulation time | 10541973713 ps |
CPU time | 94.8 seconds |
Started | May 23 12:36:42 PM PDT 24 |
Finished | May 23 12:38:20 PM PDT 24 |
Peak memory | 863892 kb |
Host | smart-36bbaac9-18f6-470e-9d2f-052e3444cac0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392473412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1392473412 |
Directory | /workspace/42.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.312127097 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 170076022 ps |
CPU time | 0.98 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:36:59 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-739f6f78-eff4-4697-980d-33b845d15af9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312127097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm t.312127097 |
Directory | /workspace/42.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_reset_rx.68251923 |
Short name | T1303 |
Test name | |
Test status | |
Simulation time | 115404551 ps |
CPU time | 2.41 seconds |
Started | May 23 12:36:59 PM PDT 24 |
Finished | May 23 12:37:04 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-74b3800c-56f8-4d9a-a0be-ac815c526559 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68251923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.68251923 |
Directory | /workspace/42.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/42.i2c_host_fifo_watermark.3149335625 |
Short name | T1127 |
Test name | |
Test status | |
Simulation time | 3808756915 ps |
CPU time | 93 seconds |
Started | May 23 12:36:44 PM PDT 24 |
Finished | May 23 12:38:20 PM PDT 24 |
Peak memory | 1152960 kb |
Host | smart-943bcc29-8b4d-43b1-9fb8-3a32aaf75265 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149335625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3149335625 |
Directory | /workspace/42.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/42.i2c_host_may_nack.3594229059 |
Short name | T1189 |
Test name | |
Test status | |
Simulation time | 1104516123 ps |
CPU time | 9.7 seconds |
Started | May 23 12:36:59 PM PDT 24 |
Finished | May 23 12:37:10 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-0d602a0c-818c-42c5-88a9-0cc3e31db686 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594229059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3594229059 |
Directory | /workspace/42.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/42.i2c_host_mode_toggle.2480006905 |
Short name | T1246 |
Test name | |
Test status | |
Simulation time | 1688616251 ps |
CPU time | 82.73 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:38:18 PM PDT 24 |
Peak memory | 431788 kb |
Host | smart-89b62d22-e2d8-482a-b0b1-21cd75a3accb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480006905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2480006905 |
Directory | /workspace/42.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/42.i2c_host_override.3987811826 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 193486775 ps |
CPU time | 0.65 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:36:42 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-fad9d244-c9cd-4a6c-8722-a8a9a6e358fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987811826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3987811826 |
Directory | /workspace/42.i2c_host_override/latest |
Test location | /workspace/coverage/default/42.i2c_host_perf.2796393254 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 6650955943 ps |
CPU time | 10.13 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 213128 kb |
Host | smart-aae21679-6638-4b5e-8edf-057bef5f970f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796393254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2796393254 |
Directory | /workspace/42.i2c_host_perf/latest |
Test location | /workspace/coverage/default/42.i2c_host_smoke.170767938 |
Short name | T1336 |
Test name | |
Test status | |
Simulation time | 37715364196 ps |
CPU time | 30.72 seconds |
Started | May 23 12:36:40 PM PDT 24 |
Finished | May 23 12:37:13 PM PDT 24 |
Peak memory | 327064 kb |
Host | smart-7b5970f8-d99d-4aa8-91ff-df6786d0e99a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170767938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.170767938 |
Directory | /workspace/42.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/42.i2c_host_stretch_timeout.3896534002 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2013437562 ps |
CPU time | 25.27 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:25 PM PDT 24 |
Peak memory | 212260 kb |
Host | smart-ad29d529-3121-4e1a-9b98-eabd336af817 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896534002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3896534002 |
Directory | /workspace/42.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/42.i2c_target_bad_addr.2452797517 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 606966367 ps |
CPU time | 2.77 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-25245791-e7f2-4306-9432-9e731894f4c8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452797517 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2452797517 |
Directory | /workspace/42.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3946736623 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 10283986142 ps |
CPU time | 13.79 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 255268 kb |
Host | smart-2fefbe78-11d9-4fca-8058-d409e2377a8b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946736623 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.3946736623 |
Directory | /workspace/42.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1488158164 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 10563616044 ps |
CPU time | 12.94 seconds |
Started | May 23 12:36:53 PM PDT 24 |
Finished | May 23 12:37:07 PM PDT 24 |
Peak memory | 289476 kb |
Host | smart-7deaab04-99d8-4f34-9537-bd1f5ad72569 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488158164 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 42.i2c_target_fifo_reset_tx.1488158164 |
Directory | /workspace/42.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/42.i2c_target_hrst.1200688948 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 789124907 ps |
CPU time | 2.59 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:00 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-7a9d0f90-7f16-4a47-914c-36ad89dfce19 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200688948 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.1200688948 |
Directory | /workspace/42.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/42.i2c_target_intr_smoke.3383209414 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 1064318815 ps |
CPU time | 5.68 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:03 PM PDT 24 |
Peak memory | 220616 kb |
Host | smart-ed183f65-1367-4ce0-bcaa-68d3df9e6a11 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383209414 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.i2c_target_intr_smoke.3383209414 |
Directory | /workspace/42.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/42.i2c_target_intr_stress_wr.818960361 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 10404873314 ps |
CPU time | 5.75 seconds |
Started | May 23 12:36:59 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-6ecce7ef-c6e4-4d9e-bb69-f5c4a73235ac |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818960361 -assert nopostproc +UVM_TEST NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.818960361 |
Directory | /workspace/42.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/42.i2c_target_smoke.536796939 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 795024956 ps |
CPU time | 12.86 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-14d356ba-ebd8-407b-9c70-8ea6626fb164 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536796939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar get_smoke.536796939 |
Directory | /workspace/42.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/42.i2c_target_stress_rd.3640126701 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1481232831 ps |
CPU time | 15.57 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-1abdd29f-c41f-4b70-8581-7d22c4e4e21e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640126701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2 c_target_stress_rd.3640126701 |
Directory | /workspace/42.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/42.i2c_target_stress_wr.3721421957 |
Short name | T1315 |
Test name | |
Test status | |
Simulation time | 38262332864 ps |
CPU time | 99.2 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:38:42 PM PDT 24 |
Peak memory | 1555120 kb |
Host | smart-c4538ea9-e7aa-47c9-840a-558164f4abc8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721421957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2 c_target_stress_wr.3721421957 |
Directory | /workspace/42.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/42.i2c_target_stretch.2551155490 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 41889847469 ps |
CPU time | 3384.65 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 01:33:21 PM PDT 24 |
Peak memory | 9965776 kb |
Host | smart-e289fe0f-4715-4392-9091-335d789a314d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551155490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ target_stretch.2551155490 |
Directory | /workspace/42.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/42.i2c_target_timeout.1281113475 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 2635067181 ps |
CPU time | 7.07 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:05 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-37105672-5a8d-4d49-9018-58872b75ea79 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281113475 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 42.i2c_target_timeout.1281113475 |
Directory | /workspace/42.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/43.i2c_alert_test.2874910211 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 14371472 ps |
CPU time | 0.64 seconds |
Started | May 23 12:37:01 PM PDT 24 |
Finished | May 23 12:37:04 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-a66afea6-8f07-42f3-8eac-bbdb2c9044dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874910211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2874910211 |
Directory | /workspace/43.i2c_alert_test/latest |
Test location | /workspace/coverage/default/43.i2c_host_error_intr.2369298753 |
Short name | T1198 |
Test name | |
Test status | |
Simulation time | 573676365 ps |
CPU time | 3.53 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:02 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-10d0b449-d227-4bde-ace7-b24f18ac0f19 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369298753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2369298753 |
Directory | /workspace/43.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.398302312 |
Short name | T1113 |
Test name | |
Test status | |
Simulation time | 1439892990 ps |
CPU time | 8.57 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:07 PM PDT 24 |
Peak memory | 267180 kb |
Host | smart-4d13a4df-057d-405f-b488-cea020fbff43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398302312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt y.398302312 |
Directory | /workspace/43.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_full.4126987406 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 32040964386 ps |
CPU time | 50.32 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 603304 kb |
Host | smart-c5eda1e8-6e28-4c2d-bf65-80e39264be6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126987406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4126987406 |
Directory | /workspace/43.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_overflow.2072213550 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 2339907987 ps |
CPU time | 80.09 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:38:15 PM PDT 24 |
Peak memory | 761500 kb |
Host | smart-b3e18d98-16da-4680-b251-98bc80c98242 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072213550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2072213550 |
Directory | /workspace/43.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.321176358 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 427765265 ps |
CPU time | 0.91 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:36:56 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-50724531-d856-4608-b501-cdafe1850ed8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321176358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm t.321176358 |
Directory | /workspace/43.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2182914845 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 408421737 ps |
CPU time | 5.06 seconds |
Started | May 23 12:36:59 PM PDT 24 |
Finished | May 23 12:37:05 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-38a88d97-9cc4-404c-9e82-9180611aa4d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182914845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx .2182914845 |
Directory | /workspace/43.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/43.i2c_host_fifo_watermark.2129763677 |
Short name | T1082 |
Test name | |
Test status | |
Simulation time | 3901239630 ps |
CPU time | 108.49 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:38:45 PM PDT 24 |
Peak memory | 1134124 kb |
Host | smart-994454c2-7f4c-4f9a-8fe4-a2372ec49f61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129763677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2129763677 |
Directory | /workspace/43.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/43.i2c_host_may_nack.594027823 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 1770443763 ps |
CPU time | 6.17 seconds |
Started | May 23 12:37:02 PM PDT 24 |
Finished | May 23 12:37:10 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-b69f572b-fef8-471d-af39-e131b0875a92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594027823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.594027823 |
Directory | /workspace/43.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/43.i2c_host_mode_toggle.4250907451 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 3131146981 ps |
CPU time | 76.9 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:38:22 PM PDT 24 |
Peak memory | 332980 kb |
Host | smart-ef721707-9e07-495d-94a4-dd281b586a9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250907451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4250907451 |
Directory | /workspace/43.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/43.i2c_host_override.384650205 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 130608087 ps |
CPU time | 0.65 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:36:58 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-4ad37e18-26c4-4c2b-b4a8-7baafd84030e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384650205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.384650205 |
Directory | /workspace/43.i2c_host_override/latest |
Test location | /workspace/coverage/default/43.i2c_host_perf.3435151017 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 25675820534 ps |
CPU time | 230.79 seconds |
Started | May 23 12:37:01 PM PDT 24 |
Finished | May 23 12:40:54 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-d44f4fe3-0864-432e-ad22-1f21c4d5fb56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435151017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3435151017 |
Directory | /workspace/43.i2c_host_perf/latest |
Test location | /workspace/coverage/default/43.i2c_host_smoke.611786132 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 1289461202 ps |
CPU time | 58.06 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:57 PM PDT 24 |
Peak memory | 294256 kb |
Host | smart-8522349f-7b68-444a-9b65-ec65d5e02411 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611786132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.611786132 |
Directory | /workspace/43.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/43.i2c_host_stress_all.802699262 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 25645545927 ps |
CPU time | 1298.09 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:58:34 PM PDT 24 |
Peak memory | 2815884 kb |
Host | smart-0de33cfe-8918-41c0-8374-2f5f172fc0f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802699262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.802699262 |
Directory | /workspace/43.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/43.i2c_host_stretch_timeout.2822998205 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 825032453 ps |
CPU time | 35.38 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:37:31 PM PDT 24 |
Peak memory | 213080 kb |
Host | smart-3fea4c75-678d-4bd8-816f-a383d8ea2691 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822998205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2822998205 |
Directory | /workspace/43.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/43.i2c_target_bad_addr.83316004 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 3807807475 ps |
CPU time | 4.6 seconds |
Started | May 23 12:37:01 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-418f6a20-c330-48e9-b6c3-cca16b505a74 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83316004 -assert nopostproc +UV M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.83316004 |
Directory | /workspace/43.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/43.i2c_target_fifo_reset_acq.730521487 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 10209657085 ps |
CPU time | 13.19 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:37:16 PM PDT 24 |
Peak memory | 247132 kb |
Host | smart-e6d9514c-2583-4b5a-b381-858700240a8b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730521487 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.i2c_target_fifo_reset_acq.730521487 |
Directory | /workspace/43.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3774728954 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 10069020253 ps |
CPU time | 86.34 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:38:26 PM PDT 24 |
Peak memory | 467616 kb |
Host | smart-0e4a9932-cb83-4972-9883-1a392d10eae1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774728954 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.i2c_target_fifo_reset_tx.3774728954 |
Directory | /workspace/43.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/43.i2c_target_hrst.1565182354 |
Short name | T1245 |
Test name | |
Test status | |
Simulation time | 395583282 ps |
CPU time | 2.46 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:37:05 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-40f001b1-d6a8-485c-97af-15d19ff83ff4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565182354 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_hrst.1565182354 |
Directory | /workspace/43.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/43.i2c_target_intr_smoke.1717836819 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 8787294550 ps |
CPU time | 5.81 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:06 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-bab2c8cc-82be-4e5e-bfab-45428b879ec6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717836819 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 43.i2c_target_intr_smoke.1717836819 |
Directory | /workspace/43.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/43.i2c_target_intr_stress_wr.3054715350 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 13086071230 ps |
CPU time | 96.6 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:38:32 PM PDT 24 |
Peak memory | 1519984 kb |
Host | smart-429e2dda-4a03-4902-a540-d3b481c5eb6e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054715350 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3054715350 |
Directory | /workspace/43.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/43.i2c_target_smoke.2760585314 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 1337185352 ps |
CPU time | 18.13 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:37:14 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-b6f4f7df-ea31-42cb-a14c-34849a7e9d8c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760585314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta rget_smoke.2760585314 |
Directory | /workspace/43.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/43.i2c_target_stress_rd.2113855051 |
Short name | T1181 |
Test name | |
Test status | |
Simulation time | 3555563803 ps |
CPU time | 37.43 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:35 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-16fb23b9-3688-479f-81b4-7169aa279853 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113855051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2 c_target_stress_rd.2113855051 |
Directory | /workspace/43.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/43.i2c_target_stress_wr.74546904 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 62361430444 ps |
CPU time | 597.61 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:46:52 PM PDT 24 |
Peak memory | 5115704 kb |
Host | smart-c0e01782-2f67-4c3b-a8c0-20fd602f0c20 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74546904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ= i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ target_stress_wr.74546904 |
Directory | /workspace/43.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/43.i2c_target_stretch.17977391 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 12040498592 ps |
CPU time | 82.01 seconds |
Started | May 23 12:36:54 PM PDT 24 |
Finished | May 23 12:38:17 PM PDT 24 |
Peak memory | 989132 kb |
Host | smart-dd733c18-6549-4490-bd99-99c72f80d921 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ= i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta rget_stretch.17977391 |
Directory | /workspace/43.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/43.i2c_target_timeout.1390559769 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 3711661116 ps |
CPU time | 6.91 seconds |
Started | May 23 12:37:02 PM PDT 24 |
Finished | May 23 12:37:11 PM PDT 24 |
Peak memory | 218448 kb |
Host | smart-741f2bd3-4ca8-4ecb-a43f-76782fc99c0c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390559769 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.i2c_target_timeout.1390559769 |
Directory | /workspace/43.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/44.i2c_alert_test.215590342 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 70918616 ps |
CPU time | 0.65 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:09 PM PDT 24 |
Peak memory | 204452 kb |
Host | smart-878705b2-98cc-44dd-b6ac-747bb1aadb72 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215590342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.215590342 |
Directory | /workspace/44.i2c_alert_test/latest |
Test location | /workspace/coverage/default/44.i2c_host_error_intr.143252261 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 280515917 ps |
CPU time | 1.27 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:00 PM PDT 24 |
Peak memory | 213088 kb |
Host | smart-e2934c55-b2b3-4b28-b37b-4613456ed73d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143252261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.143252261 |
Directory | /workspace/44.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1994431513 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 2716254699 ps |
CPU time | 7.19 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 268472 kb |
Host | smart-90320779-f89e-4fac-bc87-ed2c2106bb3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994431513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp ty.1994431513 |
Directory | /workspace/44.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_full.3790308807 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 1833020015 ps |
CPU time | 57.94 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:58 PM PDT 24 |
Peak memory | 635252 kb |
Host | smart-1fa52212-811e-4400-82fe-b3c803790770 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790308807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3790308807 |
Directory | /workspace/44.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_overflow.1742246247 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 9733475908 ps |
CPU time | 79.33 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:38:24 PM PDT 24 |
Peak memory | 786620 kb |
Host | smart-6ed20a34-3b05-429c-bf59-46961be99490 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742246247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1742246247 |
Directory | /workspace/44.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.4203353404 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 552521625 ps |
CPU time | 1.03 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:01 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-d184e7ff-0b1a-4c0b-90a3-590854e83b0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203353404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f mt.4203353404 |
Directory | /workspace/44.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_reset_rx.895975478 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 258381676 ps |
CPU time | 4.43 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:03 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-abe33c37-ab81-4b36-9a1e-17bc7637fb95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895975478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx. 895975478 |
Directory | /workspace/44.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/44.i2c_host_fifo_watermark.1816045597 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 9225470206 ps |
CPU time | 119.57 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:38:56 PM PDT 24 |
Peak memory | 1329100 kb |
Host | smart-131da0ae-ae99-4cb2-a4a6-60f30beee24f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816045597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1816045597 |
Directory | /workspace/44.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/44.i2c_host_may_nack.2266637491 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 342780236 ps |
CPU time | 5.55 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:14 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-8f8f3f86-4d54-448a-a013-41e2481337a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266637491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2266637491 |
Directory | /workspace/44.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/44.i2c_host_mode_toggle.1706750180 |
Short name | T1265 |
Test name | |
Test status | |
Simulation time | 2078045932 ps |
CPU time | 41.58 seconds |
Started | May 23 12:37:02 PM PDT 24 |
Finished | May 23 12:37:46 PM PDT 24 |
Peak memory | 382856 kb |
Host | smart-4b73c629-42b1-4402-bfb0-a2dfa7582f5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706750180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1706750180 |
Directory | /workspace/44.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/44.i2c_host_override.2130619357 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 75137362 ps |
CPU time | 0.69 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:37:06 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-ecd7ed07-b66a-4802-b78b-de504f477287 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130619357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2130619357 |
Directory | /workspace/44.i2c_host_override/latest |
Test location | /workspace/coverage/default/44.i2c_host_perf.1737732687 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 26293458186 ps |
CPU time | 122.83 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:39:03 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-c1557de8-5537-490d-b4bc-f93dc6480e3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737732687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1737732687 |
Directory | /workspace/44.i2c_host_perf/latest |
Test location | /workspace/coverage/default/44.i2c_host_smoke.2914231819 |
Short name | T1238 |
Test name | |
Test status | |
Simulation time | 4643274472 ps |
CPU time | 35.3 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:35 PM PDT 24 |
Peak memory | 334220 kb |
Host | smart-dcfcd018-a676-460e-bba3-f25d467a182f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914231819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2914231819 |
Directory | /workspace/44.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/44.i2c_host_stress_all.2584682157 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 20052243384 ps |
CPU time | 1427.26 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 01:00:47 PM PDT 24 |
Peak memory | 4261404 kb |
Host | smart-6de6fd6d-7b26-429e-a586-46ea2e0b0637 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584682157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2584682157 |
Directory | /workspace/44.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/44.i2c_host_stretch_timeout.2483497933 |
Short name | T1316 |
Test name | |
Test status | |
Simulation time | 835752442 ps |
CPU time | 15.87 seconds |
Started | May 23 12:36:57 PM PDT 24 |
Finished | May 23 12:37:15 PM PDT 24 |
Peak memory | 217836 kb |
Host | smart-ba62bb25-6da6-44ed-a60d-28d2b2e5fc01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483497933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2483497933 |
Directory | /workspace/44.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/44.i2c_target_bad_addr.3352742923 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 2792296013 ps |
CPU time | 5.98 seconds |
Started | May 23 12:37:02 PM PDT 24 |
Finished | May 23 12:37:10 PM PDT 24 |
Peak memory | 207580 kb |
Host | smart-f151fb1e-d999-4a5d-ba61-8524efb5bfcc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352742923 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3352742923 |
Directory | /workspace/44.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3406049906 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 10094622957 ps |
CPU time | 75.29 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:38:20 PM PDT 24 |
Peak memory | 438376 kb |
Host | smart-4e5b972f-2592-4ae2-b193-44f657773449 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406049906 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.3406049906 |
Directory | /workspace/44.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/44.i2c_target_fifo_reset_tx.4235798024 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 10102518996 ps |
CPU time | 69.63 seconds |
Started | May 23 12:37:01 PM PDT 24 |
Finished | May 23 12:38:13 PM PDT 24 |
Peak memory | 470804 kb |
Host | smart-ae3f6ae0-3a69-4c60-8210-da5dc68d3b4a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235798024 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 44.i2c_target_fifo_reset_tx.4235798024 |
Directory | /workspace/44.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/44.i2c_target_hrst.1973441662 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 455383346 ps |
CPU time | 2.96 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:11 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-f57100ef-3c28-4543-89a6-fe61e55f09f3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973441662 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_hrst.1973441662 |
Directory | /workspace/44.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/44.i2c_target_intr_smoke.859074693 |
Short name | T1168 |
Test name | |
Test status | |
Simulation time | 4252625799 ps |
CPU time | 5.65 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:03 PM PDT 24 |
Peak memory | 216508 kb |
Host | smart-6882b631-959e-460e-a55e-e9281dbfd33f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859074693 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.859074693 |
Directory | /workspace/44.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/44.i2c_target_intr_stress_wr.1668997200 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 4810722049 ps |
CPU time | 45.96 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:37:50 PM PDT 24 |
Peak memory | 1256428 kb |
Host | smart-339ecd00-0088-480b-b43a-17dd4d051522 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668997200 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1668997200 |
Directory | /workspace/44.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/44.i2c_target_smoke.1034317497 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 20568724137 ps |
CPU time | 48.2 seconds |
Started | May 23 12:36:58 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 203956 kb |
Host | smart-821f1c2a-23a9-49a3-9ef6-95d8e7a4d502 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034317497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta rget_smoke.1034317497 |
Directory | /workspace/44.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/44.i2c_target_stress_rd.3762461554 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 231798041 ps |
CPU time | 3.83 seconds |
Started | May 23 12:36:56 PM PDT 24 |
Finished | May 23 12:37:01 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-4eea4c06-914a-44ce-bee7-5e8faa3a3504 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762461554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2 c_target_stress_rd.3762461554 |
Directory | /workspace/44.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/44.i2c_target_stress_wr.3210502992 |
Short name | T1191 |
Test name | |
Test status | |
Simulation time | 21393754510 ps |
CPU time | 45.18 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 359528 kb |
Host | smart-e2d32e34-d11d-4e45-ab5b-b1e7ac982042 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210502992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2 c_target_stress_wr.3210502992 |
Directory | /workspace/44.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/44.i2c_target_stretch.1623985009 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 22075308679 ps |
CPU time | 147.15 seconds |
Started | May 23 12:37:00 PM PDT 24 |
Finished | May 23 12:39:30 PM PDT 24 |
Peak memory | 1373012 kb |
Host | smart-d192fea7-a372-4b70-afd6-ff9b4dd35cf5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623985009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ target_stretch.1623985009 |
Directory | /workspace/44.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/44.i2c_target_timeout.3229878444 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 4499401851 ps |
CPU time | 7.25 seconds |
Started | May 23 12:36:55 PM PDT 24 |
Finished | May 23 12:37:04 PM PDT 24 |
Peak memory | 218712 kb |
Host | smart-3ead4a8f-adfa-435a-bb2f-5a2d0a742af6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229878444 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 44.i2c_target_timeout.3229878444 |
Directory | /workspace/44.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/45.i2c_alert_test.1285211237 |
Short name | T1186 |
Test name | |
Test status | |
Simulation time | 42958385 ps |
CPU time | 0.59 seconds |
Started | May 23 12:37:05 PM PDT 24 |
Finished | May 23 12:37:08 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-d3112d83-976b-4233-95d6-75446f865456 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285211237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1285211237 |
Directory | /workspace/45.i2c_alert_test/latest |
Test location | /workspace/coverage/default/45.i2c_host_error_intr.3247941350 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 57701726 ps |
CPU time | 1.25 seconds |
Started | May 23 12:37:09 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-af76ba60-c954-42b6-ae71-dece1146a0af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247941350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3247941350 |
Directory | /workspace/45.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3740995029 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 352755120 ps |
CPU time | 1.95 seconds |
Started | May 23 12:37:05 PM PDT 24 |
Finished | May 23 12:37:09 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-8d9b649a-dc22-4d88-9586-f203d3deaa91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740995029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp ty.3740995029 |
Directory | /workspace/45.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_full.2442045736 |
Short name | T1136 |
Test name | |
Test status | |
Simulation time | 10511226385 ps |
CPU time | 154.85 seconds |
Started | May 23 12:37:04 PM PDT 24 |
Finished | May 23 12:39:40 PM PDT 24 |
Peak memory | 730272 kb |
Host | smart-f567ad6d-20d8-4c77-8d7a-90fc94d62b9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442045736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2442045736 |
Directory | /workspace/45.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_overflow.2791419071 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 18231932989 ps |
CPU time | 131.65 seconds |
Started | May 23 12:37:05 PM PDT 24 |
Finished | May 23 12:39:19 PM PDT 24 |
Peak memory | 628900 kb |
Host | smart-514e901e-61fe-4c6b-84c2-c832d5a6b50e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791419071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2791419071 |
Directory | /workspace/45.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1152556197 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 151124226 ps |
CPU time | 1.02 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:37:06 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-16cf5c3d-2475-458c-9812-88ecfc3f96cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152556197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f mt.1152556197 |
Directory | /workspace/45.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3627746005 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 199447154 ps |
CPU time | 5.66 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:37:11 PM PDT 24 |
Peak memory | 241000 kb |
Host | smart-713bb993-9b45-4127-983b-cf5549460934 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627746005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx .3627746005 |
Directory | /workspace/45.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/45.i2c_host_may_nack.2283808303 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 1177162375 ps |
CPU time | 3.92 seconds |
Started | May 23 12:37:14 PM PDT 24 |
Finished | May 23 12:37:19 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-0ea53779-1f5b-483a-9e3b-d4d8ecb18ccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283808303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2283808303 |
Directory | /workspace/45.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/45.i2c_host_mode_toggle.3211340149 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 8186366226 ps |
CPU time | 97.57 seconds |
Started | May 23 12:37:05 PM PDT 24 |
Finished | May 23 12:38:44 PM PDT 24 |
Peak memory | 380152 kb |
Host | smart-69768a38-6630-49b9-9870-4957df2b9621 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211340149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3211340149 |
Directory | /workspace/45.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/45.i2c_host_override.4206493869 |
Short name | T1236 |
Test name | |
Test status | |
Simulation time | 50290825 ps |
CPU time | 0.67 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:09 PM PDT 24 |
Peak memory | 204476 kb |
Host | smart-18327c37-6696-4060-92f6-820bfe8b2060 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206493869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.4206493869 |
Directory | /workspace/45.i2c_host_override/latest |
Test location | /workspace/coverage/default/45.i2c_host_perf.1865356699 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 17622046533 ps |
CPU time | 167.91 seconds |
Started | May 23 12:37:04 PM PDT 24 |
Finished | May 23 12:39:54 PM PDT 24 |
Peak memory | 858680 kb |
Host | smart-d5438e03-a9d0-4e35-aaa6-a0c0178b30ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865356699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1865356699 |
Directory | /workspace/45.i2c_host_perf/latest |
Test location | /workspace/coverage/default/45.i2c_host_smoke.3223627690 |
Short name | T1233 |
Test name | |
Test status | |
Simulation time | 5792708259 ps |
CPU time | 75.92 seconds |
Started | May 23 12:37:03 PM PDT 24 |
Finished | May 23 12:38:21 PM PDT 24 |
Peak memory | 327580 kb |
Host | smart-657754f4-ba53-4ebc-92c6-83c50292fc0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223627690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3223627690 |
Directory | /workspace/45.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/45.i2c_host_stretch_timeout.1549788185 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 675812325 ps |
CPU time | 7.93 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:16 PM PDT 24 |
Peak memory | 214160 kb |
Host | smart-7f02880d-f91e-42b1-b422-f437bdae169a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549788185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1549788185 |
Directory | /workspace/45.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/45.i2c_target_bad_addr.4144615400 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 3668818445 ps |
CPU time | 4.78 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 207196 kb |
Host | smart-fe35bee2-38eb-4231-a83d-e9819e3cb24c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144615400 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.4144615400 |
Directory | /workspace/45.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/45.i2c_target_fifo_reset_acq.173702179 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 10064052225 ps |
CPU time | 27.3 seconds |
Started | May 23 12:37:11 PM PDT 24 |
Finished | May 23 12:37:40 PM PDT 24 |
Peak memory | 334252 kb |
Host | smart-d89507e3-a24c-4ed7-90f3-27c96cdd236f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173702179 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 45.i2c_target_fifo_reset_acq.173702179 |
Directory | /workspace/45.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1922932882 |
Short name | T1192 |
Test name | |
Test status | |
Simulation time | 10070530356 ps |
CPU time | 28.85 seconds |
Started | May 23 12:37:09 PM PDT 24 |
Finished | May 23 12:37:39 PM PDT 24 |
Peak memory | 357892 kb |
Host | smart-0186583e-81d6-4b8e-90f4-e9ae4b6b63ba |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922932882 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 45.i2c_target_fifo_reset_tx.1922932882 |
Directory | /workspace/45.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/45.i2c_target_hrst.2139688738 |
Short name | T1224 |
Test name | |
Test status | |
Simulation time | 1857979242 ps |
CPU time | 2.76 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:37:11 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-f9349bf5-30d8-47bc-bfec-9d752096fddf |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139688738 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.2139688738 |
Directory | /workspace/45.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/45.i2c_target_intr_smoke.476745938 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 1074793205 ps |
CPU time | 5.98 seconds |
Started | May 23 12:37:04 PM PDT 24 |
Finished | May 23 12:37:12 PM PDT 24 |
Peak memory | 207504 kb |
Host | smart-b2f0397b-9f70-4cb8-ad87-ee484123d32d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476745938 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.476745938 |
Directory | /workspace/45.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/45.i2c_target_intr_stress_wr.3476559308 |
Short name | T1093 |
Test name | |
Test status | |
Simulation time | 5066491077 ps |
CPU time | 10.21 seconds |
Started | May 23 12:37:12 PM PDT 24 |
Finished | May 23 12:37:24 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-215b6fe0-7696-47ee-963c-934d836b4cfb |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476559308 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3476559308 |
Directory | /workspace/45.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/45.i2c_target_smoke.312290749 |
Short name | T1277 |
Test name | |
Test status | |
Simulation time | 1705299611 ps |
CPU time | 10.43 seconds |
Started | May 23 12:37:02 PM PDT 24 |
Finished | May 23 12:37:14 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-68501621-a16f-4c6e-8dca-857e264270a0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312290749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar get_smoke.312290749 |
Directory | /workspace/45.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/45.i2c_target_stress_rd.1816282602 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 2630729494 ps |
CPU time | 21.34 seconds |
Started | May 23 12:37:12 PM PDT 24 |
Finished | May 23 12:37:35 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-165fc13e-3dcb-4f4f-9ceb-7f6e988e85af |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816282602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2 c_target_stress_rd.1816282602 |
Directory | /workspace/45.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/45.i2c_target_stress_wr.2658933845 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 31428548437 ps |
CPU time | 35.62 seconds |
Started | May 23 12:37:09 PM PDT 24 |
Finished | May 23 12:37:46 PM PDT 24 |
Peak memory | 762984 kb |
Host | smart-da212f2a-3997-46fb-9f06-6a356899c831 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658933845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2 c_target_stress_wr.2658933845 |
Directory | /workspace/45.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/45.i2c_target_stretch.2194772171 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 37549743373 ps |
CPU time | 166.6 seconds |
Started | May 23 12:37:06 PM PDT 24 |
Finished | May 23 12:39:55 PM PDT 24 |
Peak memory | 1393616 kb |
Host | smart-eda2d57e-a0ec-45fd-8e10-d1aa1dbb8edc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194772171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ target_stretch.2194772171 |
Directory | /workspace/45.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/45.i2c_target_timeout.2630740322 |
Short name | T1270 |
Test name | |
Test status | |
Simulation time | 5726008021 ps |
CPU time | 7.41 seconds |
Started | May 23 12:37:09 PM PDT 24 |
Finished | May 23 12:37:18 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-5f402236-2330-4bc1-aca9-6378693489c2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630740322 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.i2c_target_timeout.2630740322 |
Directory | /workspace/45.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/46.i2c_alert_test.2926279558 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 22424090 ps |
CPU time | 0.62 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:21 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-cfb159b9-18ae-4597-892f-601919664e57 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926279558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2926279558 |
Directory | /workspace/46.i2c_alert_test/latest |
Test location | /workspace/coverage/default/46.i2c_host_error_intr.86665190 |
Short name | T1149 |
Test name | |
Test status | |
Simulation time | 1069587870 ps |
CPU time | 8.29 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:37:31 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-c580bbca-ddef-46c0-8848-9c5b3b8f1fbf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86665190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.86665190 |
Directory | /workspace/46.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1442395121 |
Short name | T1088 |
Test name | |
Test status | |
Simulation time | 1147627080 ps |
CPU time | 14.3 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 261108 kb |
Host | smart-924f8601-adc0-43e5-aa67-bc311a368807 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442395121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp ty.1442395121 |
Directory | /workspace/46.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_full.1865238210 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 5894721272 ps |
CPU time | 140.88 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:39:37 PM PDT 24 |
Peak memory | 688116 kb |
Host | smart-69ad6b1e-0263-4885-9971-e6173ce95af9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865238210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1865238210 |
Directory | /workspace/46.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_overflow.667703623 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 11597382872 ps |
CPU time | 78.93 seconds |
Started | May 23 12:37:07 PM PDT 24 |
Finished | May 23 12:38:28 PM PDT 24 |
Peak memory | 757884 kb |
Host | smart-d208f319-f2f6-49ba-adbf-0f7ad283953f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667703623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.667703623 |
Directory | /workspace/46.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.468104281 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 221581323 ps |
CPU time | 1.14 seconds |
Started | May 23 12:37:12 PM PDT 24 |
Finished | May 23 12:37:15 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-ece1b5b9-faa3-41ad-b0f5-c6f1d80ecf8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468104281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm t.468104281 |
Directory | /workspace/46.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2599598769 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 880391576 ps |
CPU time | 8.38 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:37:24 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-bde4a922-4c28-46a3-a3e7-70102ed06b94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599598769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx .2599598769 |
Directory | /workspace/46.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/46.i2c_host_fifo_watermark.1606537624 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 15996394173 ps |
CPU time | 229.51 seconds |
Started | May 23 12:37:07 PM PDT 24 |
Finished | May 23 12:40:59 PM PDT 24 |
Peak memory | 1002508 kb |
Host | smart-9c97ad81-7577-4803-9dae-eeef017b0a8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606537624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1606537624 |
Directory | /workspace/46.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/46.i2c_host_may_nack.4007316567 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 438273542 ps |
CPU time | 6.65 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:26 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-4e963179-19f6-4d07-a0e7-88e72feb9112 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007316567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.4007316567 |
Directory | /workspace/46.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/46.i2c_host_mode_toggle.3029165272 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 20076877132 ps |
CPU time | 82.95 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:38:41 PM PDT 24 |
Peak memory | 350628 kb |
Host | smart-c3b00d3b-d658-4d3d-b565-851cdcb35a51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029165272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3029165272 |
Directory | /workspace/46.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/46.i2c_host_override.751797451 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 34551248 ps |
CPU time | 0.65 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:37:17 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-12cdff67-95fa-446a-8436-e89c4f018aa0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751797451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.751797451 |
Directory | /workspace/46.i2c_host_override/latest |
Test location | /workspace/coverage/default/46.i2c_host_perf.2905597991 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 12209272462 ps |
CPU time | 230.68 seconds |
Started | May 23 12:37:12 PM PDT 24 |
Finished | May 23 12:41:04 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-8f47c29f-37e5-4364-8c19-f9464cb95153 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905597991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2905597991 |
Directory | /workspace/46.i2c_host_perf/latest |
Test location | /workspace/coverage/default/46.i2c_host_smoke.1390104554 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 6328334899 ps |
CPU time | 29.24 seconds |
Started | May 23 12:37:05 PM PDT 24 |
Finished | May 23 12:37:36 PM PDT 24 |
Peak memory | 311436 kb |
Host | smart-1601d64c-ecc7-46b6-9c79-232d496585f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390104554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1390104554 |
Directory | /workspace/46.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/46.i2c_host_stress_all.791459892 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 62374999636 ps |
CPU time | 3560 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 01:36:39 PM PDT 24 |
Peak memory | 5724936 kb |
Host | smart-ea5a6515-42a6-412b-ae95-a747a2ea246e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791459892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.791459892 |
Directory | /workspace/46.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/46.i2c_host_stretch_timeout.2910449561 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3446241832 ps |
CPU time | 35.46 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:37:52 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-fd0266a4-b885-4a06-814d-58013da4dc53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910449561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2910449561 |
Directory | /workspace/46.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/46.i2c_target_bad_addr.4277902248 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1418555626 ps |
CPU time | 3.67 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:37:27 PM PDT 24 |
Peak memory | 213044 kb |
Host | smart-496af109-d37f-47d1-a87a-17cb10b9e1ac |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277902248 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.4277902248 |
Directory | /workspace/46.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1150132917 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 10475192605 ps |
CPU time | 11.58 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:32 PM PDT 24 |
Peak memory | 248676 kb |
Host | smart-ba3afd3d-70f9-4d83-9191-7b5d66a7a114 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150132917 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.1150132917 |
Directory | /workspace/46.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2113264635 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 10105792980 ps |
CPU time | 74.47 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:38:35 PM PDT 24 |
Peak memory | 470636 kb |
Host | smart-07bc2b67-5cf1-447d-9db4-a724b125283b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113264635 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 46.i2c_target_fifo_reset_tx.2113264635 |
Directory | /workspace/46.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/46.i2c_target_hrst.3800415673 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 412947054 ps |
CPU time | 2.6 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-2f35efbd-3697-471c-90ec-56ba31e31e11 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800415673 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_hrst.3800415673 |
Directory | /workspace/46.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/46.i2c_target_intr_smoke.1928021071 |
Short name | T1147 |
Test name | |
Test status | |
Simulation time | 1071699999 ps |
CPU time | 6.26 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-ae09891a-079a-48c6-8816-0531d0b51ccc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928021071 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 46.i2c_target_intr_smoke.1928021071 |
Directory | /workspace/46.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/46.i2c_target_intr_stress_wr.2807641947 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 17945795197 ps |
CPU time | 36.4 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:57 PM PDT 24 |
Peak memory | 737080 kb |
Host | smart-b74ee282-5695-45f5-b209-3f673eb93389 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807641947 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2807641947 |
Directory | /workspace/46.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/46.i2c_target_smoke.1949866079 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 1317402213 ps |
CPU time | 48.04 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:38:06 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-d8906cd1-abd4-4bb4-8b0c-4a7961f66dad |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949866079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta rget_smoke.1949866079 |
Directory | /workspace/46.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/46.i2c_target_stress_rd.894838004 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 1921426317 ps |
CPU time | 5.26 seconds |
Started | May 23 12:37:22 PM PDT 24 |
Finished | May 23 12:37:29 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-941004bc-846f-41b9-a8db-0722e435fd0a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894838004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c _target_stress_rd.894838004 |
Directory | /workspace/46.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/46.i2c_target_stress_wr.1217885149 |
Short name | T1057 |
Test name | |
Test status | |
Simulation time | 24875550421 ps |
CPU time | 86.8 seconds |
Started | May 23 12:37:15 PM PDT 24 |
Finished | May 23 12:38:43 PM PDT 24 |
Peak memory | 1287296 kb |
Host | smart-ee943766-f7b3-46bf-a90d-d63bd5cd1418 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217885149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2 c_target_stress_wr.1217885149 |
Directory | /workspace/46.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/46.i2c_target_stretch.3086757154 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 23831621749 ps |
CPU time | 357.36 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:43:16 PM PDT 24 |
Peak memory | 2705996 kb |
Host | smart-83c236ea-1cb7-46b5-b6a3-1dad1bccac57 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086757154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ target_stretch.3086757154 |
Directory | /workspace/46.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/46.i2c_target_timeout.2121797066 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 1242760489 ps |
CPU time | 7.29 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 215160 kb |
Host | smart-8c70833e-5a87-4c84-ab8c-7319d4ab6731 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121797066 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.i2c_target_timeout.2121797066 |
Directory | /workspace/46.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/47.i2c_alert_test.3372766049 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 24803375 ps |
CPU time | 0.6 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:21 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-dcccd6b1-756b-4933-a246-fca3d59ae3fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372766049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3372766049 |
Directory | /workspace/47.i2c_alert_test/latest |
Test location | /workspace/coverage/default/47.i2c_host_error_intr.3257140559 |
Short name | T1219 |
Test name | |
Test status | |
Simulation time | 89566904 ps |
CPU time | 2.05 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:24 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-2aa2c220-3f59-411f-a944-a4425576da9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257140559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3257140559 |
Directory | /workspace/47.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3932870059 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 415338471 ps |
CPU time | 7.52 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:37:26 PM PDT 24 |
Peak memory | 290528 kb |
Host | smart-fd5d68b4-7f8e-46e3-b94c-b12b20330d6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932870059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp ty.3932870059 |
Directory | /workspace/47.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_full.4021290119 |
Short name | T1274 |
Test name | |
Test status | |
Simulation time | 9258434382 ps |
CPU time | 164.93 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:40:04 PM PDT 24 |
Peak memory | 675760 kb |
Host | smart-a108a580-e1f2-41ab-895c-90801c54938e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021290119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.4021290119 |
Directory | /workspace/47.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_overflow.1145104994 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 3605558677 ps |
CPU time | 42.95 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:38:05 PM PDT 24 |
Peak memory | 489068 kb |
Host | smart-41702d62-eebb-4a8b-b1af-37425e233e10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145104994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1145104994 |
Directory | /workspace/47.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1316524627 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 643459325 ps |
CPU time | 1.01 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:20 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-064df35c-f5c6-4c93-8342-62797362c001 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316524627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f mt.1316524627 |
Directory | /workspace/47.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_reset_rx.156196299 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 235538844 ps |
CPU time | 5.42 seconds |
Started | May 23 12:37:24 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 247604 kb |
Host | smart-4c93546c-5327-4cd2-95c5-aad51e17aab9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156196299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx. 156196299 |
Directory | /workspace/47.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/47.i2c_host_fifo_watermark.587468778 |
Short name | T1078 |
Test name | |
Test status | |
Simulation time | 4007871249 ps |
CPU time | 275.88 seconds |
Started | May 23 12:37:16 PM PDT 24 |
Finished | May 23 12:41:54 PM PDT 24 |
Peak memory | 1139712 kb |
Host | smart-c9c88598-00e0-4338-b0a6-15ba108bed86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587468778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.587468778 |
Directory | /workspace/47.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/47.i2c_host_may_nack.3069979761 |
Short name | T1128 |
Test name | |
Test status | |
Simulation time | 1551743056 ps |
CPU time | 14.98 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:37:37 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-849807d7-729d-439e-9e96-59d126e04e91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069979761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3069979761 |
Directory | /workspace/47.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/47.i2c_host_mode_toggle.3068981258 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 1958687309 ps |
CPU time | 36.33 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:56 PM PDT 24 |
Peak memory | 334640 kb |
Host | smart-6b76a829-7d70-4bbf-8fd5-bc85acf943ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068981258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3068981258 |
Directory | /workspace/47.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/47.i2c_host_override.2367689242 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 16866384 ps |
CPU time | 0.69 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 204564 kb |
Host | smart-ae03f162-b7bd-4a22-857e-30aaf8e6fb04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367689242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2367689242 |
Directory | /workspace/47.i2c_host_override/latest |
Test location | /workspace/coverage/default/47.i2c_host_perf.3865457818 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 7617058370 ps |
CPU time | 69.44 seconds |
Started | May 23 12:37:16 PM PDT 24 |
Finished | May 23 12:38:27 PM PDT 24 |
Peak memory | 361312 kb |
Host | smart-dc281b19-409d-4c55-95f0-68bea87e977f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865457818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3865457818 |
Directory | /workspace/47.i2c_host_perf/latest |
Test location | /workspace/coverage/default/47.i2c_host_smoke.3487517638 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 1707056039 ps |
CPU time | 27.88 seconds |
Started | May 23 12:37:16 PM PDT 24 |
Finished | May 23 12:37:45 PM PDT 24 |
Peak memory | 371996 kb |
Host | smart-b44895b4-4208-4cf6-a034-7afd623796c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487517638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3487517638 |
Directory | /workspace/47.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/47.i2c_host_stress_all.3063190212 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 26251871041 ps |
CPU time | 1181.66 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:57:00 PM PDT 24 |
Peak memory | 1888496 kb |
Host | smart-a79b19a8-c549-45af-a4f2-a8ae96c6881c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063190212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3063190212 |
Directory | /workspace/47.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/47.i2c_host_stretch_timeout.1311380876 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 5526954433 ps |
CPU time | 28.61 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 213108 kb |
Host | smart-92c17703-c4d4-4b1e-b705-e28bd593417c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311380876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1311380876 |
Directory | /workspace/47.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/47.i2c_target_bad_addr.4280662234 |
Short name | T1333 |
Test name | |
Test status | |
Simulation time | 650645250 ps |
CPU time | 4.16 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-1581286d-ed42-46c1-bdd5-b04b480aa302 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280662234 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4280662234 |
Directory | /workspace/47.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2699270733 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 10065074379 ps |
CPU time | 69.73 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:38:31 PM PDT 24 |
Peak memory | 496104 kb |
Host | smart-3aa41070-b6a7-4a5f-bf9f-b15b6a8a4682 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699270733 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.2699270733 |
Directory | /workspace/47.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2620883208 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 10677457308 ps |
CPU time | 7 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:28 PM PDT 24 |
Peak memory | 245628 kb |
Host | smart-ef5f187a-3165-40a7-9a4e-6696513c8f3e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620883208 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 47.i2c_target_fifo_reset_tx.2620883208 |
Directory | /workspace/47.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/47.i2c_target_hrst.3199672889 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1312561847 ps |
CPU time | 2.19 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-e0144b1e-4735-4331-996d-dad459b47507 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199672889 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.3199672889 |
Directory | /workspace/47.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/47.i2c_target_intr_smoke.728976413 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 2537386911 ps |
CPU time | 3.62 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 206140 kb |
Host | smart-01c40f6e-f5da-4ea5-83cd-77f5c0b58a8b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728976413 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.728976413 |
Directory | /workspace/47.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/47.i2c_target_intr_stress_wr.3322282046 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 25620930482 ps |
CPU time | 161.79 seconds |
Started | May 23 12:37:16 PM PDT 24 |
Finished | May 23 12:39:59 PM PDT 24 |
Peak memory | 2631320 kb |
Host | smart-c33634f2-8be4-4cae-a3bf-fbb0ce2783fc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322282046 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3322282046 |
Directory | /workspace/47.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/47.i2c_target_smoke.3093041312 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 1905722646 ps |
CPU time | 8.32 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:29 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-89ae5a48-14dd-4706-b0aa-083583fb2db6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093041312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta rget_smoke.3093041312 |
Directory | /workspace/47.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/47.i2c_target_stress_rd.590669012 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 26213987678 ps |
CPU time | 24.92 seconds |
Started | May 23 12:37:16 PM PDT 24 |
Finished | May 23 12:37:42 PM PDT 24 |
Peak memory | 222316 kb |
Host | smart-09ab1ba3-f1c8-45aa-8f2f-2d8c529593b9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590669012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c _target_stress_rd.590669012 |
Directory | /workspace/47.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/47.i2c_target_stress_wr.3948910107 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 43066173264 ps |
CPU time | 267.35 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:41:51 PM PDT 24 |
Peak memory | 2983432 kb |
Host | smart-1ab81512-58ce-4fdd-a2ff-e563693676c5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948910107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2 c_target_stress_wr.3948910107 |
Directory | /workspace/47.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/47.i2c_target_stretch.3133228423 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 22008946809 ps |
CPU time | 1147.81 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:56:31 PM PDT 24 |
Peak memory | 5141624 kb |
Host | smart-efaea2cc-cc8b-4f6d-9151-5e8c5fb92c87 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133228423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ target_stretch.3133228423 |
Directory | /workspace/47.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/47.i2c_target_timeout.1582545054 |
Short name | T1264 |
Test name | |
Test status | |
Simulation time | 2460556143 ps |
CPU time | 7.26 seconds |
Started | May 23 12:37:18 PM PDT 24 |
Finished | May 23 12:37:27 PM PDT 24 |
Peak memory | 217608 kb |
Host | smart-44044a07-c7a6-4357-96bb-aaf1a2de91d1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582545054 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.i2c_target_timeout.1582545054 |
Directory | /workspace/47.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/48.i2c_alert_test.1259438420 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 14250019 ps |
CPU time | 0.61 seconds |
Started | May 23 12:37:33 PM PDT 24 |
Finished | May 23 12:37:35 PM PDT 24 |
Peak memory | 204460 kb |
Host | smart-2e744cc8-70f6-4f57-b76b-996a398e3b54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259438420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1259438420 |
Directory | /workspace/48.i2c_alert_test/latest |
Test location | /workspace/coverage/default/48.i2c_host_error_intr.1997604597 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 229623149 ps |
CPU time | 1.79 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:37:24 PM PDT 24 |
Peak memory | 213104 kb |
Host | smart-d9a565e1-69ec-47b4-a123-a7c4bb24cbec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997604597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1997604597 |
Directory | /workspace/48.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.831421318 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 792432571 ps |
CPU time | 7.43 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:29 PM PDT 24 |
Peak memory | 230472 kb |
Host | smart-e39555aa-5fff-4e60-9674-5b55231417a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831421318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt y.831421318 |
Directory | /workspace/48.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_full.3138450506 |
Short name | T1118 |
Test name | |
Test status | |
Simulation time | 2989274953 ps |
CPU time | 76.67 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:38:40 PM PDT 24 |
Peak memory | 255296 kb |
Host | smart-8b4dd70c-9d39-4681-bb7f-e895474d25d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138450506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3138450506 |
Directory | /workspace/48.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_overflow.3553724890 |
Short name | T1252 |
Test name | |
Test status | |
Simulation time | 3171561611 ps |
CPU time | 53.36 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:38:12 PM PDT 24 |
Peak memory | 600164 kb |
Host | smart-4057633f-48b1-4d61-8788-3758dc6d24f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553724890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3553724890 |
Directory | /workspace/48.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2805058200 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 200805384 ps |
CPU time | 0.99 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-08539201-e7f3-487f-bc57-c1b0a7ada515 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805058200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f mt.2805058200 |
Directory | /workspace/48.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_reset_rx.46082110 |
Short name | T1292 |
Test name | |
Test status | |
Simulation time | 498234446 ps |
CPU time | 3.32 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:25 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-f83b2c5b-3802-4d78-ac94-266b9ef0a09c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46082110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.46082110 |
Directory | /workspace/48.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/48.i2c_host_fifo_watermark.3398950988 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 2813794921 ps |
CPU time | 186.17 seconds |
Started | May 23 12:37:21 PM PDT 24 |
Finished | May 23 12:40:29 PM PDT 24 |
Peak memory | 864280 kb |
Host | smart-72be8101-e099-459b-9b9b-4d677bc3acb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398950988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3398950988 |
Directory | /workspace/48.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/48.i2c_host_may_nack.2376272163 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 1514096880 ps |
CPU time | 4.38 seconds |
Started | May 23 12:37:31 PM PDT 24 |
Finished | May 23 12:37:37 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-2b4d7c37-d450-436c-b4dc-df191fd277ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376272163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2376272163 |
Directory | /workspace/48.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/48.i2c_host_mode_toggle.2733709245 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 1537453624 ps |
CPU time | 23.77 seconds |
Started | May 23 12:37:36 PM PDT 24 |
Finished | May 23 12:38:01 PM PDT 24 |
Peak memory | 344344 kb |
Host | smart-8f318d12-45f4-4fe2-b2af-2c6716dc39ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733709245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2733709245 |
Directory | /workspace/48.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/48.i2c_host_override.3965973238 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 47031568 ps |
CPU time | 0.66 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:37:23 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-5b087205-0369-44c9-b248-784e288ee952 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965973238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3965973238 |
Directory | /workspace/48.i2c_host_override/latest |
Test location | /workspace/coverage/default/48.i2c_host_perf.2671294143 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1183326094 ps |
CPU time | 12.71 seconds |
Started | May 23 12:37:19 PM PDT 24 |
Finished | May 23 12:37:34 PM PDT 24 |
Peak memory | 229412 kb |
Host | smart-7680646a-5e55-40d7-9c70-45406a9b575f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671294143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2671294143 |
Directory | /workspace/48.i2c_host_perf/latest |
Test location | /workspace/coverage/default/48.i2c_host_smoke.1488927572 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 2795696222 ps |
CPU time | 23.6 seconds |
Started | May 23 12:37:17 PM PDT 24 |
Finished | May 23 12:37:42 PM PDT 24 |
Peak memory | 315312 kb |
Host | smart-1f2e49d0-d800-48d9-9442-2f82a9c3adc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488927572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1488927572 |
Directory | /workspace/48.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/48.i2c_host_stress_all.3731178757 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 22247078628 ps |
CPU time | 1505.2 seconds |
Started | May 23 12:37:24 PM PDT 24 |
Finished | May 23 01:02:30 PM PDT 24 |
Peak memory | 2511356 kb |
Host | smart-6e65e23c-f686-4a39-932c-c8b6369dbe03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3731178757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3731178757 |
Directory | /workspace/48.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/48.i2c_host_stretch_timeout.3903679060 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 1864269530 ps |
CPU time | 22.01 seconds |
Started | May 23 12:37:20 PM PDT 24 |
Finished | May 23 12:37:44 PM PDT 24 |
Peak memory | 213120 kb |
Host | smart-5ff0c166-45d1-46e1-9c19-6d1a30583cb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903679060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3903679060 |
Directory | /workspace/48.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/48.i2c_target_bad_addr.1638975424 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 817779712 ps |
CPU time | 4.49 seconds |
Started | May 23 12:37:31 PM PDT 24 |
Finished | May 23 12:37:38 PM PDT 24 |
Peak memory | 213076 kb |
Host | smart-4ee0235e-8d27-4e7d-bd74-2baac408794d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638975424 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1638975424 |
Directory | /workspace/48.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/48.i2c_target_fifo_reset_acq.441216329 |
Short name | T1285 |
Test name | |
Test status | |
Simulation time | 10069720780 ps |
CPU time | 70.73 seconds |
Started | May 23 12:37:30 PM PDT 24 |
Finished | May 23 12:38:42 PM PDT 24 |
Peak memory | 482684 kb |
Host | smart-9bd29828-6f4e-4085-bf6e-ff77bb226132 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441216329 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 48.i2c_target_fifo_reset_acq.441216329 |
Directory | /workspace/48.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4178653425 |
Short name | T1213 |
Test name | |
Test status | |
Simulation time | 10216209109 ps |
CPU time | 11.54 seconds |
Started | May 23 12:37:30 PM PDT 24 |
Finished | May 23 12:37:43 PM PDT 24 |
Peak memory | 281064 kb |
Host | smart-3c76eaae-2c9e-40c4-968d-d7cbd3ec4768 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178653425 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 48.i2c_target_fifo_reset_tx.4178653425 |
Directory | /workspace/48.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/48.i2c_target_hrst.2624843109 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1446610996 ps |
CPU time | 2.63 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:37:36 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-8047ac15-0645-4d63-a209-a16b27dd0262 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624843109 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_hrst.2624843109 |
Directory | /workspace/48.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/48.i2c_target_intr_smoke.1354669766 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 4951312230 ps |
CPU time | 6.55 seconds |
Started | May 23 12:37:30 PM PDT 24 |
Finished | May 23 12:37:38 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-4416c170-dc2b-4e7e-948f-84fd80cdc32c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354669766 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 48.i2c_target_intr_smoke.1354669766 |
Directory | /workspace/48.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/48.i2c_target_intr_stress_wr.3481014922 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 7692488666 ps |
CPU time | 5.78 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:37:40 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-8b1590f8-57eb-4121-a274-49565195d8da |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481014922 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3481014922 |
Directory | /workspace/48.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/48.i2c_target_smoke.2330889719 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 2156046374 ps |
CPU time | 16.82 seconds |
Started | May 23 12:37:30 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-a7db8508-5f01-4ef0-95ec-7cbb9b7d9cee |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330889719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta rget_smoke.2330889719 |
Directory | /workspace/48.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/48.i2c_target_stress_rd.1201993319 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 2717016868 ps |
CPU time | 10.57 seconds |
Started | May 23 12:37:28 PM PDT 24 |
Finished | May 23 12:37:39 PM PDT 24 |
Peak memory | 212984 kb |
Host | smart-c17b8a78-09b7-4b04-b531-8349bb9dd45d |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201993319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2 c_target_stress_rd.1201993319 |
Directory | /workspace/48.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/48.i2c_target_stress_wr.2312410681 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 42834618785 ps |
CPU time | 89.1 seconds |
Started | May 23 12:37:29 PM PDT 24 |
Finished | May 23 12:38:59 PM PDT 24 |
Peak memory | 1480576 kb |
Host | smart-2fb5b054-3b75-41e4-981c-fea9fa83b4a8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312410681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2 c_target_stress_wr.2312410681 |
Directory | /workspace/48.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/48.i2c_target_stretch.3951237978 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 22061492718 ps |
CPU time | 38.86 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:38:12 PM PDT 24 |
Peak memory | 273944 kb |
Host | smart-7a50066f-a53b-4dc4-8499-346b6b8eeef8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951237978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ target_stretch.3951237978 |
Directory | /workspace/48.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/48.i2c_target_timeout.4080060925 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 1562840115 ps |
CPU time | 7.62 seconds |
Started | May 23 12:37:31 PM PDT 24 |
Finished | May 23 12:37:41 PM PDT 24 |
Peak memory | 220620 kb |
Host | smart-4fd04ad9-de89-4bc4-8136-bba6a30b10aa |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080060925 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.i2c_target_timeout.4080060925 |
Directory | /workspace/48.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/49.i2c_alert_test.2774223642 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 28018418 ps |
CPU time | 0.63 seconds |
Started | May 23 12:37:35 PM PDT 24 |
Finished | May 23 12:37:37 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-f097e91c-22d3-47d1-b0fe-399d9f9e6256 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774223642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2774223642 |
Directory | /workspace/49.i2c_alert_test/latest |
Test location | /workspace/coverage/default/49.i2c_host_error_intr.1701168967 |
Short name | T1300 |
Test name | |
Test status | |
Simulation time | 209275119 ps |
CPU time | 6.04 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:37:40 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-907c0ef6-21eb-456d-a88a-76d5aa5853e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701168967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1701168967 |
Directory | /workspace/49.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4062905737 |
Short name | T1330 |
Test name | |
Test status | |
Simulation time | 293376560 ps |
CPU time | 14.89 seconds |
Started | May 23 12:37:33 PM PDT 24 |
Finished | May 23 12:37:50 PM PDT 24 |
Peak memory | 253868 kb |
Host | smart-3de42d1b-90ea-438b-a540-1616ca5607ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062905737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp ty.4062905737 |
Directory | /workspace/49.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_full.2516601516 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 2694856390 ps |
CPU time | 74.88 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:38:49 PM PDT 24 |
Peak memory | 298220 kb |
Host | smart-34d4af36-2651-4272-8da9-cc1990aa3be3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516601516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2516601516 |
Directory | /workspace/49.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_overflow.366037486 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 2345749237 ps |
CPU time | 179.88 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:40:34 PM PDT 24 |
Peak memory | 747016 kb |
Host | smart-0dd750c6-5fe6-4ab3-95ee-267b40d87d68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366037486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.366037486 |
Directory | /workspace/49.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.551416661 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 96541689 ps |
CPU time | 0.86 seconds |
Started | May 23 12:37:31 PM PDT 24 |
Finished | May 23 12:37:34 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-0ebe9c60-7f6c-4a99-95d9-c277154bd4dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551416661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm t.551416661 |
Directory | /workspace/49.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_reset_rx.115880481 |
Short name | T1282 |
Test name | |
Test status | |
Simulation time | 137884557 ps |
CPU time | 6.88 seconds |
Started | May 23 12:37:33 PM PDT 24 |
Finished | May 23 12:37:42 PM PDT 24 |
Peak memory | 224572 kb |
Host | smart-c628a45a-f22c-4544-8778-379000d8d6bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115880481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx. 115880481 |
Directory | /workspace/49.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/49.i2c_host_fifo_watermark.3009015303 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 31486480954 ps |
CPU time | 187.39 seconds |
Started | May 23 12:37:31 PM PDT 24 |
Finished | May 23 12:40:40 PM PDT 24 |
Peak memory | 1489112 kb |
Host | smart-5cbff958-632a-4b9a-9b9d-78fc490ed76a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009015303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3009015303 |
Directory | /workspace/49.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/49.i2c_host_may_nack.3142258331 |
Short name | T1069 |
Test name | |
Test status | |
Simulation time | 228132839 ps |
CPU time | 8.62 seconds |
Started | May 23 12:37:45 PM PDT 24 |
Finished | May 23 12:37:56 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-2dd7ce53-43c9-49a7-a2b3-30fa1cabced6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142258331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3142258331 |
Directory | /workspace/49.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/49.i2c_host_mode_toggle.2098592549 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 4527537622 ps |
CPU time | 22.72 seconds |
Started | May 23 12:37:43 PM PDT 24 |
Finished | May 23 12:38:08 PM PDT 24 |
Peak memory | 330220 kb |
Host | smart-4240fb7d-2526-4f30-aca2-b2e2030c9b45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098592549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2098592549 |
Directory | /workspace/49.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/49.i2c_host_override.2923210384 |
Short name | T1293 |
Test name | |
Test status | |
Simulation time | 27444996 ps |
CPU time | 0.67 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:37:34 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-20efc721-78ea-48b4-ae53-fafc932f6b26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923210384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2923210384 |
Directory | /workspace/49.i2c_host_override/latest |
Test location | /workspace/coverage/default/49.i2c_host_perf.1740497512 |
Short name | T1205 |
Test name | |
Test status | |
Simulation time | 6857390043 ps |
CPU time | 20.08 seconds |
Started | May 23 12:37:37 PM PDT 24 |
Finished | May 23 12:37:59 PM PDT 24 |
Peak memory | 241288 kb |
Host | smart-93f95398-30f1-4d67-8f44-162675539743 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740497512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1740497512 |
Directory | /workspace/49.i2c_host_perf/latest |
Test location | /workspace/coverage/default/49.i2c_host_smoke.2114959014 |
Short name | T1337 |
Test name | |
Test status | |
Simulation time | 6370009947 ps |
CPU time | 26.31 seconds |
Started | May 23 12:37:34 PM PDT 24 |
Finished | May 23 12:38:02 PM PDT 24 |
Peak memory | 361372 kb |
Host | smart-d241c1f3-2fb6-4dce-8585-1373338ed3f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114959014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2114959014 |
Directory | /workspace/49.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/49.i2c_host_stretch_timeout.599773602 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 868192419 ps |
CPU time | 39.05 seconds |
Started | May 23 12:37:37 PM PDT 24 |
Finished | May 23 12:38:18 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-d4ea5b7a-8b0c-43a6-a9c9-f9d85e927a5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599773602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.599773602 |
Directory | /workspace/49.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/49.i2c_target_bad_addr.2418292718 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 2219883435 ps |
CPU time | 3.04 seconds |
Started | May 23 12:37:34 PM PDT 24 |
Finished | May 23 12:37:39 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-f11b78bf-2a7b-44a7-a2b0-7cfc9f2fcb6e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418292718 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2418292718 |
Directory | /workspace/49.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1447028982 |
Short name | T1040 |
Test name | |
Test status | |
Simulation time | 10062723434 ps |
CPU time | 70.49 seconds |
Started | May 23 12:37:29 PM PDT 24 |
Finished | May 23 12:38:40 PM PDT 24 |
Peak memory | 418196 kb |
Host | smart-062e3402-fe1e-492f-bd7f-68327cb21d85 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447028982 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.1447028982 |
Directory | /workspace/49.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1279100689 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 10049370227 ps |
CPU time | 78.27 seconds |
Started | May 23 12:37:32 PM PDT 24 |
Finished | May 23 12:38:52 PM PDT 24 |
Peak memory | 477960 kb |
Host | smart-65c460c4-75ad-476d-9876-823dbd575320 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279100689 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 49.i2c_target_fifo_reset_tx.1279100689 |
Directory | /workspace/49.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/49.i2c_target_hrst.76539030 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 2087737112 ps |
CPU time | 1.86 seconds |
Started | May 23 12:37:44 PM PDT 24 |
Finished | May 23 12:37:49 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-d3fc7cc9-8b3b-45e7-9679-fb264683352f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76539030 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.i2c_target_hrst.76539030 |
Directory | /workspace/49.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/49.i2c_target_intr_smoke.4033816401 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 3646816346 ps |
CPU time | 4.91 seconds |
Started | May 23 12:37:37 PM PDT 24 |
Finished | May 23 12:37:43 PM PDT 24 |
Peak memory | 213108 kb |
Host | smart-11dc66d0-db4c-41b1-8a12-a0048d575f6f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033816401 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 49.i2c_target_intr_smoke.4033816401 |
Directory | /workspace/49.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/49.i2c_target_intr_stress_wr.3335153408 |
Short name | T1171 |
Test name | |
Test status | |
Simulation time | 15375294828 ps |
CPU time | 5.48 seconds |
Started | May 23 12:37:35 PM PDT 24 |
Finished | May 23 12:37:42 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-ff0d3bfd-2983-458e-a606-8b2c8c43a1d5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335153408 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3335153408 |
Directory | /workspace/49.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/49.i2c_target_smoke.3830903247 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 11555239682 ps |
CPU time | 38.6 seconds |
Started | May 23 12:37:36 PM PDT 24 |
Finished | May 23 12:38:16 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-d929283d-69f5-4010-9b51-87862e070131 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830903247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta rget_smoke.3830903247 |
Directory | /workspace/49.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/49.i2c_target_stress_rd.1677179385 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1121775016 ps |
CPU time | 9.03 seconds |
Started | May 23 12:37:38 PM PDT 24 |
Finished | May 23 12:37:48 PM PDT 24 |
Peak memory | 208592 kb |
Host | smart-38072263-191d-4be3-9078-b77c65ed42f6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677179385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2 c_target_stress_rd.1677179385 |
Directory | /workspace/49.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/49.i2c_target_stress_wr.2914923790 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 13413951664 ps |
CPU time | 7.12 seconds |
Started | May 23 12:37:37 PM PDT 24 |
Finished | May 23 12:37:45 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-658352c5-c300-4d16-96a9-9e189d8c3b75 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914923790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2 c_target_stress_wr.2914923790 |
Directory | /workspace/49.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/49.i2c_target_stretch.1537900384 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 22994784235 ps |
CPU time | 303.77 seconds |
Started | May 23 12:37:34 PM PDT 24 |
Finished | May 23 12:42:40 PM PDT 24 |
Peak memory | 2488604 kb |
Host | smart-d2a3e601-4811-4c71-8c8a-01bcbd6af9ba |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537900384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ target_stretch.1537900384 |
Directory | /workspace/49.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/49.i2c_target_timeout.3375957473 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 10844137308 ps |
CPU time | 7.61 seconds |
Started | May 23 12:37:35 PM PDT 24 |
Finished | May 23 12:37:44 PM PDT 24 |
Peak memory | 219808 kb |
Host | smart-b83cf573-dcc9-4b97-8a2a-36f40be63735 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375957473 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.i2c_target_timeout.3375957473 |
Directory | /workspace/49.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/5.i2c_alert_test.3455256119 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 36899126 ps |
CPU time | 0.63 seconds |
Started | May 23 12:33:03 PM PDT 24 |
Finished | May 23 12:33:07 PM PDT 24 |
Peak memory | 204440 kb |
Host | smart-b142e45e-ae1d-4dd8-a4ea-8dda189b1fd7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455256119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3455256119 |
Directory | /workspace/5.i2c_alert_test/latest |
Test location | /workspace/coverage/default/5.i2c_host_error_intr.2362352713 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 126353510 ps |
CPU time | 2.22 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 221360 kb |
Host | smart-ddc7d7ef-9464-46dd-a999-62d8acbd7234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362352713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2362352713 |
Directory | /workspace/5.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1403199916 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 867108263 ps |
CPU time | 4.3 seconds |
Started | May 23 12:33:04 PM PDT 24 |
Finished | May 23 12:33:11 PM PDT 24 |
Peak memory | 238152 kb |
Host | smart-4c179953-2287-40c6-89f0-98b3a92d7062 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403199916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt y.1403199916 |
Directory | /workspace/5.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_full.3638737808 |
Short name | T1050 |
Test name | |
Test status | |
Simulation time | 2495031135 ps |
CPU time | 62.55 seconds |
Started | May 23 12:32:57 PM PDT 24 |
Finished | May 23 12:34:02 PM PDT 24 |
Peak memory | 604016 kb |
Host | smart-8e243d69-9922-4f6c-9f7b-e61830cd4be9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638737808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3638737808 |
Directory | /workspace/5.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_overflow.782274154 |
Short name | T1227 |
Test name | |
Test status | |
Simulation time | 3047464943 ps |
CPU time | 88.55 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:34:31 PM PDT 24 |
Peak memory | 780124 kb |
Host | smart-edc0ec1e-b9cd-48da-a39a-5b217b3727bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782274154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.782274154 |
Directory | /workspace/5.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.4229084168 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 124074391 ps |
CPU time | 1.13 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:04 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-3633a94f-bd80-4617-aee9-0776980c6440 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229084168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm t.4229084168 |
Directory | /workspace/5.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3115164173 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1518832237 ps |
CPU time | 3.94 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:33:08 PM PDT 24 |
Peak memory | 233332 kb |
Host | smart-f9105e37-51c4-46c2-9b11-5b0341b4f371 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115164173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx. 3115164173 |
Directory | /workspace/5.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/5.i2c_host_fifo_watermark.3105014438 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 25851610733 ps |
CPU time | 77.62 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:34:20 PM PDT 24 |
Peak memory | 880072 kb |
Host | smart-eda95a11-4386-4d00-ac0f-d06d06ba6a6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105014438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3105014438 |
Directory | /workspace/5.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/5.i2c_host_may_nack.4103342510 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 863768602 ps |
CPU time | 5.68 seconds |
Started | May 23 12:32:57 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-4683b7d0-6856-487e-a55f-5a80caa4fada |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103342510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4103342510 |
Directory | /workspace/5.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/5.i2c_host_mode_toggle.62383287 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 6384332743 ps |
CPU time | 67.98 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:34:13 PM PDT 24 |
Peak memory | 277652 kb |
Host | smart-ba3b82b0-261b-4b5f-881c-453441bdb152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62383287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.62383287 |
Directory | /workspace/5.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/5.i2c_host_override.365080309 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 41991401 ps |
CPU time | 0.62 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:04 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-89607b2e-6241-4272-be54-b2f7bccf567f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365080309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.365080309 |
Directory | /workspace/5.i2c_host_override/latest |
Test location | /workspace/coverage/default/5.i2c_host_perf.1543080768 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 13618548941 ps |
CPU time | 1093.7 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:51:18 PM PDT 24 |
Peak memory | 1903172 kb |
Host | smart-e580d8b3-4b92-4ade-a331-c310912f00a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543080768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1543080768 |
Directory | /workspace/5.i2c_host_perf/latest |
Test location | /workspace/coverage/default/5.i2c_host_smoke.2103515789 |
Short name | T1216 |
Test name | |
Test status | |
Simulation time | 7586636685 ps |
CPU time | 102.47 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:34:48 PM PDT 24 |
Peak memory | 429468 kb |
Host | smart-b863503d-43ca-470b-825d-8174b8b7886e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103515789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2103515789 |
Directory | /workspace/5.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/5.i2c_host_stress_all.4292060235 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 25760598904 ps |
CPU time | 2043.69 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 01:07:06 PM PDT 24 |
Peak memory | 4280580 kb |
Host | smart-5b5e09b0-eed9-4fea-8af4-08d13c1eb553 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292060235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.4292060235 |
Directory | /workspace/5.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/5.i2c_host_stretch_timeout.4147207297 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 475509626 ps |
CPU time | 7.06 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-bc53adbc-08b3-4ece-bb14-5d82ea0dab7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147207297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.4147207297 |
Directory | /workspace/5.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/5.i2c_target_bad_addr.2778118837 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 623273276 ps |
CPU time | 2.48 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:03 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-127ee4e3-9d4d-48bb-8056-3daec2798b84 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778118837 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2778118837 |
Directory | /workspace/5.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/5.i2c_target_fifo_reset_acq.254601287 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 10064366005 ps |
CPU time | 67.91 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:34:08 PM PDT 24 |
Peak memory | 421392 kb |
Host | smart-05b17357-8f0b-4da2-8f3e-9f6d05c038ff |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254601287 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.i2c_target_fifo_reset_acq.254601287 |
Directory | /workspace/5.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1420364271 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 10343468180 ps |
CPU time | 16.49 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:20 PM PDT 24 |
Peak memory | 280044 kb |
Host | smart-4fa8b513-80dd-4f0b-b145-8342c8df457a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420364271 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.i2c_target_fifo_reset_tx.1420364271 |
Directory | /workspace/5.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/5.i2c_target_hrst.3623328061 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 1516166150 ps |
CPU time | 2.65 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:33:08 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-5b96eefd-ed45-442e-b39c-f6bbbba5e2e0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623328061 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_hrst.3623328061 |
Directory | /workspace/5.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/5.i2c_target_intr_smoke.1579274762 |
Short name | T1146 |
Test name | |
Test status | |
Simulation time | 1213077718 ps |
CPU time | 6.81 seconds |
Started | May 23 12:32:57 PM PDT 24 |
Finished | May 23 12:33:06 PM PDT 24 |
Peak memory | 218724 kb |
Host | smart-725334c6-7d08-4ee9-9c8e-dd5db588768a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579274762 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 5.i2c_target_intr_smoke.1579274762 |
Directory | /workspace/5.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/5.i2c_target_intr_stress_wr.2005569328 |
Short name | T1288 |
Test name | |
Test status | |
Simulation time | 10113482459 ps |
CPU time | 40.2 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:41 PM PDT 24 |
Peak memory | 810296 kb |
Host | smart-675723a9-d759-45e6-b548-bedcf8ae4074 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005569328 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2005569328 |
Directory | /workspace/5.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/5.i2c_target_smoke.1434790143 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 4927297563 ps |
CPU time | 14.26 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-7f924f3c-048e-4a19-892e-cf9aedef9d7e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434790143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar get_smoke.1434790143 |
Directory | /workspace/5.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/5.i2c_target_stress_rd.115824233 |
Short name | T1240 |
Test name | |
Test status | |
Simulation time | 930251230 ps |
CPU time | 35.95 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:37 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-f5f3e135-efcb-46b0-829e-12ad3998e57f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115824233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ target_stress_rd.115824233 |
Directory | /workspace/5.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/5.i2c_target_stress_wr.4282096427 |
Short name | T1124 |
Test name | |
Test status | |
Simulation time | 21020952681 ps |
CPU time | 23.59 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:33:28 PM PDT 24 |
Peak memory | 261268 kb |
Host | smart-ac5af032-e86c-4dd9-8e37-afb18c888b1b |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282096427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c _target_stress_wr.4282096427 |
Directory | /workspace/5.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/5.i2c_target_stretch.541707120 |
Short name | T1241 |
Test name | |
Test status | |
Simulation time | 19869783567 ps |
CPU time | 383.49 seconds |
Started | May 23 12:33:05 PM PDT 24 |
Finished | May 23 12:39:30 PM PDT 24 |
Peak memory | 1209056 kb |
Host | smart-29c949d4-25ab-408c-a883-a565daa20862 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541707120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ta rget_stretch.541707120 |
Directory | /workspace/5.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/5.i2c_target_timeout.4031606566 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 5362495987 ps |
CPU time | 7.13 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:07 PM PDT 24 |
Peak memory | 215104 kb |
Host | smart-dac456a7-c2c7-4b64-81cb-9cfc058e16e5 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031606566 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.i2c_target_timeout.4031606566 |
Directory | /workspace/5.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/6.i2c_alert_test.1556582650 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 32433185 ps |
CPU time | 0.65 seconds |
Started | May 23 12:33:09 PM PDT 24 |
Finished | May 23 12:33:12 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-de3d5ec4-5637-49a9-90f0-8b847617643a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556582650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1556582650 |
Directory | /workspace/6.i2c_alert_test/latest |
Test location | /workspace/coverage/default/6.i2c_host_error_intr.519913079 |
Short name | T1054 |
Test name | |
Test status | |
Simulation time | 254545935 ps |
CPU time | 2.55 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 229352 kb |
Host | smart-6e9c8df7-3cdf-46ac-b6b8-443b86803f96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519913079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.519913079 |
Directory | /workspace/6.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3893076134 |
Short name | T1203 |
Test name | |
Test status | |
Simulation time | 934935613 ps |
CPU time | 6.31 seconds |
Started | May 23 12:33:08 PM PDT 24 |
Finished | May 23 12:33:15 PM PDT 24 |
Peak memory | 270596 kb |
Host | smart-c3d520fd-db3d-4d12-ac70-451c538a7c99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893076134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt y.3893076134 |
Directory | /workspace/6.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_full.2984906327 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 2866376828 ps |
CPU time | 85.28 seconds |
Started | May 23 12:33:08 PM PDT 24 |
Finished | May 23 12:34:34 PM PDT 24 |
Peak memory | 453232 kb |
Host | smart-812549a5-56e2-4921-bb79-c880f9e49d0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984906327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2984906327 |
Directory | /workspace/6.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_overflow.130920349 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 7919455221 ps |
CPU time | 144.76 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:35:29 PM PDT 24 |
Peak memory | 699500 kb |
Host | smart-1f9a38bd-c626-4271-8013-28c38a83fc4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130920349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.130920349 |
Directory | /workspace/6.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.707905862 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 458926078 ps |
CPU time | 0.92 seconds |
Started | May 23 12:33:07 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-af5de80a-751c-4979-a659-6415f224b0cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707905862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt .707905862 |
Directory | /workspace/6.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1334555683 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 385107724 ps |
CPU time | 10.96 seconds |
Started | May 23 12:33:08 PM PDT 24 |
Finished | May 23 12:33:20 PM PDT 24 |
Peak memory | 242180 kb |
Host | smart-7fb23cd2-c305-45ac-a324-d2d09881ffa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334555683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx. 1334555683 |
Directory | /workspace/6.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/6.i2c_host_fifo_watermark.2346366727 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 10799936727 ps |
CPU time | 137.78 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:35:19 PM PDT 24 |
Peak memory | 1477272 kb |
Host | smart-36b44921-7a5f-4e92-8d58-c3e7118a71de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346366727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2346366727 |
Directory | /workspace/6.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/6.i2c_host_may_nack.1165409679 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 4226961746 ps |
CPU time | 4.8 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:18 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-d5223c06-f625-4feb-aa5a-b8a120137c07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165409679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1165409679 |
Directory | /workspace/6.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/6.i2c_host_mode_toggle.990243048 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1433606424 ps |
CPU time | 22.03 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:33:34 PM PDT 24 |
Peak memory | 329568 kb |
Host | smart-efb40090-1476-4a2c-8f8a-5de872cd05fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990243048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.990243048 |
Directory | /workspace/6.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/6.i2c_host_override.3298214438 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 29284892 ps |
CPU time | 0.65 seconds |
Started | May 23 12:33:01 PM PDT 24 |
Finished | May 23 12:33:05 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-21f51b87-addb-4333-9daf-c6c777743f9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298214438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3298214438 |
Directory | /workspace/6.i2c_host_override/latest |
Test location | /workspace/coverage/default/6.i2c_host_smoke.439056974 |
Short name | T1138 |
Test name | |
Test status | |
Simulation time | 1375853061 ps |
CPU time | 30 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:30 PM PDT 24 |
Peak memory | 346060 kb |
Host | smart-415089b1-29c6-4b8f-b047-3ac3ab000910 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439056974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.439056974 |
Directory | /workspace/6.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/6.i2c_host_stress_all.3774257010 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 13733034423 ps |
CPU time | 96.54 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:34:40 PM PDT 24 |
Peak memory | 586116 kb |
Host | smart-0e8a60ba-816d-4338-a4f1-86771c175760 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774257010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3774257010 |
Directory | /workspace/6.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/6.i2c_host_stretch_timeout.2238947168 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 593708972 ps |
CPU time | 10.62 seconds |
Started | May 23 12:32:59 PM PDT 24 |
Finished | May 23 12:33:14 PM PDT 24 |
Peak memory | 212964 kb |
Host | smart-9b9001e6-53c9-4085-827a-bd66ab4be7f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238947168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2238947168 |
Directory | /workspace/6.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/6.i2c_target_bad_addr.3769180988 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 3388067740 ps |
CPU time | 4.35 seconds |
Started | May 23 12:33:09 PM PDT 24 |
Finished | May 23 12:33:15 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-f25a3297-867f-4c54-b421-2186284820d3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769180988 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3769180988 |
Directory | /workspace/6.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/6.i2c_target_fifo_reset_acq.4201451532 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 10095495848 ps |
CPU time | 20.36 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:36 PM PDT 24 |
Peak memory | 280736 kb |
Host | smart-b4108167-c44f-4ca2-b2e5-8c251d8f6af4 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201451532 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.4201451532 |
Directory | /workspace/6.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3321075919 |
Short name | T1237 |
Test name | |
Test status | |
Simulation time | 10123287688 ps |
CPU time | 14.55 seconds |
Started | May 23 12:33:16 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 268128 kb |
Host | smart-c5d007ce-faa8-4627-83f8-9b6be7767908 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321075919 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.i2c_target_fifo_reset_tx.3321075919 |
Directory | /workspace/6.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/6.i2c_target_hrst.3093319915 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 1203706675 ps |
CPU time | 2.26 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:33:14 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-a54a8cb1-8717-4c13-b4de-6e078b71d8fa |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093319915 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.3093319915 |
Directory | /workspace/6.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/6.i2c_target_intr_smoke.3485754116 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 932787533 ps |
CPU time | 5.29 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:07 PM PDT 24 |
Peak memory | 206488 kb |
Host | smart-42b7db9f-01c1-4f65-ab76-4e8a2dded5d0 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485754116 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.i2c_target_intr_smoke.3485754116 |
Directory | /workspace/6.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/6.i2c_target_intr_stress_wr.1570323871 |
Short name | T1150 |
Test name | |
Test status | |
Simulation time | 5293298190 ps |
CPU time | 4.23 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:33:10 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-c7b0f46e-337b-4ec9-9eb5-2983f760ef77 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570323871 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1570323871 |
Directory | /workspace/6.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/6.i2c_target_smoke.3676239156 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 3395865492 ps |
CPU time | 13.42 seconds |
Started | May 23 12:33:02 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-49dbd208-2f7b-4d84-8565-8de57684b858 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676239156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar get_smoke.3676239156 |
Directory | /workspace/6.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/6.i2c_target_stress_rd.1351847332 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 4255855625 ps |
CPU time | 44.3 seconds |
Started | May 23 12:33:03 PM PDT 24 |
Finished | May 23 12:33:50 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-ccb0a9e2-d724-4bab-9275-4a3e4ac020ef |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351847332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c _target_stress_rd.1351847332 |
Directory | /workspace/6.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/6.i2c_target_stress_wr.1974653542 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 10814853369 ps |
CPU time | 4.97 seconds |
Started | May 23 12:33:00 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c71e51d0-b8ff-412e-8de2-880ca6505a74 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974653542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c _target_stress_wr.1974653542 |
Directory | /workspace/6.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/6.i2c_target_stretch.679034940 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 8456179477 ps |
CPU time | 264.18 seconds |
Started | May 23 12:33:03 PM PDT 24 |
Finished | May 23 12:37:30 PM PDT 24 |
Peak memory | 2160008 kb |
Host | smart-1d09f8be-3489-46fe-87a9-0e7457b969b7 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679034940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta rget_stretch.679034940 |
Directory | /workspace/6.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/6.i2c_target_timeout.437994024 |
Short name | T1043 |
Test name | |
Test status | |
Simulation time | 1532078172 ps |
CPU time | 7.5 seconds |
Started | May 23 12:32:58 PM PDT 24 |
Finished | May 23 12:33:09 PM PDT 24 |
Peak memory | 219796 kb |
Host | smart-feac2b47-431f-4630-a2be-c6063297a0dc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437994024 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.i2c_target_timeout.437994024 |
Directory | /workspace/6.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/7.i2c_alert_test.3143293074 |
Short name | T1123 |
Test name | |
Test status | |
Simulation time | 24718867 ps |
CPU time | 0.67 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:16 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-e92ebfc9-f5a8-4d04-98c9-bb4d81b9686f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143293074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3143293074 |
Directory | /workspace/7.i2c_alert_test/latest |
Test location | /workspace/coverage/default/7.i2c_host_error_intr.2402947612 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 240229749 ps |
CPU time | 2.05 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 214552 kb |
Host | smart-49d4a4a4-a0aa-4079-a6c8-b0a38f5390aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402947612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2402947612 |
Directory | /workspace/7.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.7967689 |
Short name | T1266 |
Test name | |
Test status | |
Simulation time | 3790584404 ps |
CPU time | 10.8 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:24 PM PDT 24 |
Peak memory | 243248 kb |
Host | smart-4fcee5ff-6fae-4b68-b6d6-e4010ddf57e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7967689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.7967689 |
Directory | /workspace/7.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_full.2867622117 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 2695952951 ps |
CPU time | 69.33 seconds |
Started | May 23 12:33:12 PM PDT 24 |
Finished | May 23 12:34:23 PM PDT 24 |
Peak memory | 648764 kb |
Host | smart-b881c33f-7f00-47da-883c-2800e0a1b7a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867622117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2867622117 |
Directory | /workspace/7.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_overflow.3017318517 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 5212172854 ps |
CPU time | 198.53 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:36:33 PM PDT 24 |
Peak memory | 728612 kb |
Host | smart-f82d093f-66ba-4ac4-8684-7e0d8360c5c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017318517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3017318517 |
Directory | /workspace/7.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1709071508 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 154416860 ps |
CPU time | 0.89 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:16 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-abb001d1-9f33-4a30-9cc4-ab9bec72f473 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709071508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm t.1709071508 |
Directory | /workspace/7.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3772142002 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 760564832 ps |
CPU time | 4.41 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 238704 kb |
Host | smart-a8da810a-7eb4-4a9d-8f6a-8adec63ad274 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772142002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx. 3772142002 |
Directory | /workspace/7.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/7.i2c_host_fifo_watermark.2053368054 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 11199835711 ps |
CPU time | 437.64 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:40:31 PM PDT 24 |
Peak memory | 1510860 kb |
Host | smart-36ea9b42-e8bb-4271-82e1-ed4aabc9ca64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053368054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2053368054 |
Directory | /workspace/7.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/7.i2c_host_may_nack.2362666605 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 760731957 ps |
CPU time | 6.48 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-f117d39f-18d9-46d9-ae75-61ddea31e208 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362666605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.2362666605 |
Directory | /workspace/7.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/7.i2c_host_mode_toggle.1467196060 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 1830485279 ps |
CPU time | 31.91 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:47 PM PDT 24 |
Peak memory | 318160 kb |
Host | smart-f02636a5-973c-41b3-8a79-3c3fc411be3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467196060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1467196060 |
Directory | /workspace/7.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/7.i2c_host_override.227555297 |
Short name | T1115 |
Test name | |
Test status | |
Simulation time | 26943851 ps |
CPU time | 0.68 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:13 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-b955e3bb-b2dc-4cf2-b2e3-1d656f713e5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227555297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.227555297 |
Directory | /workspace/7.i2c_host_override/latest |
Test location | /workspace/coverage/default/7.i2c_host_perf.1451722844 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 4841752256 ps |
CPU time | 66.89 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:34:18 PM PDT 24 |
Peak memory | 220620 kb |
Host | smart-a7cf5bea-13bd-4704-a2f2-01b9e7a1b7b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451722844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1451722844 |
Directory | /workspace/7.i2c_host_perf/latest |
Test location | /workspace/coverage/default/7.i2c_host_smoke.1724748119 |
Short name | T1125 |
Test name | |
Test status | |
Simulation time | 6421256447 ps |
CPU time | 76.69 seconds |
Started | May 23 12:33:12 PM PDT 24 |
Finished | May 23 12:34:31 PM PDT 24 |
Peak memory | 344256 kb |
Host | smart-a98046d6-bf4f-4869-ac38-8d527f019db6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724748119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1724748119 |
Directory | /workspace/7.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/7.i2c_host_stress_all.2186480609 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 16516877127 ps |
CPU time | 933.24 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:48:46 PM PDT 24 |
Peak memory | 2036076 kb |
Host | smart-af729452-0813-4e14-9716-9f6717e6bcc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186480609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2186480609 |
Directory | /workspace/7.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/7.i2c_host_stretch_timeout.127422303 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 610221408 ps |
CPU time | 7.54 seconds |
Started | May 23 12:33:14 PM PDT 24 |
Finished | May 23 12:33:23 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-2a5b0411-510c-4b14-934f-51782f4b2797 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127422303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.127422303 |
Directory | /workspace/7.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/7.i2c_target_bad_addr.1170276722 |
Short name | T1044 |
Test name | |
Test status | |
Simulation time | 2794196859 ps |
CPU time | 3.62 seconds |
Started | May 23 12:33:14 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-388d6f52-da62-4d49-b677-3e6abc8b2588 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170276722 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1170276722 |
Directory | /workspace/7.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3629619934 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 10069640825 ps |
CPU time | 15.76 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 252012 kb |
Host | smart-f1946ee9-2bfc-4642-b40a-74935f45ca72 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629619934 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.3629619934 |
Directory | /workspace/7.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1813897701 |
Short name | T1295 |
Test name | |
Test status | |
Simulation time | 10206338352 ps |
CPU time | 10.96 seconds |
Started | May 23 12:33:09 PM PDT 24 |
Finished | May 23 12:33:21 PM PDT 24 |
Peak memory | 257852 kb |
Host | smart-1848b9af-f771-4e3b-b35a-440b52e445c3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813897701 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.i2c_target_fifo_reset_tx.1813897701 |
Directory | /workspace/7.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/7.i2c_target_hrst.3042434170 |
Short name | T1194 |
Test name | |
Test status | |
Simulation time | 362340290 ps |
CPU time | 2.45 seconds |
Started | May 23 12:33:09 PM PDT 24 |
Finished | May 23 12:33:14 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-9db19fb7-c22a-4bcf-a831-59c2c75d7014 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042434170 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.3042434170 |
Directory | /workspace/7.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/7.i2c_target_intr_smoke.3413763536 |
Short name | T1215 |
Test name | |
Test status | |
Simulation time | 947083523 ps |
CPU time | 5.7 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:33:18 PM PDT 24 |
Peak memory | 216572 kb |
Host | smart-f19bd835-dc16-4259-9860-ad90a2612e80 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413763536 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.i2c_target_intr_smoke.3413763536 |
Directory | /workspace/7.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/7.i2c_target_intr_stress_wr.1643877199 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 13160776484 ps |
CPU time | 4.56 seconds |
Started | May 23 12:33:12 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-01071d19-9135-4f87-a886-796c4cf5fa9e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643877199 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1643877199 |
Directory | /workspace/7.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/7.i2c_target_smoke.1516799017 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 891048173 ps |
CPU time | 16.19 seconds |
Started | May 23 12:33:09 PM PDT 24 |
Finished | May 23 12:33:27 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-3456eb5a-1d7c-43c7-9299-029f5a673a30 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516799017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar get_smoke.1516799017 |
Directory | /workspace/7.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/7.i2c_target_stress_rd.3318822548 |
Short name | T1256 |
Test name | |
Test status | |
Simulation time | 1687240661 ps |
CPU time | 72.26 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:34:25 PM PDT 24 |
Peak memory | 207800 kb |
Host | smart-de5c8a80-876f-4782-92ac-f827b1af70d9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318822548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c _target_stress_rd.3318822548 |
Directory | /workspace/7.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/7.i2c_target_stress_wr.1088034626 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 10832174672 ps |
CPU time | 21.58 seconds |
Started | May 23 12:33:14 PM PDT 24 |
Finished | May 23 12:33:37 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-aeb089fb-88c3-4e7c-9022-cb063b0f5a58 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088034626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c _target_stress_wr.1088034626 |
Directory | /workspace/7.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/7.i2c_target_stretch.3389899725 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 36084824790 ps |
CPU time | 249.83 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:37:22 PM PDT 24 |
Peak memory | 2083016 kb |
Host | smart-4c230ade-103b-4c32-922b-8ef569399120 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389899725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t arget_stretch.3389899725 |
Directory | /workspace/7.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/7.i2c_target_timeout.3402275780 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 1345142262 ps |
CPU time | 7.01 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-95e9a5ef-1e1f-4b98-8936-bb7ced67276a |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402275780 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.i2c_target_timeout.3402275780 |
Directory | /workspace/7.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/8.i2c_alert_test.1114018305 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 27031478 ps |
CPU time | 0.61 seconds |
Started | May 23 12:33:15 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-5eb07824-25b5-458e-a6c6-5d5e04834cdd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114018305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1114018305 |
Directory | /workspace/8.i2c_alert_test/latest |
Test location | /workspace/coverage/default/8.i2c_host_error_intr.3096678078 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 431524780 ps |
CPU time | 3.88 seconds |
Started | May 23 12:33:18 PM PDT 24 |
Finished | May 23 12:33:23 PM PDT 24 |
Peak memory | 229452 kb |
Host | smart-9207d135-e866-435c-81ab-87f0f4f5e8d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096678078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3096678078 |
Directory | /workspace/8.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3631065382 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 250978135 ps |
CPU time | 12.87 seconds |
Started | May 23 12:33:10 PM PDT 24 |
Finished | May 23 12:33:25 PM PDT 24 |
Peak memory | 253880 kb |
Host | smart-65356982-9e04-4f0a-8fae-e534c001e4ca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631065382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt y.3631065382 |
Directory | /workspace/8.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_full.2634368975 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 7463536050 ps |
CPU time | 102.85 seconds |
Started | May 23 12:33:18 PM PDT 24 |
Finished | May 23 12:35:02 PM PDT 24 |
Peak memory | 433240 kb |
Host | smart-dafbd90e-c87a-4ead-a9b9-aa077a9e7189 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634368975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2634368975 |
Directory | /workspace/8.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_overflow.3710273346 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 1571291877 ps |
CPU time | 38.42 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:51 PM PDT 24 |
Peak memory | 547804 kb |
Host | smart-38cc4d33-3c9d-4659-8aa5-abf717fc1ec6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710273346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3710273346 |
Directory | /workspace/8.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_reset_rx.884956226 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 724666608 ps |
CPU time | 3.85 seconds |
Started | May 23 12:33:12 PM PDT 24 |
Finished | May 23 12:33:17 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-be46040a-1397-4ace-8dcb-eba6eb1614a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884956226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.884956226 |
Directory | /workspace/8.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/8.i2c_host_fifo_watermark.1665330755 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 14256253145 ps |
CPU time | 100.88 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:34:56 PM PDT 24 |
Peak memory | 1017008 kb |
Host | smart-d63afd9f-acd7-4ef3-befa-685885747ff1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1665330755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1665330755 |
Directory | /workspace/8.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/8.i2c_host_may_nack.3936942355 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 254027960 ps |
CPU time | 3.28 seconds |
Started | May 23 12:33:14 PM PDT 24 |
Finished | May 23 12:33:19 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-399f00f2-1f5a-4038-8dce-27c820e5ed2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936942355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3936942355 |
Directory | /workspace/8.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/8.i2c_host_mode_toggle.1984668781 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 6830131713 ps |
CPU time | 23.64 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:39 PM PDT 24 |
Peak memory | 299780 kb |
Host | smart-60e0a8ec-f148-49cd-89f2-4d1860e2c6b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984668781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1984668781 |
Directory | /workspace/8.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/8.i2c_host_override.507036366 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 19801057 ps |
CPU time | 0.75 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:15 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-01a70881-7a7a-46d9-a5dc-855fc0e83b4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507036366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.507036366 |
Directory | /workspace/8.i2c_host_override/latest |
Test location | /workspace/coverage/default/8.i2c_host_perf.2415013113 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 7439825255 ps |
CPU time | 77.9 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:34:36 PM PDT 24 |
Peak memory | 222320 kb |
Host | smart-edad87f1-c860-4173-82ab-20f8bd6fbfd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415013113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2415013113 |
Directory | /workspace/8.i2c_host_perf/latest |
Test location | /workspace/coverage/default/8.i2c_host_smoke.509552163 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 10699347547 ps |
CPU time | 78.69 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:34:34 PM PDT 24 |
Peak memory | 366880 kb |
Host | smart-23d99831-6ac8-4b72-b4ab-72f27c173cc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509552163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.509552163 |
Directory | /workspace/8.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/8.i2c_host_stress_all.21352478 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 37165127711 ps |
CPU time | 444.87 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:40:43 PM PDT 24 |
Peak memory | 2174540 kb |
Host | smart-0eed2a46-6e65-4777-9031-7a1739bea10e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21352478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.21352478 |
Directory | /workspace/8.i2c_host_stress_all/latest |
Test location | /workspace/coverage/default/8.i2c_host_stretch_timeout.1021900701 |
Short name | T1323 |
Test name | |
Test status | |
Simulation time | 756324464 ps |
CPU time | 13.5 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:28 PM PDT 24 |
Peak memory | 218020 kb |
Host | smart-ded0de6c-2e90-497f-b1d2-baafe939c080 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021900701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1021900701 |
Directory | /workspace/8.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/8.i2c_target_bad_addr.3206292209 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 1471982112 ps |
CPU time | 2.83 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:18 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-5c70debb-9c4e-4c8e-a0cb-7cc91d5e724e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206292209 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3206292209 |
Directory | /workspace/8.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3469087371 |
Short name | T1338 |
Test name | |
Test status | |
Simulation time | 10082727573 ps |
CPU time | 88.02 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:34:43 PM PDT 24 |
Peak memory | 460080 kb |
Host | smart-ed110589-d689-4db9-86f0-d68f475fcd9f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469087371 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.3469087371 |
Directory | /workspace/8.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/8.i2c_target_fifo_reset_tx.50498427 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 10107073278 ps |
CPU time | 76.16 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:34:31 PM PDT 24 |
Peak memory | 463224 kb |
Host | smart-d1d6ee1b-5eaf-4493-a760-8f0eafa7b1af |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50498427 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.i2c_target_fifo_reset_tx.50498427 |
Directory | /workspace/8.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/8.i2c_target_hrst.3916100208 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 4874192262 ps |
CPU time | 2.73 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:18 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-e7cf9fe8-bad1-476f-8f51-c6bd47eef109 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916100208 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_hrst.3916100208 |
Directory | /workspace/8.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/8.i2c_target_intr_smoke.1045099870 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 1587688013 ps |
CPU time | 7.83 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 220144 kb |
Host | smart-52f2352a-0425-4d53-b19d-0b7730116050 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045099870 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.i2c_target_intr_smoke.1045099870 |
Directory | /workspace/8.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/8.i2c_target_intr_stress_wr.1112191475 |
Short name | T1290 |
Test name | |
Test status | |
Simulation time | 4255736796 ps |
CPU time | 9.43 seconds |
Started | May 23 12:33:11 PM PDT 24 |
Finished | May 23 12:33:22 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-3761e1ce-943f-40a8-97e7-2bbb38bd3af8 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112191475 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1112191475 |
Directory | /workspace/8.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/8.i2c_target_smoke.2933598458 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 8272587278 ps |
CPU time | 15.52 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-c4e5c4b5-ccf5-4a50-89fb-8edcb24674fc |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933598458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar get_smoke.2933598458 |
Directory | /workspace/8.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/8.i2c_target_stress_rd.861735953 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 5494398103 ps |
CPU time | 57.59 seconds |
Started | May 23 12:33:13 PM PDT 24 |
Finished | May 23 12:34:12 PM PDT 24 |
Peak memory | 207540 kb |
Host | smart-cee20b43-e891-46f1-bcca-4eb2fd9c590e |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861735953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ target_stress_rd.861735953 |
Directory | /workspace/8.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/8.i2c_target_stress_wr.3010754659 |
Short name | T1234 |
Test name | |
Test status | |
Simulation time | 51087679498 ps |
CPU time | 149.26 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:35:48 PM PDT 24 |
Peak memory | 1964376 kb |
Host | smart-95c03c2d-844b-4329-95f5-26fa93557b01 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010754659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c _target_stress_wr.3010754659 |
Directory | /workspace/8.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/8.i2c_target_stretch.2227037333 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 8185656336 ps |
CPU time | 39.93 seconds |
Started | May 23 12:33:18 PM PDT 24 |
Finished | May 23 12:33:59 PM PDT 24 |
Peak memory | 571228 kb |
Host | smart-7726a5e2-79e5-4b85-a050-4b24ef7fabc2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227037333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t arget_stretch.2227037333 |
Directory | /workspace/8.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/8.i2c_target_timeout.874410189 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 5465558332 ps |
CPU time | 7.03 seconds |
Started | May 23 12:33:17 PM PDT 24 |
Finished | May 23 12:33:25 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-5b19d06a-5ba7-466c-89a8-c809bdf5c342 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874410189 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.i2c_target_timeout.874410189 |
Directory | /workspace/8.i2c_target_timeout/latest |
Test location | /workspace/coverage/default/9.i2c_alert_test.3231322443 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 47476311 ps |
CPU time | 0.64 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:26 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-8d6e8f97-060f-4eeb-bc64-41308ef0c3de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231322443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3231322443 |
Directory | /workspace/9.i2c_alert_test/latest |
Test location | /workspace/coverage/default/9.i2c_host_error_intr.3105259539 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 543530569 ps |
CPU time | 2.46 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:28 PM PDT 24 |
Peak memory | 221352 kb |
Host | smart-a491a108-a93a-41c0-96a1-e94395436813 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105259539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3105259539 |
Directory | /workspace/9.i2c_host_error_intr/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1389451003 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 831787864 ps |
CPU time | 8.54 seconds |
Started | May 23 12:33:21 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 277104 kb |
Host | smart-52c1c1f3-abcb-4c85-8d25-d31e84aeeb16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389451003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt y.1389451003 |
Directory | /workspace/9.i2c_host_fifo_fmt_empty/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_full.3269076018 |
Short name | T1068 |
Test name | |
Test status | |
Simulation time | 9750662916 ps |
CPU time | 82.59 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:34:49 PM PDT 24 |
Peak memory | 787892 kb |
Host | smart-4385c5d0-8b42-4868-baab-fe82bea2f168 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269076018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3269076018 |
Directory | /workspace/9.i2c_host_fifo_full/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_overflow.1157785555 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1651478171 ps |
CPU time | 101.96 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:35:08 PM PDT 24 |
Peak memory | 428500 kb |
Host | smart-83202087-9447-40a6-9080-092627b2eae5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157785555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1157785555 |
Directory | /workspace/9.i2c_host_fifo_overflow/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3106985712 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 487891887 ps |
CPU time | 1.11 seconds |
Started | May 23 12:33:25 PM PDT 24 |
Finished | May 23 12:33:29 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-65734621-edfa-4c68-8ad8-0fbeaf2fbc58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106985712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_ fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm t.3106985712 |
Directory | /workspace/9.i2c_host_fifo_reset_fmt/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_reset_rx.320533859 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1750566494 ps |
CPU time | 9.96 seconds |
Started | May 23 12:33:21 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 240692 kb |
Host | smart-4fad174a-3abc-45f3-8b4e-0c9d375a5276 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320533859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.320533859 |
Directory | /workspace/9.i2c_host_fifo_reset_rx/latest |
Test location | /workspace/coverage/default/9.i2c_host_fifo_watermark.4043721746 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 5110382279 ps |
CPU time | 132.89 seconds |
Started | May 23 12:33:19 PM PDT 24 |
Finished | May 23 12:35:33 PM PDT 24 |
Peak memory | 1328972 kb |
Host | smart-5359eddd-a984-4749-b64b-0a7991dc512f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043721746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.4043721746 |
Directory | /workspace/9.i2c_host_fifo_watermark/latest |
Test location | /workspace/coverage/default/9.i2c_host_may_nack.3618670333 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 489930998 ps |
CPU time | 6.09 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-fef2c04e-9d79-43b4-89f9-a3a15c8bf32f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618670333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3618670333 |
Directory | /workspace/9.i2c_host_may_nack/latest |
Test location | /workspace/coverage/default/9.i2c_host_mode_toggle.2368467844 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 3605258094 ps |
CPU time | 39.14 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:34:04 PM PDT 24 |
Peak memory | 352716 kb |
Host | smart-be9fe5e9-30c6-44b9-99ab-496889c4c00b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368467844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2368467844 |
Directory | /workspace/9.i2c_host_mode_toggle/latest |
Test location | /workspace/coverage/default/9.i2c_host_override.1420360607 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 36049604 ps |
CPU time | 0.67 seconds |
Started | May 23 12:33:12 PM PDT 24 |
Finished | May 23 12:33:15 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-3bcf07ab-e2cf-495e-8838-1bf75eee7719 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420360607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1420360607 |
Directory | /workspace/9.i2c_host_override/latest |
Test location | /workspace/coverage/default/9.i2c_host_perf.2701214495 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 384904831 ps |
CPU time | 11.28 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:36 PM PDT 24 |
Peak memory | 229428 kb |
Host | smart-e7fd9a4c-8154-46f6-9f73-6e22d0b24ddc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701214495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2701214495 |
Directory | /workspace/9.i2c_host_perf/latest |
Test location | /workspace/coverage/default/9.i2c_host_smoke.2607982117 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 6551102662 ps |
CPU time | 27.65 seconds |
Started | May 23 12:33:14 PM PDT 24 |
Finished | May 23 12:33:43 PM PDT 24 |
Peak memory | 365016 kb |
Host | smart-9480c609-cc4b-4e50-a094-c83dbc4e4041 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607982117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2607982117 |
Directory | /workspace/9.i2c_host_smoke/latest |
Test location | /workspace/coverage/default/9.i2c_host_stretch_timeout.3476067290 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 955255982 ps |
CPU time | 9.5 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:33:37 PM PDT 24 |
Peak memory | 212820 kb |
Host | smart-390dc520-06a2-4f67-9331-81814b7dc5d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476067290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3476067290 |
Directory | /workspace/9.i2c_host_stretch_timeout/latest |
Test location | /workspace/coverage/default/9.i2c_target_bad_addr.2307074265 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 983783047 ps |
CPU time | 4.94 seconds |
Started | May 23 12:33:22 PM PDT 24 |
Finished | May 23 12:33:29 PM PDT 24 |
Peak memory | 214244 kb |
Host | smart-8aeece59-7ddc-4de7-b985-5099a0b8e3c9 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307074265 -assert nopostproc + UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2307074265 |
Directory | /workspace/9.i2c_target_bad_addr/latest |
Test location | /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1177939600 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 10068731504 ps |
CPU time | 33.95 seconds |
Started | May 23 12:33:22 PM PDT 24 |
Finished | May 23 12:33:58 PM PDT 24 |
Peak memory | 332500 kb |
Host | smart-8bd10897-0439-4e15-a8c2-b7fddda10e04 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177939600 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.1177939600 |
Directory | /workspace/9.i2c_target_fifo_reset_acq/latest |
Test location | /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2946464332 |
Short name | T1081 |
Test name | |
Test status | |
Simulation time | 10654802529 ps |
CPU time | 5.08 seconds |
Started | May 23 12:33:25 PM PDT 24 |
Finished | May 23 12:33:33 PM PDT 24 |
Peak memory | 243848 kb |
Host | smart-261fb858-496e-49c0-bf4a-cb6d9618bc29 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946464332 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.i2c_target_fifo_reset_tx.2946464332 |
Directory | /workspace/9.i2c_target_fifo_reset_tx/latest |
Test location | /workspace/coverage/default/9.i2c_target_hrst.3393931334 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 333401095 ps |
CPU time | 2.47 seconds |
Started | May 23 12:33:25 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-fe312b8a-9603-4048-8778-c937ee3c3fc3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393931334 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_hrst.3393931334 |
Directory | /workspace/9.i2c_target_hrst/latest |
Test location | /workspace/coverage/default/9.i2c_target_intr_smoke.2967991685 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1270454610 ps |
CPU time | 5.7 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:31 PM PDT 24 |
Peak memory | 214448 kb |
Host | smart-26a51089-afa0-481b-ae9c-4049e2ad50d3 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967991685 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.i2c_target_intr_smoke.2967991685 |
Directory | /workspace/9.i2c_target_intr_smoke/latest |
Test location | /workspace/coverage/default/9.i2c_target_intr_stress_wr.2946894664 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 16591970776 ps |
CPU time | 8.7 seconds |
Started | May 23 12:33:22 PM PDT 24 |
Finished | May 23 12:33:33 PM PDT 24 |
Peak memory | 364900 kb |
Host | smart-00323afc-24a6-4a03-85bd-084437ef41dd |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946894664 -assert nopostproc +UVM_TES TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2946894664 |
Directory | /workspace/9.i2c_target_intr_stress_wr/latest |
Test location | /workspace/coverage/default/9.i2c_target_smoke.917144209 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 6691559745 ps |
CPU time | 41.51 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:34:07 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-df305507-953d-4eb6-8c36-df6ed7cc258f |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917144209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ =i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ et_smoke.917144209 |
Directory | /workspace/9.i2c_target_smoke/latest |
Test location | /workspace/coverage/default/9.i2c_target_stress_rd.2380185583 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 2215835012 ps |
CPU time | 44.2 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:34:11 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-36f5655f-b105-44f6-a5e9-9da2002a9ed6 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380185583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c _target_stress_rd.2380185583 |
Directory | /workspace/9.i2c_target_stress_rd/latest |
Test location | /workspace/coverage/default/9.i2c_target_stress_wr.3065334871 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 28849214603 ps |
CPU time | 181.7 seconds |
Started | May 23 12:33:24 PM PDT 24 |
Finished | May 23 12:36:29 PM PDT 24 |
Peak memory | 2335604 kb |
Host | smart-1f711788-226a-4fc9-ba55-3bd3f5400f6c |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065334871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c _target_stress_wr.3065334871 |
Directory | /workspace/9.i2c_target_stress_wr/latest |
Test location | /workspace/coverage/default/9.i2c_target_stretch.1041072188 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 19727171490 ps |
CPU time | 100.41 seconds |
Started | May 23 12:33:25 PM PDT 24 |
Finished | May 23 12:35:09 PM PDT 24 |
Peak memory | 1116672 kb |
Host | smart-82e8bc96-5079-45bb-968b-9d11976f18f2 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041072188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t arget_stretch.1041072188 |
Directory | /workspace/9.i2c_target_stretch/latest |
Test location | /workspace/coverage/default/9.i2c_target_timeout.1223867398 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 8652248334 ps |
CPU time | 7.03 seconds |
Started | May 23 12:33:23 PM PDT 24 |
Finished | May 23 12:33:32 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-92cb7b91-a645-4cec-bc3c-b29815c927f1 |
User | root |
Command | /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223867398 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.i2c_target_timeout.1223867398 |
Directory | /workspace/9.i2c_target_timeout/latest |
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