Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	858514	1			T1	15012		T2	3		T3	3
all_values[1]	858514	1			T1	15012		T2	3		T3	3
all_values[2]	858514	1			T1	15012		T2	3		T3	3
all_values[3]	858514	1			T1	15012		T2	3		T3	3
all_values[4]	858514	1			T1	15012		T2	3		T3	3
all_values[5]	858514	1			T1	15012		T2	3		T3	3
all_values[6]	858514	1			T1	15012		T2	3		T3	3
all_values[7]	858514	1			T1	15012		T2	3		T3	3
all_values[8]	858514	1			T1	15012		T2	3		T3	3
all_values[9]	858514	1			T1	15012		T2	3		T3	3
all_values[10]	858514	1			T1	15012		T2	3		T3	3
all_values[11]	858514	1			T1	15012		T2	3		T3	3
all_values[12]	858514	1			T1	15012		T2	3		T3	3
all_values[13]	858514	1			T1	15012		T2	3		T3	3
all_values[14]	858514	1			T1	15012		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10562847

1

T1

181580

T2

39

T3

39

auto[1]

2314863

1

T1

43600

T2

6

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11473104

1

T1

225180

T2

45

T3

45

auto[1]

1404606

1

T38

147

T82

152505

T151

80572

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84813	1			T1	1479		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11245	1			T38	6		T82	1647		T151	3
all_values[0]	auto[1]	auto[0]	684353	1			T1	13533		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	78103	1			T38	6		T82	8521		T151	3
all_values[1]	auto[0]	auto[0]	772924	1			T1	15012		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	84914	1			T38	10		T82	10163		T151	5752
all_values[1]	auto[1]	auto[0]	449	1			T37	1		T58	9		T36	1
all_values[1]	auto[1]	auto[1]	227	1			T38	1		T82	3		T151	3
all_values[2]	auto[0]	auto[0]	764171	1			T1	15012		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	94026	1			T38	6		T82	10165		T151	5750
all_values[2]	auto[1]	auto[0]	114	1			T168	2		T237	3		T238	2
all_values[2]	auto[1]	auto[1]	203	1			T38	2		T82	3		T151	5
all_values[3]	auto[0]	auto[0]	763493	1			T1	15012		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	94774	1			T38	5		T82	10162		T151	5747
all_values[3]	auto[1]	auto[1]	247	1			T38	2		T82	5		T151	8
all_values[4]	auto[0]	auto[0]	763733	1			T1	15012		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	94566	1			T38	6		T82	10164		T151	5752
all_values[4]	auto[1]	auto[0]	16	1			T45	1		T239	1		T240	1
all_values[4]	auto[1]	auto[1]	199	1			T38	1		T82	4		T151	3
all_values[5]	auto[0]	auto[0]	763415	1			T1	15012		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	94852	1			T38	7		T82	10164		T151	5747
all_values[5]	auto[1]	auto[1]	247	1			T38	3		T82	2		T151	8
all_values[6]	auto[0]	auto[0]	763473	1			T1	15012		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	94798	1			T38	8		T82	10162		T151	5751
all_values[6]	auto[1]	auto[1]	243	1			T38	4		T82	5		T151	4
all_values[7]	auto[0]	auto[0]	736144	1			T1	14846		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	91072	1			T38	4		T82	9736		T151	5490
all_values[7]	auto[1]	auto[0]	28191	1			T1	166		T2	1		T3	1
all_values[7]	auto[1]	auto[1]	3107	1			T38	8		T82	428		T151	265
all_values[8]	auto[0]	auto[0]	764190	1			T1	15012		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	94075	1			T38	6		T82	10166		T151	5748
all_values[8]	auto[1]	auto[1]	249	1			T38	6		T82	2		T151	7
all_values[9]	auto[0]	auto[0]	177432	1			T1	114		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	18387	1			T38	7		T82	242		T151	426
all_values[9]	auto[1]	auto[0]	586569	1			T1	14898		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	76126	1			T38	5		T82	9926		T151	5329
all_values[10]	auto[0]	auto[0]	765103	1			T1	15012		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	93223	1			T38	8		T82	10163		T151	5751
all_values[10]	auto[1]	auto[1]	188	1			T38	4		T82	2		T151	3
all_values[11]	auto[0]	auto[0]	2644	1			T1	9		T2	1		T3	1
all_values[11]	auto[0]	auto[1]	529	1			T38	4		T82	2		T151	25
all_values[11]	auto[1]	auto[0]	761621	1			T1	15003		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	93720	1			T38	7		T82	10166		T151	5730
all_values[12]	auto[0]	auto[0]	763421	1			T1	15012		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	94879	1			T82	10164		T151	5750		T153	10
all_values[12]	auto[1]	auto[0]	25	1			T238	1		T241	1		T242	1
all_values[12]	auto[1]	auto[1]	189	1			T82	4		T151	3		T153	2
all_values[13]	auto[0]	auto[0]	763403	1			T1	15012		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	94872	1			T38	5		T82	10165		T151	5748
all_values[13]	auto[1]	auto[1]	239	1			T38	4		T82	3		T151	6
all_values[14]	auto[0]	auto[0]	763407	1			T1	15012		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	94869	1			T38	7		T82	10164		T151	5750
all_values[14]	auto[1]	auto[1]	238	1			T38	5		T82	2		T151	5