Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	858514	1			T1	15012		T2	3		T3	3
all_pins[1]	858514	1			T1	15012		T2	3		T3	3
all_pins[2]	858514	1			T1	15012		T2	3		T3	3
all_pins[3]	858514	1			T1	15012		T2	3		T3	3
all_pins[4]	858514	1			T1	15012		T2	3		T3	3
all_pins[5]	858514	1			T1	15012		T2	3		T3	3
all_pins[6]	858514	1			T1	15012		T2	3		T3	3
all_pins[7]	858514	1			T1	15012		T2	3		T3	3
all_pins[8]	858514	1			T1	15012		T2	3		T3	3
all_pins[9]	858514	1			T1	15012		T2	3		T3	3
all_pins[10]	858514	1			T1	15012		T2	3		T3	3
all_pins[11]	858514	1			T1	15012		T2	3		T3	3
all_pins[12]	858514	1			T1	15012		T2	3		T3	3
all_pins[13]	858514	1			T1	15012		T2	3		T3	3
all_pins[14]	858514	1			T1	15012		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10568672	1			T1	181541		T2	39		T3	39
values[0x1]	2309038	1			T1	43639		T2	6		T3	6
transitions[0x0=>0x1]	2308058	1			T1	43639		T2	6		T3	6
transitions[0x1=>0x0]	2306940	1			T1	43638		T2	5		T3	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99607	1			T1	1481		T2	1		T3	1
all_pins[0]	values[0x1]	758907	1			T1	13531		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	758334	1			T1	13531		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	77	1			T38	1		T82	1		T151	3
all_pins[1]	values[0x0]	857864	1			T1	15012		T2	3		T3	3
all_pins[1]	values[0x1]	650	1			T37	1		T38	1		T58	13
all_pins[1]	transitions[0x0=>0x1]	627	1			T37	1		T38	1		T58	13
all_pins[1]	transitions[0x1=>0x0]	187	1			T168	2		T237	3		T38	2
all_pins[2]	values[0x0]	858304	1			T1	15012		T2	3		T3	3
all_pins[2]	values[0x1]	210	1			T168	2		T237	3		T38	2
all_pins[2]	transitions[0x0=>0x1]	183	1			T168	2		T237	3		T38	2
all_pins[2]	transitions[0x1=>0x0]	103	1			T82	2		T151	5		T153	2
all_pins[3]	values[0x0]	858384	1			T1	15012		T2	3		T3	3
all_pins[3]	values[0x1]	130	1			T82	3		T151	5		T153	3
all_pins[3]	transitions[0x0=>0x1]	105	1			T82	2		T151	3		T153	3
all_pins[3]	transitions[0x1=>0x0]	79	1			T45	2		T153	1		T263	1
all_pins[4]	values[0x0]	858410	1			T1	15012		T2	3		T3	3
all_pins[4]	values[0x1]	104	1			T45	2		T82	1		T151	2
all_pins[4]	transitions[0x0=>0x1]	87	1			T45	2		T151	1		T153	1
all_pins[4]	transitions[0x1=>0x0]	100	1			T38	1		T82	1		T151	4
all_pins[5]	values[0x0]	858397	1			T1	15012		T2	3		T3	3
all_pins[5]	values[0x1]	117	1			T38	1		T82	2		T151	5
all_pins[5]	transitions[0x0=>0x1]	87	1			T82	2		T151	2		T264	1
all_pins[5]	transitions[0x1=>0x0]	76	1			T82	2		T151	1		T153	1
all_pins[6]	values[0x0]	858408	1			T1	15012		T2	3		T3	3
all_pins[6]	values[0x1]	106	1			T38	1		T82	2		T151	4
all_pins[6]	transitions[0x0=>0x1]	76	1			T38	1		T82	2		T151	3
all_pins[6]	transitions[0x1=>0x0]	34105	1			T1	207		T2	1		T3	1
all_pins[7]	values[0x0]	824379	1			T1	14805		T2	2		T3	2
all_pins[7]	values[0x1]	34135	1			T1	207		T2	1		T3	1
all_pins[7]	transitions[0x0=>0x1]	34103	1			T1	207		T2	1		T3	1
all_pins[7]	transitions[0x1=>0x0]	116	1			T38	2		T82	1		T151	3
all_pins[8]	values[0x0]	858366	1			T1	15012		T2	3		T3	3
all_pins[8]	values[0x1]	148	1			T38	3		T82	1		T151	3
all_pins[8]	transitions[0x0=>0x1]	111	1			T38	2		T82	1		T153	2
all_pins[8]	transitions[0x1=>0x0]	662564	1			T1	14898		T2	1		T3	1
all_pins[9]	values[0x0]	195913	1			T1	114		T2	2		T3	2
all_pins[9]	values[0x1]	662601	1			T1	14898		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	662580	1			T1	14898		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	62	1			T83	1		T55	1		T56	1
all_pins[10]	values[0x0]	858431	1			T1	15012		T2	3		T3	3
all_pins[10]	values[0x1]	83	1			T38	1		T151	2		T153	2
all_pins[10]	transitions[0x0=>0x1]	69	1			T38	1		T151	2		T153	2
all_pins[10]	transitions[0x1=>0x0]	851456	1			T1	15003		T2	2		T3	2
all_pins[11]	values[0x0]	7044	1			T1	9		T2	1		T3	1
all_pins[11]	values[0x1]	851470	1			T1	15003		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	851412	1			T1	15003		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	86	1			T82	2		T151	1		T153	2
all_pins[12]	values[0x0]	858370	1			T1	15012		T2	3		T3	3
all_pins[12]	values[0x1]	144	1			T238	1		T82	2		T151	1
all_pins[12]	transitions[0x0=>0x1]	116	1			T238	1		T82	2		T151	1
all_pins[12]	transitions[0x1=>0x0]	93	1			T38	2		T82	3		T151	1
all_pins[13]	values[0x0]	858393	1			T1	15012		T2	3		T3	3
all_pins[13]	values[0x1]	121	1			T38	2		T82	3		T151	1
all_pins[13]	transitions[0x0=>0x1]	92	1			T38	1		T82	2		T263	4
all_pins[13]	transitions[0x1=>0x0]	83	1			T38	2		T151	3		T153	2
all_pins[14]	values[0x0]	858402	1			T1	15012		T2	3		T3	3
all_pins[14]	values[0x1]	112	1			T38	3		T82	1		T151	4
all_pins[14]	transitions[0x0=>0x1]	76	1			T38	2		T82	1		T151	4
all_pins[14]	transitions[0x1=>0x0]	757753	1			T1	13530		T2	1		T3	1