Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	502	1			T38	7		T82	7		T151	8
all_values[1]	502	1			T38	7		T82	7		T151	8
all_values[2]	502	1			T38	7		T82	7		T151	8
all_values[3]	502	1			T38	7		T82	7		T151	8
all_values[4]	502	1			T38	7		T82	7		T151	8
all_values[5]	502	1			T38	7		T82	7		T151	8
all_values[6]	502	1			T38	7		T82	7		T151	8
all_values[7]	502	1			T38	7		T82	7		T151	8
all_values[8]	502	1			T38	7		T82	7		T151	8
all_values[9]	502	1			T38	7		T82	7		T151	8
all_values[10]	502	1			T38	7		T82	7		T151	8
all_values[11]	502	1			T38	7		T82	7		T151	8
all_values[12]	502	1			T38	7		T82	7		T151	8
all_values[13]	502	1			T38	7		T82	7		T151	8
all_values[14]	502	1			T38	7		T82	7		T151	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4008

1

T38

61

T82

45

T151

71

auto[1]

3522

1

T38

44

T82

60

T151

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T38

28

T82

15

T151

8

auto[1]

6383

1

T38

77

T82

90

T151

112

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4447

1

T38

65

T82

58

T151

64

auto[1]

3083

1

T38

40

T82

47

T151

56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	57	1			T151	4		T153	1		T263	1
all_values[0]	auto[0]	auto[0]	auto[1]	116	1			T38	1		T82	3		T151	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T65	2		T265	2		T258	2
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T38	3		T153	2		T263	1
all_values[0]	auto[1]	auto[0]	auto[1]	105	1			T38	1		T151	3		T153	1
all_values[0]	auto[1]	auto[1]	auto[1]	104	1			T38	2		T82	4		T153	1
all_values[1]	auto[0]	auto[0]	auto[0]	48	1			T38	1		T82	1		T153	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T38	3		T82	1		T151	2
all_values[1]	auto[0]	auto[1]	auto[0]	42	1			T82	1		T263	1		T264	1
all_values[1]	auto[0]	auto[1]	auto[1]	114	1			T38	2		T82	1		T151	3
all_values[1]	auto[1]	auto[0]	auto[1]	111	1			T38	1		T82	3		T151	1
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T151	2		T153	2		T263	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T38	2		T263	1		T55	1
all_values[2]	auto[0]	auto[0]	auto[1]	116	1			T82	2		T151	1		T153	2
all_values[2]	auto[0]	auto[1]	auto[0]	34	1			T38	2		T264	2		T56	2
all_values[2]	auto[0]	auto[1]	auto[1]	109	1			T38	1		T82	2		T151	2
all_values[2]	auto[1]	auto[0]	auto[1]	116	1			T151	5		T153	3		T263	1
all_values[2]	auto[1]	auto[1]	auto[1]	87	1			T38	2		T82	3		T153	1
all_values[3]	auto[0]	auto[0]	auto[0]	47	1			T38	1		T153	1		T265	2
all_values[3]	auto[0]	auto[0]	auto[1]	99	1			T38	1		T151	1		T153	2
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T38	4		T82	1		T65	1
all_values[3]	auto[0]	auto[1]	auto[1]	111	1			T82	1		T151	2		T153	1
all_values[3]	auto[1]	auto[0]	auto[1]	116	1			T38	1		T82	3		T151	3
all_values[3]	auto[1]	auto[1]	auto[1]	108	1			T82	2		T151	2		T153	2
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T38	3		T263	1		T266	1
all_values[4]	auto[0]	auto[0]	auto[1]	135	1			T38	1		T82	1		T151	2
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T38	2		T56	4		T258	1
all_values[4]	auto[0]	auto[1]	auto[1]	107	1			T82	2		T151	3		T153	1
all_values[4]	auto[1]	auto[0]	auto[1]	118	1			T38	1		T82	3		T151	2
all_values[4]	auto[1]	auto[1]	auto[1]	81	1			T82	1		T151	1		T153	1
all_values[5]	auto[0]	auto[0]	auto[0]	49	1			T38	2		T82	1		T153	1
all_values[5]	auto[0]	auto[0]	auto[1]	98	1			T38	2		T82	1		T151	1
all_values[5]	auto[0]	auto[1]	auto[0]	31	1			T82	1		T263	3		T83	1
all_values[5]	auto[0]	auto[1]	auto[1]	118	1			T82	2		T151	2		T153	2
all_values[5]	auto[1]	auto[0]	auto[1]	115	1			T38	2		T82	1		T151	4
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T38	1		T82	1		T151	1
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T83	2		T55	1		T119	1
all_values[6]	auto[0]	auto[0]	auto[1]	120	1			T38	1		T82	2		T151	3
all_values[6]	auto[0]	auto[1]	auto[0]	16	1			T82	1		T56	2		T119	1
all_values[6]	auto[0]	auto[1]	auto[1]	117	1			T38	3		T82	1		T151	1
all_values[6]	auto[1]	auto[0]	auto[1]	123	1			T38	3		T82	1		T151	2
all_values[6]	auto[1]	auto[1]	auto[1]	92	1			T82	2		T151	2		T153	1
all_values[7]	auto[0]	auto[0]	auto[0]	40	1			T82	2		T263	1		T119	1
all_values[7]	auto[0]	auto[0]	auto[1]	104	1			T82	2		T153	2		T264	1
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T82	2		T83	1		T119	1
all_values[7]	auto[0]	auto[1]	auto[1]	122	1			T38	2		T151	5		T153	1
all_values[7]	auto[1]	auto[0]	auto[1]	101	1			T38	4		T82	1		T151	2
all_values[7]	auto[1]	auto[1]	auto[1]	105	1			T38	1		T151	1		T153	3
all_values[8]	auto[0]	auto[0]	auto[0]	40	1			T263	2		T83	1		T55	1
all_values[8]	auto[0]	auto[0]	auto[1]	104	1			T38	3		T82	3		T151	2
all_values[8]	auto[0]	auto[1]	auto[0]	40	1			T263	1		T55	1		T56	1
all_values[8]	auto[0]	auto[1]	auto[1]	117	1			T38	1		T82	2		T151	2
all_values[8]	auto[1]	auto[0]	auto[1]	94	1			T38	1		T151	1		T153	2
all_values[8]	auto[1]	auto[1]	auto[1]	107	1			T38	2		T82	2		T151	3
all_values[9]	auto[0]	auto[0]	auto[0]	53	1			T153	2		T83	2		T55	2
all_values[9]	auto[0]	auto[0]	auto[1]	102	1			T38	2		T151	1		T153	1
all_values[9]	auto[0]	auto[1]	auto[0]	36	1			T119	1		T64	1		T65	1
all_values[9]	auto[0]	auto[1]	auto[1]	108	1			T38	2		T82	3		T151	1
all_values[9]	auto[1]	auto[0]	auto[1]	121	1			T38	1		T82	2		T151	2
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T38	2		T82	2		T151	4
all_values[10]	auto[0]	auto[0]	auto[0]	48	1			T151	1		T153	2		T263	1
all_values[10]	auto[0]	auto[0]	auto[1]	133	1			T38	3		T82	1		T151	3
all_values[10]	auto[0]	auto[1]	auto[0]	47	1			T82	3		T153	1		T264	4
all_values[10]	auto[0]	auto[1]	auto[1]	86	1			T82	1		T151	1		T153	1
all_values[10]	auto[1]	auto[0]	auto[1]	104	1			T38	3		T263	1		T264	1
all_values[10]	auto[1]	auto[1]	auto[1]	84	1			T38	1		T82	2		T151	3
all_values[11]	auto[0]	auto[0]	auto[0]	43	1			T38	1		T264	3		T83	2
all_values[11]	auto[0]	auto[0]	auto[1]	118	1			T38	2		T82	4		T151	6
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T264	5		T122	3		T267	1
all_values[11]	auto[0]	auto[1]	auto[1]	109	1			T151	1		T263	1		T83	1
all_values[11]	auto[1]	auto[0]	auto[1]	123	1			T38	2		T82	1		T151	1
all_values[11]	auto[1]	auto[1]	auto[1]	85	1			T38	2		T82	2		T153	1
all_values[12]	auto[0]	auto[0]	auto[0]	57	1			T38	3		T151	2		T55	2
all_values[12]	auto[0]	auto[0]	auto[1]	98	1			T82	1		T151	2		T153	3
all_values[12]	auto[0]	auto[1]	auto[0]	45	1			T38	4		T56	1		T65	1
all_values[12]	auto[0]	auto[1]	auto[1]	113	1			T82	2		T151	1		T153	2
all_values[12]	auto[1]	auto[0]	auto[1]	85	1			T82	1		T151	3		T153	1
all_values[12]	auto[1]	auto[1]	auto[1]	104	1			T82	3		T153	1		T263	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T38	3		T151	1		T268	1
all_values[13]	auto[0]	auto[0]	auto[1]	108	1			T38	1		T82	2		T151	3
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T264	2		T83	1		T56	1
all_values[13]	auto[0]	auto[1]	auto[1]	119	1			T38	1		T82	2		T153	2
all_values[13]	auto[1]	auto[0]	auto[1]	104	1			T38	1		T151	1		T153	2
all_values[13]	auto[1]	auto[1]	auto[1]	103	1			T38	1		T82	3		T151	3
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T82	1		T153	1		T55	1
all_values[14]	auto[0]	auto[0]	auto[1]	128	1			T38	1		T151	3		T153	1
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T82	1		T263	1		T268	1
all_values[14]	auto[0]	auto[1]	auto[1]	85	1			T38	1		T82	1		T151	1
all_values[14]	auto[1]	auto[0]	auto[1]	119	1			T38	3		T82	1		T151	2
all_values[14]	auto[1]	auto[1]	auto[1]	100	1			T38	2		T82	3		T151	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal