Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.98 96.59 89.81 97.67 69.64 93.62 98.44 91.05


Total test records in report: 1560
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T1510 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2865172811 May 26 12:31:00 PM PDT 24 May 26 12:31:03 PM PDT 24 120385149 ps
T1511 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2519032843 May 26 12:31:16 PM PDT 24 May 26 12:31:18 PM PDT 24 30240226 ps
T1512 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1396990944 May 26 12:31:08 PM PDT 24 May 26 12:31:10 PM PDT 24 81090122 ps
T217 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3569408207 May 26 12:31:07 PM PDT 24 May 26 12:31:09 PM PDT 24 17525451 ps
T1513 /workspace/coverage/cover_reg_top/18.i2c_intr_test.696378987 May 26 12:31:03 PM PDT 24 May 26 12:31:05 PM PDT 24 22004413 ps
T1514 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1884623421 May 26 12:31:06 PM PDT 24 May 26 12:31:08 PM PDT 24 76042725 ps
T1515 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.977916212 May 26 12:31:15 PM PDT 24 May 26 12:31:17 PM PDT 24 89826446 ps
T1516 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.323918154 May 26 12:30:59 PM PDT 24 May 26 12:31:03 PM PDT 24 449129539 ps
T1517 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3705974787 May 26 12:30:53 PM PDT 24 May 26 12:30:55 PM PDT 24 14796243 ps
T1518 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1486023158 May 26 12:30:47 PM PDT 24 May 26 12:30:49 PM PDT 24 32331390 ps
T1519 /workspace/coverage/cover_reg_top/40.i2c_intr_test.1492326800 May 26 12:31:26 PM PDT 24 May 26 12:31:29 PM PDT 24 19220101 ps
T1520 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.235928439 May 26 12:30:58 PM PDT 24 May 26 12:31:00 PM PDT 24 58461136 ps
T1521 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2294752944 May 26 12:30:58 PM PDT 24 May 26 12:31:00 PM PDT 24 54938028 ps
T1522 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3609011849 May 26 12:31:00 PM PDT 24 May 26 12:31:02 PM PDT 24 41766867 ps
T1523 /workspace/coverage/cover_reg_top/31.i2c_intr_test.1304434968 May 26 12:31:14 PM PDT 24 May 26 12:31:16 PM PDT 24 16652243 ps
T1524 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.386774141 May 26 12:31:08 PM PDT 24 May 26 12:31:10 PM PDT 24 34603674 ps
T1525 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3436466819 May 26 12:30:59 PM PDT 24 May 26 12:31:01 PM PDT 24 26174661 ps
T1526 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.278191683 May 26 12:31:01 PM PDT 24 May 26 12:31:04 PM PDT 24 25115435 ps
T1527 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3250600416 May 26 12:30:58 PM PDT 24 May 26 12:31:01 PM PDT 24 64651854 ps
T252 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.609048731 May 26 12:31:03 PM PDT 24 May 26 12:31:06 PM PDT 24 440923631 ps
T197 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3370398036 May 26 12:30:53 PM PDT 24 May 26 12:30:56 PM PDT 24 478512214 ps
T1528 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.367237160 May 26 12:31:19 PM PDT 24 May 26 12:31:21 PM PDT 24 19975083 ps
T203 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3834168333 May 26 12:31:08 PM PDT 24 May 26 12:31:11 PM PDT 24 67043381 ps
T201 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2952772972 May 26 12:31:08 PM PDT 24 May 26 12:31:12 PM PDT 24 312180655 ps
T1529 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1972194155 May 26 12:31:19 PM PDT 24 May 26 12:31:21 PM PDT 24 45204410 ps
T1530 /workspace/coverage/cover_reg_top/43.i2c_intr_test.51744612 May 26 12:31:26 PM PDT 24 May 26 12:31:29 PM PDT 24 26298395 ps
T1531 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1556943497 May 26 12:31:21 PM PDT 24 May 26 12:31:23 PM PDT 24 33354720 ps
T1532 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.646879396 May 26 12:31:01 PM PDT 24 May 26 12:31:03 PM PDT 24 49724698 ps
T1533 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2222454214 May 26 12:31:11 PM PDT 24 May 26 12:31:17 PM PDT 24 14320705 ps
T1534 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1504151307 May 26 12:31:07 PM PDT 24 May 26 12:31:09 PM PDT 24 34151738 ps
T202 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.294551960 May 26 12:30:53 PM PDT 24 May 26 12:30:55 PM PDT 24 367552109 ps
T1535 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1894302049 May 26 12:31:24 PM PDT 24 May 26 12:31:27 PM PDT 24 50703308 ps
T1536 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1476554749 May 26 12:30:53 PM PDT 24 May 26 12:30:55 PM PDT 24 42922180 ps
T1537 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1443979600 May 26 12:30:46 PM PDT 24 May 26 12:30:48 PM PDT 24 174246268 ps
T1538 /workspace/coverage/cover_reg_top/42.i2c_intr_test.74132816 May 26 12:31:33 PM PDT 24 May 26 12:31:34 PM PDT 24 21869836 ps
T1539 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2875976559 May 26 12:30:58 PM PDT 24 May 26 12:31:00 PM PDT 24 75233318 ps
T1540 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1524792989 May 26 12:30:47 PM PDT 24 May 26 12:30:48 PM PDT 24 35651740 ps
T1541 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2134107283 May 26 12:31:31 PM PDT 24 May 26 12:31:34 PM PDT 24 307849906 ps
T1542 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2611772151 May 26 12:31:07 PM PDT 24 May 26 12:31:08 PM PDT 24 18779318 ps
T1543 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3147313529 May 26 12:30:50 PM PDT 24 May 26 12:31:02 PM PDT 24 26291081 ps
T1544 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1970237415 May 26 12:30:55 PM PDT 24 May 26 12:30:57 PM PDT 24 97635012 ps
T1545 /workspace/coverage/cover_reg_top/1.i2c_intr_test.743910204 May 26 12:30:49 PM PDT 24 May 26 12:30:50 PM PDT 24 32318881 ps
T1546 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1802107979 May 26 12:31:05 PM PDT 24 May 26 12:31:07 PM PDT 24 25377542 ps
T193 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.11838326 May 26 12:31:07 PM PDT 24 May 26 12:31:09 PM PDT 24 286978488 ps
T1547 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2393322740 May 26 12:31:24 PM PDT 24 May 26 12:31:27 PM PDT 24 97769867 ps
T1548 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3371669853 May 26 12:31:21 PM PDT 24 May 26 12:31:24 PM PDT 24 42867402 ps
T1549 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2194433581 May 26 12:30:52 PM PDT 24 May 26 12:30:54 PM PDT 24 221266811 ps
T1550 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1616194020 May 26 12:31:15 PM PDT 24 May 26 12:31:17 PM PDT 24 33363997 ps
T1551 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.602376000 May 26 12:31:03 PM PDT 24 May 26 12:31:06 PM PDT 24 56759608 ps
T194 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2360857695 May 26 12:31:00 PM PDT 24 May 26 12:31:03 PM PDT 24 49142131 ps
T195 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2883825447 May 26 12:30:58 PM PDT 24 May 26 12:31:00 PM PDT 24 55339508 ps
T1552 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2106792240 May 26 12:31:00 PM PDT 24 May 26 12:31:03 PM PDT 24 246186033 ps
T1553 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2150544308 May 26 12:31:21 PM PDT 24 May 26 12:31:23 PM PDT 24 44487977 ps
T1554 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2782210933 May 26 12:30:50 PM PDT 24 May 26 12:30:51 PM PDT 24 22220742 ps
T1555 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2771072118 May 26 12:30:54 PM PDT 24 May 26 12:30:55 PM PDT 24 97146582 ps
T1556 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3869641622 May 26 12:30:59 PM PDT 24 May 26 12:31:01 PM PDT 24 56180456 ps
T1557 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1615076301 May 26 12:31:26 PM PDT 24 May 26 12:31:29 PM PDT 24 22784648 ps
T1558 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3116626196 May 26 12:30:45 PM PDT 24 May 26 12:30:46 PM PDT 24 54392159 ps
T1559 /workspace/coverage/cover_reg_top/39.i2c_intr_test.499408126 May 26 12:31:31 PM PDT 24 May 26 12:31:32 PM PDT 24 62719456 ps
T1560 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3942216705 May 26 12:30:46 PM PDT 24 May 26 12:30:48 PM PDT 24 182971361 ps

Test location /workspace/coverage/default/20.i2c_host_fifo_full.243338824
Short name T3
Test name
Test status
Simulation time 2824114886 ps
CPU time 112.1 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:47:04 PM PDT 24
Peak memory 849560 kb
Host smart-4f4f34e5-1ca6-4767-a1ea-805ea00425bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243338824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.243338824
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1444274161
Short name T9
Test name
Test status
Simulation time 7987512382 ps
CPU time 68.68 seconds
Started May 26 12:48:55 PM PDT 24
Finished May 26 12:50:04 PM PDT 24
Peak memory 1718040 kb
Host smart-62d6f263-7dab-4dde-b1d4-5ae59c949a0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444274161 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1444274161
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4189851010
Short name T8
Test name
Test status
Simulation time 10226687731 ps
CPU time 36.17 seconds
Started May 26 12:46:44 PM PDT 24
Finished May 26 12:47:21 PM PDT 24
Peak memory 368088 kb
Host smart-a75d9e40-ecd9-49ec-beeb-2bdb64dc1b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189851010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4189851010
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1341725457
Short name T14
Test name
Test status
Simulation time 4231250745 ps
CPU time 10.78 seconds
Started May 26 12:41:38 PM PDT 24
Finished May 26 12:41:50 PM PDT 24
Peak memory 213232 kb
Host smart-1518a738-90aa-4ebd-8ea0-9c9dc3088180
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341725457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1341725457
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1635439051
Short name T38
Test name
Test status
Simulation time 29668585987 ps
CPU time 1778.54 seconds
Started May 26 12:49:02 PM PDT 24
Finished May 26 01:18:41 PM PDT 24
Peak memory 2479728 kb
Host smart-de4f647c-bcd1-4077-acc6-c609ce70122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635439051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1635439051
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.492627099
Short name T96
Test name
Test status
Simulation time 349240287 ps
CPU time 1.85 seconds
Started May 26 12:31:15 PM PDT 24
Finished May 26 12:31:18 PM PDT 24
Peak memory 203856 kb
Host smart-7981f32a-82f4-4a5d-8ecc-0ff17b0e4688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492627099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.492627099
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.1815776126
Short name T51
Test name
Test status
Simulation time 107097716087 ps
CPU time 1605.5 seconds
Started May 26 12:41:56 PM PDT 24
Finished May 26 01:08:42 PM PDT 24
Peak memory 4384488 kb
Host smart-5a048a53-41ed-413e-89aa-8be484d5a6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815776126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.1815776126
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2962722661
Short name T56
Test name
Test status
Simulation time 8547995585 ps
CPU time 198.14 seconds
Started May 26 12:44:27 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 1340140 kb
Host smart-9af44d0d-de07-4bda-95c3-6f7b75523eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962722661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2962722661
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_override.3648865235
Short name T79
Test name
Test status
Simulation time 35905157 ps
CPU time 0.67 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:44:10 PM PDT 24
Peak memory 204156 kb
Host smart-50f84b4d-45f7-4424-855d-77f016b8fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648865235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3648865235
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.855139990
Short name T384
Test name
Test status
Simulation time 2666508083 ps
CPU time 17.75 seconds
Started May 26 12:43:37 PM PDT 24
Finished May 26 12:43:55 PM PDT 24
Peak memory 204640 kb
Host smart-2c2c8b77-2b67-4824-ade1-0d7832772847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855139990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.855139990
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.281946399
Short name T99
Test name
Test status
Simulation time 164043292 ps
CPU time 3.22 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:12 PM PDT 24
Peak memory 203884 kb
Host smart-6a726d90-0a91-4a26-b5bf-e93909313b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281946399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.281946399
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.4043612330
Short name T174
Test name
Test status
Simulation time 85594653 ps
CPU time 0.99 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:38 PM PDT 24
Peak memory 222568 kb
Host smart-9f501a19-bff7-4ba2-bb5d-f885647d67f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043612330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.4043612330
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3419353645
Short name T17
Test name
Test status
Simulation time 37456744921 ps
CPU time 162.77 seconds
Started May 26 12:49:51 PM PDT 24
Finished May 26 12:52:35 PM PDT 24
Peak memory 2131188 kb
Host smart-94d3305a-1aa9-41e9-bd8b-30ab94da1c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419353645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3419353645
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.83087381
Short name T209
Test name
Test status
Simulation time 28470200 ps
CPU time 0.72 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:30:59 PM PDT 24
Peak memory 203592 kb
Host smart-0a68a938-fb74-4dec-9531-4c6f9583dccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83087381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.83087381
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2289420586
Short name T34
Test name
Test status
Simulation time 5122309329 ps
CPU time 7.81 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:50:17 PM PDT 24
Peak memory 219232 kb
Host smart-dfbe7743-b9b6-4377-9b4e-cc37ec926bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289420586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2289420586
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.305469107
Short name T65
Test name
Test status
Simulation time 15865646099 ps
CPU time 1550.65 seconds
Started May 26 12:48:15 PM PDT 24
Finished May 26 01:14:06 PM PDT 24
Peak memory 2373676 kb
Host smart-051d1250-24b2-42e8-b732-dfb96f3544bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305469107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.305469107
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.934981374
Short name T50
Test name
Test status
Simulation time 604432334 ps
CPU time 14.05 seconds
Started May 26 12:50:00 PM PDT 24
Finished May 26 12:50:14 PM PDT 24
Peak memory 266408 kb
Host smart-b473b9f2-cd93-4ecb-a6b7-a5b4beb47a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934981374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.934981374
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1756422964
Short name T90
Test name
Test status
Simulation time 10160357163 ps
CPU time 41.97 seconds
Started May 26 12:42:49 PM PDT 24
Finished May 26 12:43:31 PM PDT 24
Peak memory 310568 kb
Host smart-905e78c2-794e-4764-830f-7857609781e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756422964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1756422964
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3387223534
Short name T773
Test name
Test status
Simulation time 2035084406 ps
CPU time 3.14 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:45:23 PM PDT 24
Peak memory 204528 kb
Host smart-6d5cdb24-270a-480e-9b71-4173e4ba6bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387223534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3387223534
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3870441799
Short name T82
Test name
Test status
Simulation time 28385034929 ps
CPU time 613.72 seconds
Started May 26 12:49:36 PM PDT 24
Finished May 26 12:59:50 PM PDT 24
Peak memory 2358612 kb
Host smart-da4a9a28-0d4f-4237-94c4-d6fdc5b78a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870441799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3870441799
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3678014017
Short name T26
Test name
Test status
Simulation time 497677760 ps
CPU time 3.21 seconds
Started May 26 12:43:13 PM PDT 24
Finished May 26 12:43:16 PM PDT 24
Peak memory 204368 kb
Host smart-0de8217d-630e-40bc-836c-ea4f93829cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678014017 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3678014017
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1189398949
Short name T12
Test name
Test status
Simulation time 378907391 ps
CPU time 2.45 seconds
Started May 26 12:41:26 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 203748 kb
Host smart-d978dc0a-3bfc-48e2-a599-d59290c31d7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189398949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1189398949
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3087955674
Short name T83
Test name
Test status
Simulation time 43424287099 ps
CPU time 487.6 seconds
Started May 26 12:46:38 PM PDT 24
Finished May 26 12:54:46 PM PDT 24
Peak memory 1510972 kb
Host smart-f795603c-2803-4c15-89ca-729d1af25a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087955674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3087955674
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_alert_test.617206768
Short name T172
Test name
Test status
Simulation time 175057318 ps
CPU time 0.62 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:41:27 PM PDT 24
Peak memory 204084 kb
Host smart-52e24324-e4ef-4124-93bc-c7420d965873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617206768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.617206768
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1927457903
Short name T10
Test name
Test status
Simulation time 6583651011 ps
CPU time 27.39 seconds
Started May 26 12:45:37 PM PDT 24
Finished May 26 12:46:05 PM PDT 24
Peak memory 356644 kb
Host smart-b8f6072b-8a8f-417d-a99f-11b5360bd532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927457903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1927457903
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1002910795
Short name T647
Test name
Test status
Simulation time 285036192 ps
CPU time 0.89 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:44:37 PM PDT 24
Peak memory 204176 kb
Host smart-86fbc234-9967-4b35-b7ab-aaff2dc7bc66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002910795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1002910795
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.817397254
Short name T230
Test name
Test status
Simulation time 39485848218 ps
CPU time 1320.72 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 01:07:28 PM PDT 24
Peak memory 3864760 kb
Host smart-10541e87-3c24-4bdd-a2ad-27c42d0d5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817397254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.817397254
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1708683470
Short name T235
Test name
Test status
Simulation time 366456283 ps
CPU time 1.04 seconds
Started May 26 12:46:14 PM PDT 24
Finished May 26 12:46:16 PM PDT 24
Peak memory 204204 kb
Host smart-0fca09b9-5245-43ce-9274-bf5143be951e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708683470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1708683470
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1690274514
Short name T153
Test name
Test status
Simulation time 21469853788 ps
CPU time 405.82 seconds
Started May 26 12:49:18 PM PDT 24
Finished May 26 12:56:05 PM PDT 24
Peak memory 1159540 kb
Host smart-f7f72b84-eeee-4277-8b08-935d94fc4463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690274514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1690274514
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.375651465
Short name T87
Test name
Test status
Simulation time 10139016289 ps
CPU time 33.08 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:42:16 PM PDT 24
Peak memory 449520 kb
Host smart-dd376936-6e3d-47c7-8b71-ede7ed80016b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375651465 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.375651465
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.756471764
Short name T800
Test name
Test status
Simulation time 193994045 ps
CPU time 3.8 seconds
Started May 26 12:44:12 PM PDT 24
Finished May 26 12:44:16 PM PDT 24
Peak memory 226984 kb
Host smart-6be9c86c-ca40-4aac-9a55-6ed9acfa7814
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756471764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
756471764
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2952772972
Short name T201
Test name
Test status
Simulation time 312180655 ps
CPU time 2.64 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:12 PM PDT 24
Peak memory 203876 kb
Host smart-989b1d16-fd0f-4d1a-bd57-feb8e6c5dcf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952772972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2952772972
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3965123133
Short name T67
Test name
Test status
Simulation time 1021107945 ps
CPU time 20.04 seconds
Started May 26 12:48:43 PM PDT 24
Finished May 26 12:49:04 PM PDT 24
Peak memory 310276 kb
Host smart-543f2f64-857c-4930-95f1-adc99674ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965123133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3965123133
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.1148711719
Short name T241
Test name
Test status
Simulation time 1489298157 ps
CPU time 6.72 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:50 PM PDT 24
Peak memory 204432 kb
Host smart-77cff7b7-1fa9-4120-bb46-f11d813415d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148711719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.1148711719
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2688568373
Short name T700
Test name
Test status
Simulation time 455328462 ps
CPU time 6.06 seconds
Started May 26 12:42:04 PM PDT 24
Finished May 26 12:42:10 PM PDT 24
Peak memory 204408 kb
Host smart-5ca13814-2982-40ab-95c0-870ff43ed8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688568373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2688568373
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.191925927
Short name T1501
Test name
Test status
Simulation time 131319974 ps
CPU time 2 seconds
Started May 26 12:31:16 PM PDT 24
Finished May 26 12:31:18 PM PDT 24
Peak memory 203908 kb
Host smart-98aebbeb-d02c-49d3-8e70-4967a721950f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191925927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.191925927
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.146888603
Short name T215
Test name
Test status
Simulation time 52063475 ps
CPU time 0.79 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:07 PM PDT 24
Peak memory 203708 kb
Host smart-ac41feea-826d-4fc8-b9e0-241888c31c5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146888603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.146888603
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1160969682
Short name T254
Test name
Test status
Simulation time 778350529 ps
CPU time 11.77 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 12:41:28 PM PDT 24
Peak memory 204448 kb
Host smart-2b2f477c-2e03-45ca-8e48-d8970f83dbbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160969682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1160969682
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.904246497
Short name T40
Test name
Test status
Simulation time 998264234 ps
CPU time 9.39 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:41:35 PM PDT 24
Peak memory 228592 kb
Host smart-2f76f9b4-2db3-4c5c-b00e-825852d47331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904246497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.904246497
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2369718162
Short name T258
Test name
Test status
Simulation time 33816539192 ps
CPU time 676.51 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:54:40 PM PDT 24
Peak memory 972328 kb
Host smart-eaba61b7-28b5-4443-a767-0d701d0a542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369718162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2369718162
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.653147617
Short name T121
Test name
Test status
Simulation time 12202149264 ps
CPU time 415.22 seconds
Started May 26 12:44:09 PM PDT 24
Finished May 26 12:51:05 PM PDT 24
Peak memory 2481792 kb
Host smart-6deafe2e-9c2e-488c-8344-40328b751ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653147617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.653147617
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.1548166917
Short name T962
Test name
Test status
Simulation time 1037590324 ps
CPU time 3.05 seconds
Started May 26 12:44:18 PM PDT 24
Finished May 26 12:44:22 PM PDT 24
Peak memory 204456 kb
Host smart-24deace7-63b6-4d20-b79d-b4f687ecc12a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548166917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.1548166917
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2953824861
Short name T243
Test name
Test status
Simulation time 1565770540 ps
CPU time 33.02 seconds
Started May 26 12:44:36 PM PDT 24
Finished May 26 12:45:10 PM PDT 24
Peak memory 301916 kb
Host smart-72be6cdf-5e99-46e7-9ca2-aba667bd8190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953824861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2953824861
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2865349048
Short name T255
Test name
Test status
Simulation time 7660302640 ps
CPU time 93.91 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:47:48 PM PDT 24
Peak memory 1104496 kb
Host smart-d5fb8da8-fc60-4889-a344-4d1624bec285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865349048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2865349048
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2752409129
Short name T247
Test name
Test status
Simulation time 40781017133 ps
CPU time 201.13 seconds
Started May 26 12:50:11 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 1527404 kb
Host smart-1d26acf4-6165-4f1f-a094-9ff37d5e76fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752409129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2752409129
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2360857695
Short name T194
Test name
Test status
Simulation time 49142131 ps
CPU time 1.43 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203892 kb
Host smart-d818f174-5bc1-4ea8-b409-da27883b8fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360857695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2360857695
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3370398036
Short name T197
Test name
Test status
Simulation time 478512214 ps
CPU time 1.42 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:56 PM PDT 24
Peak memory 203932 kb
Host smart-f97326b9-5441-4bcb-bf40-a3dd87669c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370398036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3370398036
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1536153454
Short name T199
Test name
Test status
Simulation time 284119286 ps
CPU time 1.7 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203860 kb
Host smart-1dfa70d6-7568-4726-86b6-bd82189a7fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536153454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1536153454
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3734573165
Short name T74
Test name
Test status
Simulation time 2329501518 ps
CPU time 41.46 seconds
Started May 26 12:43:13 PM PDT 24
Finished May 26 12:43:55 PM PDT 24
Peak memory 306100 kb
Host smart-7c63ffc7-70fd-4d5a-9a94-6a50582d4c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734573165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3734573165
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3958877144
Short name T312
Test name
Test status
Simulation time 887308142 ps
CPU time 41.35 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:49 PM PDT 24
Peak memory 212692 kb
Host smart-d3213887-1ba0-4ddb-b652-4d2cabf049a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958877144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3958877144
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.890393132
Short name T933
Test name
Test status
Simulation time 10104600764 ps
CPU time 23.68 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:52 PM PDT 24
Peak memory 299520 kb
Host smart-2d111ecc-51e8-4f00-9ab1-36bf98bef0b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890393132 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.890393132
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1619425963
Short name T84
Test name
Test status
Simulation time 66434199003 ps
CPU time 1083.19 seconds
Started May 26 12:46:54 PM PDT 24
Finished May 26 01:04:58 PM PDT 24
Peak memory 3071812 kb
Host smart-bf622568-78e8-4ece-a4e4-c24f46486234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619425963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1619425963
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2016173687
Short name T210
Test name
Test status
Simulation time 46694922 ps
CPU time 2.02 seconds
Started May 26 12:30:54 PM PDT 24
Finished May 26 12:30:57 PM PDT 24
Peak memory 203808 kb
Host smart-f2b6a798-e10d-4555-bbdf-7324a38e84d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016173687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2016173687
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.570826715
Short name T211
Test name
Test status
Simulation time 42102612 ps
CPU time 0.75 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203600 kb
Host smart-de9011c7-68f5-434b-9090-4b90884c9390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570826715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.570826715
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.813314992
Short name T188
Test name
Test status
Simulation time 58561887 ps
CPU time 0.78 seconds
Started May 26 12:31:01 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203776 kb
Host smart-c362ccdd-da85-4b10-a3e9-59a707c0b2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813314992 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.813314992
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.113512543
Short name T1505
Test name
Test status
Simulation time 18865355 ps
CPU time 0.68 seconds
Started May 26 12:30:42 PM PDT 24
Finished May 26 12:30:43 PM PDT 24
Peak memory 203568 kb
Host smart-7eb58c50-c788-42e0-9b18-0a2b64888cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113512543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.113512543
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2865172811
Short name T1510
Test name
Test status
Simulation time 120385149 ps
CPU time 0.85 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203588 kb
Host smart-3caa0246-7a7c-42ff-928d-2438a38fb046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865172811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2865172811
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.323918154
Short name T1516
Test name
Test status
Simulation time 449129539 ps
CPU time 2.5 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203908 kb
Host smart-3e6d4986-3d49-4686-80c1-6f09bc4ee750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323918154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.323918154
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.36756359
Short name T236
Test name
Test status
Simulation time 32608283 ps
CPU time 1.37 seconds
Started May 26 12:31:22 PM PDT 24
Finished May 26 12:31:26 PM PDT 24
Peak memory 203852 kb
Host smart-d66441fd-2c22-465b-a5d0-88bd73f3f578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36756359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.36756359
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3474039127
Short name T1472
Test name
Test status
Simulation time 1634621756 ps
CPU time 6.33 seconds
Started May 26 12:30:37 PM PDT 24
Finished May 26 12:30:44 PM PDT 24
Peak memory 203824 kb
Host smart-5053b750-913f-4a80-aa0a-c7f8a6d2ce3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474039127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3474039127
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2875976559
Short name T1539
Test name
Test status
Simulation time 75233318 ps
CPU time 0.81 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203696 kb
Host smart-fdd80214-4315-4a91-a8cb-f538d0b0af6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875976559 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2875976559
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3116626196
Short name T1558
Test name
Test status
Simulation time 54392159 ps
CPU time 0.7 seconds
Started May 26 12:30:45 PM PDT 24
Finished May 26 12:30:46 PM PDT 24
Peak memory 203652 kb
Host smart-55404b52-9063-4770-b4ba-c4db20562f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116626196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3116626196
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.743910204
Short name T1545
Test name
Test status
Simulation time 32318881 ps
CPU time 0.64 seconds
Started May 26 12:30:49 PM PDT 24
Finished May 26 12:30:50 PM PDT 24
Peak memory 203616 kb
Host smart-0a695bcd-155d-4133-aba6-3efa55554ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743910204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.743910204
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.550224989
Short name T1500
Test name
Test status
Simulation time 327769340 ps
CPU time 0.8 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203608 kb
Host smart-9d2d0cc7-66fb-4ee3-8eb2-2aa4b5b69016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550224989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.550224989
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1486023158
Short name T1518
Test name
Test status
Simulation time 32331390 ps
CPU time 1.48 seconds
Started May 26 12:30:47 PM PDT 24
Finished May 26 12:30:49 PM PDT 24
Peak memory 203908 kb
Host smart-5d7f6bda-174e-4735-9be8-3565443190a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486023158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1486023158
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3139057142
Short name T1474
Test name
Test status
Simulation time 44263892 ps
CPU time 1.17 seconds
Started May 26 12:31:09 PM PDT 24
Finished May 26 12:31:11 PM PDT 24
Peak memory 204000 kb
Host smart-44001706-5d23-4df3-9ad3-dadc81cf2bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139057142 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3139057142
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3108609565
Short name T212
Test name
Test status
Simulation time 22109745 ps
CPU time 0.71 seconds
Started May 26 12:31:09 PM PDT 24
Finished May 26 12:31:11 PM PDT 24
Peak memory 203728 kb
Host smart-84291d44-5cbc-4e79-b9ab-c45e9cace2ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108609565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3108609565
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4037709348
Short name T1464
Test name
Test status
Simulation time 126910603 ps
CPU time 0.66 seconds
Started May 26 12:31:09 PM PDT 24
Finished May 26 12:31:10 PM PDT 24
Peak memory 203624 kb
Host smart-af3e2b78-42b8-499f-b863-f0031edb5bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037709348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4037709348
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1652831233
Short name T1490
Test name
Test status
Simulation time 21664233 ps
CPU time 0.86 seconds
Started May 26 12:31:17 PM PDT 24
Finished May 26 12:31:19 PM PDT 24
Peak memory 203544 kb
Host smart-95266b21-a2c2-4a62-9c79-2b45f735e281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652831233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1652831233
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3250600416
Short name T1527
Test name
Test status
Simulation time 64651854 ps
CPU time 1.73 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:31:01 PM PDT 24
Peak memory 203796 kb
Host smart-2490c556-dfa4-4135-9b04-bfa0a63ed303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250600416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3250600416
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3834168333
Short name T203
Test name
Test status
Simulation time 67043381 ps
CPU time 1.47 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:11 PM PDT 24
Peak memory 203960 kb
Host smart-7bc523e0-6252-4f3d-a6e2-c07433711819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834168333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3834168333
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3488139401
Short name T1495
Test name
Test status
Simulation time 69569686 ps
CPU time 0.82 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203652 kb
Host smart-14389866-64af-43e2-879a-8cb8910eacdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488139401 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3488139401
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2828542745
Short name T223
Test name
Test status
Simulation time 83936734 ps
CPU time 0.82 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 202984 kb
Host smart-4011447c-6777-4442-86c2-c3a0571fd296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828542745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2828542745
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3705974787
Short name T1517
Test name
Test status
Simulation time 14796243 ps
CPU time 0.7 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203568 kb
Host smart-a687dc9e-b9eb-430f-b8c9-9020dbfa1a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705974787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3705974787
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1616194020
Short name T1550
Test name
Test status
Simulation time 33363997 ps
CPU time 0.85 seconds
Started May 26 12:31:15 PM PDT 24
Finished May 26 12:31:17 PM PDT 24
Peak memory 203604 kb
Host smart-8d75105f-ef11-4b1f-85af-830481874a9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616194020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1616194020
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2106792240
Short name T1552
Test name
Test status
Simulation time 246186033 ps
CPU time 1.63 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203004 kb
Host smart-9b34ac3c-b678-4d59-be98-7f0bd32ae705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106792240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2106792240
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3761275328
Short name T1485
Test name
Test status
Simulation time 307381909 ps
CPU time 1.58 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203212 kb
Host smart-26ec1762-9141-45ef-9eb7-d67b5e7d2f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761275328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3761275328
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2194433581
Short name T1549
Test name
Test status
Simulation time 221266811 ps
CPU time 1.02 seconds
Started May 26 12:30:52 PM PDT 24
Finished May 26 12:30:54 PM PDT 24
Peak memory 203740 kb
Host smart-f226ef9b-6f4e-4400-b4dd-d9edfe85470b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194433581 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2194433581
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3569408207
Short name T217
Test name
Test status
Simulation time 17525451 ps
CPU time 0.83 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:09 PM PDT 24
Peak memory 203704 kb
Host smart-aa86dc70-c0e5-4eca-87c3-3c7922860f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569408207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3569408207
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.978657843
Short name T1507
Test name
Test status
Simulation time 22903234 ps
CPU time 0.67 seconds
Started May 26 12:30:56 PM PDT 24
Finished May 26 12:30:57 PM PDT 24
Peak memory 203624 kb
Host smart-71a8a09b-3b65-4930-b8c8-ac01afdd1774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978657843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.978657843
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4242046670
Short name T222
Test name
Test status
Simulation time 31228477 ps
CPU time 1.17 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 202596 kb
Host smart-e3108353-c433-476d-8c8f-d6d3b5651ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242046670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.4242046670
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.783873238
Short name T1504
Test name
Test status
Simulation time 25258993 ps
CPU time 0.86 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 202460 kb
Host smart-5178c5de-68f3-4422-83f8-638d345fd55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783873238 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.783873238
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.4193992044
Short name T1466
Test name
Test status
Simulation time 71772163 ps
CPU time 0.8 seconds
Started May 26 12:31:03 PM PDT 24
Finished May 26 12:31:05 PM PDT 24
Peak memory 203688 kb
Host smart-53e41f2a-6718-436b-b8f8-513bfe5a3c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193992044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.4193992044
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2309408755
Short name T1463
Test name
Test status
Simulation time 15763426 ps
CPU time 0.75 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203572 kb
Host smart-42b2d437-e008-406c-9125-d3241200ae26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309408755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2309408755
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3613330008
Short name T1468
Test name
Test status
Simulation time 27821385 ps
CPU time 1.1 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:09 PM PDT 24
Peak memory 203912 kb
Host smart-ad1c90f8-b787-45af-a664-353721181ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613330008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3613330008
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1504151307
Short name T1534
Test name
Test status
Simulation time 34151738 ps
CPU time 1.38 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:09 PM PDT 24
Peak memory 203900 kb
Host smart-4e9efe23-7953-4f04-b8ca-54febd511e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504151307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1504151307
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.246860502
Short name T190
Test name
Test status
Simulation time 140407676 ps
CPU time 2.47 seconds
Started May 26 12:30:49 PM PDT 24
Finished May 26 12:30:52 PM PDT 24
Peak memory 203904 kb
Host smart-7e3fe205-495d-4361-b44c-e502e4469427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246860502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.246860502
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.278191683
Short name T1526
Test name
Test status
Simulation time 25115435 ps
CPU time 1.09 seconds
Started May 26 12:31:01 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203624 kb
Host smart-797d3ed8-434e-42c6-b44f-1a393917b171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278191683 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.278191683
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.113310562
Short name T219
Test name
Test status
Simulation time 49422595 ps
CPU time 0.73 seconds
Started May 26 12:31:10 PM PDT 24
Finished May 26 12:31:12 PM PDT 24
Peak memory 203616 kb
Host smart-a2edc752-0113-4d36-bb8b-66e81599b47e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113310562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.113310562
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3149607650
Short name T1492
Test name
Test status
Simulation time 27876238 ps
CPU time 0.72 seconds
Started May 26 12:31:39 PM PDT 24
Finished May 26 12:31:41 PM PDT 24
Peak memory 203572 kb
Host smart-9f09adcf-0a50-43e2-9df4-210b129de41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149607650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3149607650
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.235928439
Short name T1520
Test name
Test status
Simulation time 58461136 ps
CPU time 0.92 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203668 kb
Host smart-3788271e-15de-4de3-b869-e937a92428f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235928439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.235928439
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3718576904
Short name T192
Test name
Test status
Simulation time 409958235 ps
CPU time 1.45 seconds
Started May 26 12:30:48 PM PDT 24
Finished May 26 12:30:50 PM PDT 24
Peak memory 203824 kb
Host smart-b40479b6-fd51-4881-aa27-dbe1f6576a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718576904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3718576904
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.442675271
Short name T200
Test name
Test status
Simulation time 135073197 ps
CPU time 2.44 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203744 kb
Host smart-1a07ca57-2f8f-4efa-b8e0-526d4ec371da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442675271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.442675271
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1952252263
Short name T95
Test name
Test status
Simulation time 100194249 ps
CPU time 0.83 seconds
Started May 26 12:31:01 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203788 kb
Host smart-4a055728-42fd-43dd-99e3-b5d9a3da8249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952252263 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1952252263
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.367237160
Short name T1528
Test name
Test status
Simulation time 19975083 ps
CPU time 0.69 seconds
Started May 26 12:31:19 PM PDT 24
Finished May 26 12:31:21 PM PDT 24
Peak memory 203632 kb
Host smart-a440c304-9c07-49f6-96cd-7e9e04f021cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367237160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.367237160
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3719398937
Short name T1489
Test name
Test status
Simulation time 16876283 ps
CPU time 0.65 seconds
Started May 26 12:31:30 PM PDT 24
Finished May 26 12:31:31 PM PDT 24
Peak memory 203656 kb
Host smart-77343882-33b9-4ad6-8b7d-369363cfb930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719398937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3719398937
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2134107283
Short name T1541
Test name
Test status
Simulation time 307849906 ps
CPU time 1.2 seconds
Started May 26 12:31:31 PM PDT 24
Finished May 26 12:31:34 PM PDT 24
Peak memory 203928 kb
Host smart-535b055b-1e38-435a-95f9-a0429cbb8aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134107283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2134107283
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.977916212
Short name T1515
Test name
Test status
Simulation time 89826446 ps
CPU time 1.36 seconds
Started May 26 12:31:15 PM PDT 24
Finished May 26 12:31:17 PM PDT 24
Peak memory 203916 kb
Host smart-39e6456a-5cdb-489c-b52e-3166b30b29f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977916212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.977916212
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2856091359
Short name T251
Test name
Test status
Simulation time 291010455 ps
CPU time 1.63 seconds
Started May 26 12:30:52 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203924 kb
Host smart-ee0757bd-6a95-425b-8e02-dd49cfb539a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856091359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2856091359
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.967024665
Short name T1481
Test name
Test status
Simulation time 38717971 ps
CPU time 1.01 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:05 PM PDT 24
Peak memory 203752 kb
Host smart-a7d17b5b-e5a2-4f3d-8db5-3d47d21bfa12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967024665 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.967024665
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2489390202
Short name T208
Test name
Test status
Simulation time 38528847 ps
CPU time 0.76 seconds
Started May 26 12:31:36 PM PDT 24
Finished May 26 12:31:38 PM PDT 24
Peak memory 203696 kb
Host smart-63654662-cb1b-4828-aff2-9f9295636f41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489390202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2489390202
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3147313529
Short name T1543
Test name
Test status
Simulation time 26291081 ps
CPU time 0.65 seconds
Started May 26 12:30:50 PM PDT 24
Finished May 26 12:31:02 PM PDT 24
Peak memory 203568 kb
Host smart-d496bd24-e247-409e-8956-d1c99ef1b77b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147313529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3147313529
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2393322740
Short name T1547
Test name
Test status
Simulation time 97769867 ps
CPU time 1.09 seconds
Started May 26 12:31:24 PM PDT 24
Finished May 26 12:31:27 PM PDT 24
Peak memory 203896 kb
Host smart-42a034c0-d5a1-4a7b-b604-19104c8fa5d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393322740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2393322740
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.294551960
Short name T202
Test name
Test status
Simulation time 367552109 ps
CPU time 1.61 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203912 kb
Host smart-3b297946-d99c-4c93-8da4-e785b262a566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294551960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.294551960
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3734427717
Short name T1506
Test name
Test status
Simulation time 71714938 ps
CPU time 0.82 seconds
Started May 26 12:31:17 PM PDT 24
Finished May 26 12:31:19 PM PDT 24
Peak memory 203704 kb
Host smart-db729e8b-a83f-47e1-97b8-ba82be511db7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734427717 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3734427717
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1884623421
Short name T1514
Test name
Test status
Simulation time 76042725 ps
CPU time 0.7 seconds
Started May 26 12:31:06 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203712 kb
Host smart-11260c75-3043-4f57-a3b6-c2c6e25196c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884623421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1884623421
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2222454214
Short name T1533
Test name
Test status
Simulation time 14320705 ps
CPU time 0.62 seconds
Started May 26 12:31:11 PM PDT 24
Finished May 26 12:31:17 PM PDT 24
Peak memory 203628 kb
Host smart-296f95c4-d1cd-4fb6-b8aa-18ae5af01e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222454214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2222454214
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1695132354
Short name T224
Test name
Test status
Simulation time 62927816 ps
CPU time 1.33 seconds
Started May 26 12:31:30 PM PDT 24
Finished May 26 12:31:32 PM PDT 24
Peak memory 204036 kb
Host smart-9542bfe6-d3bf-4cfa-b2ac-1edca175606b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695132354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1695132354
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1032152932
Short name T97
Test name
Test status
Simulation time 1067343069 ps
CPU time 2.18 seconds
Started May 26 12:30:55 PM PDT 24
Finished May 26 12:30:58 PM PDT 24
Peak memory 203820 kb
Host smart-6c601f48-9cc0-4ad1-aba6-300d4af03523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032152932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1032152932
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3865957262
Short name T1480
Test name
Test status
Simulation time 248747745 ps
CPU time 1.69 seconds
Started May 26 12:31:04 PM PDT 24
Finished May 26 12:31:07 PM PDT 24
Peak memory 203928 kb
Host smart-72b76583-3c36-49ab-98e2-38bcf842f809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865957262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3865957262
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.406066041
Short name T205
Test name
Test status
Simulation time 88326630 ps
CPU time 0.89 seconds
Started May 26 12:31:10 PM PDT 24
Finished May 26 12:31:12 PM PDT 24
Peak memory 204128 kb
Host smart-1b9692d6-dbd7-44d3-8ddb-9786793d2885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406066041 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.406066041
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.606404845
Short name T214
Test name
Test status
Simulation time 28600740 ps
CPU time 0.76 seconds
Started May 26 12:31:18 PM PDT 24
Finished May 26 12:31:20 PM PDT 24
Peak memory 203616 kb
Host smart-2dd37fa8-69eb-42e2-abd1-87273f4b1c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606404845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.606404845
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.696378987
Short name T1513
Test name
Test status
Simulation time 22004413 ps
CPU time 0.71 seconds
Started May 26 12:31:03 PM PDT 24
Finished May 26 12:31:05 PM PDT 24
Peak memory 203560 kb
Host smart-77775ad1-a064-4d47-92ca-3bb90a5843e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696378987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.696378987
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1482684038
Short name T1494
Test name
Test status
Simulation time 21934590 ps
CPU time 0.87 seconds
Started May 26 12:31:25 PM PDT 24
Finished May 26 12:31:28 PM PDT 24
Peak memory 203188 kb
Host smart-a4c8e1eb-6893-48de-b02e-b1d84eb705e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482684038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1482684038
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1188089778
Short name T149
Test name
Test status
Simulation time 356454958 ps
CPU time 1.8 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:10 PM PDT 24
Peak memory 203920 kb
Host smart-f317370d-4012-4cc4-8151-052efc93e926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188089778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1188089778
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.4087269038
Short name T198
Test name
Test status
Simulation time 256958689 ps
CPU time 1.49 seconds
Started May 26 12:31:17 PM PDT 24
Finished May 26 12:31:19 PM PDT 24
Peak memory 203944 kb
Host smart-264c5b67-a341-4a27-9687-564fa1e5b536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087269038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.4087269038
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3314116986
Short name T189
Test name
Test status
Simulation time 104166864 ps
CPU time 1.37 seconds
Started May 26 12:31:17 PM PDT 24
Finished May 26 12:31:20 PM PDT 24
Peak memory 212116 kb
Host smart-842c5a73-a503-487a-9593-6fe1525afdea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314116986 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3314116986
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3568599556
Short name T104
Test name
Test status
Simulation time 43980800 ps
CPU time 0.77 seconds
Started May 26 12:31:13 PM PDT 24
Finished May 26 12:31:14 PM PDT 24
Peak memory 203700 kb
Host smart-e69e3122-cb5b-4dc9-af8f-fde7567824d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568599556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3568599556
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1314822232
Short name T1453
Test name
Test status
Simulation time 37607514 ps
CPU time 0.69 seconds
Started May 26 12:31:33 PM PDT 24
Finished May 26 12:31:34 PM PDT 24
Peak memory 203632 kb
Host smart-087000e5-8f90-43cf-9056-959c697617a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314822232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1314822232
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1935198875
Short name T1471
Test name
Test status
Simulation time 47367589 ps
CPU time 1.23 seconds
Started May 26 12:30:55 PM PDT 24
Finished May 26 12:30:57 PM PDT 24
Peak memory 203916 kb
Host smart-34113231-cfed-4276-b901-6dc76f4ecd0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935198875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1935198875
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1909887374
Short name T204
Test name
Test status
Simulation time 106525415 ps
CPU time 2.39 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:21 PM PDT 24
Peak memory 203880 kb
Host smart-0d28272c-08be-4627-a243-ec5c2258513e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909887374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1909887374
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3284270772
Short name T101
Test name
Test status
Simulation time 436270182 ps
CPU time 1.37 seconds
Started May 26 12:30:48 PM PDT 24
Finished May 26 12:30:50 PM PDT 24
Peak memory 203816 kb
Host smart-959d3f48-b7fe-4c03-8af1-cab644a994d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284270772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3284270772
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4015145863
Short name T1483
Test name
Test status
Simulation time 47609396 ps
CPU time 0.78 seconds
Started May 26 12:30:47 PM PDT 24
Finished May 26 12:30:48 PM PDT 24
Peak memory 203480 kb
Host smart-f82b7ef4-d3cf-40b1-bee8-05360947b691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015145863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4015145863
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2782210933
Short name T1554
Test name
Test status
Simulation time 22220742 ps
CPU time 0.79 seconds
Started May 26 12:30:50 PM PDT 24
Finished May 26 12:30:51 PM PDT 24
Peak memory 203680 kb
Host smart-f1b17d6a-1aec-41cf-a258-e1fbe445640d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782210933 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2782210933
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2024723511
Short name T1482
Test name
Test status
Simulation time 22390015 ps
CPU time 0.73 seconds
Started May 26 12:30:43 PM PDT 24
Finished May 26 12:30:45 PM PDT 24
Peak memory 203568 kb
Host smart-fda4e550-526e-4774-ad86-a34385a331d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024723511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2024723511
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3861648484
Short name T1460
Test name
Test status
Simulation time 21096490 ps
CPU time 0.62 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:07 PM PDT 24
Peak memory 203564 kb
Host smart-13565293-ff69-4bb4-8178-eda3fbe5a9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861648484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3861648484
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1524792989
Short name T1540
Test name
Test status
Simulation time 35651740 ps
CPU time 0.91 seconds
Started May 26 12:30:47 PM PDT 24
Finished May 26 12:30:48 PM PDT 24
Peak memory 203592 kb
Host smart-1b43416f-296a-422b-9781-9e5cd9a46e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524792989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1524792989
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3942216705
Short name T1560
Test name
Test status
Simulation time 182971361 ps
CPU time 1.28 seconds
Started May 26 12:30:46 PM PDT 24
Finished May 26 12:30:48 PM PDT 24
Peak memory 203888 kb
Host smart-fc3f4d2f-d01f-4649-b311-8173810c96b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942216705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3942216705
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2883825447
Short name T195
Test name
Test status
Simulation time 55339508 ps
CPU time 1.47 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203864 kb
Host smart-45bd0032-d992-4879-8a06-6058d4d0272d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883825447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2883825447
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1928629916
Short name T1451
Test name
Test status
Simulation time 18043907 ps
CPU time 0.69 seconds
Started May 26 12:31:16 PM PDT 24
Finished May 26 12:31:18 PM PDT 24
Peak memory 203572 kb
Host smart-d94839f4-6686-45e4-9edf-d8e6415070b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928629916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1928629916
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.138974367
Short name T1456
Test name
Test status
Simulation time 133848562 ps
CPU time 0.64 seconds
Started May 26 12:31:29 PM PDT 24
Finished May 26 12:31:31 PM PDT 24
Peak memory 203624 kb
Host smart-683598b4-342a-49dd-b083-303779d57d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138974367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.138974367
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2813543857
Short name T1452
Test name
Test status
Simulation time 23400425 ps
CPU time 0.7 seconds
Started May 26 12:31:10 PM PDT 24
Finished May 26 12:31:12 PM PDT 24
Peak memory 203636 kb
Host smart-a8651074-4377-40c2-8ae8-1e34e90836f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813543857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2813543857
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.853559780
Short name T1458
Test name
Test status
Simulation time 17729417 ps
CPU time 0.66 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203556 kb
Host smart-c2a55ac1-2ea0-48b5-90e7-90c46ab73d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853559780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.853559780
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2013636293
Short name T1470
Test name
Test status
Simulation time 45218962 ps
CPU time 0.68 seconds
Started May 26 12:31:17 PM PDT 24
Finished May 26 12:31:19 PM PDT 24
Peak memory 203624 kb
Host smart-bb11855e-e3d6-4c27-b82b-016a606a9a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013636293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2013636293
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2026405286
Short name T1454
Test name
Test status
Simulation time 19691987 ps
CPU time 0.66 seconds
Started May 26 12:31:09 PM PDT 24
Finished May 26 12:31:11 PM PDT 24
Peak memory 203636 kb
Host smart-29e6a58f-050b-481f-9d99-97f58c542d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026405286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2026405286
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1235059349
Short name T1467
Test name
Test status
Simulation time 24522606 ps
CPU time 0.66 seconds
Started May 26 12:31:18 PM PDT 24
Finished May 26 12:31:20 PM PDT 24
Peak memory 203648 kb
Host smart-ef77b1a8-0e51-4d52-aebe-3bbbe5670600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235059349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1235059349
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3765380508
Short name T1488
Test name
Test status
Simulation time 27743168 ps
CPU time 0.65 seconds
Started May 26 12:31:26 PM PDT 24
Finished May 26 12:31:28 PM PDT 24
Peak memory 203632 kb
Host smart-d57ec52e-7bfd-4309-8074-11daeac63591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765380508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3765380508
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1165063777
Short name T1491
Test name
Test status
Simulation time 17708683 ps
CPU time 0.66 seconds
Started May 26 12:31:45 PM PDT 24
Finished May 26 12:31:48 PM PDT 24
Peak memory 204000 kb
Host smart-a90979a9-58d9-46d6-b116-6f6ca1c5d0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165063777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1165063777
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1622900285
Short name T1469
Test name
Test status
Simulation time 17778517 ps
CPU time 0.7 seconds
Started May 26 12:31:06 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203636 kb
Host smart-82f25bed-43bc-41f6-8399-dff76cd1dfcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622900285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1622900285
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3336548459
Short name T216
Test name
Test status
Simulation time 830355271 ps
CPU time 2.15 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203900 kb
Host smart-29855a46-c00c-4d1b-a8a2-964a8201e2b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336548459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3336548459
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2626472969
Short name T103
Test name
Test status
Simulation time 2870789680 ps
CPU time 3.59 seconds
Started May 26 12:30:49 PM PDT 24
Finished May 26 12:30:53 PM PDT 24
Peak memory 203956 kb
Host smart-7b1922ec-559c-4144-a1d8-b916839c93be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626472969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2626472969
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2814106626
Short name T272
Test name
Test status
Simulation time 34221575 ps
CPU time 0.72 seconds
Started May 26 12:30:54 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203596 kb
Host smart-c7960c77-ee4f-4fa7-880a-cdfbaa15e64a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814106626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2814106626
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1802107979
Short name T1546
Test name
Test status
Simulation time 25377542 ps
CPU time 0.78 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:07 PM PDT 24
Peak memory 203704 kb
Host smart-5dd55358-ea5c-401c-aadb-a8ba9f8a4584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802107979 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1802107979
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1549279053
Short name T218
Test name
Test status
Simulation time 47157052 ps
CPU time 0.69 seconds
Started May 26 12:30:50 PM PDT 24
Finished May 26 12:30:51 PM PDT 24
Peak memory 203688 kb
Host smart-4aea7ba6-e868-4b66-a16a-87b779653d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549279053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1549279053
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.922019491
Short name T1508
Test name
Test status
Simulation time 43604470 ps
CPU time 0.64 seconds
Started May 26 12:30:45 PM PDT 24
Finished May 26 12:30:46 PM PDT 24
Peak memory 203568 kb
Host smart-c3868297-7f55-4803-8894-ae1eb26e8d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922019491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.922019491
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2064974336
Short name T102
Test name
Test status
Simulation time 56012034 ps
CPU time 1.17 seconds
Started May 26 12:30:46 PM PDT 24
Finished May 26 12:30:48 PM PDT 24
Peak memory 203872 kb
Host smart-8f7396f1-a8ff-4a07-b2ea-bc7d9f95d362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064974336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2064974336
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1443979600
Short name T1537
Test name
Test status
Simulation time 174246268 ps
CPU time 1.35 seconds
Started May 26 12:30:46 PM PDT 24
Finished May 26 12:30:48 PM PDT 24
Peak memory 203828 kb
Host smart-805d1317-c1b9-4b45-9c96-3f485402b130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443979600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1443979600
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4055947085
Short name T150
Test name
Test status
Simulation time 58281263 ps
CPU time 1.53 seconds
Started May 26 12:30:56 PM PDT 24
Finished May 26 12:30:58 PM PDT 24
Peak memory 203924 kb
Host smart-2d5c97b0-9c3b-4e1c-95a6-d3999c35ad6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055947085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4055947085
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2611772151
Short name T1542
Test name
Test status
Simulation time 18779318 ps
CPU time 0.66 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203600 kb
Host smart-4aef8bf8-18a3-4e15-93b8-f440a7216d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611772151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2611772151
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.1304434968
Short name T1523
Test name
Test status
Simulation time 16652243 ps
CPU time 0.78 seconds
Started May 26 12:31:14 PM PDT 24
Finished May 26 12:31:16 PM PDT 24
Peak memory 203640 kb
Host smart-51ad7dfa-cfa4-4cd1-ba00-78a4334f5d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304434968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1304434968
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1365368357
Short name T1461
Test name
Test status
Simulation time 17238506 ps
CPU time 0.65 seconds
Started May 26 12:31:16 PM PDT 24
Finished May 26 12:31:23 PM PDT 24
Peak memory 203572 kb
Host smart-b2e2365d-862f-459a-b6dd-e276fd89cab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365368357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1365368357
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2256483396
Short name T1465
Test name
Test status
Simulation time 27135023 ps
CPU time 0.63 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:06 PM PDT 24
Peak memory 203608 kb
Host smart-a958f92f-0729-4404-a6e6-22b091c36b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256483396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2256483396
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4079042969
Short name T1457
Test name
Test status
Simulation time 31046667 ps
CPU time 0.7 seconds
Started May 26 12:31:29 PM PDT 24
Finished May 26 12:31:31 PM PDT 24
Peak memory 203628 kb
Host smart-83bb92a1-74b1-413c-aff2-4a07fdcab7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079042969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4079042969
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3609011849
Short name T1522
Test name
Test status
Simulation time 41766867 ps
CPU time 0.65 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:02 PM PDT 24
Peak memory 203712 kb
Host smart-dd869d29-7042-4c52-bf9b-c2601dd5f4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609011849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3609011849
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1894302049
Short name T1535
Test name
Test status
Simulation time 50703308 ps
CPU time 0.66 seconds
Started May 26 12:31:24 PM PDT 24
Finished May 26 12:31:27 PM PDT 24
Peak memory 203656 kb
Host smart-54f0af0d-8ced-430d-b596-82d616aea4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894302049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1894302049
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1556943497
Short name T1531
Test name
Test status
Simulation time 33354720 ps
CPU time 0.7 seconds
Started May 26 12:31:21 PM PDT 24
Finished May 26 12:31:23 PM PDT 24
Peak memory 203636 kb
Host smart-9992d978-167d-43af-a299-346536f43ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556943497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1556943497
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2519032843
Short name T1511
Test name
Test status
Simulation time 30240226 ps
CPU time 0.68 seconds
Started May 26 12:31:16 PM PDT 24
Finished May 26 12:31:18 PM PDT 24
Peak memory 203676 kb
Host smart-5d2a982d-bbbc-450f-867c-fb15641ddd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519032843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2519032843
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.499408126
Short name T1559
Test name
Test status
Simulation time 62719456 ps
CPU time 0.67 seconds
Started May 26 12:31:31 PM PDT 24
Finished May 26 12:31:32 PM PDT 24
Peak memory 203628 kb
Host smart-47d522ab-a7f3-4f91-9db9-5005866d1faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499408126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.499408126
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2725137249
Short name T1496
Test name
Test status
Simulation time 106054967 ps
CPU time 2.1 seconds
Started May 26 12:30:47 PM PDT 24
Finished May 26 12:30:49 PM PDT 24
Peak memory 203860 kb
Host smart-99f725ed-be20-4e11-8981-72b9c6667913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725137249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2725137249
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2807355096
Short name T273
Test name
Test status
Simulation time 52079048 ps
CPU time 0.72 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203596 kb
Host smart-95c2f760-fce1-4604-843e-47f99b3e995f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807355096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2807355096
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3436466819
Short name T1525
Test name
Test status
Simulation time 26174661 ps
CPU time 0.88 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:01 PM PDT 24
Peak memory 203720 kb
Host smart-d09c4895-51d4-4f26-b8fa-2c04da363fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436466819 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3436466819
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1052075248
Short name T220
Test name
Test status
Simulation time 27638568 ps
CPU time 0.83 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203680 kb
Host smart-34f1e547-7df3-4c3d-a44d-51de13a244b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052075248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1052075248
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3149799139
Short name T1476
Test name
Test status
Simulation time 60542587 ps
CPU time 0.67 seconds
Started May 26 12:31:03 PM PDT 24
Finished May 26 12:31:05 PM PDT 24
Peak memory 203560 kb
Host smart-713dffb9-472f-4df8-a4cf-b096ac6dc99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149799139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3149799139
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1804313938
Short name T1487
Test name
Test status
Simulation time 199608817 ps
CPU time 0.99 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203840 kb
Host smart-1e65573a-82e5-4f14-b019-044f99afcac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804313938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1804313938
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.646879396
Short name T1532
Test name
Test status
Simulation time 49724698 ps
CPU time 1.19 seconds
Started May 26 12:31:01 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203892 kb
Host smart-eb54b2f4-8ace-42b4-9b5d-514abe94d90c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646879396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.646879396
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3471867760
Short name T1498
Test name
Test status
Simulation time 65063223 ps
CPU time 1.42 seconds
Started May 26 12:30:48 PM PDT 24
Finished May 26 12:30:50 PM PDT 24
Peak memory 203904 kb
Host smart-6659492b-142f-460d-bb82-ad9f18108406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471867760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3471867760
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.1492326800
Short name T1519
Test name
Test status
Simulation time 19220101 ps
CPU time 0.65 seconds
Started May 26 12:31:26 PM PDT 24
Finished May 26 12:31:29 PM PDT 24
Peak memory 203572 kb
Host smart-80b7505c-3c44-4b83-b0ef-0fd84f337c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492326800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1492326800
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1519656888
Short name T1455
Test name
Test status
Simulation time 16432765 ps
CPU time 0.7 seconds
Started May 26 12:31:29 PM PDT 24
Finished May 26 12:31:31 PM PDT 24
Peak memory 203704 kb
Host smart-b2886b92-5918-4ad3-b055-5695f7bd4732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519656888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1519656888
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.74132816
Short name T1538
Test name
Test status
Simulation time 21869836 ps
CPU time 0.69 seconds
Started May 26 12:31:33 PM PDT 24
Finished May 26 12:31:34 PM PDT 24
Peak memory 203704 kb
Host smart-19cbf139-a5f0-43c5-b4d8-cff07adbc60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74132816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.74132816
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.51744612
Short name T1530
Test name
Test status
Simulation time 26298395 ps
CPU time 0.64 seconds
Started May 26 12:31:26 PM PDT 24
Finished May 26 12:31:29 PM PDT 24
Peak memory 203652 kb
Host smart-5db785ef-d177-407b-93a0-e4b2b5018e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51744612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.51744612
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1476554749
Short name T1536
Test name
Test status
Simulation time 42922180 ps
CPU time 0.62 seconds
Started May 26 12:30:53 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203580 kb
Host smart-ead517d0-efcf-4708-91a3-6d0a2118e4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476554749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1476554749
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.407151869
Short name T1509
Test name
Test status
Simulation time 34499926 ps
CPU time 0.65 seconds
Started May 26 12:31:06 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203624 kb
Host smart-741d8162-c0c7-4baf-bc85-9c6fb16cdeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407151869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.407151869
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1972194155
Short name T1529
Test name
Test status
Simulation time 45204410 ps
CPU time 0.68 seconds
Started May 26 12:31:19 PM PDT 24
Finished May 26 12:31:21 PM PDT 24
Peak memory 203632 kb
Host smart-4cb42d77-a56e-4f01-84f4-b7eb550b256c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972194155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1972194155
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2889065909
Short name T1459
Test name
Test status
Simulation time 16752446 ps
CPU time 0.67 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203608 kb
Host smart-4ce9e3af-fa0b-43a9-ba40-a63071a7db68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889065909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2889065909
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3371669853
Short name T1548
Test name
Test status
Simulation time 42867402 ps
CPU time 0.65 seconds
Started May 26 12:31:21 PM PDT 24
Finished May 26 12:31:24 PM PDT 24
Peak memory 203700 kb
Host smart-cce64d14-51f0-4b96-b7e2-7a17590f828b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371669853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3371669853
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3469655924
Short name T1493
Test name
Test status
Simulation time 41831351 ps
CPU time 0.66 seconds
Started May 26 12:31:25 PM PDT 24
Finished May 26 12:31:28 PM PDT 24
Peak memory 203260 kb
Host smart-a17f16ca-312c-4e63-a8f1-bdf42ec8fd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469655924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3469655924
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1817814247
Short name T1497
Test name
Test status
Simulation time 43859219 ps
CPU time 1.03 seconds
Started May 26 12:31:05 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203712 kb
Host smart-a300061a-cd48-492e-a589-44685abadc19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817814247 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1817814247
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1677888670
Short name T100
Test name
Test status
Simulation time 46295408 ps
CPU time 0.8 seconds
Started May 26 12:30:56 PM PDT 24
Finished May 26 12:30:57 PM PDT 24
Peak memory 203608 kb
Host smart-cf2b0ab9-034f-4d38-94db-1f5448ab7c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677888670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1677888670
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2294752944
Short name T1521
Test name
Test status
Simulation time 54938028 ps
CPU time 0.67 seconds
Started May 26 12:30:58 PM PDT 24
Finished May 26 12:31:00 PM PDT 24
Peak memory 203552 kb
Host smart-66e5f1c2-6789-4f98-bd01-8d3581974918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294752944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2294752944
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3459713414
Short name T1486
Test name
Test status
Simulation time 66620811 ps
CPU time 0.86 seconds
Started May 26 12:31:21 PM PDT 24
Finished May 26 12:31:24 PM PDT 24
Peak memory 203696 kb
Host smart-49a37b42-fb63-4bf0-bb2d-7483a7c29738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459713414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3459713414
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1396990944
Short name T1512
Test name
Test status
Simulation time 81090122 ps
CPU time 1.86 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:10 PM PDT 24
Peak memory 203872 kb
Host smart-15df6c02-d34f-44b8-822e-78eab9dfdaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396990944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1396990944
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1740708262
Short name T1477
Test name
Test status
Simulation time 120920396 ps
CPU time 0.97 seconds
Started May 26 12:30:52 PM PDT 24
Finished May 26 12:30:54 PM PDT 24
Peak memory 203052 kb
Host smart-801685a4-1a6f-498a-821d-e3c2d1832590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740708262 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1740708262
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2701611438
Short name T1503
Test name
Test status
Simulation time 102746379 ps
CPU time 0.74 seconds
Started May 26 12:31:06 PM PDT 24
Finished May 26 12:31:08 PM PDT 24
Peak memory 203576 kb
Host smart-02e839b3-b373-4e89-87f9-037275a79058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701611438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2701611438
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2150544308
Short name T1553
Test name
Test status
Simulation time 44487977 ps
CPU time 0.63 seconds
Started May 26 12:31:21 PM PDT 24
Finished May 26 12:31:23 PM PDT 24
Peak memory 203636 kb
Host smart-408a602b-0bbe-41b9-b4a5-c7d95017df48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150544308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2150544308
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1970237415
Short name T1544
Test name
Test status
Simulation time 97635012 ps
CPU time 1.24 seconds
Started May 26 12:30:55 PM PDT 24
Finished May 26 12:30:57 PM PDT 24
Peak memory 203804 kb
Host smart-fa615fa6-a4b4-4be0-b2a9-2bdb4901a986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970237415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1970237415
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.602376000
Short name T1551
Test name
Test status
Simulation time 56759608 ps
CPU time 1.31 seconds
Started May 26 12:31:03 PM PDT 24
Finished May 26 12:31:06 PM PDT 24
Peak memory 203884 kb
Host smart-331729ae-2010-41d5-9aec-59c30914dcdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602376000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.602376000
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3818785445
Short name T98
Test name
Test status
Simulation time 530614979 ps
CPU time 2.62 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203184 kb
Host smart-278dc351-0b51-4c0b-ab03-758a6875a428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818785445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3818785445
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3662301492
Short name T1479
Test name
Test status
Simulation time 64527625 ps
CPU time 0.93 seconds
Started May 26 12:30:49 PM PDT 24
Finished May 26 12:30:50 PM PDT 24
Peak memory 203704 kb
Host smart-931472fd-d3f2-432a-ae76-020d2c6f5028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662301492 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3662301492
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3980664939
Short name T213
Test name
Test status
Simulation time 28621571 ps
CPU time 0.79 seconds
Started May 26 12:31:26 PM PDT 24
Finished May 26 12:31:28 PM PDT 24
Peak memory 203636 kb
Host smart-6c16390d-6ef7-4b04-ba72-e9fdee53c9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980664939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3980664939
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1022183406
Short name T1475
Test name
Test status
Simulation time 43286268 ps
CPU time 0.65 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:01 PM PDT 24
Peak memory 203612 kb
Host smart-7bfccd80-6899-4171-8793-3423af31f597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022183406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1022183406
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3065971693
Short name T1502
Test name
Test status
Simulation time 129483736 ps
CPU time 1.15 seconds
Started May 26 12:31:01 PM PDT 24
Finished May 26 12:31:03 PM PDT 24
Peak memory 203816 kb
Host smart-f6a82ab9-d359-4000-a8b2-967e71df29af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065971693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3065971693
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.386774141
Short name T1524
Test name
Test status
Simulation time 34603674 ps
CPU time 1.53 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:10 PM PDT 24
Peak memory 203848 kb
Host smart-f3f8011f-6991-4d1b-97b6-41c0048483d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386774141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.386774141
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.609048731
Short name T252
Test name
Test status
Simulation time 440923631 ps
CPU time 1.53 seconds
Started May 26 12:31:03 PM PDT 24
Finished May 26 12:31:06 PM PDT 24
Peak memory 203864 kb
Host smart-bd92cf70-fd46-4a0f-aba9-bf45c89e99b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609048731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.609048731
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.100930477
Short name T1484
Test name
Test status
Simulation time 43729910 ps
CPU time 1 seconds
Started May 26 12:31:22 PM PDT 24
Finished May 26 12:31:26 PM PDT 24
Peak memory 203772 kb
Host smart-a6dacc04-a64f-478b-8701-d9a886070100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100930477 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.100930477
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3672227892
Short name T1478
Test name
Test status
Simulation time 46748588 ps
CPU time 0.67 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 203604 kb
Host smart-56a62294-6457-4dc2-8b68-d572ed211809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672227892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3672227892
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.747921605
Short name T1462
Test name
Test status
Simulation time 19225290 ps
CPU time 0.69 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:07 PM PDT 24
Peak memory 203632 kb
Host smart-45908e13-1500-44f9-beff-982b626cbf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747921605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.747921605
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2771072118
Short name T1555
Test name
Test status
Simulation time 97146582 ps
CPU time 0.81 seconds
Started May 26 12:30:54 PM PDT 24
Finished May 26 12:30:55 PM PDT 24
Peak memory 203564 kb
Host smart-7d49bdfb-97cf-4fd4-978d-cf1fabe208e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771072118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2771072118
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.592520778
Short name T191
Test name
Test status
Simulation time 43448481 ps
CPU time 1.15 seconds
Started May 26 12:30:51 PM PDT 24
Finished May 26 12:30:52 PM PDT 24
Peak memory 203888 kb
Host smart-9ca2d62f-b9b1-4304-b8a0-a96f9a7a5b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592520778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.592520778
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.11838326
Short name T193
Test name
Test status
Simulation time 286978488 ps
CPU time 1.54 seconds
Started May 26 12:31:07 PM PDT 24
Finished May 26 12:31:09 PM PDT 24
Peak memory 204324 kb
Host smart-ff877fb2-f6fa-4ebc-9b52-7ab5605d377c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.11838326
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1687229092
Short name T196
Test name
Test status
Simulation time 31184202 ps
CPU time 1.35 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:04 PM PDT 24
Peak memory 212636 kb
Host smart-7595527c-8e3e-479e-a4f3-776177aa9988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687229092 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1687229092
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2607425660
Short name T221
Test name
Test status
Simulation time 21026305 ps
CPU time 0.74 seconds
Started May 26 12:31:00 PM PDT 24
Finished May 26 12:31:02 PM PDT 24
Peak memory 203560 kb
Host smart-9b6a3d03-5088-4d1f-b65d-f1cfd5352c31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607425660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2607425660
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1615076301
Short name T1557
Test name
Test status
Simulation time 22784648 ps
CPU time 0.65 seconds
Started May 26 12:31:26 PM PDT 24
Finished May 26 12:31:29 PM PDT 24
Peak memory 203624 kb
Host smart-0ba57915-5192-4f5c-9657-4e5b619d73b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615076301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1615076301
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3869641622
Short name T1556
Test name
Test status
Simulation time 56180456 ps
CPU time 0.8 seconds
Started May 26 12:30:59 PM PDT 24
Finished May 26 12:31:01 PM PDT 24
Peak memory 203672 kb
Host smart-85648240-5b87-4a80-a1f1-3b95490dbc80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869641622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3869641622
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.27299771
Short name T1499
Test name
Test status
Simulation time 809172995 ps
CPU time 1.55 seconds
Started May 26 12:31:02 PM PDT 24
Finished May 26 12:31:05 PM PDT 24
Peak memory 203900 kb
Host smart-922c3cbe-739c-4cd0-97b6-d16b2ea4e178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27299771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.27299771
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1508464476
Short name T1473
Test name
Test status
Simulation time 355425112 ps
CPU time 1.44 seconds
Started May 26 12:31:08 PM PDT 24
Finished May 26 12:31:11 PM PDT 24
Peak memory 203924 kb
Host smart-e9e73263-2685-4174-8a57-c24418cd0a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508464476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1508464476
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2821878489
Short name T132
Test name
Test status
Simulation time 85781946 ps
CPU time 1.28 seconds
Started May 26 12:41:20 PM PDT 24
Finished May 26 12:41:22 PM PDT 24
Peak memory 212696 kb
Host smart-0e2b4002-6d08-4bdc-acb7-f4797db06c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821878489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2821878489
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.4080777763
Short name T1038
Test name
Test status
Simulation time 2096895177 ps
CPU time 11.68 seconds
Started May 26 12:41:18 PM PDT 24
Finished May 26 12:41:30 PM PDT 24
Peak memory 338560 kb
Host smart-2a8d9bb5-9ea7-4bfd-b939-974f588821c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080777763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.4080777763
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3932924616
Short name T48
Test name
Test status
Simulation time 9421377756 ps
CPU time 167.88 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:44:06 PM PDT 24
Peak memory 765876 kb
Host smart-088056d0-5d5d-4ec3-b483-545afc6ae9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932924616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3932924616
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3871404295
Short name T1024
Test name
Test status
Simulation time 11178093771 ps
CPU time 136.39 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:43:34 PM PDT 24
Peak memory 578856 kb
Host smart-3452ddda-81c5-4c76-8f29-2311f6883eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871404295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3871404295
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1053177602
Short name T961
Test name
Test status
Simulation time 174294134 ps
CPU time 0.88 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 12:41:17 PM PDT 24
Peak memory 204232 kb
Host smart-2611f6f6-cf64-4941-bb64-84b828729c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053177602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1053177602
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.4284400110
Short name T294
Test name
Test status
Simulation time 143498720 ps
CPU time 7.39 seconds
Started May 26 12:41:19 PM PDT 24
Finished May 26 12:41:27 PM PDT 24
Peak memory 204484 kb
Host smart-f9f19fc4-5510-46c4-84cc-36e843f3ebb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284400110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
4284400110
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1005731603
Short name T110
Test name
Test status
Simulation time 5337678491 ps
CPU time 154.14 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 12:43:51 PM PDT 24
Peak memory 1561724 kb
Host smart-f16af4fb-86c5-4ab0-8a53-8f63b0bf18cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005731603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1005731603
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1204981126
Short name T1010
Test name
Test status
Simulation time 697250746 ps
CPU time 4.81 seconds
Started May 26 12:41:24 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 204372 kb
Host smart-42dedaa1-8274-4845-b4ea-5fb5ba09fc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204981126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1204981126
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3741298817
Short name T993
Test name
Test status
Simulation time 2458605010 ps
CPU time 52.29 seconds
Started May 26 12:41:24 PM PDT 24
Finished May 26 12:42:16 PM PDT 24
Peak memory 479396 kb
Host smart-984e4ed9-a3c5-424c-bf49-cc8014f1fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741298817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3741298817
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.966100848
Short name T139
Test name
Test status
Simulation time 18862737 ps
CPU time 0.66 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:41:19 PM PDT 24
Peak memory 204136 kb
Host smart-92d57630-7042-40fd-8a95-76e1f007b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966100848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.966100848
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3137886936
Short name T1433
Test name
Test status
Simulation time 27392254424 ps
CPU time 132.4 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 12:43:29 PM PDT 24
Peak memory 204576 kb
Host smart-60b59888-f919-41a8-8b36-5a82002cd049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137886936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3137886936
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.699058344
Short name T430
Test name
Test status
Simulation time 1442809266 ps
CPU time 25.04 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:41:42 PM PDT 24
Peak memory 317896 kb
Host smart-fdf7f0b1-6d95-4822-845a-c53a947def30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699058344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.699058344
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.599404407
Short name T880
Test name
Test status
Simulation time 14618659472 ps
CPU time 1439.67 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 01:05:17 PM PDT 24
Peak memory 1925176 kb
Host smart-4d52dec5-d1f0-4cb7-b15f-9aa725d5edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599404407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.599404407
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2240163688
Short name T133
Test name
Test status
Simulation time 542923676 ps
CPU time 11.35 seconds
Started May 26 12:41:18 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 220652 kb
Host smart-33d39098-028f-4a45-a952-262d9b46ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240163688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2240163688
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.36384948
Short name T175
Test name
Test status
Simulation time 437436746 ps
CPU time 0.95 seconds
Started May 26 12:41:26 PM PDT 24
Finished May 26 12:41:28 PM PDT 24
Peak memory 222644 kb
Host smart-b1eb539a-f559-47f2-a559-8e154aad4666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36384948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.36384948
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.576229581
Short name T1394
Test name
Test status
Simulation time 838335097 ps
CPU time 3.65 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 204408 kb
Host smart-d54f536b-3078-437d-acba-198731d3a950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576229581 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.576229581
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3401605472
Short name T1265
Test name
Test status
Simulation time 10112517981 ps
CPU time 47.72 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:42:05 PM PDT 24
Peak memory 375776 kb
Host smart-1471ba89-79f0-408d-89c7-31d27520a5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401605472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3401605472
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1451500670
Short name T323
Test name
Test status
Simulation time 11097861867 ps
CPU time 6.7 seconds
Started May 26 12:41:29 PM PDT 24
Finished May 26 12:41:36 PM PDT 24
Peak memory 278740 kb
Host smart-1bd9e415-3ed4-45eb-8207-7e596830ec5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451500670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1451500670
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1060000223
Short name T1293
Test name
Test status
Simulation time 1169548648 ps
CPU time 3.14 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 204444 kb
Host smart-6959a497-d396-46e1-ba21-799ba09d8112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060000223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1060000223
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.2357146791
Short name T537
Test name
Test status
Simulation time 1206473512 ps
CPU time 3.12 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 204568 kb
Host smart-34e5569f-5ff6-47f5-8809-76b762055397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357146791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2357146791
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2156902895
Short name T15
Test name
Test status
Simulation time 4472313407 ps
CPU time 11.52 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:41:29 PM PDT 24
Peak memory 213232 kb
Host smart-7e1e4b4f-91c7-4299-97bd-702e27592776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156902895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2156902895
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.652163715
Short name T1220
Test name
Test status
Simulation time 726715271 ps
CPU time 3.98 seconds
Started May 26 12:41:19 PM PDT 24
Finished May 26 12:41:23 PM PDT 24
Peak memory 204492 kb
Host smart-fe63b0ef-13d8-476d-9dc3-67e7b47ff84d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652163715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.652163715
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1328316799
Short name T1068
Test name
Test status
Simulation time 11114991823 ps
CPU time 192.4 seconds
Started May 26 12:41:16 PM PDT 24
Finished May 26 12:44:29 PM PDT 24
Peak memory 2831176 kb
Host smart-7b122d14-f07c-46e2-b6e3-dea938ce14a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328316799 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1328316799
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2975910651
Short name T472
Test name
Test status
Simulation time 685884871 ps
CPU time 10.75 seconds
Started May 26 12:41:15 PM PDT 24
Finished May 26 12:41:26 PM PDT 24
Peak memory 209160 kb
Host smart-9dffc2f8-cd71-4416-80b6-b29f28ec0521
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975910651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2975910651
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1968904529
Short name T1407
Test name
Test status
Simulation time 24511548419 ps
CPU time 12.07 seconds
Started May 26 12:41:17 PM PDT 24
Finished May 26 12:41:30 PM PDT 24
Peak memory 276872 kb
Host smart-2976d23f-ec40-4dc5-9908-b136da94bbdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968904529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1968904529
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.4230232818
Short name T707
Test name
Test status
Simulation time 36401652226 ps
CPU time 2176.68 seconds
Started May 26 12:41:18 PM PDT 24
Finished May 26 01:17:35 PM PDT 24
Peak memory 3903992 kb
Host smart-7f9f5ee9-3b31-492a-86d7-425a764f4b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230232818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.4230232818
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3533630901
Short name T670
Test name
Test status
Simulation time 2688400862 ps
CPU time 6.65 seconds
Started May 26 12:41:20 PM PDT 24
Finished May 26 12:41:28 PM PDT 24
Peak memory 218224 kb
Host smart-e84f4c3d-ce76-43a5-b419-f297698cbe55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533630901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3533630901
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1411502978
Short name T571
Test name
Test status
Simulation time 59290704 ps
CPU time 0.6 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:37 PM PDT 24
Peak memory 204052 kb
Host smart-517330e0-5e9a-4805-9574-d64669d72243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411502978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1411502978
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3644319533
Short name T1430
Test name
Test status
Simulation time 2646212746 ps
CPU time 12.81 seconds
Started May 26 12:41:26 PM PDT 24
Finished May 26 12:41:40 PM PDT 24
Peak memory 346132 kb
Host smart-6938f9d9-5d52-412a-a24a-fd72144d38f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644319533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3644319533
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1946562840
Short name T737
Test name
Test status
Simulation time 1875990169 ps
CPU time 69.68 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 12:42:35 PM PDT 24
Peak memory 665932 kb
Host smart-61599eec-54c0-4b2d-a9ce-58ef102e545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946562840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1946562840
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2964996749
Short name T415
Test name
Test status
Simulation time 1795238813 ps
CPU time 129.74 seconds
Started May 26 12:41:23 PM PDT 24
Finished May 26 12:43:33 PM PDT 24
Peak memory 645884 kb
Host smart-37eb4c94-efa2-4c0d-9212-1ff8c74fee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964996749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2964996749
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.504451532
Short name T392
Test name
Test status
Simulation time 285713549 ps
CPU time 1.01 seconds
Started May 26 12:41:27 PM PDT 24
Finished May 26 12:41:28 PM PDT 24
Peak memory 204236 kb
Host smart-34a010a2-2263-4529-aee4-3205a6e8b7e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504451532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.504451532
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2029896727
Short name T740
Test name
Test status
Simulation time 228680998 ps
CPU time 11.45 seconds
Started May 26 12:41:28 PM PDT 24
Finished May 26 12:41:39 PM PDT 24
Peak memory 204376 kb
Host smart-ca4ca135-fe0c-4538-8358-324447efcdf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029896727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2029896727
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.317053567
Short name T645
Test name
Test status
Simulation time 10517874431 ps
CPU time 143.77 seconds
Started May 26 12:41:29 PM PDT 24
Finished May 26 12:43:53 PM PDT 24
Peak memory 1476444 kb
Host smart-3a6b959c-39f7-4fa9-9041-f32c46ce514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317053567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.317053567
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4206644646
Short name T784
Test name
Test status
Simulation time 643990504 ps
CPU time 13.69 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:41:49 PM PDT 24
Peak memory 204508 kb
Host smart-53acc725-2726-4f81-a3d5-758e1166722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206644646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4206644646
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1046036356
Short name T786
Test name
Test status
Simulation time 2280476228 ps
CPU time 42.94 seconds
Started May 26 12:41:33 PM PDT 24
Finished May 26 12:42:17 PM PDT 24
Peak memory 405172 kb
Host smart-0bc679a6-950e-4bff-a069-5be69c455419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046036356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1046036356
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1856267461
Short name T381
Test name
Test status
Simulation time 18601408 ps
CPU time 0.66 seconds
Started May 26 12:41:26 PM PDT 24
Finished May 26 12:41:27 PM PDT 24
Peak memory 204096 kb
Host smart-68ace346-be17-4e0b-b8b9-fe6efb44166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856267461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1856267461
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3367573364
Short name T1168
Test name
Test status
Simulation time 27109402784 ps
CPU time 3415.41 seconds
Started May 26 12:41:25 PM PDT 24
Finished May 26 01:38:21 PM PDT 24
Peak memory 2489340 kb
Host smart-7679f3a4-e54f-4eca-aef6-da9dd82399da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367573364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3367573364
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2642532029
Short name T923
Test name
Test status
Simulation time 4147673174 ps
CPU time 43.15 seconds
Started May 26 12:41:23 PM PDT 24
Finished May 26 12:42:07 PM PDT 24
Peak memory 403140 kb
Host smart-25dc0add-5824-4250-b2e4-9b354f7d2d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642532029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2642532029
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3480467906
Short name T644
Test name
Test status
Simulation time 605304007 ps
CPU time 29.02 seconds
Started May 26 12:41:26 PM PDT 24
Finished May 26 12:41:56 PM PDT 24
Peak memory 212620 kb
Host smart-4d233076-d526-47fe-8e5d-c6b8d326e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480467906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3480467906
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1274166380
Short name T1202
Test name
Test status
Simulation time 1084834199 ps
CPU time 3.14 seconds
Started May 26 12:41:33 PM PDT 24
Finished May 26 12:41:37 PM PDT 24
Peak memory 204448 kb
Host smart-8773193c-1f4f-413a-a2fb-e982b2099ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274166380 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1274166380
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3906981313
Short name T1441
Test name
Test status
Simulation time 10166892557 ps
CPU time 24.92 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:42:02 PM PDT 24
Peak memory 259924 kb
Host smart-febd7698-56d6-473e-8c95-ef865640af70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906981313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3906981313
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2921478803
Short name T89
Test name
Test status
Simulation time 10212244327 ps
CPU time 35.05 seconds
Started May 26 12:41:38 PM PDT 24
Finished May 26 12:42:14 PM PDT 24
Peak memory 373684 kb
Host smart-1352e4ec-9ff9-4cfa-8ca7-dc5942955cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921478803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2921478803
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.1069789110
Short name T1422
Test name
Test status
Simulation time 1248831563 ps
CPU time 4.01 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:41:40 PM PDT 24
Peak memory 204396 kb
Host smart-d76da91c-9d95-4393-9d63-3bb42952f471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069789110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.1069789110
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2412855303
Short name T1281
Test name
Test status
Simulation time 1380217971 ps
CPU time 2.23 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:39 PM PDT 24
Peak memory 204448 kb
Host smart-70fcc230-6ea1-43a3-975f-1feb27a2d2fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412855303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2412855303
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3393127177
Short name T1228
Test name
Test status
Simulation time 2366960539 ps
CPU time 2.11 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:41:38 PM PDT 24
Peak memory 204708 kb
Host smart-be08d1fc-0fd0-4a51-b4fd-e7f02b294c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393127177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3393127177
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2288152282
Short name T562
Test name
Test status
Simulation time 554487039 ps
CPU time 3.12 seconds
Started May 26 12:41:38 PM PDT 24
Finished May 26 12:41:42 PM PDT 24
Peak memory 204412 kb
Host smart-c32c8864-e9ed-4c54-bb35-e54a38cae5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288152282 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2288152282
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1593056278
Short name T994
Test name
Test status
Simulation time 27793011774 ps
CPU time 73.2 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 1519992 kb
Host smart-e938c529-980f-424c-980d-853159161877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593056278 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1593056278
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.273355974
Short name T830
Test name
Test status
Simulation time 7711506998 ps
CPU time 12.09 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:49 PM PDT 24
Peak memory 204512 kb
Host smart-d46c5e33-edde-4df2-85dd-ad5379b185c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273355974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.273355974
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2326106998
Short name T1420
Test name
Test status
Simulation time 2668059264 ps
CPU time 47.82 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:42:24 PM PDT 24
Peak memory 205272 kb
Host smart-47e14a65-4e10-466b-81e7-74e67de2099f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326106998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2326106998
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2387784080
Short name T16
Test name
Test status
Simulation time 53579122133 ps
CPU time 1401.22 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 01:04:57 PM PDT 24
Peak memory 8557564 kb
Host smart-dd2461eb-717f-4ae0-8ecd-35318a04c662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387784080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2387784080
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.206733933
Short name T1084
Test name
Test status
Simulation time 32582627368 ps
CPU time 147.31 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:44:03 PM PDT 24
Peak memory 1492196 kb
Host smart-eeaad53b-8d9c-4a8b-aaee-0b7db8890f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206733933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.206733933
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.4232765672
Short name T1159
Test name
Test status
Simulation time 1387353361 ps
CPU time 8.62 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:41:44 PM PDT 24
Peak memory 220832 kb
Host smart-8268bf70-e53c-4755-b374-e545f7081683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232765672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.4232765672
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2542472507
Short name T868
Test name
Test status
Simulation time 26253120 ps
CPU time 0.63 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 204072 kb
Host smart-3f648dab-3d9a-4952-90c3-608924bb07c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542472507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2542472507
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.778308493
Short name T376
Test name
Test status
Simulation time 1343767138 ps
CPU time 1.95 seconds
Started May 26 12:43:04 PM PDT 24
Finished May 26 12:43:07 PM PDT 24
Peak memory 213772 kb
Host smart-4580391b-e652-4859-aca7-0b13197a9c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778308493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.778308493
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3497790693
Short name T642
Test name
Test status
Simulation time 320533026 ps
CPU time 6.16 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:13 PM PDT 24
Peak memory 243476 kb
Host smart-736d7e7c-55bc-44c1-aec9-4e368b21794f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497790693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3497790693
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2936675661
Short name T480
Test name
Test status
Simulation time 2554862511 ps
CPU time 30.6 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:36 PM PDT 24
Peak memory 402336 kb
Host smart-714a84af-d784-4a63-ba02-b31ecd47956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936675661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2936675661
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3609069033
Short name T160
Test name
Test status
Simulation time 3788141928 ps
CPU time 61.88 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:44:08 PM PDT 24
Peak memory 609492 kb
Host smart-f559d4ce-14cb-4cf5-9ddd-e875413cf333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609069033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3609069033
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3028749034
Short name T867
Test name
Test status
Simulation time 103861914 ps
CPU time 1.06 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:07 PM PDT 24
Peak memory 204456 kb
Host smart-5e97e849-fde9-4451-a385-0c9ac96e8884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028749034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3028749034
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.625189791
Short name T1400
Test name
Test status
Simulation time 796841952 ps
CPU time 7.95 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 204496 kb
Host smart-9320672a-a515-4e17-a43a-0be139548a79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625189791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
625189791
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1940428118
Short name T956
Test name
Test status
Simulation time 13074686617 ps
CPU time 92.39 seconds
Started May 26 12:43:04 PM PDT 24
Finished May 26 12:44:37 PM PDT 24
Peak memory 951332 kb
Host smart-43ca47d6-35c9-43dd-ae99-363d6fac4e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940428118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1940428118
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1352191505
Short name T186
Test name
Test status
Simulation time 321015800 ps
CPU time 4.07 seconds
Started May 26 12:43:14 PM PDT 24
Finished May 26 12:43:18 PM PDT 24
Peak memory 204444 kb
Host smart-c1621d03-d634-4922-8a73-d0aa83225333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352191505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1352191505
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.3156266619
Short name T901
Test name
Test status
Simulation time 41767510 ps
CPU time 0.64 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:08 PM PDT 24
Peak memory 204160 kb
Host smart-bb3aec30-3722-4070-9cda-eb6d72341f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156266619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3156266619
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.151794771
Short name T505
Test name
Test status
Simulation time 7516129091 ps
CPU time 550.73 seconds
Started May 26 12:43:04 PM PDT 24
Finished May 26 12:52:15 PM PDT 24
Peak memory 1346092 kb
Host smart-b8d9326c-a88f-466f-9181-e61839ac4c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151794771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.151794771
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.508903109
Short name T382
Test name
Test status
Simulation time 1389565506 ps
CPU time 25.43 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:31 PM PDT 24
Peak memory 414912 kb
Host smart-294de8a6-9e9f-4a13-b3fd-9aea13c46406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508903109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.508903109
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.4102575748
Short name T123
Test name
Test status
Simulation time 184990128088 ps
CPU time 227.44 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:46:52 PM PDT 24
Peak memory 890068 kb
Host smart-e35f4a57-c5ad-4eb8-837d-c06ab334828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102575748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.4102575748
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2641425504
Short name T1416
Test name
Test status
Simulation time 10563714107 ps
CPU time 9.71 seconds
Started May 26 12:43:12 PM PDT 24
Finished May 26 12:43:22 PM PDT 24
Peak memory 222724 kb
Host smart-65bbffaa-9020-4259-9055-5e66bf75cb42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641425504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2641425504
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3687257326
Short name T516
Test name
Test status
Simulation time 10747251171 ps
CPU time 8.01 seconds
Started May 26 12:43:15 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 247532 kb
Host smart-00136e57-7566-43d1-8caa-740dedbcc992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687257326 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3687257326
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3971172405
Short name T860
Test name
Test status
Simulation time 1877919574 ps
CPU time 1.33 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 204332 kb
Host smart-5a766952-c1cd-4b31-ade4-ec3718f28e15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971172405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3971172405
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2492121231
Short name T1330
Test name
Test status
Simulation time 1212691863 ps
CPU time 2.28 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:43:26 PM PDT 24
Peak memory 204416 kb
Host smart-a0c92970-89fb-4b71-bf1b-9cd692ab06cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492121231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2492121231
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2135824014
Short name T1310
Test name
Test status
Simulation time 779720618 ps
CPU time 2.53 seconds
Started May 26 12:43:14 PM PDT 24
Finished May 26 12:43:17 PM PDT 24
Peak memory 204568 kb
Host smart-11d708d1-1e64-4f5e-ad39-c7b63fe5e9be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135824014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2135824014
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3615463170
Short name T389
Test name
Test status
Simulation time 3063982441 ps
CPU time 4.35 seconds
Started May 26 12:43:15 PM PDT 24
Finished May 26 12:43:20 PM PDT 24
Peak memory 205028 kb
Host smart-c2f4dd59-6da2-4ade-a37e-20be71dcc800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615463170 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3615463170
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1585698706
Short name T1114
Test name
Test status
Simulation time 5691757656 ps
CPU time 53.54 seconds
Started May 26 12:43:13 PM PDT 24
Finished May 26 12:44:07 PM PDT 24
Peak memory 1477548 kb
Host smart-33cbe527-2bde-447d-8bbc-f66cc3a28f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585698706 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1585698706
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1399592056
Short name T1102
Test name
Test status
Simulation time 3756375420 ps
CPU time 13.65 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:20 PM PDT 24
Peak memory 204484 kb
Host smart-a3960bb8-efe6-4ffb-9a94-0f1d65c747c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399592056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1399592056
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3782838937
Short name T1062
Test name
Test status
Simulation time 3535451170 ps
CPU time 17.66 seconds
Started May 26 12:43:06 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 211964 kb
Host smart-5a9b2907-55cc-4c3f-9499-7c3d396e8626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782838937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3782838937
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2041357662
Short name T1072
Test name
Test status
Simulation time 55602716715 ps
CPU time 542.36 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:52:09 PM PDT 24
Peak memory 4665348 kb
Host smart-a1124d18-e148-4326-ac00-91f0e0669e14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041357662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2041357662
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3177460404
Short name T801
Test name
Test status
Simulation time 12092466883 ps
CPU time 529.72 seconds
Started May 26 12:43:15 PM PDT 24
Finished May 26 12:52:06 PM PDT 24
Peak memory 2933596 kb
Host smart-0bc1a89d-5cc7-40bb-a9d0-dc7faf70a449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177460404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3177460404
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2939318670
Short name T925
Test name
Test status
Simulation time 1300040231 ps
CPU time 7.01 seconds
Started May 26 12:43:15 PM PDT 24
Finished May 26 12:43:23 PM PDT 24
Peak memory 212688 kb
Host smart-5317423d-8b10-422b-938d-8afb8d6dc38e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939318670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2939318670
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.583594338
Short name T567
Test name
Test status
Simulation time 19310595 ps
CPU time 0.65 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:43:34 PM PDT 24
Peak memory 204052 kb
Host smart-621509e6-86ad-459b-9149-167d3c3284ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583594338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.583594338
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3341202528
Short name T895
Test name
Test status
Simulation time 197446177 ps
CPU time 2.67 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:43:27 PM PDT 24
Peak memory 212848 kb
Host smart-7adc704b-617d-4e43-b9ea-c177f7b8e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341202528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3341202528
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.212745319
Short name T906
Test name
Test status
Simulation time 318445292 ps
CPU time 16.27 seconds
Started May 26 12:43:21 PM PDT 24
Finished May 26 12:43:38 PM PDT 24
Peak memory 269036 kb
Host smart-e78ebb59-0f60-4df5-afa9-b89be32fe85e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212745319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.212745319
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1863675162
Short name T463
Test name
Test status
Simulation time 1818007531 ps
CPU time 137.69 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:45:42 PM PDT 24
Peak memory 653392 kb
Host smart-5b6820ab-ad00-4971-976b-d12bcacdaede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863675162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1863675162
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1156615291
Short name T1078
Test name
Test status
Simulation time 17441061595 ps
CPU time 193.24 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:46:36 PM PDT 24
Peak memory 754664 kb
Host smart-daa0b55d-2f24-4cf1-9e13-722572aa7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156615291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1156615291
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.4281854998
Short name T1439
Test name
Test status
Simulation time 116694293 ps
CPU time 1.05 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:43:25 PM PDT 24
Peak memory 204204 kb
Host smart-1b903031-d9ed-4891-b945-4d04c80b6171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281854998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.4281854998
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.750789026
Short name T717
Test name
Test status
Simulation time 1191598909 ps
CPU time 4.77 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:43:29 PM PDT 24
Peak memory 236892 kb
Host smart-d5449966-ac71-44a3-8651-78ff9a7de5b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750789026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
750789026
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.285619018
Short name T837
Test name
Test status
Simulation time 6387572935 ps
CPU time 217.74 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:47:01 PM PDT 24
Peak memory 965504 kb
Host smart-729b290f-c826-498d-bd09-ad386bda64cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285619018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.285619018
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3102489849
Short name T587
Test name
Test status
Simulation time 9691115418 ps
CPU time 25.16 seconds
Started May 26 12:43:31 PM PDT 24
Finished May 26 12:43:57 PM PDT 24
Peak memory 323980 kb
Host smart-37c3aaca-cec7-41d0-9deb-ebefa526b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102489849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3102489849
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2491355092
Short name T136
Test name
Test status
Simulation time 85796012 ps
CPU time 0.65 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 204244 kb
Host smart-9395790d-6242-43e1-b035-14ff92e74cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491355092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2491355092
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2538610572
Short name T685
Test name
Test status
Simulation time 28754368934 ps
CPU time 729.46 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:55:32 PM PDT 24
Peak memory 2519032 kb
Host smart-74f6a255-1e48-4a39-b816-415f3ca91d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538610572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2538610572
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2521215483
Short name T308
Test name
Test status
Simulation time 20739201950 ps
CPU time 46.91 seconds
Started May 26 12:43:21 PM PDT 24
Finished May 26 12:44:09 PM PDT 24
Peak memory 406212 kb
Host smart-c8ad41d3-3949-46db-8de6-b719bc228e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521215483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2521215483
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.4161510922
Short name T1
Test name
Test status
Simulation time 1289752780 ps
CPU time 30.95 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:43:54 PM PDT 24
Peak memory 212768 kb
Host smart-3fe614ba-ebee-48d0-9cb9-8d7b00473336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161510922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4161510922
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2195171611
Short name T344
Test name
Test status
Simulation time 10856835637 ps
CPU time 5.06 seconds
Started May 26 12:43:31 PM PDT 24
Finished May 26 12:43:37 PM PDT 24
Peak memory 212768 kb
Host smart-ec95543a-dc4f-49e8-ba62-efae20f25853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195171611 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2195171611
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3723462231
Short name T227
Test name
Test status
Simulation time 10273643460 ps
CPU time 28.41 seconds
Started May 26 12:43:36 PM PDT 24
Finished May 26 12:44:05 PM PDT 24
Peak memory 294696 kb
Host smart-47cc4522-bbd6-4b6b-896d-9d4346d542fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723462231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3723462231
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1555229462
Short name T88
Test name
Test status
Simulation time 10368412184 ps
CPU time 19.02 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:43:53 PM PDT 24
Peak memory 356416 kb
Host smart-8cfedcb2-5e1c-441a-b9d9-e6781596b807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555229462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1555229462
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.1211842386
Short name T318
Test name
Test status
Simulation time 2292228991 ps
CPU time 3.19 seconds
Started May 26 12:43:31 PM PDT 24
Finished May 26 12:43:34 PM PDT 24
Peak memory 204652 kb
Host smart-69f4ed00-d233-483b-a054-f5e0be5a30fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211842386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.1211842386
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2781964559
Short name T366
Test name
Test status
Simulation time 1134470436 ps
CPU time 5.83 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:43:39 PM PDT 24
Peak memory 204380 kb
Host smart-eccfa9e1-5bb0-499c-9319-dc91e8cf4449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781964559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2781964559
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2675999157
Short name T19
Test name
Test status
Simulation time 1350516658 ps
CPU time 1.78 seconds
Started May 26 12:43:38 PM PDT 24
Finished May 26 12:43:40 PM PDT 24
Peak memory 204576 kb
Host smart-18fad2bf-bc18-4770-bef6-6d6a5bd3dcb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675999157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2675999157
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1562992897
Short name T434
Test name
Test status
Simulation time 4536949680 ps
CPU time 5.93 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:43:39 PM PDT 24
Peak memory 212752 kb
Host smart-ae5c131b-5bf8-42b4-bc71-ce72e50eae2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562992897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1562992897
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1662168362
Short name T1199
Test name
Test status
Simulation time 13757228686 ps
CPU time 53.69 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:44:27 PM PDT 24
Peak memory 975224 kb
Host smart-9e0bd97e-a876-4f45-bcae-29e138b668e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662168362 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1662168362
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.412407504
Short name T455
Test name
Test status
Simulation time 1259269723 ps
CPU time 5.04 seconds
Started May 26 12:43:22 PM PDT 24
Finished May 26 12:43:28 PM PDT 24
Peak memory 204432 kb
Host smart-92ac57eb-ba36-4ae9-8191-7570f2ffa60e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412407504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.412407504
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1904615306
Short name T1165
Test name
Test status
Simulation time 1162811274 ps
CPU time 10.79 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:43:44 PM PDT 24
Peak memory 204452 kb
Host smart-a58f630e-b40e-43f6-8311-62ef4ef4a3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904615306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1904615306
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2883690012
Short name T1269
Test name
Test status
Simulation time 65230774534 ps
CPU time 82.3 seconds
Started May 26 12:43:23 PM PDT 24
Finished May 26 12:44:46 PM PDT 24
Peak memory 1124888 kb
Host smart-b61a0a02-dbd7-496c-8d40-f7208cbc5dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883690012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2883690012
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1703363705
Short name T664
Test name
Test status
Simulation time 21064530623 ps
CPU time 1080.54 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 01:01:35 PM PDT 24
Peak memory 4223192 kb
Host smart-29121b8b-6a3a-4d43-9c09-4b624d757111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703363705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1703363705
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1846880830
Short name T1019
Test name
Test status
Simulation time 5946483347 ps
CPU time 7.46 seconds
Started May 26 12:43:37 PM PDT 24
Finished May 26 12:43:45 PM PDT 24
Peak memory 219752 kb
Host smart-6f3f3874-65c1-4efc-9c00-31ea51abb637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846880830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1846880830
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.658403916
Short name T1411
Test name
Test status
Simulation time 16199991 ps
CPU time 0.63 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:43 PM PDT 24
Peak memory 204072 kb
Host smart-7192df3a-0bfb-46c9-bfd3-a3ff95ecee0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658403916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.658403916
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2253992894
Short name T706
Test name
Test status
Simulation time 247152747 ps
CPU time 4.56 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:43:38 PM PDT 24
Peak memory 222636 kb
Host smart-ede35cb1-8322-4157-9d5e-2fdf4cdfed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253992894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2253992894
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1434460106
Short name T1105
Test name
Test status
Simulation time 1954756231 ps
CPU time 9.85 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:43:43 PM PDT 24
Peak memory 314520 kb
Host smart-70943964-6333-4171-91ba-7f02c2443889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434460106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1434460106
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3024438060
Short name T408
Test name
Test status
Simulation time 12192434718 ps
CPU time 107.42 seconds
Started May 26 12:43:31 PM PDT 24
Finished May 26 12:45:19 PM PDT 24
Peak memory 556916 kb
Host smart-da6759e9-7833-4b5b-91d0-b20abaa0d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024438060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3024438060
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4118737193
Short name T1221
Test name
Test status
Simulation time 3102461408 ps
CPU time 93.68 seconds
Started May 26 12:43:37 PM PDT 24
Finished May 26 12:45:11 PM PDT 24
Peak memory 854376 kb
Host smart-ff23dfc2-80d3-480e-886f-1d73f88ae675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118737193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4118737193
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.622132891
Short name T755
Test name
Test status
Simulation time 147888118 ps
CPU time 0.8 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:43:34 PM PDT 24
Peak memory 204240 kb
Host smart-dd28a222-d309-4176-b269-5c9014921922
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622132891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.622132891
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2990756821
Short name T1296
Test name
Test status
Simulation time 365444232 ps
CPU time 5.02 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:43:39 PM PDT 24
Peak memory 237488 kb
Host smart-9c446912-eff3-4992-83dd-f852365e16e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990756821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2990756821
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.4114246613
Short name T582
Test name
Test status
Simulation time 4602029163 ps
CPU time 159.12 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 12:46:12 PM PDT 24
Peak memory 1346968 kb
Host smart-69e3b144-1952-4423-a1a4-4395d80eefc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114246613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.4114246613
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1214518640
Short name T1043
Test name
Test status
Simulation time 767024540 ps
CPU time 24 seconds
Started May 26 12:43:40 PM PDT 24
Finished May 26 12:44:04 PM PDT 24
Peak memory 204464 kb
Host smart-c4b011df-8cbc-4bcb-abc2-97eeb184c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214518640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1214518640
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1919233323
Short name T35
Test name
Test status
Simulation time 17921360110 ps
CPU time 31.71 seconds
Started May 26 12:43:41 PM PDT 24
Finished May 26 12:44:13 PM PDT 24
Peak memory 277676 kb
Host smart-374bbf84-f20e-4413-a58f-bdccda2b7088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919233323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1919233323
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1085002867
Short name T1129
Test name
Test status
Simulation time 30988032 ps
CPU time 0.69 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:43:35 PM PDT 24
Peak memory 204232 kb
Host smart-87d74582-b1ab-490e-bf74-c19e131b763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085002867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1085002867
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.650632402
Short name T1147
Test name
Test status
Simulation time 27976302380 ps
CPU time 1744.04 seconds
Started May 26 12:43:32 PM PDT 24
Finished May 26 01:12:37 PM PDT 24
Peak memory 2667236 kb
Host smart-cff006ed-85bb-426a-b9b6-f0e29a5cf141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650632402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.650632402
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1273219958
Short name T1044
Test name
Test status
Simulation time 1676795708 ps
CPU time 80.01 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:44:54 PM PDT 24
Peak memory 280836 kb
Host smart-deb29e14-0d80-49be-897a-63e7734c5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273219958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1273219958
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.126033275
Short name T266
Test name
Test status
Simulation time 22380128973 ps
CPU time 302.55 seconds
Started May 26 12:43:33 PM PDT 24
Finished May 26 12:48:37 PM PDT 24
Peak memory 972460 kb
Host smart-d8989a30-e046-4377-8200-bb7d73c3813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126033275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.126033275
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1986436270
Short name T838
Test name
Test status
Simulation time 1935848941 ps
CPU time 23.14 seconds
Started May 26 12:43:36 PM PDT 24
Finished May 26 12:43:59 PM PDT 24
Peak memory 212600 kb
Host smart-96d0dbaa-dd1a-437b-a0d0-8f3db289603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986436270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1986436270
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2600483209
Short name T597
Test name
Test status
Simulation time 590262729 ps
CPU time 3.1 seconds
Started May 26 12:43:43 PM PDT 24
Finished May 26 12:43:46 PM PDT 24
Peak memory 204556 kb
Host smart-cbfb2b76-8361-4e32-883b-92d58e0d7374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600483209 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2600483209
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.94426737
Short name T686
Test name
Test status
Simulation time 10211008077 ps
CPU time 8.49 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:51 PM PDT 24
Peak memory 226628 kb
Host smart-b32334e6-452c-494d-8021-172caa9a43b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94426737 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_acq.94426737
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4126437704
Short name T1283
Test name
Test status
Simulation time 10129124090 ps
CPU time 68.18 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:44:50 PM PDT 24
Peak memory 460364 kb
Host smart-9d0ba5a2-330d-404a-9fd2-a3b844dbc46c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126437704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4126437704
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.188426164
Short name T274
Test name
Test status
Simulation time 1100052396 ps
CPU time 5.92 seconds
Started May 26 12:43:45 PM PDT 24
Finished May 26 12:43:52 PM PDT 24
Peak memory 204520 kb
Host smart-634c4ba5-6df5-43af-8012-26a947e63a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188426164 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.188426164
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3511223798
Short name T458
Test name
Test status
Simulation time 3100843375 ps
CPU time 2.66 seconds
Started May 26 12:43:40 PM PDT 24
Finished May 26 12:43:43 PM PDT 24
Peak memory 204556 kb
Host smart-06762ece-bf09-4bef-a332-396d2e6cde5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511223798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3511223798
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2200904224
Short name T1013
Test name
Test status
Simulation time 1320501246 ps
CPU time 6.73 seconds
Started May 26 12:43:39 PM PDT 24
Finished May 26 12:43:46 PM PDT 24
Peak memory 210224 kb
Host smart-5a354cf9-ac3b-4ccd-baab-487b2431aa43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200904224 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2200904224
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3655606583
Short name T1326
Test name
Test status
Simulation time 7699392596 ps
CPU time 3.84 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:47 PM PDT 24
Peak memory 204532 kb
Host smart-f7952cd5-d80d-4f59-9abb-14ce27706331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655606583 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3655606583
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2941571767
Short name T998
Test name
Test status
Simulation time 5761905354 ps
CPU time 47.91 seconds
Started May 26 12:43:39 PM PDT 24
Finished May 26 12:44:27 PM PDT 24
Peak memory 204480 kb
Host smart-4a046e5b-cc5d-40b6-8cd8-2c332cc8a6b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941571767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2941571767
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3688755340
Short name T1277
Test name
Test status
Simulation time 3031901005 ps
CPU time 11.95 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:55 PM PDT 24
Peak memory 208360 kb
Host smart-b4d1d9f5-a5e3-4242-acc8-c533a003a45f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688755340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3688755340
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1063409785
Short name T285
Test name
Test status
Simulation time 17477179787 ps
CPU time 9.57 seconds
Started May 26 12:43:41 PM PDT 24
Finished May 26 12:43:51 PM PDT 24
Peak memory 204496 kb
Host smart-f58795ca-de6d-4a09-88a3-0f504d60f637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063409785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1063409785
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.713229686
Short name T1399
Test name
Test status
Simulation time 13989635352 ps
CPU time 40.54 seconds
Started May 26 12:43:45 PM PDT 24
Finished May 26 12:44:26 PM PDT 24
Peak memory 540040 kb
Host smart-6492653f-5c3e-43e7-964a-81a330c902e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713229686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.713229686
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1219833007
Short name T655
Test name
Test status
Simulation time 5630516517 ps
CPU time 7.76 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:43:50 PM PDT 24
Peak memory 212748 kb
Host smart-2bc111f5-1fb4-4077-be15-b9819b3293e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219833007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1219833007
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.460494831
Short name T1387
Test name
Test status
Simulation time 22973644 ps
CPU time 0.61 seconds
Started May 26 12:44:00 PM PDT 24
Finished May 26 12:44:01 PM PDT 24
Peak memory 204148 kb
Host smart-d7ac5612-6d61-4084-a75d-1b2c44b29e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460494831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.460494831
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2080610720
Short name T736
Test name
Test status
Simulation time 935537308 ps
CPU time 4.52 seconds
Started May 26 12:43:47 PM PDT 24
Finished May 26 12:43:52 PM PDT 24
Peak memory 212716 kb
Host smart-f4b3693a-6f9e-430a-ae87-b153bcd3fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080610720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2080610720
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1787447184
Short name T1095
Test name
Test status
Simulation time 534478217 ps
CPU time 5.7 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:43:55 PM PDT 24
Peak memory 267480 kb
Host smart-38803c43-8d8f-45d1-9617-73039586bd4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787447184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1787447184
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.4107642349
Short name T1317
Test name
Test status
Simulation time 31697799912 ps
CPU time 46.68 seconds
Started May 26 12:43:49 PM PDT 24
Finished May 26 12:44:37 PM PDT 24
Peak memory 597588 kb
Host smart-9869c42e-838d-419e-8f2c-50680edbe362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107642349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.4107642349
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3194484524
Short name T437
Test name
Test status
Simulation time 1829390644 ps
CPU time 102.05 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:45:25 PM PDT 24
Peak memory 515808 kb
Host smart-c704e11f-e2a6-47a1-a38c-be19ff494a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194484524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3194484524
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2976171555
Short name T145
Test name
Test status
Simulation time 249398819 ps
CPU time 0.98 seconds
Started May 26 12:43:45 PM PDT 24
Finished May 26 12:43:46 PM PDT 24
Peak memory 204320 kb
Host smart-19d7d612-58bb-49d7-84cf-f2b176ca6218
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976171555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2976171555
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3436383683
Short name T526
Test name
Test status
Simulation time 590657118 ps
CPU time 9.73 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:43:58 PM PDT 24
Peak memory 234880 kb
Host smart-f8937962-1b6f-451f-a7a8-4c79a89a761a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436383683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3436383683
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1199120079
Short name T684
Test name
Test status
Simulation time 5705614684 ps
CPU time 200.91 seconds
Started May 26 12:43:40 PM PDT 24
Finished May 26 12:47:01 PM PDT 24
Peak memory 912476 kb
Host smart-96f4e7e4-1310-44ab-9b5b-9ad975906bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199120079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1199120079
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3031036434
Short name T1270
Test name
Test status
Simulation time 549496249 ps
CPU time 6.46 seconds
Started May 26 12:44:02 PM PDT 24
Finished May 26 12:44:09 PM PDT 24
Peak memory 204524 kb
Host smart-d19f8a16-c069-49c0-951c-deb4886bba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031036434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3031036434
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2083132666
Short name T728
Test name
Test status
Simulation time 2471504930 ps
CPU time 125.69 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:46:04 PM PDT 24
Peak memory 461224 kb
Host smart-6c0fff59-d1be-4199-86fb-8b07ae3456ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083132666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2083132666
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2576476438
Short name T385
Test name
Test status
Simulation time 16302384 ps
CPU time 0.62 seconds
Started May 26 12:43:41 PM PDT 24
Finished May 26 12:43:42 PM PDT 24
Peak memory 204112 kb
Host smart-627eba2d-a9ff-4303-8c51-78cceb4a4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576476438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2576476438
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2282858204
Short name T790
Test name
Test status
Simulation time 1480319897 ps
CPU time 18.29 seconds
Started May 26 12:43:55 PM PDT 24
Finished May 26 12:44:14 PM PDT 24
Peak memory 280664 kb
Host smart-6547c4eb-a819-426f-8485-b011a3b01ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282858204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2282858204
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1441181279
Short name T916
Test name
Test status
Simulation time 8773540300 ps
CPU time 36.4 seconds
Started May 26 12:43:42 PM PDT 24
Finished May 26 12:44:20 PM PDT 24
Peak memory 353832 kb
Host smart-cfd69d0a-5360-4908-98c7-44bd159fd920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441181279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1441181279
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3227060822
Short name T256
Test name
Test status
Simulation time 1764873168 ps
CPU time 20.11 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:44:09 PM PDT 24
Peak memory 212656 kb
Host smart-44ed7d72-cfb6-45cd-aeb7-76d7d2381276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227060822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3227060822
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3152131430
Short name T329
Test name
Test status
Simulation time 1456955714 ps
CPU time 4.38 seconds
Started May 26 12:43:53 PM PDT 24
Finished May 26 12:43:58 PM PDT 24
Peak memory 212688 kb
Host smart-d0359821-626f-4617-ac78-873657d154e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152131430 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3152131430
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.941807789
Short name T452
Test name
Test status
Simulation time 10267456053 ps
CPU time 7.81 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:44:05 PM PDT 24
Peak memory 228288 kb
Host smart-2f138f5d-3931-4c16-8716-e1e8f090069c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941807789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.941807789
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.555206535
Short name T1264
Test name
Test status
Simulation time 10207913388 ps
CPU time 14.32 seconds
Started May 26 12:43:50 PM PDT 24
Finished May 26 12:44:06 PM PDT 24
Peak memory 305524 kb
Host smart-b33cad8f-1ee1-430b-a070-4d514666407e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555206535 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.555206535
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3248855697
Short name T1086
Test name
Test status
Simulation time 2288885217 ps
CPU time 2.65 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:44:02 PM PDT 24
Peak memory 204440 kb
Host smart-75504de7-2dde-4fbd-87be-e95325baec78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248855697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3248855697
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.1750836524
Short name T746
Test name
Test status
Simulation time 1494391576 ps
CPU time 1.61 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:00 PM PDT 24
Peak memory 204564 kb
Host smart-387bd1e3-517b-485e-af39-ffa87abd85fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750836524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.1750836524
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1354497824
Short name T991
Test name
Test status
Simulation time 658407808 ps
CPU time 2.38 seconds
Started May 26 12:43:49 PM PDT 24
Finished May 26 12:43:54 PM PDT 24
Peak memory 204544 kb
Host smart-9617450b-3c8d-4616-898b-f8bcdf7f5320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354497824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1354497824
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.728495080
Short name T397
Test name
Test status
Simulation time 1701198496 ps
CPU time 5.14 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:43:54 PM PDT 24
Peak memory 215280 kb
Host smart-723c935c-d97b-485d-8fe4-64e650297a37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728495080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.728495080
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2524369411
Short name T1408
Test name
Test status
Simulation time 5311378011 ps
CPU time 21.18 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:44:10 PM PDT 24
Peak memory 785344 kb
Host smart-c8a1718e-7c50-4cab-904f-0bf30b24061d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524369411 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2524369411
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1805564246
Short name T1090
Test name
Test status
Simulation time 7234047072 ps
CPU time 26.24 seconds
Started May 26 12:43:49 PM PDT 24
Finished May 26 12:44:16 PM PDT 24
Peak memory 204552 kb
Host smart-88f01087-8c38-495a-b5dc-d60bf9b10e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805564246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1805564246
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.674817390
Short name T957
Test name
Test status
Simulation time 25637823903 ps
CPU time 38.59 seconds
Started May 26 12:43:49 PM PDT 24
Finished May 26 12:44:30 PM PDT 24
Peak memory 232088 kb
Host smart-9f22cadd-0df5-49c2-a06e-f4573ecbff44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674817390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.674817390
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2221958783
Short name T681
Test name
Test status
Simulation time 39216205074 ps
CPU time 435.54 seconds
Started May 26 12:43:48 PM PDT 24
Finished May 26 12:51:04 PM PDT 24
Peak memory 4244572 kb
Host smart-f8820614-bc41-4f01-aac9-9e26f7db2256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221958783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2221958783
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1824021891
Short name T781
Test name
Test status
Simulation time 8288712241 ps
CPU time 14.73 seconds
Started May 26 12:43:50 PM PDT 24
Finished May 26 12:44:06 PM PDT 24
Peak memory 321060 kb
Host smart-6bc9512b-1fb8-4465-954c-7891b9605853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824021891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1824021891
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.203133723
Short name T182
Test name
Test status
Simulation time 5517628117 ps
CPU time 7.93 seconds
Started May 26 12:43:54 PM PDT 24
Finished May 26 12:44:02 PM PDT 24
Peak memory 212736 kb
Host smart-a4de3d24-7b63-4366-b471-e6c1b200be6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203133723 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.203133723
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.1478748056
Short name T568
Test name
Test status
Simulation time 16177047 ps
CPU time 0.62 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:44:10 PM PDT 24
Peak memory 204160 kb
Host smart-8f482bda-07b7-404b-aead-74f4bf38db25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478748056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1478748056
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2516834348
Short name T970
Test name
Test status
Simulation time 1281403948 ps
CPU time 4.74 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:44:05 PM PDT 24
Peak memory 228964 kb
Host smart-966118df-3a1b-4649-8771-df8f62c9c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516834348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2516834348
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.194888224
Short name T279
Test name
Test status
Simulation time 152591194 ps
CPU time 7.62 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:07 PM PDT 24
Peak memory 228768 kb
Host smart-5ecb93f9-6be5-4c5d-9b34-51540acbea1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194888224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.194888224
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3110059402
Short name T934
Test name
Test status
Simulation time 9556383178 ps
CPU time 172.37 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:46:51 PM PDT 24
Peak memory 739104 kb
Host smart-b0129a6e-f289-4db9-93de-a9b33057b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110059402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3110059402
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1312929968
Short name T779
Test name
Test status
Simulation time 6681123424 ps
CPU time 73.56 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:45:11 PM PDT 24
Peak memory 692264 kb
Host smart-b924635e-ac81-4889-8449-8cf0b05c7276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312929968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1312929968
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1727205846
Short name T445
Test name
Test status
Simulation time 356969989 ps
CPU time 0.75 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:43:58 PM PDT 24
Peak memory 204220 kb
Host smart-44f385f2-e3ee-46d5-887a-44699c6de48a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727205846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1727205846
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.946687399
Short name T1404
Test name
Test status
Simulation time 1596854304 ps
CPU time 6.33 seconds
Started May 26 12:43:56 PM PDT 24
Finished May 26 12:44:03 PM PDT 24
Peak memory 248296 kb
Host smart-fb5ffa27-76f7-46bc-9d82-3e3d06730fe5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946687399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
946687399
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1378721707
Short name T678
Test name
Test status
Simulation time 5921279629 ps
CPU time 142.67 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:46:21 PM PDT 24
Peak memory 1500824 kb
Host smart-7c391cec-89a4-48c7-afb7-470e3c51d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378721707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1378721707
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2534375995
Short name T683
Test name
Test status
Simulation time 1635822341 ps
CPU time 6.33 seconds
Started May 26 12:44:07 PM PDT 24
Finished May 26 12:44:14 PM PDT 24
Peak memory 204492 kb
Host smart-44d44ab1-1ffd-412f-8e45-fae13b7905f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534375995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2534375995
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3469643220
Short name T576
Test name
Test status
Simulation time 4069896917 ps
CPU time 32.38 seconds
Started May 26 12:44:07 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 310532 kb
Host smart-3df3e1a1-9d62-4661-9568-13496cb5d2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469643220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3469643220
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3259277341
Short name T400
Test name
Test status
Simulation time 75392107 ps
CPU time 0.67 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:43:59 PM PDT 24
Peak memory 204156 kb
Host smart-3e36f2b2-4094-44b7-b2b2-b889079a5157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259277341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3259277341
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1608071857
Short name T1003
Test name
Test status
Simulation time 48721656846 ps
CPU time 1502.22 seconds
Started May 26 12:43:56 PM PDT 24
Finished May 26 01:08:59 PM PDT 24
Peak memory 212784 kb
Host smart-7983833d-ce0c-4407-8b0b-de23245427f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608071857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1608071857
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3791324802
Short name T550
Test name
Test status
Simulation time 1075772825 ps
CPU time 56.16 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:55 PM PDT 24
Peak memory 350112 kb
Host smart-db4b532f-bffb-480a-920d-6ee8d62a5069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791324802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3791324802
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2339901721
Short name T119
Test name
Test status
Simulation time 32083744445 ps
CPU time 261.66 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:48:21 PM PDT 24
Peak memory 1289472 kb
Host smart-bb2aa99f-040c-4237-87b9-d63eda4157c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339901721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2339901721
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.517877308
Short name T6
Test name
Test status
Simulation time 2691571154 ps
CPU time 31.27 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:44:31 PM PDT 24
Peak memory 213004 kb
Host smart-fccd1358-6d51-43d3-b269-644018df5079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517877308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.517877308
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1260894905
Short name T630
Test name
Test status
Simulation time 1074009568 ps
CPU time 5.51 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:44:15 PM PDT 24
Peak memory 212748 kb
Host smart-a9b84d41-6b48-4931-9b90-ab891a484857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260894905 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1260894905
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2264074210
Short name T766
Test name
Test status
Simulation time 10136597222 ps
CPU time 45.39 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:44:45 PM PDT 24
Peak memory 343260 kb
Host smart-cd067cd5-9b37-47e9-b381-728bf5797881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264074210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2264074210
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2490638795
Short name T390
Test name
Test status
Simulation time 10105040600 ps
CPU time 66.57 seconds
Started May 26 12:43:59 PM PDT 24
Finished May 26 12:45:06 PM PDT 24
Peak memory 595884 kb
Host smart-4d3eaffb-eb6f-4c5c-96f8-e4ad9f30ef2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490638795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2490638795
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.763583111
Short name T1391
Test name
Test status
Simulation time 1575749241 ps
CPU time 5.95 seconds
Started May 26 12:44:09 PM PDT 24
Finished May 26 12:44:15 PM PDT 24
Peak memory 204496 kb
Host smart-e9b3b364-cd01-4f04-a8f9-17f8a66f360b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763583111 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.763583111
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3928258246
Short name T1191
Test name
Test status
Simulation time 1157560478 ps
CPU time 5.37 seconds
Started May 26 12:44:06 PM PDT 24
Finished May 26 12:44:12 PM PDT 24
Peak memory 204508 kb
Host smart-b12c2359-63d4-4269-9ffd-4688b7f00d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928258246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3928258246
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1957541338
Short name T1432
Test name
Test status
Simulation time 455275413 ps
CPU time 2.91 seconds
Started May 26 12:44:10 PM PDT 24
Finished May 26 12:44:14 PM PDT 24
Peak memory 204544 kb
Host smart-358bd3a3-3ff6-4484-9980-d2fb5851a3b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957541338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1957541338
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2076610578
Short name T1401
Test name
Test status
Simulation time 4043704052 ps
CPU time 6.09 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:05 PM PDT 24
Peak memory 218252 kb
Host smart-7a26346e-506c-43ea-adb2-aad40f6918d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076610578 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2076610578
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1501555193
Short name T621
Test name
Test status
Simulation time 10282682150 ps
CPU time 19.91 seconds
Started May 26 12:43:56 PM PDT 24
Finished May 26 12:44:17 PM PDT 24
Peak memory 680992 kb
Host smart-7ba1588a-cf98-4962-b3c4-ae0dd2d27c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501555193 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1501555193
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.435023451
Short name T922
Test name
Test status
Simulation time 664389498 ps
CPU time 26.13 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:25 PM PDT 24
Peak memory 204440 kb
Host smart-96aa3985-2969-49ed-bcba-cfb326e2d216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435023451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.435023451
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2153205119
Short name T976
Test name
Test status
Simulation time 476605220 ps
CPU time 21.07 seconds
Started May 26 12:43:58 PM PDT 24
Finished May 26 12:44:20 PM PDT 24
Peak memory 204484 kb
Host smart-a5ada026-4c32-4427-80a5-33813df0ca74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153205119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2153205119
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2781138298
Short name T1171
Test name
Test status
Simulation time 28491310730 ps
CPU time 157.37 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 2153820 kb
Host smart-d217e6f9-7be0-45b5-bd51-9eb4b39d8c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781138298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2781138298
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2652486104
Short name T703
Test name
Test status
Simulation time 15009169698 ps
CPU time 53.47 seconds
Started May 26 12:43:56 PM PDT 24
Finished May 26 12:44:50 PM PDT 24
Peak memory 278700 kb
Host smart-04cc2cb9-e1df-4830-a119-34ec41d8a5c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652486104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2652486104
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.5604889
Short name T1080
Test name
Test status
Simulation time 4117930089 ps
CPU time 7.6 seconds
Started May 26 12:43:57 PM PDT 24
Finished May 26 12:44:06 PM PDT 24
Peak memory 219540 kb
Host smart-d9f8ed39-c43d-4b09-a3ce-8a0c2c06d558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5604889 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_timeout.5604889
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3008305481
Short name T1338
Test name
Test status
Simulation time 14862951 ps
CPU time 0.64 seconds
Started May 26 12:44:20 PM PDT 24
Finished May 26 12:44:21 PM PDT 24
Peak memory 204088 kb
Host smart-285536eb-565a-48cb-8e06-69a94c2d1a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008305481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3008305481
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1304622591
Short name T614
Test name
Test status
Simulation time 574804654 ps
CPU time 2.31 seconds
Started May 26 12:44:07 PM PDT 24
Finished May 26 12:44:10 PM PDT 24
Peak memory 212756 kb
Host smart-f7c59138-ee61-48c7-9bf7-6f221b494018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304622591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1304622591
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1660693189
Short name T635
Test name
Test status
Simulation time 379318604 ps
CPU time 8.72 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:44:17 PM PDT 24
Peak memory 282196 kb
Host smart-8d93bb8f-b427-435e-8c52-59e814f3bc43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660693189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1660693189
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.670235088
Short name T1203
Test name
Test status
Simulation time 3186791923 ps
CPU time 98.7 seconds
Started May 26 12:44:12 PM PDT 24
Finished May 26 12:45:51 PM PDT 24
Peak memory 497464 kb
Host smart-f7057749-5118-4e59-8c19-2ba62a71d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670235088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.670235088
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2660095237
Short name T1207
Test name
Test status
Simulation time 19347152421 ps
CPU time 73.54 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:45:22 PM PDT 24
Peak memory 580512 kb
Host smart-e7aa8a9f-4a6a-420e-bee6-a5ea75f3df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660095237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2660095237
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2621791474
Short name T760
Test name
Test status
Simulation time 419838927 ps
CPU time 0.97 seconds
Started May 26 12:44:10 PM PDT 24
Finished May 26 12:44:11 PM PDT 24
Peak memory 204328 kb
Host smart-40f601de-35b8-4acc-b4b8-ef4078a58ff1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621791474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2621791474
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1018050110
Short name T1383
Test name
Test status
Simulation time 4559701092 ps
CPU time 368.33 seconds
Started May 26 12:44:06 PM PDT 24
Finished May 26 12:50:15 PM PDT 24
Peak memory 1255124 kb
Host smart-e74ae30b-8ca7-41f3-86be-f3d28124f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018050110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1018050110
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1614687468
Short name T1262
Test name
Test status
Simulation time 1879515089 ps
CPU time 6.23 seconds
Started May 26 12:44:18 PM PDT 24
Finished May 26 12:44:25 PM PDT 24
Peak memory 204388 kb
Host smart-a59a4939-6177-4ad0-86e2-8aaa75c99820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614687468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1614687468
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.321909840
Short name T759
Test name
Test status
Simulation time 3566689417 ps
CPU time 26.41 seconds
Started May 26 12:44:20 PM PDT 24
Finished May 26 12:44:47 PM PDT 24
Peak memory 329672 kb
Host smart-2fc82365-5e3f-4f9a-9136-96fa8a7cc3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321909840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.321909840
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2553702
Short name T722
Test name
Test status
Simulation time 773302899 ps
CPU time 2.61 seconds
Started May 26 12:44:12 PM PDT 24
Finished May 26 12:44:15 PM PDT 24
Peak memory 219204 kb
Host smart-e0f6fdec-08db-496f-abf3-68bd3bb00881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2553702
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2279557409
Short name T808
Test name
Test status
Simulation time 1466888826 ps
CPU time 21.29 seconds
Started May 26 12:44:09 PM PDT 24
Finished May 26 12:44:31 PM PDT 24
Peak memory 299664 kb
Host smart-aa8985ae-9771-4339-b87c-ad109c7a8c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279557409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2279557409
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1417804874
Short name T710
Test name
Test status
Simulation time 499311214 ps
CPU time 8.93 seconds
Started May 26 12:44:10 PM PDT 24
Finished May 26 12:44:19 PM PDT 24
Peak memory 212656 kb
Host smart-93b22c15-73ea-4501-b1d2-014da80e7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417804874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1417804874
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2755974238
Short name T1304
Test name
Test status
Simulation time 674849804 ps
CPU time 3.77 seconds
Started May 26 12:44:21 PM PDT 24
Finished May 26 12:44:25 PM PDT 24
Peak memory 212708 kb
Host smart-68f9a007-0349-4159-b482-4ec19ce36ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755974238 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2755974238
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.551241640
Short name T1240
Test name
Test status
Simulation time 10513068205 ps
CPU time 11.59 seconds
Started May 26 12:44:17 PM PDT 24
Finished May 26 12:44:30 PM PDT 24
Peak memory 245112 kb
Host smart-f7d110e1-9e1f-4c41-b946-63b7f8f8950d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551241640 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.551241640
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2313860444
Short name T438
Test name
Test status
Simulation time 10594427000 ps
CPU time 19.34 seconds
Started May 26 12:44:20 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 348900 kb
Host smart-d44c4407-2781-46ac-b893-ec0629c9ae7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313860444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2313860444
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.321736020
Short name T168
Test name
Test status
Simulation time 1312218187 ps
CPU time 3.81 seconds
Started May 26 12:44:19 PM PDT 24
Finished May 26 12:44:23 PM PDT 24
Peak memory 204380 kb
Host smart-d3c3706d-3845-42a1-8d10-ae16f0cb156e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321736020 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.321736020
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2080355008
Short name T13
Test name
Test status
Simulation time 2232539627 ps
CPU time 3.34 seconds
Started May 26 12:44:16 PM PDT 24
Finished May 26 12:44:21 PM PDT 24
Peak memory 204572 kb
Host smart-0f67420b-1c98-42e5-b863-e8bcfe0952be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080355008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2080355008
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2891821033
Short name T324
Test name
Test status
Simulation time 1347885536 ps
CPU time 6.86 seconds
Started May 26 12:44:18 PM PDT 24
Finished May 26 12:44:26 PM PDT 24
Peak memory 220152 kb
Host smart-6274ffaf-4851-47d1-b909-7e289b342882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891821033 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2891821033
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3716489025
Short name T1002
Test name
Test status
Simulation time 4744423041 ps
CPU time 7.87 seconds
Started May 26 12:44:17 PM PDT 24
Finished May 26 12:44:26 PM PDT 24
Peak memory 417644 kb
Host smart-6e42bfe8-5864-4ecf-8dc3-b60afbd1b3c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716489025 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3716489025
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2513730148
Short name T292
Test name
Test status
Simulation time 4198042684 ps
CPU time 19.03 seconds
Started May 26 12:44:07 PM PDT 24
Finished May 26 12:44:26 PM PDT 24
Peak memory 204664 kb
Host smart-372f5a1d-45e3-4855-b649-74c79601bba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513730148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2513730148
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1845114089
Short name T941
Test name
Test status
Simulation time 4949694967 ps
CPU time 28.43 seconds
Started May 26 12:44:08 PM PDT 24
Finished May 26 12:44:37 PM PDT 24
Peak memory 217020 kb
Host smart-f02564c2-f096-4a73-bb8d-ddabbc188bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845114089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1845114089
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2152229392
Short name T530
Test name
Test status
Simulation time 54456886016 ps
CPU time 154.29 seconds
Started May 26 12:44:09 PM PDT 24
Finished May 26 12:46:44 PM PDT 24
Peak memory 1946512 kb
Host smart-278322cf-60ab-4b58-a2c8-aacb8800535e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152229392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2152229392
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.184203020
Short name T595
Test name
Test status
Simulation time 5140788754 ps
CPU time 26.58 seconds
Started May 26 12:44:12 PM PDT 24
Finished May 26 12:44:39 PM PDT 24
Peak memory 457280 kb
Host smart-214294c4-15c8-44d9-b9e0-438a1ec93b7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184203020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.184203020
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.796691749
Short name T1274
Test name
Test status
Simulation time 5674224960 ps
CPU time 7.18 seconds
Started May 26 12:44:23 PM PDT 24
Finished May 26 12:44:30 PM PDT 24
Peak memory 220784 kb
Host smart-23121af4-f2c1-48f3-8f73-5e5e8d403806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796691749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.796691749
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3819943263
Short name T1355
Test name
Test status
Simulation time 15822601 ps
CPU time 0.63 seconds
Started May 26 12:44:39 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 204156 kb
Host smart-8eb168be-dbd8-43b0-927f-2d57f3d7a52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819943263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3819943263
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1202245824
Short name T910
Test name
Test status
Simulation time 159916980 ps
CPU time 3.34 seconds
Started May 26 12:44:30 PM PDT 24
Finished May 26 12:44:34 PM PDT 24
Peak memory 215780 kb
Host smart-deedac69-f8fb-43ff-8376-5a2755cd7e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202245824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1202245824
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.940348199
Short name T1397
Test name
Test status
Simulation time 418586950 ps
CPU time 4.54 seconds
Started May 26 12:44:28 PM PDT 24
Finished May 26 12:44:33 PM PDT 24
Peak memory 245492 kb
Host smart-c6460e16-76df-4172-a834-176e60f87fb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940348199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.940348199
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.15345892
Short name T1356
Test name
Test status
Simulation time 1330778016 ps
CPU time 95.13 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:46:07 PM PDT 24
Peak memory 531224 kb
Host smart-ca8cf8d6-cc95-48e8-9a92-25bccb4301af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15345892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.15345892
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1186094153
Short name T296
Test name
Test status
Simulation time 10800739782 ps
CPU time 55.26 seconds
Started May 26 12:44:17 PM PDT 24
Finished May 26 12:45:13 PM PDT 24
Peak memory 660876 kb
Host smart-403a4237-b69f-4775-9585-45211ed5d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186094153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1186094153
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1473669046
Short name T751
Test name
Test status
Simulation time 546342027 ps
CPU time 0.84 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:44:33 PM PDT 24
Peak memory 204320 kb
Host smart-5ef0544d-b6d4-4dd8-9b87-6803d1736b1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473669046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1473669046
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3077577108
Short name T658
Test name
Test status
Simulation time 354975051 ps
CPU time 6.06 seconds
Started May 26 12:44:33 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 245648 kb
Host smart-1057901b-8962-4af1-88f8-e1cdbd4c8690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077577108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3077577108
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1373474068
Short name T490
Test name
Test status
Simulation time 14569930020 ps
CPU time 109.25 seconds
Started May 26 12:44:19 PM PDT 24
Finished May 26 12:46:09 PM PDT 24
Peak memory 1018160 kb
Host smart-6496a1cc-e1f0-4ab1-abde-d08eec301f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373474068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1373474068
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.888653171
Short name T474
Test name
Test status
Simulation time 12647368155 ps
CPU time 27.76 seconds
Started May 26 12:44:38 PM PDT 24
Finished May 26 12:45:06 PM PDT 24
Peak memory 204532 kb
Host smart-97bb592c-8287-4289-8203-4371c72fdeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888653171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.888653171
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.2459346500
Short name T138
Test name
Test status
Simulation time 95240466 ps
CPU time 0.67 seconds
Started May 26 12:44:20 PM PDT 24
Finished May 26 12:44:21 PM PDT 24
Peak memory 204156 kb
Host smart-c3dbca87-30fa-42d4-a929-5b0d189a807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459346500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2459346500
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.657505851
Short name T1081
Test name
Test status
Simulation time 49324748755 ps
CPU time 950.08 seconds
Started May 26 12:44:30 PM PDT 24
Finished May 26 01:00:20 PM PDT 24
Peak memory 204552 kb
Host smart-de2b1c71-cc74-469c-b92e-c3c649ddb73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657505851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.657505851
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1281087870
Short name T1403
Test name
Test status
Simulation time 4993065473 ps
CPU time 27.01 seconds
Started May 26 12:44:20 PM PDT 24
Finished May 26 12:44:48 PM PDT 24
Peak memory 397320 kb
Host smart-cec22a2f-a4db-4e91-9ac2-e015f24c940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281087870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1281087870
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2753755634
Short name T419
Test name
Test status
Simulation time 1143264459 ps
CPU time 10.84 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:44:43 PM PDT 24
Peak memory 212728 kb
Host smart-31e0fdd7-c307-406f-9857-6a90fb36b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753755634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2753755634
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2626093843
Short name T181
Test name
Test status
Simulation time 570021656 ps
CPU time 3.27 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:44:35 PM PDT 24
Peak memory 204596 kb
Host smart-7e37f750-c69f-42ef-9d9a-340ebc5ec0a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626093843 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2626093843
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2410052664
Short name T306
Test name
Test status
Simulation time 10112283180 ps
CPU time 12.69 seconds
Started May 26 12:44:27 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 253572 kb
Host smart-af809c44-fcaa-4c05-869f-56aab99093a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410052664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2410052664
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1393290215
Short name T1389
Test name
Test status
Simulation time 10164947833 ps
CPU time 65 seconds
Started May 26 12:44:30 PM PDT 24
Finished May 26 12:45:35 PM PDT 24
Peak memory 587740 kb
Host smart-af7d471b-0520-400c-86c9-3cf24897063f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393290215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1393290215
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.1259113480
Short name T679
Test name
Test status
Simulation time 1471394821 ps
CPU time 2.19 seconds
Started May 26 12:44:38 PM PDT 24
Finished May 26 12:44:41 PM PDT 24
Peak memory 204540 kb
Host smart-a6507ad9-7fb5-439d-9c12-47b3e40e12ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259113480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.1259113480
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.430868175
Short name T1204
Test name
Test status
Simulation time 1387670434 ps
CPU time 2.36 seconds
Started May 26 12:44:36 PM PDT 24
Finished May 26 12:44:39 PM PDT 24
Peak memory 204608 kb
Host smart-758ab356-6433-4fe2-966f-f780e27f252d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430868175 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.430868175
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4034386930
Short name T1126
Test name
Test status
Simulation time 5686571598 ps
CPU time 2.54 seconds
Started May 26 12:44:26 PM PDT 24
Finished May 26 12:44:29 PM PDT 24
Peak memory 204516 kb
Host smart-0e236886-7ed9-4e4d-a145-e91b01c25c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034386930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4034386930
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1832333720
Short name T951
Test name
Test status
Simulation time 3958390436 ps
CPU time 3.54 seconds
Started May 26 12:44:26 PM PDT 24
Finished May 26 12:44:31 PM PDT 24
Peak memory 204492 kb
Host smart-a52ef6bb-201c-4acd-b945-6072ab98bd18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832333720 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1832333720
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3276538476
Short name T1421
Test name
Test status
Simulation time 13458035277 ps
CPU time 101.03 seconds
Started May 26 12:44:26 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 1591688 kb
Host smart-4dff75cb-ee8a-4e53-b202-d153b9c153f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276538476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3276538476
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2488611415
Short name T470
Test name
Test status
Simulation time 2837612116 ps
CPU time 18.92 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:44:50 PM PDT 24
Peak memory 204512 kb
Host smart-42528623-e6bb-4e5f-ad29-d84af7ca3f73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488611415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2488611415
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3387222568
Short name T889
Test name
Test status
Simulation time 1828252992 ps
CPU time 20.04 seconds
Started May 26 12:44:32 PM PDT 24
Finished May 26 12:44:53 PM PDT 24
Peak memory 204420 kb
Host smart-d647d378-9ac2-4615-b0b4-93bdc91e3370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387222568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3387222568
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2816039131
Short name T1214
Test name
Test status
Simulation time 12843621072 ps
CPU time 3.34 seconds
Started May 26 12:44:27 PM PDT 24
Finished May 26 12:44:31 PM PDT 24
Peak memory 204452 kb
Host smart-f96b9d97-360a-4657-b599-7730b2ed95ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816039131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2816039131
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1072088223
Short name T1107
Test name
Test status
Simulation time 42795673605 ps
CPU time 349.04 seconds
Started May 26 12:44:27 PM PDT 24
Finished May 26 12:50:17 PM PDT 24
Peak memory 2387132 kb
Host smart-6cb5de6d-5c53-413a-8838-22f5a1302868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072088223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1072088223
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1145738270
Short name T739
Test name
Test status
Simulation time 5646180748 ps
CPU time 6.91 seconds
Started May 26 12:44:31 PM PDT 24
Finished May 26 12:44:38 PM PDT 24
Peak memory 218948 kb
Host smart-16f37b9d-8f89-440a-8121-631fdb9feecc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145738270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1145738270
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2157190885
Short name T744
Test name
Test status
Simulation time 41481522 ps
CPU time 0.62 seconds
Started May 26 12:44:43 PM PDT 24
Finished May 26 12:44:44 PM PDT 24
Peak memory 204088 kb
Host smart-659b489d-7f76-4134-a980-0c662dd48376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157190885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2157190885
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.988565773
Short name T1300
Test name
Test status
Simulation time 500220926 ps
CPU time 3.45 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:44:39 PM PDT 24
Peak memory 212748 kb
Host smart-e2125efe-2ca3-4507-acf4-3dcd74eea7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988565773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.988565773
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.608160877
Short name T861
Test name
Test status
Simulation time 358808730 ps
CPU time 7.94 seconds
Started May 26 12:44:39 PM PDT 24
Finished May 26 12:44:47 PM PDT 24
Peak memory 276192 kb
Host smart-c900c723-b221-4b6d-bd7f-7716bb2f184d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608160877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.608160877
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.218645945
Short name T1354
Test name
Test status
Simulation time 1504996683 ps
CPU time 101.28 seconds
Started May 26 12:44:40 PM PDT 24
Finished May 26 12:46:22 PM PDT 24
Peak memory 563656 kb
Host smart-fe6dd6e6-a8ff-48f3-8b1a-a8d9ae4e44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218645945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.218645945
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2629730293
Short name T1346
Test name
Test status
Simulation time 2402016441 ps
CPU time 89.18 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:46:05 PM PDT 24
Peak memory 800596 kb
Host smart-2a30f4e2-fe92-4a99-b04d-68d9958b7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629730293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2629730293
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1114983821
Short name T1313
Test name
Test status
Simulation time 160480747 ps
CPU time 9.29 seconds
Started May 26 12:44:38 PM PDT 24
Finished May 26 12:44:48 PM PDT 24
Peak memory 233672 kb
Host smart-b4eb17ac-74ac-481c-82d7-da75ab9e9641
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114983821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1114983821
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3109774492
Short name T599
Test name
Test status
Simulation time 4528101330 ps
CPU time 142.36 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:46:58 PM PDT 24
Peak memory 1285948 kb
Host smart-dd8f64f8-1daa-4f68-a1f6-1d13456ddcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109774492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3109774492
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.2083214757
Short name T380
Test name
Test status
Simulation time 811424220 ps
CPU time 8.06 seconds
Started May 26 12:44:50 PM PDT 24
Finished May 26 12:44:58 PM PDT 24
Peak memory 204524 kb
Host smart-7811f6d5-dd88-4f2d-b9eb-d09cb93587b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083214757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.2083214757
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.796649363
Short name T638
Test name
Test status
Simulation time 7395384550 ps
CPU time 22.98 seconds
Started May 26 12:44:45 PM PDT 24
Finished May 26 12:45:09 PM PDT 24
Peak memory 345076 kb
Host smart-d5999094-0574-4d19-bca9-f8b62674ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796649363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.796649363
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.559647189
Short name T141
Test name
Test status
Simulation time 31192773 ps
CPU time 0.73 seconds
Started May 26 12:44:40 PM PDT 24
Finished May 26 12:44:41 PM PDT 24
Peak memory 204132 kb
Host smart-ac3424be-96a8-4fba-bb59-611414b40e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559647189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.559647189
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2827549083
Short name T1238
Test name
Test status
Simulation time 51528291383 ps
CPU time 391.15 seconds
Started May 26 12:44:39 PM PDT 24
Finished May 26 12:51:11 PM PDT 24
Peak memory 983968 kb
Host smart-16d046c4-8676-40a2-9002-cea76bafef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827549083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2827549083
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1847076704
Short name T1272
Test name
Test status
Simulation time 6773254309 ps
CPU time 81.68 seconds
Started May 26 12:44:36 PM PDT 24
Finished May 26 12:45:58 PM PDT 24
Peak memory 326484 kb
Host smart-d82783fb-e27e-4053-a8c5-3139392b58c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847076704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1847076704
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1174844966
Short name T122
Test name
Test status
Simulation time 89520347456 ps
CPU time 479.21 seconds
Started May 26 12:44:39 PM PDT 24
Finished May 26 12:52:38 PM PDT 24
Peak memory 1789784 kb
Host smart-630b32d1-8345-47b9-856f-3ad24c6918cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174844966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1174844966
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1182336462
Short name T345
Test name
Test status
Simulation time 1689275442 ps
CPU time 8.87 seconds
Started May 26 12:44:36 PM PDT 24
Finished May 26 12:44:45 PM PDT 24
Peak memory 213672 kb
Host smart-c82b7808-32ae-417d-8941-c093c1b8cefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182336462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1182336462
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.881200235
Short name T870
Test name
Test status
Simulation time 3882077251 ps
CPU time 4.87 seconds
Started May 26 12:44:44 PM PDT 24
Finished May 26 12:44:49 PM PDT 24
Peak memory 212752 kb
Host smart-b7539ca9-1dd5-4dc4-a8ae-374839830764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881200235 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.881200235
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.560276
Short name T950
Test name
Test status
Simulation time 11276243482 ps
CPU time 6.96 seconds
Started May 26 12:44:44 PM PDT 24
Finished May 26 12:44:52 PM PDT 24
Peak memory 228224 kb
Host smart-bd94c3cb-5a47-448d-a61c-0c8142704b7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560276 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_target_fifo_reset_acq.560276
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3062411924
Short name T420
Test name
Test status
Simulation time 10216322422 ps
CPU time 9.46 seconds
Started May 26 12:44:42 PM PDT 24
Finished May 26 12:44:52 PM PDT 24
Peak memory 251652 kb
Host smart-e6466c8f-dbc0-4e9c-ae40-7671aa3bfd49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062411924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3062411924
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.2988548651
Short name T884
Test name
Test status
Simulation time 1250022702 ps
CPU time 5.65 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:44:53 PM PDT 24
Peak memory 204552 kb
Host smart-b25af919-f9dc-48cf-a3d9-02c7c553a4f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988548651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.2988548651
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2308020062
Short name T157
Test name
Test status
Simulation time 1759717175 ps
CPU time 1.35 seconds
Started May 26 12:44:50 PM PDT 24
Finished May 26 12:44:52 PM PDT 24
Peak memory 204248 kb
Host smart-8482aa66-72c5-45ab-86c1-a6b125e0019f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308020062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2308020062
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.187298676
Short name T761
Test name
Test status
Simulation time 445084625 ps
CPU time 2.58 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:44:50 PM PDT 24
Peak memory 204520 kb
Host smart-d7f0cfca-50e9-43d5-ab1d-5867af61e115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187298676 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.187298676
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1019769327
Short name T590
Test name
Test status
Simulation time 3876334116 ps
CPU time 5 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:44:41 PM PDT 24
Peak memory 204496 kb
Host smart-cbf427a1-b3f9-47e5-89ad-27bf4c873b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019769327 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1019769327
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.356819512
Short name T936
Test name
Test status
Simulation time 12747418687 ps
CPU time 90.86 seconds
Started May 26 12:44:37 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 1550608 kb
Host smart-04b3ff59-47d8-49b5-bc0f-8b5fca9303b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356819512 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.356819512
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1694082322
Short name T654
Test name
Test status
Simulation time 723295309 ps
CPU time 29.07 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 12:45:05 PM PDT 24
Peak memory 204400 kb
Host smart-231c036c-f637-418b-847f-15bbbaa8a741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694082322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1694082322
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1439830127
Short name T632
Test name
Test status
Simulation time 5907308920 ps
CPU time 15.82 seconds
Started May 26 12:44:39 PM PDT 24
Finished May 26 12:44:55 PM PDT 24
Peak memory 213040 kb
Host smart-e7985cf1-0263-4eeb-926c-1099fb910245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439830127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1439830127
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2998273889
Short name T128
Test name
Test status
Simulation time 25756798503 ps
CPU time 41.77 seconds
Started May 26 12:44:40 PM PDT 24
Finished May 26 12:45:22 PM PDT 24
Peak memory 778116 kb
Host smart-9a29fdf5-f8c8-464d-922d-2a2342e7ed4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998273889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2998273889
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2535566223
Short name T4
Test name
Test status
Simulation time 40158001425 ps
CPU time 951.06 seconds
Started May 26 12:44:35 PM PDT 24
Finished May 26 01:00:27 PM PDT 24
Peak memory 4526920 kb
Host smart-d4c10c4a-2ca3-4a9b-a577-095b35a8f9ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535566223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2535566223
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2132085362
Short name T1079
Test name
Test status
Simulation time 6091509873 ps
CPU time 8.27 seconds
Started May 26 12:44:37 PM PDT 24
Finished May 26 12:44:46 PM PDT 24
Peak memory 212736 kb
Host smart-f99c84d0-81ed-4e00-be25-23f997a9275d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132085362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2132085362
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.588154558
Short name T743
Test name
Test status
Simulation time 33216270 ps
CPU time 0.63 seconds
Started May 26 12:44:54 PM PDT 24
Finished May 26 12:44:56 PM PDT 24
Peak memory 204072 kb
Host smart-b0b3c2cd-e06a-446b-905d-a2eac6ac5a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588154558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.588154558
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.331976594
Short name T1437
Test name
Test status
Simulation time 112750704 ps
CPU time 3.66 seconds
Started May 26 12:44:45 PM PDT 24
Finished May 26 12:44:49 PM PDT 24
Peak memory 220868 kb
Host smart-2946e6eb-dc89-4ff4-90c4-a3276c331018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331976594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.331976594
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3547471099
Short name T1360
Test name
Test status
Simulation time 1274245339 ps
CPU time 6.36 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:44:54 PM PDT 24
Peak memory 271312 kb
Host smart-ee3aa164-d49c-4333-bb7d-d2ec213415e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547471099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3547471099
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2647166833
Short name T1388
Test name
Test status
Simulation time 6694370453 ps
CPU time 44.54 seconds
Started May 26 12:44:50 PM PDT 24
Finished May 26 12:45:35 PM PDT 24
Peak memory 541068 kb
Host smart-00e7ace3-a941-4acd-b25c-e5990771ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647166833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2647166833
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.792494066
Short name T1053
Test name
Test status
Simulation time 3083924846 ps
CPU time 45.3 seconds
Started May 26 12:44:46 PM PDT 24
Finished May 26 12:45:32 PM PDT 24
Peak memory 578752 kb
Host smart-52512bb1-0695-450d-acda-d2e1b709b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792494066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.792494066
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3072355976
Short name T711
Test name
Test status
Simulation time 325070619 ps
CPU time 1.15 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:44:49 PM PDT 24
Peak memory 204420 kb
Host smart-96c358e7-1eaa-4d0d-82eb-dc8ce7e9c8cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072355976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3072355976
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1579766958
Short name T551
Test name
Test status
Simulation time 692140443 ps
CPU time 4.73 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:44:52 PM PDT 24
Peak memory 204420 kb
Host smart-d76ae55b-f9bd-4262-bea1-bb8bbc027ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579766958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1579766958
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.767246792
Short name T1101
Test name
Test status
Simulation time 24043777092 ps
CPU time 94.55 seconds
Started May 26 12:44:46 PM PDT 24
Finished May 26 12:46:21 PM PDT 24
Peak memory 1103456 kb
Host smart-f2443827-3bdb-4a64-a7fb-1f7386ab152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767246792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.767246792
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3384609024
Short name T45
Test name
Test status
Simulation time 1291314936 ps
CPU time 7.23 seconds
Started May 26 12:44:55 PM PDT 24
Finished May 26 12:45:03 PM PDT 24
Peak memory 204524 kb
Host smart-fa915ac8-d76f-4077-850e-76d93a13d2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384609024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3384609024
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2594704266
Short name T59
Test name
Test status
Simulation time 2020071447 ps
CPU time 31.41 seconds
Started May 26 12:44:55 PM PDT 24
Finished May 26 12:45:28 PM PDT 24
Peak memory 370004 kb
Host smart-49e70430-dda6-4ee7-9b16-045feabd3680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594704266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2594704266
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1675013681
Short name T1448
Test name
Test status
Simulation time 20301768 ps
CPU time 0.62 seconds
Started May 26 12:44:43 PM PDT 24
Finished May 26 12:44:44 PM PDT 24
Peak memory 204208 kb
Host smart-d3ab6e31-6855-490c-ab7c-8acbe9be9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675013681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1675013681
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1462250554
Short name T840
Test name
Test status
Simulation time 6063497577 ps
CPU time 33.76 seconds
Started May 26 12:44:45 PM PDT 24
Finished May 26 12:45:19 PM PDT 24
Peak memory 237072 kb
Host smart-1e91deaa-229f-402d-a9e3-084a9830f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462250554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1462250554
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2643712769
Short name T544
Test name
Test status
Simulation time 7962641552 ps
CPU time 99.37 seconds
Started May 26 12:44:47 PM PDT 24
Finished May 26 12:46:27 PM PDT 24
Peak memory 383280 kb
Host smart-b2b5a3dc-656c-4af2-9cdd-46f44fb0a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643712769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2643712769
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.285488842
Short name T817
Test name
Test status
Simulation time 15697564521 ps
CPU time 244.44 seconds
Started May 26 12:44:46 PM PDT 24
Finished May 26 12:48:51 PM PDT 24
Peak memory 971780 kb
Host smart-db1da368-219e-4f72-9c27-38fd2e6a3551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285488842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.285488842
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3614631877
Short name T1347
Test name
Test status
Simulation time 727527202 ps
CPU time 34.84 seconds
Started May 26 12:44:45 PM PDT 24
Finished May 26 12:45:21 PM PDT 24
Peak memory 212612 kb
Host smart-b025529b-a367-423c-899f-646d8ee2af44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614631877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3614631877
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.402972579
Short name T25
Test name
Test status
Simulation time 1768691680 ps
CPU time 3.91 seconds
Started May 26 12:44:58 PM PDT 24
Finished May 26 12:45:03 PM PDT 24
Peak memory 204440 kb
Host smart-44dc13b8-6238-4859-b305-5e859a755363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402972579 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.402972579
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2552473969
Short name T143
Test name
Test status
Simulation time 10404175072 ps
CPU time 13.12 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:45:08 PM PDT 24
Peak memory 242152 kb
Host smart-89317799-1185-47e7-a288-58e51a599394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552473969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2552473969
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2750889984
Short name T1285
Test name
Test status
Simulation time 10105729736 ps
CPU time 76.85 seconds
Started May 26 12:44:54 PM PDT 24
Finished May 26 12:46:12 PM PDT 24
Peak memory 629424 kb
Host smart-d9283080-652e-43ae-a32b-f3c7dea8542c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750889984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2750889984
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2186987104
Short name T648
Test name
Test status
Simulation time 1039407092 ps
CPU time 5.05 seconds
Started May 26 12:44:58 PM PDT 24
Finished May 26 12:45:04 PM PDT 24
Peak memory 204404 kb
Host smart-356a24a3-9bf8-4937-b7d1-e4dc10fb8f80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186987104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2186987104
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.838719124
Short name T616
Test name
Test status
Simulation time 1043062861 ps
CPU time 4.99 seconds
Started May 26 12:44:54 PM PDT 24
Finished May 26 12:45:00 PM PDT 24
Peak memory 204480 kb
Host smart-f61688ca-ba07-4944-95a9-3b8e39eac874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838719124 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.838719124
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.10804633
Short name T782
Test name
Test status
Simulation time 372604142 ps
CPU time 2.27 seconds
Started May 26 12:44:52 PM PDT 24
Finished May 26 12:44:56 PM PDT 24
Peak memory 204492 kb
Host smart-c076c99b-0bf7-47e9-988d-c206c1f5b268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10804633 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.i2c_target_hrst.10804633
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3565744657
Short name T31
Test name
Test status
Simulation time 745273518 ps
CPU time 4.27 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:44:59 PM PDT 24
Peak memory 204480 kb
Host smart-54dbb049-c072-4e9a-95a6-612670393091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565744657 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3565744657
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2638131214
Short name T969
Test name
Test status
Simulation time 16011017407 ps
CPU time 32.51 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:45:27 PM PDT 24
Peak memory 602996 kb
Host smart-ff293204-2043-4258-834d-73232fb2c0c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638131214 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2638131214
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3315518633
Short name T1279
Test name
Test status
Simulation time 1953482856 ps
CPU time 14.5 seconds
Started May 26 12:44:54 PM PDT 24
Finished May 26 12:45:10 PM PDT 24
Peak memory 204380 kb
Host smart-af5d53c1-5db6-4527-b7d9-e42bb744cd1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315518633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3315518633
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3339498246
Short name T414
Test name
Test status
Simulation time 791133082 ps
CPU time 32.26 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:45:27 PM PDT 24
Peak memory 204488 kb
Host smart-c9ce645d-a94c-491f-88be-d36f9f6494af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339498246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3339498246
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1749330083
Short name T1438
Test name
Test status
Simulation time 37694651961 ps
CPU time 448.49 seconds
Started May 26 12:44:52 PM PDT 24
Finished May 26 12:52:22 PM PDT 24
Peak memory 4347948 kb
Host smart-dfd8b232-257b-498f-a60d-ca5f5f337247
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749330083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1749330083
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3546585871
Short name T892
Test name
Test status
Simulation time 5892152634 ps
CPU time 7.29 seconds
Started May 26 12:44:54 PM PDT 24
Finished May 26 12:45:02 PM PDT 24
Peak memory 220848 kb
Host smart-0286f68b-74c7-4fb0-8890-1aea0b43cf29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546585871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3546585871
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.867734937
Short name T765
Test name
Test status
Simulation time 28381876 ps
CPU time 0.59 seconds
Started May 26 12:45:09 PM PDT 24
Finished May 26 12:45:10 PM PDT 24
Peak memory 204056 kb
Host smart-05179f52-ea60-4695-869f-0597b7969674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867734937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.867734937
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.440356665
Short name T1073
Test name
Test status
Simulation time 93264177 ps
CPU time 2.26 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:45:14 PM PDT 24
Peak memory 212688 kb
Host smart-e5d56d84-625f-497f-bcc6-8be7148e3a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440356665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.440356665
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.4072155926
Short name T473
Test name
Test status
Simulation time 1289655294 ps
CPU time 6.86 seconds
Started May 26 12:45:04 PM PDT 24
Finished May 26 12:45:12 PM PDT 24
Peak memory 273540 kb
Host smart-5f702767-eb3d-4837-9162-b29b067d5402
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072155926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.4072155926
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3721285429
Short name T477
Test name
Test status
Simulation time 6340353564 ps
CPU time 80.94 seconds
Started May 26 12:45:01 PM PDT 24
Finished May 26 12:46:22 PM PDT 24
Peak memory 444168 kb
Host smart-70e11f71-55e2-4905-b5ee-16856bf84905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721285429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3721285429
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3617176714
Short name T899
Test name
Test status
Simulation time 2176615786 ps
CPU time 157.76 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 701644 kb
Host smart-2995fef6-dbe5-4b1b-84c6-5e9484f1f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617176714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3617176714
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1404048925
Short name T928
Test name
Test status
Simulation time 548934507 ps
CPU time 1.15 seconds
Started May 26 12:44:57 PM PDT 24
Finished May 26 12:44:58 PM PDT 24
Peak memory 204504 kb
Host smart-66d14e2c-7a7f-4e11-a847-d051ad9c20ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404048925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1404048925
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4250726230
Short name T1243
Test name
Test status
Simulation time 145548430 ps
CPU time 7.43 seconds
Started May 26 12:45:04 PM PDT 24
Finished May 26 12:45:12 PM PDT 24
Peak memory 204508 kb
Host smart-bc114476-5055-48ad-9095-cd056dc10c28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250726230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4250726230
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2897707013
Short name T643
Test name
Test status
Simulation time 5259879065 ps
CPU time 167.58 seconds
Started May 26 12:44:55 PM PDT 24
Finished May 26 12:47:43 PM PDT 24
Peak memory 1465808 kb
Host smart-833e204a-0c61-4f6d-aab4-5fd80a6cdfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897707013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2897707013
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3769103217
Short name T548
Test name
Test status
Simulation time 2120324779 ps
CPU time 8.93 seconds
Started May 26 12:45:10 PM PDT 24
Finished May 26 12:45:20 PM PDT 24
Peak memory 204496 kb
Host smart-f84f5cfc-0790-4294-af5f-f25f7bc60202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769103217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3769103217
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.4116576545
Short name T754
Test name
Test status
Simulation time 1846744333 ps
CPU time 82.81 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 316828 kb
Host smart-f447d618-c1e2-4113-b5a2-5a48697028a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116576545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.4116576545
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.188153481
Short name T938
Test name
Test status
Simulation time 81673205 ps
CPU time 0.67 seconds
Started May 26 12:44:56 PM PDT 24
Finished May 26 12:44:58 PM PDT 24
Peak memory 204148 kb
Host smart-ceb17624-e93b-4027-93de-d50beea9af77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188153481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.188153481
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3907264796
Short name T1185
Test name
Test status
Simulation time 28896356090 ps
CPU time 105.21 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:46:57 PM PDT 24
Peak memory 212624 kb
Host smart-1ca19c2b-c89f-4f43-b928-e84077526f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907264796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3907264796
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.197655528
Short name T1074
Test name
Test status
Simulation time 8229413108 ps
CPU time 44.28 seconds
Started May 26 12:44:53 PM PDT 24
Finished May 26 12:45:39 PM PDT 24
Peak memory 474616 kb
Host smart-51b49de8-f18b-423a-81c4-9a947f390578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197655528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.197655528
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.973707530
Short name T49
Test name
Test status
Simulation time 6999750035 ps
CPU time 318.09 seconds
Started May 26 12:45:03 PM PDT 24
Finished May 26 12:50:22 PM PDT 24
Peak memory 1618720 kb
Host smart-4ee9584f-f94c-44de-970a-9aace9f26114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973707530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.973707530
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.692773050
Short name T1111
Test name
Test status
Simulation time 6565653166 ps
CPU time 12.3 seconds
Started May 26 12:45:03 PM PDT 24
Finished May 26 12:45:16 PM PDT 24
Peak memory 220980 kb
Host smart-35cad22c-cc00-43e2-911f-012ed8c70be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692773050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.692773050
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3741212327
Short name T396
Test name
Test status
Simulation time 3893987848 ps
CPU time 4.88 seconds
Started May 26 12:45:01 PM PDT 24
Finished May 26 12:45:07 PM PDT 24
Peak memory 204560 kb
Host smart-8130f350-711e-4f3a-9529-d873ab96d168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741212327 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3741212327
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1677566954
Short name T116
Test name
Test status
Simulation time 10243779275 ps
CPU time 6.48 seconds
Started May 26 12:45:01 PM PDT 24
Finished May 26 12:45:08 PM PDT 24
Peak memory 229504 kb
Host smart-9697b940-d642-4aa7-a58e-d6759ef51857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677566954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1677566954
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3134081963
Short name T1339
Test name
Test status
Simulation time 10452617554 ps
CPU time 14.23 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:45:26 PM PDT 24
Peak memory 316088 kb
Host smart-be10e063-6a4a-49cd-a112-588a048c5b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134081963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3134081963
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3070188957
Short name T1418
Test name
Test status
Simulation time 1325335264 ps
CPU time 5.17 seconds
Started May 26 12:45:12 PM PDT 24
Finished May 26 12:45:18 PM PDT 24
Peak memory 204316 kb
Host smart-b1769c50-d8bb-4335-ba7e-0d74c1e96a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070188957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3070188957
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1019918097
Short name T1321
Test name
Test status
Simulation time 1213088171 ps
CPU time 1.92 seconds
Started May 26 12:45:10 PM PDT 24
Finished May 26 12:45:13 PM PDT 24
Peak memory 204512 kb
Host smart-51fe6b7a-5acc-4b2d-8447-e3722da71e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019918097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1019918097
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.376069579
Short name T503
Test name
Test status
Simulation time 393944070 ps
CPU time 2.76 seconds
Started May 26 12:45:03 PM PDT 24
Finished May 26 12:45:06 PM PDT 24
Peak memory 204548 kb
Host smart-cd603c20-725f-4cdf-95af-1608429cab0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376069579 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.376069579
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2893180989
Short name T871
Test name
Test status
Simulation time 4618148857 ps
CPU time 6.37 seconds
Started May 26 12:45:04 PM PDT 24
Finished May 26 12:45:11 PM PDT 24
Peak memory 212696 kb
Host smart-59221513-8fbb-495b-99d5-a6661e7b0ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893180989 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2893180989
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.691658564
Short name T163
Test name
Test status
Simulation time 14758269227 ps
CPU time 254.18 seconds
Started May 26 12:45:03 PM PDT 24
Finished May 26 12:49:17 PM PDT 24
Peak memory 3508376 kb
Host smart-741946dc-d104-48b0-8093-d1de1bc4082e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691658564 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.691658564
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.556600054
Short name T340
Test name
Test status
Simulation time 3572903496 ps
CPU time 21.49 seconds
Started May 26 12:45:04 PM PDT 24
Finished May 26 12:45:26 PM PDT 24
Peak memory 204428 kb
Host smart-89820e67-a1d7-44dc-86cf-e477d08beb87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556600054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.556600054
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3980911541
Short name T607
Test name
Test status
Simulation time 598269624 ps
CPU time 24.87 seconds
Started May 26 12:45:05 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 204496 kb
Host smart-0d5e535d-b2d2-4549-a603-83d07af61c7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980911541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3980911541
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1303135572
Short name T1379
Test name
Test status
Simulation time 22465279250 ps
CPU time 12.69 seconds
Started May 26 12:45:01 PM PDT 24
Finished May 26 12:45:14 PM PDT 24
Peak memory 221656 kb
Host smart-2fbf6238-5086-4b4d-9ae6-b03ada22547a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303135572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1303135572
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1383102226
Short name T1381
Test name
Test status
Simulation time 41307542572 ps
CPU time 62.76 seconds
Started May 26 12:45:04 PM PDT 24
Finished May 26 12:46:07 PM PDT 24
Peak memory 556532 kb
Host smart-c146b5e7-31ae-491f-9a2f-c11dbc538afd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383102226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1383102226
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1398124104
Short name T583
Test name
Test status
Simulation time 1475303952 ps
CPU time 7.25 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:45:19 PM PDT 24
Peak memory 213348 kb
Host smart-71f88529-c214-4d23-a09a-152c133281a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398124104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1398124104
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.338016257
Short name T545
Test name
Test status
Simulation time 119858156 ps
CPU time 0.59 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:41:45 PM PDT 24
Peak memory 204052 kb
Host smart-27940b48-fcff-4cb4-a0dd-cfd29e8396ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338016257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.338016257
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.959633861
Short name T1014
Test name
Test status
Simulation time 118709537 ps
CPU time 3.5 seconds
Started May 26 12:41:38 PM PDT 24
Finished May 26 12:41:42 PM PDT 24
Peak memory 212760 kb
Host smart-8cbc63ec-e4c5-4eea-9a92-697fb011abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959633861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.959633861
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3967417586
Short name T1444
Test name
Test status
Simulation time 353932109 ps
CPU time 18.37 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:41:55 PM PDT 24
Peak memory 278124 kb
Host smart-d84d7c32-858c-4a81-939e-47d39715c623
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967417586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3967417586
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3066579357
Short name T476
Test name
Test status
Simulation time 5096777926 ps
CPU time 153.12 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:44:09 PM PDT 24
Peak memory 522668 kb
Host smart-6f12f204-0494-49d3-b4bb-5d73c9f4afd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066579357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3066579357
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2330920530
Short name T1028
Test name
Test status
Simulation time 2600956202 ps
CPU time 182.54 seconds
Started May 26 12:41:40 PM PDT 24
Finished May 26 12:44:43 PM PDT 24
Peak memory 770980 kb
Host smart-ca6bde1e-0a48-4253-aff6-85ca9768e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330920530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2330920530
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.226516027
Short name T1141
Test name
Test status
Simulation time 154904619 ps
CPU time 1.1 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:38 PM PDT 24
Peak memory 204392 kb
Host smart-47ee7d1d-16de-4230-911c-71e1517a62f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226516027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.226516027
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.54506548
Short name T552
Test name
Test status
Simulation time 241409746 ps
CPU time 5.77 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:41:42 PM PDT 24
Peak memory 204448 kb
Host smart-c237d9b6-31d9-48a8-8866-10046f5cd608
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54506548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.54506548
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1315597407
Short name T259
Test name
Test status
Simulation time 4470784757 ps
CPU time 145.82 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:44:02 PM PDT 24
Peak memory 1271872 kb
Host smart-d44cd6c6-ddbf-4039-bb06-a53a386ef6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315597407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1315597407
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3653535942
Short name T1254
Test name
Test status
Simulation time 2840717746 ps
CPU time 31.31 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:42:16 PM PDT 24
Peak memory 204536 kb
Host smart-a25c7e5b-3a46-41d8-9021-77872a2bc01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653535942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3653535942
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3050646084
Short name T69
Test name
Test status
Simulation time 6113630562 ps
CPU time 23.08 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:42:07 PM PDT 24
Peak memory 301944 kb
Host smart-b4f23f05-2deb-41c6-afb7-d9cb5bd172a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050646084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3050646084
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.4165657162
Short name T1196
Test name
Test status
Simulation time 81176669 ps
CPU time 0.72 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:41:36 PM PDT 24
Peak memory 204124 kb
Host smart-19169c43-2bf4-41ce-a25e-cf52f0790201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165657162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.4165657162
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.788429414
Short name T319
Test name
Test status
Simulation time 6214325743 ps
CPU time 38.16 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:42:15 PM PDT 24
Peak memory 212732 kb
Host smart-d3c046a2-74f6-4a7c-9fe6-cbdeeb2d8f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788429414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.788429414
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2417071424
Short name T1428
Test name
Test status
Simulation time 4255301414 ps
CPU time 112.33 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:43:27 PM PDT 24
Peak memory 329816 kb
Host smart-f70d95bf-c68a-4d39-9d74-9c7669ac0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417071424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2417071424
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3517190092
Short name T111
Test name
Test status
Simulation time 23267724847 ps
CPU time 436.7 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:48:54 PM PDT 24
Peak memory 1805824 kb
Host smart-db392f5a-e4c8-452a-a79f-a0ee61866b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517190092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3517190092
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3211077933
Short name T1258
Test name
Test status
Simulation time 1109789461 ps
CPU time 22.64 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:41:57 PM PDT 24
Peak memory 220020 kb
Host smart-54c0643a-a2eb-4e43-953d-b9a97e62c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211077933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3211077933
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2909481050
Short name T177
Test name
Test status
Simulation time 275091944 ps
CPU time 0.92 seconds
Started May 26 12:41:48 PM PDT 24
Finished May 26 12:41:50 PM PDT 24
Peak memory 222544 kb
Host smart-77f178a8-40b3-40c8-a717-7cc0f8ff444f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909481050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2909481050
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2731752026
Short name T1163
Test name
Test status
Simulation time 3221558791 ps
CPU time 3.89 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:41:49 PM PDT 24
Peak memory 204432 kb
Host smart-80564f5e-facf-48c8-9cc1-56aa30dd4dff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731752026 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2731752026
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.157939190
Short name T1322
Test name
Test status
Simulation time 10515379117 ps
CPU time 12.53 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:41:58 PM PDT 24
Peak memory 262272 kb
Host smart-e54204f9-95f4-4261-88f2-bb1b6b284952
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157939190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.157939190
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.418201064
Short name T1312
Test name
Test status
Simulation time 1143538225 ps
CPU time 4.89 seconds
Started May 26 12:41:49 PM PDT 24
Finished May 26 12:41:54 PM PDT 24
Peak memory 204488 kb
Host smart-1eae84d7-9782-49ba-9809-a1fb544e6990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418201064 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.418201064
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.822010931
Short name T1050
Test name
Test status
Simulation time 1297448298 ps
CPU time 1.97 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:41:48 PM PDT 24
Peak memory 204492 kb
Host smart-e5e997a6-55b1-48a8-ae1a-52a4fb7cdbb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822010931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.822010931
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.641911558
Short name T617
Test name
Test status
Simulation time 1735120303 ps
CPU time 2.76 seconds
Started May 26 12:41:46 PM PDT 24
Finished May 26 12:41:49 PM PDT 24
Peak memory 204520 kb
Host smart-2249b5e8-6ca8-465f-a5cc-1a101ef6d7f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641911558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.641911558
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1000604467
Short name T1020
Test name
Test status
Simulation time 2797520169 ps
CPU time 4.27 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:41 PM PDT 24
Peak memory 204508 kb
Host smart-7e35e1f6-068d-4372-bb5d-774361201ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000604467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1000604467
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1712594315
Short name T1182
Test name
Test status
Simulation time 21495830637 ps
CPU time 150.14 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:44:05 PM PDT 24
Peak memory 1939356 kb
Host smart-796690ae-8ba0-4fde-a9a1-24bbeec31a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712594315 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1712594315
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3424890273
Short name T1085
Test name
Test status
Simulation time 966280008 ps
CPU time 33.79 seconds
Started May 26 12:41:34 PM PDT 24
Finished May 26 12:42:08 PM PDT 24
Peak memory 204368 kb
Host smart-d2045eda-5953-429e-aaa3-9d490364d4b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424890273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3424890273
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3091386870
Short name T666
Test name
Test status
Simulation time 3078389152 ps
CPU time 28.22 seconds
Started May 26 12:41:37 PM PDT 24
Finished May 26 12:42:06 PM PDT 24
Peak memory 204520 kb
Host smart-b60e2565-9447-4c93-9f49-627a6578522b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091386870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3091386870
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1398751599
Short name T959
Test name
Test status
Simulation time 38388020616 ps
CPU time 20.21 seconds
Started May 26 12:41:36 PM PDT 24
Finished May 26 12:41:57 PM PDT 24
Peak memory 512840 kb
Host smart-b191bcd1-a366-4e68-a24e-c686537254cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398751599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1398751599
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1218212271
Short name T769
Test name
Test status
Simulation time 22304271758 ps
CPU time 499.4 seconds
Started May 26 12:41:35 PM PDT 24
Finished May 26 12:49:55 PM PDT 24
Peak memory 1462988 kb
Host smart-37af67b4-df9d-4c97-ad07-0cad0e29035d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218212271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1218212271
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2068616253
Short name T1128
Test name
Test status
Simulation time 6515953695 ps
CPU time 7.66 seconds
Started May 26 12:41:39 PM PDT 24
Finished May 26 12:41:47 PM PDT 24
Peak memory 220852 kb
Host smart-cb7aaa4a-c339-4f57-a1d1-0db118f2bbe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068616253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2068616253
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.842514358
Short name T1419
Test name
Test status
Simulation time 26723544 ps
CPU time 0.63 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:45:20 PM PDT 24
Peak memory 204096 kb
Host smart-3ce1809e-ab46-4b9e-a687-e9dd6a6a8c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842514358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.842514358
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3638420706
Short name T949
Test name
Test status
Simulation time 2464660531 ps
CPU time 5.18 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:26 PM PDT 24
Peak memory 212876 kb
Host smart-d983e520-1de7-43a7-8488-b3ce4789a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638420706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3638420706
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.4016696893
Short name T1273
Test name
Test status
Simulation time 393531887 ps
CPU time 20.68 seconds
Started May 26 12:45:09 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 288688 kb
Host smart-6cc9eecf-391d-4733-bbed-31314c07dd0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016696893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.4016696893
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1741310779
Short name T1091
Test name
Test status
Simulation time 7424151178 ps
CPU time 53.45 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:46:06 PM PDT 24
Peak memory 630400 kb
Host smart-95d2c166-7ec4-4dfc-a865-86afcf64b4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741310779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1741310779
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2773082741
Short name T1305
Test name
Test status
Simulation time 104549173 ps
CPU time 0.97 seconds
Started May 26 12:45:10 PM PDT 24
Finished May 26 12:45:12 PM PDT 24
Peak memory 204272 kb
Host smart-9c4de8e7-2f18-4170-ae3f-d070fcb7d63a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773082741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2773082741
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3030287449
Short name T152
Test name
Test status
Simulation time 177148475 ps
CPU time 5.16 seconds
Started May 26 12:45:12 PM PDT 24
Finished May 26 12:45:18 PM PDT 24
Peak memory 237368 kb
Host smart-f7a86bb2-e85f-40e0-808c-e90c51749b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030287449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3030287449
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2475687096
Short name T713
Test name
Test status
Simulation time 13292877490 ps
CPU time 234.69 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:49:07 PM PDT 24
Peak memory 998584 kb
Host smart-86ccd2a2-5b51-42e1-a4d1-0037cb244371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475687096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2475687096
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3942238388
Short name T914
Test name
Test status
Simulation time 2188816396 ps
CPU time 6.16 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:27 PM PDT 24
Peak memory 204544 kb
Host smart-19b57fd7-34e0-4114-935f-ba256fcee300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942238388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3942238388
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3655993934
Short name T1103
Test name
Test status
Simulation time 7704771863 ps
CPU time 31.43 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:45:52 PM PDT 24
Peak memory 405968 kb
Host smart-c0076aae-4c02-43dc-ba3a-5134e3f764cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655993934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3655993934
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.307122925
Short name T1327
Test name
Test status
Simulation time 18591243 ps
CPU time 0.66 seconds
Started May 26 12:45:11 PM PDT 24
Finished May 26 12:45:13 PM PDT 24
Peak memory 204128 kb
Host smart-a134f800-9c2d-4c03-9065-29b59e63036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307122925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.307122925
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3469968207
Short name T850
Test name
Test status
Simulation time 4352905442 ps
CPU time 34.17 seconds
Started May 26 12:45:12 PM PDT 24
Finished May 26 12:45:47 PM PDT 24
Peak memory 246144 kb
Host smart-4ce0eae4-267f-4798-9a79-4386ada7a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469968207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3469968207
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.566372115
Short name T573
Test name
Test status
Simulation time 1361146966 ps
CPU time 61.49 seconds
Started May 26 12:45:12 PM PDT 24
Finished May 26 12:46:14 PM PDT 24
Peak memory 324852 kb
Host smart-25e901cd-dc3b-411c-9d77-66edf9fa87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566372115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.566372115
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.545569546
Short name T37
Test name
Test status
Simulation time 39023090390 ps
CPU time 434.12 seconds
Started May 26 12:45:21 PM PDT 24
Finished May 26 12:52:36 PM PDT 24
Peak memory 2103180 kb
Host smart-4282c301-b423-4a4e-a896-ce2b24702980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545569546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.545569546
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2417386578
Short name T802
Test name
Test status
Simulation time 3087196790 ps
CPU time 15.85 seconds
Started May 26 12:45:13 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 220052 kb
Host smart-871fc289-1923-403c-9ffc-b83fbe314a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417386578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2417386578
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.304328760
Short name T355
Test name
Test status
Simulation time 1418573494 ps
CPU time 3.92 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:45:24 PM PDT 24
Peak memory 204500 kb
Host smart-0a5cfb30-f36e-4d86-8ade-4c928137eb57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304328760 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.304328760
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1608549011
Short name T1137
Test name
Test status
Simulation time 10173392437 ps
CPU time 26.78 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:48 PM PDT 24
Peak memory 323420 kb
Host smart-a1054503-af0e-4bd1-8570-73970f09513a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608549011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1608549011
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2292377492
Short name T1386
Test name
Test status
Simulation time 10111334694 ps
CPU time 74.28 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:46:33 PM PDT 24
Peak memory 602336 kb
Host smart-88847a10-7521-4acb-a8af-559c592c7bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292377492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2292377492
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3341127535
Short name T1409
Test name
Test status
Simulation time 1745051418 ps
CPU time 2.36 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:45:22 PM PDT 24
Peak memory 204452 kb
Host smart-2a417a47-374b-4efc-a7bc-0c6ab5eb69a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341127535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3341127535
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1259968057
Short name T457
Test name
Test status
Simulation time 1097018239 ps
CPU time 5.25 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:26 PM PDT 24
Peak memory 204444 kb
Host smart-eaf3a8ff-e683-4557-be50-433e35e36634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259968057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1259968057
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.584784452
Short name T561
Test name
Test status
Simulation time 7945257311 ps
CPU time 4.45 seconds
Started May 26 12:45:22 PM PDT 24
Finished May 26 12:45:27 PM PDT 24
Peak memory 204480 kb
Host smart-e626418a-258f-4d14-a881-d77974fd950e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584784452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.584784452
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4179172505
Short name T858
Test name
Test status
Simulation time 18350268187 ps
CPU time 395.68 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:51:57 PM PDT 24
Peak memory 4517840 kb
Host smart-f028bbaa-c248-4b77-a4af-647fbf2a5db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179172505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4179172505
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1108297680
Short name T846
Test name
Test status
Simulation time 5292228085 ps
CPU time 23.5 seconds
Started May 26 12:45:21 PM PDT 24
Finished May 26 12:45:45 PM PDT 24
Peak memory 204560 kb
Host smart-ed264128-37c8-49d0-b4be-0da47f3d0b06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108297680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1108297680
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3254267188
Short name T721
Test name
Test status
Simulation time 1526970730 ps
CPU time 5.07 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:26 PM PDT 24
Peak memory 204504 kb
Host smart-9bfb404b-f5fb-4db0-b4d3-737428b76849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254267188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3254267188
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1909095259
Short name T564
Test name
Test status
Simulation time 32713222492 ps
CPU time 283.93 seconds
Started May 26 12:45:19 PM PDT 24
Finished May 26 12:50:04 PM PDT 24
Peak memory 3266120 kb
Host smart-977fd43d-7d58-4ea9-b2d9-905dbbedee09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909095259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1909095259
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.241035692
Short name T248
Test name
Test status
Simulation time 5423381844 ps
CPU time 70.97 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:46:32 PM PDT 24
Peak memory 449200 kb
Host smart-bf89a2e6-75cd-4cc5-b46f-f2f16cc2789b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241035692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.241035692
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.639270172
Short name T1187
Test name
Test status
Simulation time 9324641230 ps
CPU time 7.57 seconds
Started May 26 12:45:23 PM PDT 24
Finished May 26 12:45:32 PM PDT 24
Peak memory 218048 kb
Host smart-7340a671-72be-4e9a-a7bb-6b07e97e93d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639270172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.639270172
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1181281766
Short name T902
Test name
Test status
Simulation time 42269554 ps
CPU time 0.64 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:45:38 PM PDT 24
Peak memory 204092 kb
Host smart-c8801899-7196-4355-8df7-b632021e6c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181281766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1181281766
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.744111851
Short name T866
Test name
Test status
Simulation time 191778667 ps
CPU time 3.2 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 236080 kb
Host smart-2b5066a9-7fd5-423a-bda8-e385385dd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744111851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.744111851
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1192739276
Short name T374
Test name
Test status
Simulation time 537603103 ps
CPU time 28.24 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:45:56 PM PDT 24
Peak memory 300036 kb
Host smart-58a590ff-90bf-4fe6-8039-399e4be9d48a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192739276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1192739276
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2616406446
Short name T47
Test name
Test status
Simulation time 1586451003 ps
CPU time 47.44 seconds
Started May 26 12:45:26 PM PDT 24
Finished May 26 12:46:14 PM PDT 24
Peak memory 510668 kb
Host smart-f48a9f29-8ba2-484e-96eb-a0d4339d4832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616406446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2616406446
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1101112043
Short name T593
Test name
Test status
Simulation time 6295368197 ps
CPU time 115.88 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:47:24 PM PDT 24
Peak memory 594232 kb
Host smart-12e20b78-1a94-475b-9e28-f40284fb47ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101112043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1101112043
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1806585006
Short name T905
Test name
Test status
Simulation time 681449792 ps
CPU time 1.1 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 204472 kb
Host smart-03c48152-83d9-4865-8a26-8987df5eef16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806585006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1806585006
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1790494239
Short name T735
Test name
Test status
Simulation time 1077305900 ps
CPU time 4.56 seconds
Started May 26 12:45:26 PM PDT 24
Finished May 26 12:45:32 PM PDT 24
Peak memory 204448 kb
Host smart-c0fca447-f7b3-4b97-9c3d-b841b3dd03b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790494239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1790494239
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.13207301
Short name T1325
Test name
Test status
Simulation time 7184345716 ps
CPU time 259.1 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:49:48 PM PDT 24
Peak memory 1063180 kb
Host smart-c64981c4-b169-4c08-8e37-8d22d3096452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13207301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.13207301
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2688844772
Short name T724
Test name
Test status
Simulation time 1974303450 ps
CPU time 6.36 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:45:42 PM PDT 24
Peak memory 204512 kb
Host smart-42ac4a7b-3924-4d88-acb1-0f70bc51ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688844772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2688844772
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.410255505
Short name T803
Test name
Test status
Simulation time 90590530 ps
CPU time 0.67 seconds
Started May 26 12:45:29 PM PDT 24
Finished May 26 12:45:30 PM PDT 24
Peak memory 204252 kb
Host smart-e84bcd77-f27a-4a1a-b841-e62132b2201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410255505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.410255505
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3636291310
Short name T586
Test name
Test status
Simulation time 5181048761 ps
CPU time 210.63 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:48:59 PM PDT 24
Peak memory 221688 kb
Host smart-f1d08624-fd66-46f6-8c9d-67554f8fc726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636291310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3636291310
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3632178154
Short name T1001
Test name
Test status
Simulation time 8207435530 ps
CPU time 35.88 seconds
Started May 26 12:45:20 PM PDT 24
Finished May 26 12:45:56 PM PDT 24
Peak memory 384600 kb
Host smart-db1e161c-754e-4529-b9e8-b80cbf510b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632178154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3632178154
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.381804230
Short name T1371
Test name
Test status
Simulation time 2863907149 ps
CPU time 13.11 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:41 PM PDT 24
Peak memory 220712 kb
Host smart-e915e37b-4351-423c-9b16-5a73d0a1aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381804230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.381804230
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1731032248
Short name T411
Test name
Test status
Simulation time 3468417325 ps
CPU time 4.46 seconds
Started May 26 12:45:30 PM PDT 24
Finished May 26 12:45:35 PM PDT 24
Peak memory 212684 kb
Host smart-6f7a5c1c-2792-4100-b769-7ea58af2dd8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731032248 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1731032248
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1491463267
Short name T1378
Test name
Test status
Simulation time 10165776046 ps
CPU time 14.55 seconds
Started May 26 12:45:31 PM PDT 24
Finished May 26 12:45:46 PM PDT 24
Peak memory 283748 kb
Host smart-27cffd99-f50d-4f00-8ce7-9066fefcfbbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491463267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1491463267
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.634284815
Short name T1222
Test name
Test status
Simulation time 1331907421 ps
CPU time 5.72 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:45:41 PM PDT 24
Peak memory 204420 kb
Host smart-cd26288c-6312-4c4d-a9ee-66ab03851226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634284815 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.634284815
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1696616438
Short name T283
Test name
Test status
Simulation time 1065425953 ps
CPU time 3.05 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:45:40 PM PDT 24
Peak memory 204416 kb
Host smart-ed2f59d2-6b07-4ed5-ba09-41cff11179b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696616438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1696616438
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3871680134
Short name T1057
Test name
Test status
Simulation time 512317297 ps
CPU time 2.81 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:32 PM PDT 24
Peak memory 204644 kb
Host smart-a8bcee20-7c9d-4850-acdf-e4b9d9a2c1fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871680134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3871680134
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3208936066
Short name T1233
Test name
Test status
Simulation time 4415972997 ps
CPU time 6.46 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:35 PM PDT 24
Peak memory 212824 kb
Host smart-eedce3af-481d-4f42-9db7-0d8e8894a143
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208936066 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3208936066
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2400320291
Short name T623
Test name
Test status
Simulation time 23703521994 ps
CPU time 173.16 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:48:20 PM PDT 24
Peak memory 2736648 kb
Host smart-d1017feb-1445-404a-b3e0-15295041694d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400320291 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2400320291
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1770809262
Short name T1148
Test name
Test status
Simulation time 2612123225 ps
CPU time 22.56 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:51 PM PDT 24
Peak memory 204432 kb
Host smart-a6e0c296-a22f-4bc7-b515-83822e2684c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770809262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1770809262
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2967116474
Short name T117
Test name
Test status
Simulation time 2114017559 ps
CPU time 18.91 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:45:47 PM PDT 24
Peak memory 215104 kb
Host smart-bec19f1c-2b8e-43ad-9893-1541bcba5ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967116474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2967116474
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3521000622
Short name T370
Test name
Test status
Simulation time 44476481744 ps
CPU time 706.68 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:57:15 PM PDT 24
Peak memory 6069824 kb
Host smart-b8e47f28-d71d-4380-b3a4-c6dc5c69b455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521000622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3521000622
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.181232655
Short name T365
Test name
Test status
Simulation time 34440427601 ps
CPU time 826.5 seconds
Started May 26 12:45:27 PM PDT 24
Finished May 26 12:59:14 PM PDT 24
Peak memory 3678868 kb
Host smart-09e5067e-fbbb-4144-a565-845b81b3c359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181232655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.181232655
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.434976094
Short name T77
Test name
Test status
Simulation time 7919902641 ps
CPU time 8.04 seconds
Started May 26 12:45:28 PM PDT 24
Finished May 26 12:45:37 PM PDT 24
Peak memory 220940 kb
Host smart-3d541d42-8f9d-4c86-ab3e-88b7ec75d5f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434976094 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.434976094
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3702644269
Short name T1088
Test name
Test status
Simulation time 37555292 ps
CPU time 0.61 seconds
Started May 26 12:45:49 PM PDT 24
Finished May 26 12:45:50 PM PDT 24
Peak memory 204092 kb
Host smart-966649c2-17c9-48ae-9692-1722914561e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702644269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3702644269
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2612396715
Short name T395
Test name
Test status
Simulation time 281920553 ps
CPU time 1.34 seconds
Started May 26 12:45:37 PM PDT 24
Finished May 26 12:45:39 PM PDT 24
Peak memory 204680 kb
Host smart-a4d8993e-0bf2-4a38-85e7-0b5aa4de4574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612396715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2612396715
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.985547517
Short name T529
Test name
Test status
Simulation time 1355637099 ps
CPU time 7.14 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:45:44 PM PDT 24
Peak memory 284120 kb
Host smart-bee45908-4a1c-4cfe-86fd-c824e7a12269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985547517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.985547517
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1908847759
Short name T725
Test name
Test status
Simulation time 4232083781 ps
CPU time 63.79 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:46:41 PM PDT 24
Peak memory 722300 kb
Host smart-1a9fac7f-06cd-4b61-9752-c1c3124058df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908847759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1908847759
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.497510806
Short name T1021
Test name
Test status
Simulation time 6510797199 ps
CPU time 111.04 seconds
Started May 26 12:45:38 PM PDT 24
Finished May 26 12:47:30 PM PDT 24
Peak memory 517740 kb
Host smart-09745da2-f9cd-42da-bc3f-46cdb6a2e0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497510806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.497510806
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.4130389651
Short name T63
Test name
Test status
Simulation time 110304804 ps
CPU time 0.89 seconds
Started May 26 12:45:37 PM PDT 24
Finished May 26 12:45:39 PM PDT 24
Peak memory 204328 kb
Host smart-bff9bfd8-62ce-40f3-8909-5dc6db8ed215
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130389651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.4130389651
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.680681885
Short name T468
Test name
Test status
Simulation time 327450062 ps
CPU time 3.7 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:45:39 PM PDT 24
Peak memory 204424 kb
Host smart-87715a53-3ff1-4f65-98b2-5aedf8f53f19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680681885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
680681885
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2428554992
Short name T594
Test name
Test status
Simulation time 4538424242 ps
CPU time 146.36 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:48:02 PM PDT 24
Peak memory 1308184 kb
Host smart-d94d031b-54a5-4c4e-a760-5a27e6fe9dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428554992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2428554992
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3838038940
Short name T819
Test name
Test status
Simulation time 360459205 ps
CPU time 4.94 seconds
Started May 26 12:45:46 PM PDT 24
Finished May 26 12:45:52 PM PDT 24
Peak memory 204452 kb
Host smart-4081df28-c64c-4e5e-b549-eeda2ca559f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838038940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3838038940
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2761258776
Short name T353
Test name
Test status
Simulation time 2203040833 ps
CPU time 105.48 seconds
Started May 26 12:45:46 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 417052 kb
Host smart-7fad7dcd-1a3a-4bb4-937d-b1f9f4ac5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761258776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2761258776
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3403345122
Short name T748
Test name
Test status
Simulation time 36133735 ps
CPU time 0.63 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:45:37 PM PDT 24
Peak memory 204128 kb
Host smart-2a99fcd5-c442-4cfb-8a63-86ff69665013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403345122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3403345122
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.4113703105
Short name T912
Test name
Test status
Simulation time 6202885817 ps
CPU time 339.2 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:51:16 PM PDT 24
Peak memory 670188 kb
Host smart-2de6b6f8-761d-470f-9f49-dce5dc274123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113703105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.4113703105
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.520939759
Short name T798
Test name
Test status
Simulation time 4989829789 ps
CPU time 55.08 seconds
Started May 26 12:45:41 PM PDT 24
Finished May 26 12:46:37 PM PDT 24
Peak memory 306620 kb
Host smart-465b53df-6ba0-4fc5-adc7-0a62e9054a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520939759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.520939759
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3233336672
Short name T124
Test name
Test status
Simulation time 30728396523 ps
CPU time 353.44 seconds
Started May 26 12:45:36 PM PDT 24
Finished May 26 12:51:30 PM PDT 24
Peak memory 2122076 kb
Host smart-1190276e-a585-41eb-a72b-d9ca0f8c960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233336672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3233336672
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2337945843
Short name T302
Test name
Test status
Simulation time 567035401 ps
CPU time 10.01 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:45:45 PM PDT 24
Peak memory 215320 kb
Host smart-f6a3cdfd-59c3-4225-bf90-eec2bc36e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337945843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2337945843
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.37455961
Short name T774
Test name
Test status
Simulation time 4247633333 ps
CPU time 3.26 seconds
Started May 26 12:45:46 PM PDT 24
Finished May 26 12:45:51 PM PDT 24
Peak memory 204636 kb
Host smart-103f10e3-5843-4a23-b120-c309969e0427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37455961 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_bad_addr.37455961
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3832214483
Short name T881
Test name
Test status
Simulation time 10076764742 ps
CPU time 44.83 seconds
Started May 26 12:45:45 PM PDT 24
Finished May 26 12:46:30 PM PDT 24
Peak memory 339196 kb
Host smart-589aeaf6-d78d-4e0f-88c9-86bc72cad44f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832214483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3832214483
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3473630870
Short name T522
Test name
Test status
Simulation time 10163841955 ps
CPU time 73.45 seconds
Started May 26 12:45:45 PM PDT 24
Finished May 26 12:46:59 PM PDT 24
Peak memory 647132 kb
Host smart-3672f8a0-5e67-4d1e-bfc6-6ba4b7bfc8f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473630870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3473630870
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.782249510
Short name T816
Test name
Test status
Simulation time 1605546365 ps
CPU time 3.65 seconds
Started May 26 12:45:45 PM PDT 24
Finished May 26 12:45:50 PM PDT 24
Peak memory 204388 kb
Host smart-3af89638-67ed-4660-ba01-4911e69f165d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782249510 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.782249510
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.1460916765
Short name T1145
Test name
Test status
Simulation time 1125067044 ps
CPU time 5.56 seconds
Started May 26 12:45:46 PM PDT 24
Finished May 26 12:45:53 PM PDT 24
Peak memory 204464 kb
Host smart-98b12e90-819c-4f5e-825e-f49d11a9fe21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460916765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.1460916765
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2653110001
Short name T611
Test name
Test status
Simulation time 1281004419 ps
CPU time 2.56 seconds
Started May 26 12:45:49 PM PDT 24
Finished May 26 12:45:51 PM PDT 24
Peak memory 204500 kb
Host smart-3ca7a48f-054b-4f9c-8666-82b230719fd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653110001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2653110001
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3809877564
Short name T113
Test name
Test status
Simulation time 948646606 ps
CPU time 5.46 seconds
Started May 26 12:45:35 PM PDT 24
Finished May 26 12:45:41 PM PDT 24
Peak memory 206228 kb
Host smart-774f2f8d-b0a5-4c4e-ab13-104779813bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809877564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3809877564
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1948182467
Short name T750
Test name
Test status
Simulation time 4885816634 ps
CPU time 44.96 seconds
Started May 26 12:45:39 PM PDT 24
Finished May 26 12:46:25 PM PDT 24
Peak memory 1287828 kb
Host smart-84ec7eaa-9720-4abb-a38a-b4cad5688659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948182467 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1948182467
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3642795098
Short name T1184
Test name
Test status
Simulation time 838788084 ps
CPU time 30.57 seconds
Started May 26 12:45:40 PM PDT 24
Finished May 26 12:46:11 PM PDT 24
Peak memory 204432 kb
Host smart-01c38400-b558-42a4-b828-898e31bbfd6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642795098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3642795098
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1265220929
Short name T206
Test name
Test status
Simulation time 749811084 ps
CPU time 13.1 seconds
Started May 26 12:45:37 PM PDT 24
Finished May 26 12:45:51 PM PDT 24
Peak memory 212048 kb
Host smart-e266240a-928b-4874-96e4-cf060159e63f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265220929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1265220929
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1060216951
Short name T694
Test name
Test status
Simulation time 8273803616 ps
CPU time 16.14 seconds
Started May 26 12:45:38 PM PDT 24
Finished May 26 12:45:55 PM PDT 24
Peak memory 204532 kb
Host smart-1886127b-a26d-4131-b982-d26709f12dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060216951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1060216951
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2512712885
Short name T1037
Test name
Test status
Simulation time 22468051947 ps
CPU time 186.8 seconds
Started May 26 12:45:38 PM PDT 24
Finished May 26 12:48:45 PM PDT 24
Peak memory 1490788 kb
Host smart-265ca625-70b8-44fe-901a-8f205f72aa28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512712885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2512712885
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3971174781
Short name T375
Test name
Test status
Simulation time 4884305533 ps
CPU time 7.15 seconds
Started May 26 12:45:41 PM PDT 24
Finished May 26 12:45:49 PM PDT 24
Peak memory 220804 kb
Host smart-702475c7-fedf-4622-9e1f-eb3cc34fb565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971174781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3971174781
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2555055344
Short name T1366
Test name
Test status
Simulation time 18366715 ps
CPU time 0.63 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:07 PM PDT 24
Peak memory 204096 kb
Host smart-76e8efec-2359-432c-b0b0-34e4dd1ff806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555055344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2555055344
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3900614999
Short name T66
Test name
Test status
Simulation time 344488284 ps
CPU time 2.3 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:02 PM PDT 24
Peak memory 220940 kb
Host smart-153dd024-b3f0-4f5b-a28f-fb009a457e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900614999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3900614999
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.4189459060
Short name T626
Test name
Test status
Simulation time 1070442936 ps
CPU time 15.53 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:15 PM PDT 24
Peak memory 222348 kb
Host smart-b1fd20ba-1843-412d-b555-ccd843360d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189459060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.4189459060
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2504256836
Short name T1306
Test name
Test status
Simulation time 1431373190 ps
CPU time 45.05 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:46:44 PM PDT 24
Peak memory 455700 kb
Host smart-4173bd1a-b8f8-4363-8522-a0b4cbc1853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504256836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2504256836
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1755785361
Short name T289
Test name
Test status
Simulation time 3743375701 ps
CPU time 118.53 seconds
Started May 26 12:45:47 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 539048 kb
Host smart-b2e5bf1b-dc4f-4528-8982-dec29c7c862e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755785361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1755785361
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.472574440
Short name T584
Test name
Test status
Simulation time 1742857485 ps
CPU time 1.07 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:46:00 PM PDT 24
Peak memory 204484 kb
Host smart-547f9f42-2119-4bc0-b21f-dc2cea2bafff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472574440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.472574440
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3928707819
Short name T634
Test name
Test status
Simulation time 932276224 ps
CPU time 6.94 seconds
Started May 26 12:46:00 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 250440 kb
Host smart-68b67217-d7dd-4074-b741-c3f6ff1ec343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928707819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3928707819
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1644275888
Short name T398
Test name
Test status
Simulation time 4224457643 ps
CPU time 133.59 seconds
Started May 26 12:45:48 PM PDT 24
Finished May 26 12:48:02 PM PDT 24
Peak memory 1242696 kb
Host smart-8e6b3686-78aa-44aa-a9b0-8112e4b03c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644275888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1644275888
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2793052111
Short name T1231
Test name
Test status
Simulation time 1885438241 ps
CPU time 6.49 seconds
Started May 26 12:46:03 PM PDT 24
Finished May 26 12:46:10 PM PDT 24
Peak memory 204592 kb
Host smart-83d5a6e7-5ca4-4aa3-8fcb-d5dce30de21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793052111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2793052111
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1835614577
Short name T849
Test name
Test status
Simulation time 16010299101 ps
CPU time 108.6 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:47:55 PM PDT 24
Peak memory 443732 kb
Host smart-ffb68ea7-b1c6-43b8-ad6e-fc6640f22b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835614577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1835614577
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2445590815
Short name T756
Test name
Test status
Simulation time 35545066 ps
CPU time 0.66 seconds
Started May 26 12:45:47 PM PDT 24
Finished May 26 12:45:48 PM PDT 24
Peak memory 204208 kb
Host smart-9ab19609-0d63-4472-a8eb-9facffd355ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445590815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2445590815
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3531985261
Short name T1189
Test name
Test status
Simulation time 3001930564 ps
CPU time 87.72 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:47:27 PM PDT 24
Peak memory 277356 kb
Host smart-822f7d18-26dd-4d85-8985-326b05c4cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531985261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3531985261
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1383201894
Short name T1223
Test name
Test status
Simulation time 5492865201 ps
CPU time 65.22 seconds
Started May 26 12:45:46 PM PDT 24
Finished May 26 12:46:53 PM PDT 24
Peak memory 349464 kb
Host smart-5f6f670c-9806-4dc8-9d0f-b0daf64d61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383201894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1383201894
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2903183896
Short name T265
Test name
Test status
Simulation time 50774185966 ps
CPU time 2673.99 seconds
Started May 26 12:45:57 PM PDT 24
Finished May 26 01:30:32 PM PDT 24
Peak memory 2374092 kb
Host smart-99124796-d963-4229-bfd8-f2315501365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903183896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2903183896
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3338236609
Short name T393
Test name
Test status
Simulation time 2366214187 ps
CPU time 27.09 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:27 PM PDT 24
Peak memory 212808 kb
Host smart-7ed7213c-3648-440b-af77-3da61553ba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338236609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3338236609
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1368174937
Short name T486
Test name
Test status
Simulation time 1072411273 ps
CPU time 5.2 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:46:04 PM PDT 24
Peak memory 212680 kb
Host smart-81d7f17a-aab8-4969-bf6c-d41a9276f045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368174937 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1368174937
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2789037258
Short name T911
Test name
Test status
Simulation time 10163031693 ps
CPU time 40.28 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:40 PM PDT 24
Peak memory 356996 kb
Host smart-18a56ab5-5de7-48d4-8d26-56d2856ab0aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789037258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2789037258
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1014298354
Short name T1030
Test name
Test status
Simulation time 10224944811 ps
CPU time 25.6 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:25 PM PDT 24
Peak memory 333072 kb
Host smart-86d0d605-6916-4a5a-8f73-bbd618bf6882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014298354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1014298354
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2534371109
Short name T1450
Test name
Test status
Simulation time 1594265517 ps
CPU time 4.21 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:46:11 PM PDT 24
Peak memory 204508 kb
Host smart-9337f9e5-68c1-4585-9049-14851f14de75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534371109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2534371109
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.519565708
Short name T508
Test name
Test status
Simulation time 1081014748 ps
CPU time 5.86 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:46:10 PM PDT 24
Peak memory 204492 kb
Host smart-2bf90032-49ed-4d58-a71f-e9c02e543ae7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519565708 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.519565708
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3281199038
Short name T793
Test name
Test status
Simulation time 387755857 ps
CPU time 2.85 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:46:01 PM PDT 24
Peak memory 204548 kb
Host smart-3076c195-99a3-4715-a336-29f4729ce429
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281199038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3281199038
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.156582984
Short name T883
Test name
Test status
Simulation time 4958644525 ps
CPU time 4.92 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:46:04 PM PDT 24
Peak memory 204368 kb
Host smart-bfe39ee0-1b0c-40cd-92d9-c49947bcdee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156582984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.156582984
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.822186220
Short name T771
Test name
Test status
Simulation time 10714895708 ps
CPU time 3.93 seconds
Started May 26 12:45:59 PM PDT 24
Finished May 26 12:46:03 PM PDT 24
Peak memory 244992 kb
Host smart-cb7ca077-b724-4fa0-a35a-132f3760bcfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822186220 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.822186220
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.891007438
Short name T1239
Test name
Test status
Simulation time 1184912471 ps
CPU time 36.65 seconds
Started May 26 12:45:57 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 204420 kb
Host smart-7d0a1706-4e37-4657-897a-afc84879442d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891007438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.891007438
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3990556847
Short name T447
Test name
Test status
Simulation time 1913470782 ps
CPU time 15.99 seconds
Started May 26 12:45:57 PM PDT 24
Finished May 26 12:46:13 PM PDT 24
Peak memory 215624 kb
Host smart-b963065c-487d-4af0-ab02-af6295713d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990556847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3990556847
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4187746189
Short name T1122
Test name
Test status
Simulation time 61558901385 ps
CPU time 751.8 seconds
Started May 26 12:45:58 PM PDT 24
Finished May 26 12:58:31 PM PDT 24
Peak memory 5285504 kb
Host smart-eff1a17f-7938-4bd1-810f-fffdb951a4e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187746189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4187746189
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1700566023
Short name T660
Test name
Test status
Simulation time 7930674915 ps
CPU time 7.66 seconds
Started May 26 12:45:57 PM PDT 24
Finished May 26 12:46:05 PM PDT 24
Peak memory 220808 kb
Host smart-83b20754-8619-42c9-967e-3ac8cfb1a90c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700566023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1700566023
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1776057322
Short name T410
Test name
Test status
Simulation time 16249035 ps
CPU time 0.64 seconds
Started May 26 12:46:17 PM PDT 24
Finished May 26 12:46:18 PM PDT 24
Peak memory 204092 kb
Host smart-8b0859aa-799a-4917-963d-900bcc611834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776057322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1776057322
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2077831976
Short name T54
Test name
Test status
Simulation time 328011206 ps
CPU time 1.84 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 220820 kb
Host smart-f0f1b0fc-54c9-4aef-8f30-d539d1b15dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077831976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2077831976
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3623821084
Short name T1396
Test name
Test status
Simulation time 319648944 ps
CPU time 6.28 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:46:11 PM PDT 24
Peak memory 272740 kb
Host smart-1ab4498b-e01e-4a09-99c0-98c7adcbf4c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623821084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3623821084
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.688297540
Short name T483
Test name
Test status
Simulation time 6996790041 ps
CPU time 123.21 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:48:10 PM PDT 24
Peak memory 624088 kb
Host smart-cda77af4-d748-451f-9254-bc0d561e86a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688297540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.688297540
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3579335295
Short name T81
Test name
Test status
Simulation time 26831090053 ps
CPU time 55.89 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:47:01 PM PDT 24
Peak memory 606524 kb
Host smart-8fc42960-97a1-4273-837c-a49ad4afd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579335295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3579335295
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.4288937296
Short name T232
Test name
Test status
Simulation time 186022334 ps
CPU time 0.99 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:06 PM PDT 24
Peak memory 204424 kb
Host smart-48f2a4c6-599a-4234-bad4-fa4161c14500
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288937296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.4288937296
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3538773
Short name T1075
Test name
Test status
Simulation time 989039720 ps
CPU time 4.25 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:09 PM PDT 24
Peak memory 204420 kb
Host smart-5c9108b7-8171-4aaf-ab3b-0800d072d28d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.3538773
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3529469620
Short name T405
Test name
Test status
Simulation time 22099670031 ps
CPU time 130.48 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:48:15 PM PDT 24
Peak memory 1195864 kb
Host smart-b48ad896-5050-472c-b14d-4e84a99f4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529469620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3529469620
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1776864254
Short name T940
Test name
Test status
Simulation time 792498947 ps
CPU time 7.8 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:46:21 PM PDT 24
Peak memory 204408 kb
Host smart-0e7d77b8-08c8-410d-a009-ebabce6d4ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776864254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1776864254
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.746581370
Short name T403
Test name
Test status
Simulation time 9729821710 ps
CPU time 37.96 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:46:52 PM PDT 24
Peak memory 375088 kb
Host smart-76992b22-d4b6-4685-9e9e-f834b6b41218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746581370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.746581370
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1610343979
Short name T1054
Test name
Test status
Simulation time 68287381 ps
CPU time 0.66 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 204160 kb
Host smart-ce653215-0212-48fd-9600-9f556c9cf140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610343979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1610343979
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2561506562
Short name T727
Test name
Test status
Simulation time 48042763735 ps
CPU time 222.05 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:49:49 PM PDT 24
Peak memory 217156 kb
Host smart-e5638767-84f2-4b45-92da-48d56cbd27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561506562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2561506562
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1207627087
Short name T1140
Test name
Test status
Simulation time 6514932504 ps
CPU time 76.47 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:47:22 PM PDT 24
Peak memory 297968 kb
Host smart-d2cb6964-1175-4275-a34c-9a8ffeb29485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207627087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1207627087
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3419297792
Short name T125
Test name
Test status
Simulation time 185241199020 ps
CPU time 1018.49 seconds
Started May 26 12:46:07 PM PDT 24
Finished May 26 01:03:06 PM PDT 24
Peak memory 2762228 kb
Host smart-2a227dba-396c-4c1a-9d8d-0fc9e271fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419297792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3419297792
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3563035750
Short name T1345
Test name
Test status
Simulation time 1053118456 ps
CPU time 11.16 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:16 PM PDT 24
Peak memory 212628 kb
Host smart-a73ee4db-a84a-4ac6-a6e4-35424db618a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563035750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3563035750
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3071525659
Short name T742
Test name
Test status
Simulation time 1415865492 ps
CPU time 3.45 seconds
Started May 26 12:46:14 PM PDT 24
Finished May 26 12:46:18 PM PDT 24
Peak memory 204444 kb
Host smart-c531f221-b730-43c7-9782-4fe15ef1a711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071525659 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3071525659
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1565941038
Short name T1263
Test name
Test status
Simulation time 10107836198 ps
CPU time 49.72 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:46:56 PM PDT 24
Peak memory 315504 kb
Host smart-c4baf78c-8dc3-47bf-9c33-1de5481ec936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565941038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1565941038
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2276605552
Short name T603
Test name
Test status
Simulation time 10087456654 ps
CPU time 65.5 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:47:13 PM PDT 24
Peak memory 534200 kb
Host smart-97ef7507-2650-4a56-ac8e-980972a2884c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276605552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2276605552
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3918656808
Short name T823
Test name
Test status
Simulation time 1038312665 ps
CPU time 2.77 seconds
Started May 26 12:46:16 PM PDT 24
Finished May 26 12:46:19 PM PDT 24
Peak memory 204444 kb
Host smart-0ba3d90a-484e-4aa0-a9df-eed585aeff75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918656808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3918656808
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.3705855132
Short name T277
Test name
Test status
Simulation time 1239093443 ps
CPU time 2.01 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:46:16 PM PDT 24
Peak memory 204472 kb
Host smart-8a62bae5-3913-4c6c-8479-d511911dc80b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705855132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.3705855132
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4249033810
Short name T1302
Test name
Test status
Simulation time 1266391248 ps
CPU time 2.17 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:46:15 PM PDT 24
Peak memory 204672 kb
Host smart-848d2791-f889-457b-82e0-1e40d6af716d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249033810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4249033810
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.858854979
Short name T5
Test name
Test status
Simulation time 2921343015 ps
CPU time 5.54 seconds
Started May 26 12:46:06 PM PDT 24
Finished May 26 12:46:12 PM PDT 24
Peak memory 206820 kb
Host smart-7db966ef-37c3-4215-a7ea-8909a7bf6cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858854979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.858854979
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2967556645
Short name T939
Test name
Test status
Simulation time 12964851605 ps
CPU time 90.4 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:47:34 PM PDT 24
Peak memory 1529984 kb
Host smart-74bdcd1a-2400-4139-8c91-f2055d309e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967556645 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2967556645
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3620552717
Short name T431
Test name
Test status
Simulation time 741106519 ps
CPU time 28.38 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:46:33 PM PDT 24
Peak memory 204460 kb
Host smart-f2566a51-9bfe-4b3e-b07c-63094f45a556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620552717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3620552717
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.559190873
Short name T720
Test name
Test status
Simulation time 1739280100 ps
CPU time 32.66 seconds
Started May 26 12:46:07 PM PDT 24
Finished May 26 12:46:40 PM PDT 24
Peak memory 225876 kb
Host smart-30d3ea8d-8bfe-4a15-8f34-fbe933cb7f0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559190873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.559190873
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1311658872
Short name T499
Test name
Test status
Simulation time 40697165156 ps
CPU time 87.98 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:47:34 PM PDT 24
Peak memory 1335952 kb
Host smart-8561ef43-6dc2-4fdb-8ac3-dd3a7cba7006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311658872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1311658872
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3087994875
Short name T1127
Test name
Test status
Simulation time 17508339379 ps
CPU time 82.46 seconds
Started May 26 12:46:05 PM PDT 24
Finished May 26 12:47:29 PM PDT 24
Peak memory 958404 kb
Host smart-4454aca4-9681-4c34-8e9f-2f1f78123214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087994875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3087994875
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3181680535
Short name T361
Test name
Test status
Simulation time 1311001572 ps
CPU time 7.08 seconds
Started May 26 12:46:04 PM PDT 24
Finished May 26 12:46:12 PM PDT 24
Peak memory 217040 kb
Host smart-86084673-d0a9-453b-b273-4dd5aaa4fc43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181680535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3181680535
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1479100081
Short name T1365
Test name
Test status
Simulation time 34441652 ps
CPU time 0.6 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 204064 kb
Host smart-97367bed-0f08-4653-a61a-548c2131e54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479100081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1479100081
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3919523595
Short name T328
Test name
Test status
Simulation time 717037907 ps
CPU time 2.1 seconds
Started May 26 12:46:24 PM PDT 24
Finished May 26 12:46:27 PM PDT 24
Peak memory 212736 kb
Host smart-3c95c05a-aef6-45e2-b465-e2e7e57a7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919523595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3919523595
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2938088773
Short name T464
Test name
Test status
Simulation time 381837130 ps
CPU time 17.58 seconds
Started May 26 12:46:17 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 263088 kb
Host smart-7fa30726-aefb-441d-9242-0cbd1c4bd202
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938088773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2938088773
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.4244346645
Short name T154
Test name
Test status
Simulation time 10083508890 ps
CPU time 65.2 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:47:19 PM PDT 24
Peak memory 566468 kb
Host smart-067879e0-9d7a-4276-80aa-7bfc67f73464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244346645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.4244346645
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1647601134
Short name T937
Test name
Test status
Simulation time 3513502075 ps
CPU time 53.64 seconds
Started May 26 12:46:15 PM PDT 24
Finished May 26 12:47:09 PM PDT 24
Peak memory 640308 kb
Host smart-df527fff-06e6-4b8e-98eb-01849630f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647601134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1647601134
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1586829060
Short name T931
Test name
Test status
Simulation time 929165684 ps
CPU time 12.04 seconds
Started May 26 12:46:17 PM PDT 24
Finished May 26 12:46:29 PM PDT 24
Peak memory 204436 kb
Host smart-248b5c58-b797-4531-aaa5-74e5c2580954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586829060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1586829060
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3555561404
Short name T894
Test name
Test status
Simulation time 987814028 ps
CPU time 7.82 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:46:42 PM PDT 24
Peak memory 204524 kb
Host smart-01228b95-23b0-49ad-8185-d1dd29cb2ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555561404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3555561404
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2122738228
Short name T726
Test name
Test status
Simulation time 9387708738 ps
CPU time 101.97 seconds
Started May 26 12:46:35 PM PDT 24
Finished May 26 12:48:17 PM PDT 24
Peak memory 371700 kb
Host smart-25a05706-8591-4e57-a983-e0d143ab3d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122738228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2122738228
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.4016374270
Short name T367
Test name
Test status
Simulation time 49692121 ps
CPU time 0.66 seconds
Started May 26 12:46:13 PM PDT 24
Finished May 26 12:46:14 PM PDT 24
Peak memory 204248 kb
Host smart-1e85d85a-40fe-4f61-9802-33837676e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016374270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.4016374270
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1368700366
Short name T478
Test name
Test status
Simulation time 2467084135 ps
CPU time 48.93 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:47:11 PM PDT 24
Peak memory 618764 kb
Host smart-479ac6f9-33ec-4802-8603-434bb9dd2a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368700366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1368700366
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1622323075
Short name T1058
Test name
Test status
Simulation time 5996807409 ps
CPU time 25.4 seconds
Started May 26 12:46:14 PM PDT 24
Finished May 26 12:46:40 PM PDT 24
Peak memory 258480 kb
Host smart-365469e5-54bb-4cbd-b71a-72d5fe2acf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622323075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1622323075
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3154579733
Short name T909
Test name
Test status
Simulation time 32089915311 ps
CPU time 598.44 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:56:21 PM PDT 24
Peak memory 1362680 kb
Host smart-51a6ac3c-831c-4e3f-9525-f950e3cbf43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154579733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3154579733
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.843895333
Short name T317
Test name
Test status
Simulation time 498026719 ps
CPU time 8.8 seconds
Started May 26 12:46:23 PM PDT 24
Finished May 26 12:46:32 PM PDT 24
Peak memory 220136 kb
Host smart-24cf942b-2965-42a9-98cd-393209f3cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843895333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.843895333
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1254015375
Short name T1113
Test name
Test status
Simulation time 1406301183 ps
CPU time 3.97 seconds
Started May 26 12:46:23 PM PDT 24
Finished May 26 12:46:27 PM PDT 24
Peak memory 212660 kb
Host smart-fd3d5d74-7ea3-45cd-a6c5-72feecefeadf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254015375 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1254015375
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2009398544
Short name T799
Test name
Test status
Simulation time 10107328625 ps
CPU time 36.13 seconds
Started May 26 12:46:23 PM PDT 24
Finished May 26 12:47:00 PM PDT 24
Peak memory 327308 kb
Host smart-f60330f2-8132-4695-9782-582427fd1175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009398544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2009398544
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3962370865
Short name T1287
Test name
Test status
Simulation time 10234541185 ps
CPU time 34.46 seconds
Started May 26 12:46:24 PM PDT 24
Finished May 26 12:46:59 PM PDT 24
Peak memory 464540 kb
Host smart-c4f78436-554a-4490-ba03-eedb54c7ac36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962370865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3962370865
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.2632311846
Short name T1034
Test name
Test status
Simulation time 1293277851 ps
CPU time 5.76 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:41 PM PDT 24
Peak memory 204472 kb
Host smart-486295f6-5478-4950-869c-edfb82035b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632311846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.2632311846
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2165289842
Short name T555
Test name
Test status
Simulation time 1131266440 ps
CPU time 3.38 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:38 PM PDT 24
Peak memory 204512 kb
Host smart-c7250682-4ea4-497a-941f-3af2e7e1b8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165289842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2165289842
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1814324077
Short name T325
Test name
Test status
Simulation time 668443838 ps
CPU time 2.32 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:46:25 PM PDT 24
Peak memory 204544 kb
Host smart-70a5140a-71af-480f-8030-ebfd1c80b79b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814324077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1814324077
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2422055932
Short name T1333
Test name
Test status
Simulation time 1192222771 ps
CPU time 3.59 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:46:26 PM PDT 24
Peak memory 204488 kb
Host smart-76bcc749-c5cb-45c8-8b61-f171a3e5b223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422055932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2422055932
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.234599045
Short name T1248
Test name
Test status
Simulation time 2676435175 ps
CPU time 12.73 seconds
Started May 26 12:46:24 PM PDT 24
Finished May 26 12:46:37 PM PDT 24
Peak memory 605980 kb
Host smart-4694778d-19cc-4a44-8c6c-e7e47fb3efa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234599045 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.234599045
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2420025136
Short name T563
Test name
Test status
Simulation time 1156161381 ps
CPU time 10.72 seconds
Started May 26 12:46:26 PM PDT 24
Finished May 26 12:46:37 PM PDT 24
Peak memory 204408 kb
Host smart-46d49a3d-cea7-4fa1-bcd9-a3567c16d0b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420025136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2420025136
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1092199014
Short name T1026
Test name
Test status
Simulation time 3253575389 ps
CPU time 65.39 seconds
Started May 26 12:46:23 PM PDT 24
Finished May 26 12:47:29 PM PDT 24
Peak memory 208532 kb
Host smart-40a81855-d2a5-47f3-9f3c-7cd6b63bf8ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092199014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1092199014
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1807445315
Short name T28
Test name
Test status
Simulation time 54476546362 ps
CPU time 168.93 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:49:12 PM PDT 24
Peak memory 2154996 kb
Host smart-f34e69a8-aed6-4f7e-a00f-a6abda4d5dba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807445315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1807445315
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1572865098
Short name T815
Test name
Test status
Simulation time 15723312484 ps
CPU time 96.96 seconds
Started May 26 12:46:23 PM PDT 24
Finished May 26 12:48:01 PM PDT 24
Peak memory 994484 kb
Host smart-b59304c0-31e9-47d8-9a87-f2c02c2abc94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572865098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1572865098
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1670444735
Short name T553
Test name
Test status
Simulation time 6240831356 ps
CPU time 8.43 seconds
Started May 26 12:46:22 PM PDT 24
Finished May 26 12:46:32 PM PDT 24
Peak memory 220880 kb
Host smart-c3d7ad05-e34a-4939-8225-0a935029e92d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670444735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1670444735
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.4023609836
Short name T1077
Test name
Test status
Simulation time 45474295 ps
CPU time 0.62 seconds
Started May 26 12:46:45 PM PDT 24
Finished May 26 12:46:46 PM PDT 24
Peak memory 204088 kb
Host smart-a69a6a0e-7818-4e05-b91f-44be326be5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023609836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.4023609836
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.885717774
Short name T446
Test name
Test status
Simulation time 54995038 ps
CPU time 1.26 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:46:35 PM PDT 24
Peak memory 212728 kb
Host smart-a9fd1ed4-a118-4aab-a03b-6d2a681d784a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885717774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.885717774
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.7899827
Short name T843
Test name
Test status
Simulation time 1252340939 ps
CPU time 7.49 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:46:42 PM PDT 24
Peak memory 251064 kb
Host smart-bfaa73c3-487a-4be0-b569-3209377f5936
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7899827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.7899827
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2274031074
Short name T1245
Test name
Test status
Simulation time 4778860705 ps
CPU time 84.19 seconds
Started May 26 12:46:35 PM PDT 24
Finished May 26 12:48:00 PM PDT 24
Peak memory 775392 kb
Host smart-5df71f41-20c8-4699-94a2-6056e83d8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274031074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2274031074
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2077551867
Short name T1064
Test name
Test status
Simulation time 1695333569 ps
CPU time 59.2 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:47:35 PM PDT 24
Peak memory 625112 kb
Host smart-28cc8ba5-96a0-488c-97b5-685dc92f9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077551867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2077551867
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2832129308
Short name T775
Test name
Test status
Simulation time 154672277 ps
CPU time 0.97 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:36 PM PDT 24
Peak memory 204136 kb
Host smart-90be9161-b56c-45f9-ac47-2f89e217359b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832129308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2832129308
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3424978791
Short name T1040
Test name
Test status
Simulation time 170544651 ps
CPU time 9.84 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:46:43 PM PDT 24
Peak memory 232412 kb
Host smart-0153dfc0-d5f0-4d98-b883-08c3998b5f1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424978791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3424978791
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.996724322
Short name T162
Test name
Test status
Simulation time 20326608111 ps
CPU time 177.14 seconds
Started May 26 12:46:35 PM PDT 24
Finished May 26 12:49:33 PM PDT 24
Peak memory 1497276 kb
Host smart-bb3a4b15-2052-4cae-92f3-c2c10458868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996724322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.996724322
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3217306231
Short name T967
Test name
Test status
Simulation time 1205661689 ps
CPU time 3.97 seconds
Started May 26 12:46:44 PM PDT 24
Finished May 26 12:46:49 PM PDT 24
Peak memory 204476 kb
Host smart-63b6a47c-ef8c-4046-ae3d-28942534d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217306231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3217306231
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1359527827
Short name T1032
Test name
Test status
Simulation time 1194964770 ps
CPU time 18.89 seconds
Started May 26 12:46:47 PM PDT 24
Finished May 26 12:47:06 PM PDT 24
Peak memory 331224 kb
Host smart-2b90cc8f-997e-443e-b02d-e8f54c1046c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359527827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1359527827
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2371752728
Short name T78
Test name
Test status
Simulation time 17742314 ps
CPU time 0.65 seconds
Started May 26 12:46:35 PM PDT 24
Finished May 26 12:46:37 PM PDT 24
Peak memory 204164 kb
Host smart-2d2192bb-a6ce-428a-b7bd-9548c533a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371752728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2371752728
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.4001907790
Short name T1194
Test name
Test status
Simulation time 27558672056 ps
CPU time 518.16 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:55:12 PM PDT 24
Peak memory 924944 kb
Host smart-75fb4150-1314-4382-9eb7-dddd87fec239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001907790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.4001907790
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1628431765
Short name T560
Test name
Test status
Simulation time 2214128348 ps
CPU time 19.05 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:54 PM PDT 24
Peak memory 331356 kb
Host smart-1c8d568e-cf7e-45e9-a3e3-afadfb89b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628431765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1628431765
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1123521049
Short name T315
Test name
Test status
Simulation time 425227951 ps
CPU time 17.56 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:46:53 PM PDT 24
Peak memory 212616 kb
Host smart-97f61070-c859-47d9-b105-dfb57d484607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123521049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1123521049
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3019989011
Short name T747
Test name
Test status
Simulation time 2298677478 ps
CPU time 4.82 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:46:49 PM PDT 24
Peak memory 212664 kb
Host smart-e65a86c5-7f75-408d-9524-1955c0b6394a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019989011 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3019989011
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2280132579
Short name T807
Test name
Test status
Simulation time 10387104006 ps
CPU time 13.06 seconds
Started May 26 12:46:46 PM PDT 24
Finished May 26 12:46:59 PM PDT 24
Peak memory 264028 kb
Host smart-4d588121-9336-4e87-b5c6-35ae4e00a6b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280132579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2280132579
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.960017658
Short name T433
Test name
Test status
Simulation time 2955443237 ps
CPU time 1.43 seconds
Started May 26 12:46:44 PM PDT 24
Finished May 26 12:46:46 PM PDT 24
Peak memory 204288 kb
Host smart-0c7a6281-30d7-4232-a0d4-a28e2e36f173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960017658 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.960017658
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1434549145
Short name T785
Test name
Test status
Simulation time 1309998740 ps
CPU time 1.9 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:46:46 PM PDT 24
Peak memory 204440 kb
Host smart-1db9cf92-87d9-4e22-b4d5-cb45cc266697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434549145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1434549145
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1690735583
Short name T501
Test name
Test status
Simulation time 564196182 ps
CPU time 3.11 seconds
Started May 26 12:46:46 PM PDT 24
Finished May 26 12:46:50 PM PDT 24
Peak memory 204532 kb
Host smart-f0cc84fc-1643-4f5e-9587-1deb30b5aa37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690735583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1690735583
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1758231641
Short name T1284
Test name
Test status
Simulation time 4208985594 ps
CPU time 5.75 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:46:50 PM PDT 24
Peak memory 212712 kb
Host smart-ddb3cc92-216c-4612-a5f2-d312b10d44ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758231641 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1758231641
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1936056973
Short name T612
Test name
Test status
Simulation time 15709035630 ps
CPU time 182.38 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:49:47 PM PDT 24
Peak memory 2257272 kb
Host smart-2b783106-7b11-4895-8b58-61f2e65b268a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936056973 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1936056973
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.19878019
Short name T1157
Test name
Test status
Simulation time 6437351834 ps
CPU time 9.73 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:46:43 PM PDT 24
Peak memory 204480 kb
Host smart-306c0d72-f07b-4b9a-b42c-7970fb56145e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_targ
et_smoke.19878019
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3586602753
Short name T1036
Test name
Test status
Simulation time 5703253705 ps
CPU time 79.52 seconds
Started May 26 12:46:33 PM PDT 24
Finished May 26 12:47:53 PM PDT 24
Peak memory 206772 kb
Host smart-f4dca836-3d4e-4b43-83f7-ea555f91ea19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586602753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3586602753
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.976249459
Short name T872
Test name
Test status
Simulation time 14962214822 ps
CPU time 31 seconds
Started May 26 12:46:34 PM PDT 24
Finished May 26 12:47:06 PM PDT 24
Peak memory 204508 kb
Host smart-798ff854-2fea-42c7-b3d2-a5b33f2c0db9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976249459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.976249459
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3710185782
Short name T844
Test name
Test status
Simulation time 24857881399 ps
CPU time 514.75 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:55:19 PM PDT 24
Peak memory 1595276 kb
Host smart-3aaf5c97-5577-40c3-b16c-4443e33046d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710185782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3710185782
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1124967498
Short name T441
Test name
Test status
Simulation time 2881316805 ps
CPU time 7.44 seconds
Started May 26 12:46:45 PM PDT 24
Finished May 26 12:46:53 PM PDT 24
Peak memory 216568 kb
Host smart-faeb1274-1138-4822-955c-075ca19e14d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124967498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1124967498
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3008375365
Short name T787
Test name
Test status
Simulation time 23392814 ps
CPU time 0.62 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:46:54 PM PDT 24
Peak memory 204088 kb
Host smart-a4b0e45f-df7f-483c-a68b-7de5156c8eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008375365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3008375365
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.862483401
Short name T662
Test name
Test status
Simulation time 499063239 ps
CPU time 3.48 seconds
Started May 26 12:46:45 PM PDT 24
Finished May 26 12:46:49 PM PDT 24
Peak memory 212772 kb
Host smart-ca8e6c19-56c1-4257-b216-e4680a717d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862483401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.862483401
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1421649238
Short name T298
Test name
Test status
Simulation time 3380804707 ps
CPU time 6.47 seconds
Started May 26 12:46:42 PM PDT 24
Finished May 26 12:46:49 PM PDT 24
Peak memory 277684 kb
Host smart-3b3b0b95-840f-4d87-a9d8-ab017dd086e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421649238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1421649238
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.246920800
Short name T696
Test name
Test status
Simulation time 2082527646 ps
CPU time 70.03 seconds
Started May 26 12:46:42 PM PDT 24
Finished May 26 12:47:54 PM PDT 24
Peak memory 720384 kb
Host smart-d0bd8b8f-6526-4618-9e9c-a9e95391bec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246920800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.246920800
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3199060673
Short name T714
Test name
Test status
Simulation time 3320998091 ps
CPU time 115.95 seconds
Started May 26 12:46:45 PM PDT 24
Finished May 26 12:48:41 PM PDT 24
Peak memory 533520 kb
Host smart-b887146d-9075-4dc8-85b5-9d69e866a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199060673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3199060673
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2647881664
Short name T734
Test name
Test status
Simulation time 414020704 ps
CPU time 0.97 seconds
Started May 26 12:46:44 PM PDT 24
Finished May 26 12:46:46 PM PDT 24
Peak memory 204216 kb
Host smart-b21c7c3f-8120-4acd-803b-78797a5b2835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647881664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2647881664
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2032405001
Short name T337
Test name
Test status
Simulation time 383137676 ps
CPU time 10.24 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:46:55 PM PDT 24
Peak memory 204424 kb
Host smart-10e0ab4d-0696-405a-bd38-a4c03d970a70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032405001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2032405001
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2528996588
Short name T715
Test name
Test status
Simulation time 2706260665 ps
CPU time 68.45 seconds
Started May 26 12:46:42 PM PDT 24
Finished May 26 12:47:51 PM PDT 24
Peak memory 699116 kb
Host smart-5732143c-0eb5-4b0d-8b8d-1aadbb40d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528996588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2528996588
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1412318845
Short name T903
Test name
Test status
Simulation time 977730711 ps
CPU time 10.48 seconds
Started May 26 12:46:53 PM PDT 24
Finished May 26 12:47:05 PM PDT 24
Peak memory 204452 kb
Host smart-7e38c9ec-703d-4e0a-a783-d651102996a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412318845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1412318845
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1857947371
Short name T76
Test name
Test status
Simulation time 1494293982 ps
CPU time 76.33 seconds
Started May 26 12:46:53 PM PDT 24
Finished May 26 12:48:11 PM PDT 24
Peak memory 358648 kb
Host smart-f2f9500b-198a-4481-b484-f6ad0cfba7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857947371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1857947371
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.292316442
Short name T1315
Test name
Test status
Simulation time 18052692 ps
CPU time 0.67 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:46:45 PM PDT 24
Peak memory 204144 kb
Host smart-46e63218-ced8-4216-8dea-9a107dc32d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292316442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.292316442
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1369955636
Short name T1097
Test name
Test status
Simulation time 1088240047 ps
CPU time 46.98 seconds
Started May 26 12:46:43 PM PDT 24
Finished May 26 12:47:31 PM PDT 24
Peak memory 305640 kb
Host smart-500bc906-ed3b-4150-95ca-1e46af4adda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369955636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1369955636
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1518164643
Short name T534
Test name
Test status
Simulation time 3593521778 ps
CPU time 33.02 seconds
Started May 26 12:46:46 PM PDT 24
Finished May 26 12:47:20 PM PDT 24
Peak memory 423400 kb
Host smart-f010029c-dee7-4c5a-a4cd-16657deddfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518164643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1518164643
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1695595730
Short name T42
Test name
Test status
Simulation time 20070377472 ps
CPU time 943.68 seconds
Started May 26 12:46:42 PM PDT 24
Finished May 26 01:02:26 PM PDT 24
Peak memory 2789212 kb
Host smart-b75653ff-82bc-4366-9cb4-20b9be8e026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695595730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1695595730
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3405342101
Short name T641
Test name
Test status
Simulation time 1432379815 ps
CPU time 15.31 seconds
Started May 26 12:46:47 PM PDT 24
Finished May 26 12:47:03 PM PDT 24
Peak memory 212716 kb
Host smart-8869c20b-f2aa-4161-b0bd-dcf222f2b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405342101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3405342101
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3719489030
Short name T1292
Test name
Test status
Simulation time 616099107 ps
CPU time 3.65 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:46:55 PM PDT 24
Peak memory 204536 kb
Host smart-6c0f0e55-cbc7-4f41-a3f3-b72e14301b4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719489030 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3719489030
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.652557668
Short name T972
Test name
Test status
Simulation time 10176087786 ps
CPU time 43.88 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:47:37 PM PDT 24
Peak memory 322764 kb
Host smart-67edf1ff-42e5-4bc8-9b51-17bd5a2b4002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652557668 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.652557668
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3234273337
Short name T831
Test name
Test status
Simulation time 11335268768 ps
CPU time 8.6 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:47:00 PM PDT 24
Peak memory 256440 kb
Host smart-ce6b5d38-d6f1-44ad-9f69-e0d39cd5e0d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234273337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3234273337
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.849161149
Short name T461
Test name
Test status
Simulation time 6006921411 ps
CPU time 2.89 seconds
Started May 26 12:46:56 PM PDT 24
Finished May 26 12:47:00 PM PDT 24
Peak memory 204464 kb
Host smart-ad5bf8f5-1874-4b03-8c7f-3cb187be85a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849161149 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.849161149
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.934248925
Short name T1219
Test name
Test status
Simulation time 1070842351 ps
CPU time 5.15 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:46:57 PM PDT 24
Peak memory 204464 kb
Host smart-d4ab4fc3-4e11-4f60-95b7-f8a3aad5da49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934248925 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.934248925
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2922945330
Short name T1170
Test name
Test status
Simulation time 389606864 ps
CPU time 2.46 seconds
Started May 26 12:46:57 PM PDT 24
Finished May 26 12:47:01 PM PDT 24
Peak memory 204504 kb
Host smart-03a49084-3ca8-4a39-bdd7-2084bbe89c45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922945330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2922945330
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4124225381
Short name T1059
Test name
Test status
Simulation time 4766318420 ps
CPU time 5.44 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:46:58 PM PDT 24
Peak memory 207400 kb
Host smart-d29821cd-34df-4a81-b1d1-78991add6ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124225381 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4124225381
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.644938898
Short name T1098
Test name
Test status
Simulation time 5250223613 ps
CPU time 6.36 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:46:58 PM PDT 24
Peak memory 204444 kb
Host smart-413da22b-0b94-4c6e-93a4-2cea1ee420b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644938898 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.644938898
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2179760869
Short name T33
Test name
Test status
Simulation time 4733201094 ps
CPU time 15.81 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:47:09 PM PDT 24
Peak memory 204608 kb
Host smart-c44dfd6f-1b13-41fe-a27a-5f3c0067dc80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179760869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2179760869
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2617231277
Short name T637
Test name
Test status
Simulation time 5124787818 ps
CPU time 58 seconds
Started May 26 12:46:51 PM PDT 24
Finished May 26 12:47:50 PM PDT 24
Peak memory 205940 kb
Host smart-5a7f2238-1aec-42df-ae14-c09493822139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617231277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2617231277
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1645952812
Short name T278
Test name
Test status
Simulation time 7680573231 ps
CPU time 4.51 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:46:58 PM PDT 24
Peak memory 204412 kb
Host smart-ba686807-f234-4fcf-b149-ac5981d0c40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645952812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1645952812
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.1282235506
Short name T288
Test name
Test status
Simulation time 7012332177 ps
CPU time 87.58 seconds
Started May 26 12:46:56 PM PDT 24
Finished May 26 12:48:25 PM PDT 24
Peak memory 1294848 kb
Host smart-95923922-5e0a-464c-89a1-a97acd2b330c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282235506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.1282235506
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2491024704
Short name T653
Test name
Test status
Simulation time 1500628487 ps
CPU time 7.94 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:47:01 PM PDT 24
Peak memory 204456 kb
Host smart-0a86f8d8-abfe-4c14-9c25-d84fda5ef5d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491024704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2491024704
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2343069984
Short name T171
Test name
Test status
Simulation time 28377528 ps
CPU time 0.62 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:47:11 PM PDT 24
Peak memory 204180 kb
Host smart-11d72e9c-b994-4593-9fad-df8a89d56e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343069984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2343069984
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.436872012
Short name T935
Test name
Test status
Simulation time 128613627 ps
CPU time 1.76 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:46:56 PM PDT 24
Peak memory 212792 kb
Host smart-bb39ce5c-39f2-40b0-b71b-844657f7edb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436872012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.436872012
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3794829939
Short name T763
Test name
Test status
Simulation time 485849239 ps
CPU time 10.56 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:47:04 PM PDT 24
Peak memory 287536 kb
Host smart-57a0391d-9be3-413b-a178-783187352318
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794829939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3794829939
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3988260269
Short name T898
Test name
Test status
Simulation time 1955541694 ps
CPU time 130.59 seconds
Started May 26 12:46:54 PM PDT 24
Finished May 26 12:49:06 PM PDT 24
Peak memory 648720 kb
Host smart-13cea974-b91c-4263-949c-968007cc68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988260269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3988260269
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4129016121
Short name T1260
Test name
Test status
Simulation time 2459117043 ps
CPU time 76.72 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:48:10 PM PDT 24
Peak memory 792052 kb
Host smart-b5b470af-a00b-414b-aa6e-5a33a1f1ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129016121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4129016121
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.411693732
Short name T712
Test name
Test status
Simulation time 1079284942 ps
CPU time 1.07 seconds
Started May 26 12:46:54 PM PDT 24
Finished May 26 12:46:56 PM PDT 24
Peak memory 204236 kb
Host smart-4699f0cf-4b2c-4e06-82a4-daba45f1bbf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411693732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.411693732
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2185330015
Short name T702
Test name
Test status
Simulation time 183495598 ps
CPU time 5.2 seconds
Started May 26 12:46:57 PM PDT 24
Finished May 26 12:47:03 PM PDT 24
Peak memory 238736 kb
Host smart-e0139ff5-71fd-4613-8e94-44069ff5334a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185330015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2185330015
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.232321142
Short name T757
Test name
Test status
Simulation time 3658335696 ps
CPU time 87.36 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:48:21 PM PDT 24
Peak memory 1068952 kb
Host smart-9d6f4248-8870-42f8-a5f2-1bd8148fb1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232321142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.232321142
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2577721090
Short name T1351
Test name
Test status
Simulation time 408401813 ps
CPU time 16.26 seconds
Started May 26 12:47:09 PM PDT 24
Finished May 26 12:47:26 PM PDT 24
Peak memory 204580 kb
Host smart-f18ca2e5-b15b-409b-8033-46d34b487623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577721090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2577721090
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.47755336
Short name T1110
Test name
Test status
Simulation time 2413081075 ps
CPU time 129.86 seconds
Started May 26 12:47:11 PM PDT 24
Finished May 26 12:49:21 PM PDT 24
Peak memory 450176 kb
Host smart-c58f9702-b135-4612-8fe8-21a7a6258052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47755336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.47755336
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.436338446
Short name T856
Test name
Test status
Simulation time 152845085 ps
CPU time 0.66 seconds
Started May 26 12:46:55 PM PDT 24
Finished May 26 12:46:57 PM PDT 24
Peak memory 204144 kb
Host smart-ce179d1d-1d8d-4799-9ad8-33a564d34968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436338446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.436338446
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2452954818
Short name T897
Test name
Test status
Simulation time 6427800860 ps
CPU time 52.86 seconds
Started May 26 12:46:52 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 220920 kb
Host smart-9aa326a9-97f3-4555-9b23-b0d82f94d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452954818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2452954818
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.73878152
Short name T144
Test name
Test status
Simulation time 3589743274 ps
CPU time 44.75 seconds
Started May 26 12:46:53 PM PDT 24
Finished May 26 12:47:39 PM PDT 24
Peak memory 445812 kb
Host smart-62fd715d-aee7-4037-9840-70c806f656a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73878152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.73878152
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2667527103
Short name T538
Test name
Test status
Simulation time 5491532214 ps
CPU time 24.41 seconds
Started May 26 12:46:53 PM PDT 24
Finished May 26 12:47:18 PM PDT 24
Peak memory 212724 kb
Host smart-fa1b9879-3a51-4a20-9128-1533165ac524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667527103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2667527103
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1865145372
Short name T619
Test name
Test status
Simulation time 544874608 ps
CPU time 2.94 seconds
Started May 26 12:47:09 PM PDT 24
Finished May 26 12:47:13 PM PDT 24
Peak memory 204448 kb
Host smart-ff835e08-b101-4a46-b90e-2da3020035f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865145372 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1865145372
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.536493843
Short name T730
Test name
Test status
Simulation time 10148915525 ps
CPU time 12.39 seconds
Started May 26 12:47:02 PM PDT 24
Finished May 26 12:47:15 PM PDT 24
Peak memory 275680 kb
Host smart-1f3db217-1495-426f-88a1-5e474c9333ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536493843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.536493843
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.40696754
Short name T363
Test name
Test status
Simulation time 10222696318 ps
CPU time 10.2 seconds
Started May 26 12:46:59 PM PDT 24
Finished May 26 12:47:10 PM PDT 24
Peak memory 282300 kb
Host smart-fd6c994a-fbbf-45b9-8253-c7805592f4c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40696754 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_fifo_reset_tx.40696754
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.4107213237
Short name T1131
Test name
Test status
Simulation time 1343849336 ps
CPU time 6.91 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:47:17 PM PDT 24
Peak memory 204428 kb
Host smart-1c819f9a-58f8-44d0-b9d3-b4ee40c0b195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107213237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.4107213237
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.428639429
Short name T904
Test name
Test status
Simulation time 1166190605 ps
CPU time 2 seconds
Started May 26 12:47:09 PM PDT 24
Finished May 26 12:47:12 PM PDT 24
Peak memory 204452 kb
Host smart-969aab52-c668-4e6c-9f3c-29b806cba488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428639429 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.428639429
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1452391312
Short name T23
Test name
Test status
Simulation time 738653378 ps
CPU time 2.53 seconds
Started May 26 12:47:11 PM PDT 24
Finished May 26 12:47:14 PM PDT 24
Peak memory 204548 kb
Host smart-0cedc02b-c132-4680-91c3-3f3f6e1355d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452391312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1452391312
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.190084485
Short name T307
Test name
Test status
Simulation time 1145259611 ps
CPU time 3.94 seconds
Started May 26 12:46:59 PM PDT 24
Finished May 26 12:47:03 PM PDT 24
Peak memory 204440 kb
Host smart-a67b3bd1-0057-4f98-99ea-e65e467b33c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190084485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.190084485
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1156086660
Short name T997
Test name
Test status
Simulation time 4498511748 ps
CPU time 36.4 seconds
Started May 26 12:47:01 PM PDT 24
Finished May 26 12:47:38 PM PDT 24
Peak memory 1120196 kb
Host smart-2d00d430-c7a3-486f-b33e-c830bcc836a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156086660 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1156086660
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1884711032
Short name T598
Test name
Test status
Simulation time 2206953308 ps
CPU time 8.68 seconds
Started May 26 12:47:08 PM PDT 24
Finished May 26 12:47:17 PM PDT 24
Peak memory 204556 kb
Host smart-6d6b1445-07e3-402b-a4f4-3c07de17fcb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884711032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1884711032
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3596708660
Short name T875
Test name
Test status
Simulation time 1159915929 ps
CPU time 12.35 seconds
Started May 26 12:47:08 PM PDT 24
Finished May 26 12:47:20 PM PDT 24
Peak memory 204472 kb
Host smart-23164079-4207-47b7-9171-c53f9ff6161b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596708660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3596708660
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2063571294
Short name T1218
Test name
Test status
Simulation time 49209689118 ps
CPU time 1063.44 seconds
Started May 26 12:47:01 PM PDT 24
Finished May 26 01:04:45 PM PDT 24
Peak memory 7309208 kb
Host smart-3376c24e-4a6b-41c3-a7ad-a6416a2fc676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063571294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2063571294
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.984525333
Short name T1250
Test name
Test status
Simulation time 6484382695 ps
CPU time 154.94 seconds
Started May 26 12:47:01 PM PDT 24
Finished May 26 12:49:37 PM PDT 24
Peak memory 1691328 kb
Host smart-87876687-355e-4bc1-8a80-2b65abb72ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984525333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.984525333
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1666641918
Short name T1151
Test name
Test status
Simulation time 1227674242 ps
CPU time 7.05 seconds
Started May 26 12:47:02 PM PDT 24
Finished May 26 12:47:10 PM PDT 24
Peak memory 219380 kb
Host smart-ec5b3607-9aae-4f62-80ee-949899caafaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666641918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1666641918
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1311924515
Short name T173
Test name
Test status
Simulation time 17882568 ps
CPU time 0.63 seconds
Started May 26 12:47:28 PM PDT 24
Finished May 26 12:47:29 PM PDT 24
Peak memory 204060 kb
Host smart-c96be5e1-b304-4de1-ac6c-a60e3d892014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311924515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1311924515
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.515450562
Short name T1353
Test name
Test status
Simulation time 293968627 ps
CPU time 2.34 seconds
Started May 26 12:47:18 PM PDT 24
Finished May 26 12:47:22 PM PDT 24
Peak memory 212892 kb
Host smart-c6c3c9b5-595d-4912-8ce5-5169d91585dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515450562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.515450562
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.246939620
Short name T451
Test name
Test status
Simulation time 357988005 ps
CPU time 5.95 seconds
Started May 26 12:47:25 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 261428 kb
Host smart-6fd4f1a0-5253-4300-8349-041a3eee5886
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246939620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.246939620
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3235650703
Short name T1212
Test name
Test status
Simulation time 25769752912 ps
CPU time 82.38 seconds
Started May 26 12:47:20 PM PDT 24
Finished May 26 12:48:43 PM PDT 24
Peak memory 212632 kb
Host smart-3dd16710-5dfd-4ade-aee2-6c959b18fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235650703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3235650703
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2104410293
Short name T1385
Test name
Test status
Simulation time 4729428801 ps
CPU time 73.43 seconds
Started May 26 12:47:09 PM PDT 24
Finished May 26 12:48:23 PM PDT 24
Peak memory 771204 kb
Host smart-c53b27df-8cf9-49f4-aacf-71e974eb99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104410293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2104410293
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2467584134
Short name T814
Test name
Test status
Simulation time 84516333 ps
CPU time 0.9 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:47:11 PM PDT 24
Peak memory 204208 kb
Host smart-5e23ec52-2b79-4c21-978d-6aa689386d76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467584134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2467584134
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3055740714
Short name T129
Test name
Test status
Simulation time 242682156 ps
CPU time 11.02 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:31 PM PDT 24
Peak memory 204440 kb
Host smart-b596be4d-e610-435f-b93e-5a7bc3c80cb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055740714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3055740714
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2759320857
Short name T456
Test name
Test status
Simulation time 3332134580 ps
CPU time 230.95 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:51:01 PM PDT 24
Peak memory 990276 kb
Host smart-59c7daf7-b5fd-480b-992f-aebb33987c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759320857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2759320857
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.529955058
Short name T489
Test name
Test status
Simulation time 1555474592 ps
CPU time 24.33 seconds
Started May 26 12:47:18 PM PDT 24
Finished May 26 12:47:42 PM PDT 24
Peak memory 204580 kb
Host smart-a994e203-4990-42e6-9a7a-8957493d9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529955058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.529955058
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3749776306
Short name T244
Test name
Test status
Simulation time 3075329014 ps
CPU time 24.25 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:44 PM PDT 24
Peak memory 289444 kb
Host smart-578bee1c-7d75-4f01-81ce-28d88fba9eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749776306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3749776306
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.2004095510
Short name T137
Test name
Test status
Simulation time 66034115 ps
CPU time 0.65 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:47:11 PM PDT 24
Peak memory 204136 kb
Host smart-bcb6acdd-e212-41a5-ad08-bc09293903b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004095510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2004095510
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.314669144
Short name T821
Test name
Test status
Simulation time 7306942231 ps
CPU time 106.45 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:49:06 PM PDT 24
Peak memory 225032 kb
Host smart-1a11066d-bd9f-4a11-ac43-003c4c861b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314669144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.314669144
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1429816937
Short name T1350
Test name
Test status
Simulation time 1838313296 ps
CPU time 38.46 seconds
Started May 26 12:47:10 PM PDT 24
Finished May 26 12:47:49 PM PDT 24
Peak memory 372248 kb
Host smart-9d3694b8-5b97-4435-a015-09f5c15e3f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429816937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1429816937
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3497555271
Short name T1334
Test name
Test status
Simulation time 28369311019 ps
CPU time 121.04 seconds
Started May 26 12:47:18 PM PDT 24
Finished May 26 12:49:20 PM PDT 24
Peak memory 826224 kb
Host smart-f6f4157f-0816-4248-b0cd-e32fcddbafe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497555271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3497555271
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3212749985
Short name T1100
Test name
Test status
Simulation time 3689669319 ps
CPU time 9.3 seconds
Started May 26 12:47:20 PM PDT 24
Finished May 26 12:47:30 PM PDT 24
Peak memory 220916 kb
Host smart-ca052e48-e091-43a0-83fd-062a608c1930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212749985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3212749985
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.4253646253
Short name T1210
Test name
Test status
Simulation time 724422627 ps
CPU time 3.82 seconds
Started May 26 12:47:18 PM PDT 24
Finished May 26 12:47:22 PM PDT 24
Peak memory 212808 kb
Host smart-b54355b1-d688-46ad-8776-3331c2c4bcc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253646253 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.4253646253
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3904849215
Short name T226
Test name
Test status
Simulation time 10105069240 ps
CPU time 41.65 seconds
Started May 26 12:47:25 PM PDT 24
Finished May 26 12:48:07 PM PDT 24
Peak memory 333160 kb
Host smart-f2b1a900-f2ed-4dfd-9287-c0ec923142df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904849215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3904849215
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1611134353
Short name T1342
Test name
Test status
Simulation time 10214667223 ps
CPU time 20.65 seconds
Started May 26 12:47:25 PM PDT 24
Finished May 26 12:47:47 PM PDT 24
Peak memory 350124 kb
Host smart-4ef22b91-330d-4fa4-abc0-ddbe81f52787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611134353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1611134353
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3330972155
Short name T249
Test name
Test status
Simulation time 1053315030 ps
CPU time 4.62 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:25 PM PDT 24
Peak memory 204468 kb
Host smart-98b4dacd-2741-42b8-b61c-8d142ec3215a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330972155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3330972155
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.4004319799
Short name T559
Test name
Test status
Simulation time 1376133550 ps
CPU time 2.32 seconds
Started May 26 12:47:29 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 204448 kb
Host smart-197ea857-e513-4103-bea2-b7fadb12d6fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004319799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.4004319799
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.140045989
Short name T1375
Test name
Test status
Simulation time 1803483268 ps
CPU time 3.02 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:23 PM PDT 24
Peak memory 204536 kb
Host smart-2c320100-5955-4b99-a86f-d7395c88e210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140045989 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.140045989
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3870074800
Short name T443
Test name
Test status
Simulation time 878053378 ps
CPU time 4.51 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 205116 kb
Host smart-6e8d34e4-f8a0-42d7-8160-8059b2ca6486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870074800 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3870074800
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2366202729
Short name T1134
Test name
Test status
Simulation time 4750725885 ps
CPU time 9.95 seconds
Started May 26 12:47:20 PM PDT 24
Finished May 26 12:47:31 PM PDT 24
Peak memory 204548 kb
Host smart-cb4934c4-1177-4189-9419-e0b40c3cb9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366202729 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2366202729
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3595091861
Short name T402
Test name
Test status
Simulation time 2047380943 ps
CPU time 14.22 seconds
Started May 26 12:47:22 PM PDT 24
Finished May 26 12:47:37 PM PDT 24
Peak memory 204456 kb
Host smart-448bed6e-65c4-4b44-ae1a-ad35889dbee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595091861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3595091861
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1941965469
Short name T1055
Test name
Test status
Simulation time 323354672 ps
CPU time 5.63 seconds
Started May 26 12:47:25 PM PDT 24
Finished May 26 12:47:31 PM PDT 24
Peak memory 204476 kb
Host smart-3351888d-9ff3-4b5b-8b03-7a27876866f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941965469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1941965469
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2886129455
Short name T778
Test name
Test status
Simulation time 7585972126 ps
CPU time 4.42 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:25 PM PDT 24
Peak memory 204548 kb
Host smart-5adaf468-16d9-4ae0-9b45-2190b4c2e46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886129455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2886129455
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3229030755
Short name T1029
Test name
Test status
Simulation time 8126280539 ps
CPU time 12.96 seconds
Started May 26 12:47:18 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 296172 kb
Host smart-f0149112-4880-405b-b649-a7a7a24ebaff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229030755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3229030755
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4005981837
Short name T1423
Test name
Test status
Simulation time 4865707713 ps
CPU time 7.34 seconds
Started May 26 12:47:19 PM PDT 24
Finished May 26 12:47:27 PM PDT 24
Peak memory 220820 kb
Host smart-aea7a601-b462-442d-843b-5518b741f80a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005981837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4005981837
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4085524235
Short name T1049
Test name
Test status
Simulation time 36910839 ps
CPU time 0.64 seconds
Started May 26 12:41:55 PM PDT 24
Finished May 26 12:41:56 PM PDT 24
Peak memory 204080 kb
Host smart-196a2a82-5c38-45c3-a112-29f3c102325d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085524235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4085524235
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1393408075
Short name T1276
Test name
Test status
Simulation time 234626358 ps
CPU time 1.65 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:41:46 PM PDT 24
Peak memory 204556 kb
Host smart-c5e07bf2-583a-480f-af4d-938f5f56db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393408075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1393408075
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1158289072
Short name T1154
Test name
Test status
Simulation time 957328209 ps
CPU time 13.11 seconds
Started May 26 12:41:48 PM PDT 24
Finished May 26 12:42:02 PM PDT 24
Peak memory 256820 kb
Host smart-675ca663-aeec-4df5-9101-4e3375748243
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158289072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1158289072
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3986280521
Short name T1324
Test name
Test status
Simulation time 11099179482 ps
CPU time 89.01 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 804176 kb
Host smart-2276fb00-c8a2-4751-8470-ad3f7520796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986280521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3986280521
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3544525066
Short name T517
Test name
Test status
Simulation time 22175401689 ps
CPU time 78.43 seconds
Started May 26 12:41:49 PM PDT 24
Finished May 26 12:43:08 PM PDT 24
Peak memory 412256 kb
Host smart-3cc55fc1-095c-4c04-be47-770c0a147bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544525066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3544525066
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2796440385
Short name T61
Test name
Test status
Simulation time 217238288 ps
CPU time 1.03 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:41:45 PM PDT 24
Peak memory 204236 kb
Host smart-fbeb79a1-981d-4b3f-a47c-f01362580fac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796440385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2796440385
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.982887256
Short name T229
Test name
Test status
Simulation time 149999472 ps
CPU time 3.65 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:41:49 PM PDT 24
Peak memory 204436 kb
Host smart-ea48483b-c64d-43cc-b4c9-7313437dba9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982887256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.982887256
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3709384326
Short name T1230
Test name
Test status
Simulation time 20562070336 ps
CPU time 430.01 seconds
Started May 26 12:41:42 PM PDT 24
Finished May 26 12:48:53 PM PDT 24
Peak memory 1397340 kb
Host smart-bdcbc2fa-790d-47f3-ac8c-056c917c2e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709384326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3709384326
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.448239599
Short name T1123
Test name
Test status
Simulation time 567134499 ps
CPU time 6.69 seconds
Started May 26 12:41:56 PM PDT 24
Finished May 26 12:42:03 PM PDT 24
Peak memory 204540 kb
Host smart-1a2c0e1b-215d-43c0-ac6f-6cb593ae1741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448239599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.448239599
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2230202621
Short name T732
Test name
Test status
Simulation time 21512347539 ps
CPU time 26.8 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:21 PM PDT 24
Peak memory 335096 kb
Host smart-af6ad51c-0b8b-4a0f-a53f-cc82c4883c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230202621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2230202621
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.399803607
Short name T1173
Test name
Test status
Simulation time 41526093 ps
CPU time 0.73 seconds
Started May 26 12:41:46 PM PDT 24
Finished May 26 12:41:47 PM PDT 24
Peak memory 204168 kb
Host smart-39104d0a-b6a7-4775-a721-c3322523f011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399803607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.399803607
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2611861323
Short name T1414
Test name
Test status
Simulation time 4817125469 ps
CPU time 393.23 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:48:17 PM PDT 24
Peak memory 1327536 kb
Host smart-cd965287-11f9-4d9d-9f3d-81c4091ec1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611861323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2611861323
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.106334265
Short name T1331
Test name
Test status
Simulation time 1505074045 ps
CPU time 27.63 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:42:12 PM PDT 24
Peak memory 303864 kb
Host smart-502e88b2-b758-4669-b44c-e8ef75bde975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106334265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.106334265
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.2413681478
Short name T64
Test name
Test status
Simulation time 11225471849 ps
CPU time 1091.62 seconds
Started May 26 12:41:49 PM PDT 24
Finished May 26 01:00:02 PM PDT 24
Peak memory 1613332 kb
Host smart-ccff27aa-538a-45ad-a5fd-1b9efa37c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413681478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2413681478
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1733954275
Short name T378
Test name
Test status
Simulation time 611962493 ps
CPU time 29.14 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:42:13 PM PDT 24
Peak memory 212648 kb
Host smart-8b829140-8641-4428-a087-aaaf4821e3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733954275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1733954275
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.4155578359
Short name T176
Test name
Test status
Simulation time 244526898 ps
CPU time 0.9 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:41:56 PM PDT 24
Peak memory 222588 kb
Host smart-d583475f-47a5-4bc2-81af-8ae0fa7a8dd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155578359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.4155578359
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2756546801
Short name T992
Test name
Test status
Simulation time 784480248 ps
CPU time 4.17 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:58 PM PDT 24
Peak memory 212596 kb
Host smart-7b4f0f8d-c0aa-4aca-be58-14eec5d2d11a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756546801 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2756546801
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.4008042282
Short name T669
Test name
Test status
Simulation time 10189920770 ps
CPU time 13.05 seconds
Started May 26 12:41:43 PM PDT 24
Finished May 26 12:41:57 PM PDT 24
Peak memory 254544 kb
Host smart-144c7e47-df6c-4b95-91ac-c4c4ded8a3d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008042282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.4008042282
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1622290144
Short name T1070
Test name
Test status
Simulation time 10141535639 ps
CPU time 31.18 seconds
Started May 26 12:41:42 PM PDT 24
Finished May 26 12:42:14 PM PDT 24
Peak memory 417772 kb
Host smart-7bfa79e4-3836-416d-984d-754a4b8ecc5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622290144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1622290144
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.430576235
Short name T592
Test name
Test status
Simulation time 1075320020 ps
CPU time 4.95 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:58 PM PDT 24
Peak memory 204476 kb
Host smart-22ea6d63-f935-4f31-935a-fd58ed55b48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430576235 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.430576235
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.3518022768
Short name T310
Test name
Test status
Simulation time 1059551387 ps
CPU time 5.58 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:00 PM PDT 24
Peak memory 204452 kb
Host smart-c7e2bb12-9d13-4e2e-8d78-79bb01c0f0c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518022768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.3518022768
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.115539236
Short name T207
Test name
Test status
Simulation time 432585976 ps
CPU time 2.82 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:57 PM PDT 24
Peak memory 204532 kb
Host smart-5903027d-ea11-4dda-ba73-8f9b2c9f9482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115539236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.115539236
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1003882688
Short name T1146
Test name
Test status
Simulation time 4519704344 ps
CPU time 5.33 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:41:50 PM PDT 24
Peak memory 204624 kb
Host smart-a2d6a3c1-e7d3-458f-be8c-38b955cd7bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003882688 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1003882688
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.390902437
Short name T1156
Test name
Test status
Simulation time 17027852475 ps
CPU time 320.43 seconds
Started May 26 12:41:46 PM PDT 24
Finished May 26 12:47:07 PM PDT 24
Peak memory 4167280 kb
Host smart-42a2a0ae-02cd-40cb-9495-e4d299fb86d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390902437 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.390902437
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.165839247
Short name T615
Test name
Test status
Simulation time 643226491 ps
CPU time 10.93 seconds
Started May 26 12:41:46 PM PDT 24
Finished May 26 12:41:58 PM PDT 24
Peak memory 204484 kb
Host smart-8f2e7176-5366-43e2-8e5b-3ed8ed04d504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165839247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.165839247
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3458613846
Short name T1045
Test name
Test status
Simulation time 1305971550 ps
CPU time 14.03 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:41:59 PM PDT 24
Peak memory 204472 kb
Host smart-e91a4856-57a0-49fa-b27a-0e4dbeba841a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458613846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3458613846
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3224165474
Short name T362
Test name
Test status
Simulation time 21372837390 ps
CPU time 11.96 seconds
Started May 26 12:41:46 PM PDT 24
Finished May 26 12:41:59 PM PDT 24
Peak memory 204496 kb
Host smart-e5e9a050-f5c4-4db8-8e1d-204b93a857e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224165474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3224165474
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.288380649
Short name T533
Test name
Test status
Simulation time 36031567517 ps
CPU time 856.83 seconds
Started May 26 12:41:45 PM PDT 24
Finished May 26 12:56:03 PM PDT 24
Peak memory 4260956 kb
Host smart-f344b128-fbc9-4a71-959d-88d2694b3772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288380649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.288380649
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.738680872
Short name T752
Test name
Test status
Simulation time 1284217585 ps
CPU time 6.53 seconds
Started May 26 12:41:44 PM PDT 24
Finished May 26 12:41:51 PM PDT 24
Peak memory 213396 kb
Host smart-501b88fc-8ff7-42fb-84f2-7440a78dd435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738680872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.738680872
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.221364845
Short name T1241
Test name
Test status
Simulation time 27057254 ps
CPU time 0.61 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:38 PM PDT 24
Peak memory 204060 kb
Host smart-96cb81df-73d9-4e7e-8987-1e48bcce4782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221364845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.221364845
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.729217020
Short name T878
Test name
Test status
Simulation time 750393861 ps
CPU time 3.26 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:47:31 PM PDT 24
Peak memory 235600 kb
Host smart-227f5e64-40ab-4591-9ade-49d7224fa1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729217020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.729217020
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2394080050
Short name T401
Test name
Test status
Simulation time 1297393828 ps
CPU time 18.78 seconds
Started May 26 12:47:28 PM PDT 24
Finished May 26 12:47:47 PM PDT 24
Peak memory 277372 kb
Host smart-fa78b6ca-9c71-409d-ace9-f1835eddd32a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394080050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2394080050
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.323449982
Short name T865
Test name
Test status
Simulation time 21522310060 ps
CPU time 112.7 seconds
Started May 26 12:47:28 PM PDT 24
Finished May 26 12:49:21 PM PDT 24
Peak memory 591140 kb
Host smart-30813d31-67e4-450a-a5b6-e9c17e18aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323449982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.323449982
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3569379180
Short name T1252
Test name
Test status
Simulation time 1362611592 ps
CPU time 97.68 seconds
Started May 26 12:47:33 PM PDT 24
Finished May 26 12:49:11 PM PDT 24
Peak memory 539608 kb
Host smart-e20a0254-94d6-4841-9cbb-69ee05127c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569379180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3569379180
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3436853845
Short name T1256
Test name
Test status
Simulation time 385720739 ps
CPU time 0.99 seconds
Started May 26 12:47:30 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 204192 kb
Host smart-db803017-61a6-43ed-a9ba-af71c8e37eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436853845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3436853845
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3381379112
Short name T1063
Test name
Test status
Simulation time 288489630 ps
CPU time 3.71 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:47:32 PM PDT 24
Peak memory 229740 kb
Host smart-1da4060b-765e-46dc-b5ac-aa1ee25fe8e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381379112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3381379112
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3917119575
Short name T106
Test name
Test status
Simulation time 6400378815 ps
CPU time 80.01 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:48:48 PM PDT 24
Peak memory 950976 kb
Host smart-423fc9e2-5c41-4c28-8deb-74df736b8d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917119575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3917119575
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3645020728
Short name T1153
Test name
Test status
Simulation time 590367672 ps
CPU time 2.88 seconds
Started May 26 12:47:44 PM PDT 24
Finished May 26 12:47:47 PM PDT 24
Peak memory 204504 kb
Host smart-fe9a227b-a46e-4098-b4ea-dbb9866c1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645020728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3645020728
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.534967721
Short name T36
Test name
Test status
Simulation time 2242731651 ps
CPU time 41.43 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:48:20 PM PDT 24
Peak memory 411920 kb
Host smart-1c7bea0c-c4a7-421a-8b0d-f82559208d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534967721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.534967721
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.959648502
Short name T944
Test name
Test status
Simulation time 35145669 ps
CPU time 0.64 seconds
Started May 26 12:47:29 PM PDT 24
Finished May 26 12:47:30 PM PDT 24
Peak memory 204104 kb
Host smart-1135a724-1481-4c79-98db-faf12dc34b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959648502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.959648502
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1434515339
Short name T453
Test name
Test status
Simulation time 50670738711 ps
CPU time 519.1 seconds
Started May 26 12:47:33 PM PDT 24
Finished May 26 12:56:13 PM PDT 24
Peak memory 204560 kb
Host smart-adc716af-14ba-4321-8b3a-7f68bfef0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434515339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1434515339
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3583039298
Short name T609
Test name
Test status
Simulation time 1549811758 ps
CPU time 26.19 seconds
Started May 26 12:47:32 PM PDT 24
Finished May 26 12:47:59 PM PDT 24
Peak memory 362328 kb
Host smart-eded1234-c753-4b71-8edc-739c2da1574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583039298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3583039298
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2515309195
Short name T264
Test name
Test status
Simulation time 143978088159 ps
CPU time 955.97 seconds
Started May 26 12:47:33 PM PDT 24
Finished May 26 01:03:30 PM PDT 24
Peak memory 1752672 kb
Host smart-c3bdc045-b537-478e-b545-6acc8f1285bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515309195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2515309195
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2406501176
Short name T1261
Test name
Test status
Simulation time 3711691837 ps
CPU time 9.43 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:47:37 PM PDT 24
Peak memory 219648 kb
Host smart-09dbe195-3165-4044-b357-b7cbfa7338ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406501176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2406501176
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1525011948
Short name T1434
Test name
Test status
Simulation time 724965406 ps
CPU time 3.96 seconds
Started May 26 12:47:39 PM PDT 24
Finished May 26 12:47:43 PM PDT 24
Peak memory 204524 kb
Host smart-80fd5cd8-977a-4b1d-9452-06a5a2bbf97c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525011948 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1525011948
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1343776513
Short name T155
Test name
Test status
Simulation time 10202783332 ps
CPU time 46.13 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:48:24 PM PDT 24
Peak memory 401512 kb
Host smart-26dadd5d-2bbd-45ab-bd6e-3a26454070db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343776513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1343776513
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.623693890
Short name T523
Test name
Test status
Simulation time 10372979556 ps
CPU time 16.94 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:54 PM PDT 24
Peak memory 297840 kb
Host smart-ab2111ad-8568-4350-b1ff-ca68c8ed6d24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623693890 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.623693890
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.1333231048
Short name T1311
Test name
Test status
Simulation time 1249953701 ps
CPU time 1.88 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:39 PM PDT 24
Peak memory 204436 kb
Host smart-13b19863-e134-486f-83b0-649a0a8b75aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333231048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.1333231048
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.2223409889
Short name T987
Test name
Test status
Simulation time 1065072126 ps
CPU time 5.75 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:47:44 PM PDT 24
Peak memory 204496 kb
Host smart-a573d534-bd30-4101-bb9d-319fcc1bdc10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223409889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.2223409889
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1175262872
Short name T930
Test name
Test status
Simulation time 673331199 ps
CPU time 2.75 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:39 PM PDT 24
Peak memory 204644 kb
Host smart-1e077cbc-aec4-4b20-be19-164f3abe1117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175262872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1175262872
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.183427863
Short name T842
Test name
Test status
Simulation time 1123660812 ps
CPU time 5.41 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:42 PM PDT 24
Peak memory 212640 kb
Host smart-f91b9dd5-9c99-446d-a12f-85abbce56b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183427863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.183427863
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.648871436
Short name T978
Test name
Test status
Simulation time 17243138224 ps
CPU time 83.46 seconds
Started May 26 12:47:39 PM PDT 24
Finished May 26 12:49:03 PM PDT 24
Peak memory 1329172 kb
Host smart-105cf898-1892-476d-984b-3dfa47bdd18b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648871436 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.648871436
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2236967822
Short name T1161
Test name
Test status
Simulation time 1617787075 ps
CPU time 30.48 seconds
Started May 26 12:47:29 PM PDT 24
Finished May 26 12:48:00 PM PDT 24
Peak memory 204552 kb
Host smart-cf366d8c-8f5f-4b0a-9711-f796b481755d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236967822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2236967822
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3843127079
Short name T500
Test name
Test status
Simulation time 947815879 ps
CPU time 39.8 seconds
Started May 26 12:47:28 PM PDT 24
Finished May 26 12:48:08 PM PDT 24
Peak memory 204488 kb
Host smart-731079f4-c5c3-4f37-9c4a-3a138f79fc64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843127079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3843127079
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1009978313
Short name T1041
Test name
Test status
Simulation time 41729589537 ps
CPU time 41.61 seconds
Started May 26 12:47:27 PM PDT 24
Finished May 26 12:48:09 PM PDT 24
Peak memory 907336 kb
Host smart-3902cc93-cbfd-499c-aac7-446a1983534a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009978313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1009978313
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3839338115
Short name T349
Test name
Test status
Simulation time 2566671379 ps
CPU time 23.39 seconds
Started May 26 12:47:29 PM PDT 24
Finished May 26 12:47:52 PM PDT 24
Peak memory 276364 kb
Host smart-2e166b33-d7f3-45a9-b867-9799f0ff346e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839338115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3839338115
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3825335254
Short name T1268
Test name
Test status
Simulation time 3266977516 ps
CPU time 7.88 seconds
Started May 26 12:47:38 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 220828 kb
Host smart-d916ff93-7582-4b1d-9f5f-48ad0fdc0f6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825335254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3825335254
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1412335014
Short name T971
Test name
Test status
Simulation time 16412055 ps
CPU time 0.63 seconds
Started May 26 12:47:47 PM PDT 24
Finished May 26 12:47:48 PM PDT 24
Peak memory 204160 kb
Host smart-e13f6c0e-94cb-4feb-9531-38b2981b2bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412335014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1412335014
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1626271363
Short name T448
Test name
Test status
Simulation time 72561450 ps
CPU time 1.78 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:39 PM PDT 24
Peak memory 212744 kb
Host smart-ac1638bd-7d97-4d42-ab09-e01e61f3792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626271363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1626271363
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1304729463
Short name T536
Test name
Test status
Simulation time 1481507973 ps
CPU time 8.91 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 282760 kb
Host smart-5d5d7c47-bb59-4f9c-a5c6-9a96bb1835a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304729463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1304729463
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.361616349
Short name T43
Test name
Test status
Simulation time 8567440116 ps
CPU time 55.39 seconds
Started May 26 12:47:38 PM PDT 24
Finished May 26 12:48:34 PM PDT 24
Peak memory 342620 kb
Host smart-6785c676-5b8a-4324-9e57-2295b5d060bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361616349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.361616349
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.115412770
Short name T776
Test name
Test status
Simulation time 12093692799 ps
CPU time 88.62 seconds
Started May 26 12:47:39 PM PDT 24
Finished May 26 12:49:08 PM PDT 24
Peak memory 822588 kb
Host smart-0e1e3059-d33c-4219-9837-e836c8a9a627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115412770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.115412770
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1002084851
Short name T62
Test name
Test status
Simulation time 97598480 ps
CPU time 0.91 seconds
Started May 26 12:47:38 PM PDT 24
Finished May 26 12:47:39 PM PDT 24
Peak memory 204236 kb
Host smart-469c93b8-1c2e-451d-997b-f11f01653f23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002084851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1002084851
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2935432614
Short name T1056
Test name
Test status
Simulation time 619907341 ps
CPU time 8.49 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:47:47 PM PDT 24
Peak memory 227364 kb
Host smart-d4fe21a4-f917-4e34-9c58-6414a310a977
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935432614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2935432614
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1253397006
Short name T588
Test name
Test status
Simulation time 14439623188 ps
CPU time 130.34 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:49:49 PM PDT 24
Peak memory 1212072 kb
Host smart-4ff80dc3-15b5-40be-9391-2313cbf003c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253397006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1253397006
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.1042234877
Short name T245
Test name
Test status
Simulation time 958843074 ps
CPU time 5.68 seconds
Started May 26 12:47:46 PM PDT 24
Finished May 26 12:47:53 PM PDT 24
Peak memory 204404 kb
Host smart-c272633b-a88c-4ff4-ba01-ff45dd0757b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042234877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1042234877
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2434919373
Short name T342
Test name
Test status
Simulation time 1713107964 ps
CPU time 72.23 seconds
Started May 26 12:47:48 PM PDT 24
Finished May 26 12:49:01 PM PDT 24
Peak memory 302212 kb
Host smart-ff15e9cc-239e-4ddd-b072-caecc6a803f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434919373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2434919373
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.867898606
Short name T1449
Test name
Test status
Simulation time 18581005 ps
CPU time 0.67 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:47:37 PM PDT 24
Peak memory 204148 kb
Host smart-5895534e-c6eb-4cfe-b323-73898eb44aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867898606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.867898606
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3049774903
Short name T690
Test name
Test status
Simulation time 11965512840 ps
CPU time 398.66 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:54:15 PM PDT 24
Peak memory 2248240 kb
Host smart-21fbd4c2-fc74-460c-96ae-723c337350dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049774903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3049774903
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.376710348
Short name T293
Test name
Test status
Simulation time 16448701540 ps
CPU time 124.17 seconds
Started May 26 12:47:36 PM PDT 24
Finished May 26 12:49:41 PM PDT 24
Peak memory 447444 kb
Host smart-a5a184d1-36b7-4a9a-ad71-9e02a1424eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376710348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.376710348
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2111892967
Short name T1295
Test name
Test status
Simulation time 9756169587 ps
CPU time 1093.34 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 01:05:52 PM PDT 24
Peak memory 2095148 kb
Host smart-c9b3f82f-3853-4103-9d69-2f30469ff9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111892967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2111892967
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1841749058
Short name T1150
Test name
Test status
Simulation time 1490194075 ps
CPU time 37.74 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:48:15 PM PDT 24
Peak memory 212568 kb
Host smart-9d646809-1123-4716-a26d-ad1dfdbd02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841749058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1841749058
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3317108198
Short name T877
Test name
Test status
Simulation time 4177124240 ps
CPU time 5.15 seconds
Started May 26 12:47:45 PM PDT 24
Finished May 26 12:47:50 PM PDT 24
Peak memory 215892 kb
Host smart-bef5fd83-2129-4140-9e72-5b52e6a5f7f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317108198 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3317108198
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3751328577
Short name T1236
Test name
Test status
Simulation time 10240365262 ps
CPU time 8.68 seconds
Started May 26 12:47:45 PM PDT 24
Finished May 26 12:47:54 PM PDT 24
Peak memory 221964 kb
Host smart-8024c1fe-cba2-4618-b83b-fd35d3275307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751328577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3751328577
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1044871090
Short name T1047
Test name
Test status
Simulation time 10101551226 ps
CPU time 35.59 seconds
Started May 26 12:47:48 PM PDT 24
Finished May 26 12:48:24 PM PDT 24
Peak memory 460124 kb
Host smart-fd7e398f-53fe-439e-af0b-b26b4c580ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044871090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1044871090
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2624151714
Short name T1413
Test name
Test status
Simulation time 1370949548 ps
CPU time 2.05 seconds
Started May 26 12:47:44 PM PDT 24
Finished May 26 12:47:46 PM PDT 24
Peak memory 204456 kb
Host smart-1901b3cc-c100-45b8-a29a-562a91dd2e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624151714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2624151714
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.412984522
Short name T629
Test name
Test status
Simulation time 1159086130 ps
CPU time 1.21 seconds
Started May 26 12:47:45 PM PDT 24
Finished May 26 12:47:47 PM PDT 24
Peak memory 204336 kb
Host smart-292c9991-24bb-40cd-9b77-a86928513fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412984522 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.412984522
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3689694817
Short name T11
Test name
Test status
Simulation time 2529353704 ps
CPU time 3.1 seconds
Started May 26 12:47:49 PM PDT 24
Finished May 26 12:47:53 PM PDT 24
Peak memory 204548 kb
Host smart-17b835c6-75bb-41d3-a4fa-a55058843cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689694817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3689694817
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2855450976
Short name T1440
Test name
Test status
Simulation time 751259052 ps
CPU time 4.72 seconds
Started May 26 12:47:47 PM PDT 24
Finished May 26 12:47:52 PM PDT 24
Peak memory 204500 kb
Host smart-f4eb5126-f7e8-4d51-88b3-f4e1d005ea02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855450976 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2855450976
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1275650796
Short name T783
Test name
Test status
Simulation time 16827095039 ps
CPU time 4.98 seconds
Started May 26 12:47:44 PM PDT 24
Finished May 26 12:47:49 PM PDT 24
Peak memory 204480 kb
Host smart-f322fbbc-d1f7-4aa9-bf90-a87ead366108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275650796 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1275650796
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1140810147
Short name T1307
Test name
Test status
Simulation time 2236864785 ps
CPU time 18.71 seconds
Started May 26 12:47:37 PM PDT 24
Finished May 26 12:47:57 PM PDT 24
Peak memory 204552 kb
Host smart-e2fbc51d-7c99-4b83-af1f-fc4622ea1c59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140810147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1140810147
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1728579785
Short name T811
Test name
Test status
Simulation time 1223279806 ps
CPU time 50.58 seconds
Started May 26 12:47:50 PM PDT 24
Finished May 26 12:48:41 PM PDT 24
Peak memory 204456 kb
Host smart-144bbdd1-b33c-4f76-904a-3f5deb2575e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728579785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1728579785
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3921964508
Short name T1294
Test name
Test status
Simulation time 35525827832 ps
CPU time 57.03 seconds
Started May 26 12:47:47 PM PDT 24
Finished May 26 12:48:45 PM PDT 24
Peak memory 1027016 kb
Host smart-1c9ae344-3705-4782-8d62-a900eb8ca94b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921964508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3921964508
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2902601632
Short name T281
Test name
Test status
Simulation time 6631582500 ps
CPU time 560.23 seconds
Started May 26 12:47:46 PM PDT 24
Finished May 26 12:57:08 PM PDT 24
Peak memory 1690456 kb
Host smart-ddffdbeb-55c3-4747-9c11-9c5b65c02872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902601632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2902601632
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4259299205
Short name T1253
Test name
Test status
Simulation time 29255239943 ps
CPU time 7.94 seconds
Started May 26 12:47:47 PM PDT 24
Finished May 26 12:47:56 PM PDT 24
Peak memory 212888 kb
Host smart-0784efc6-f343-453d-ab0f-0564c6675559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259299205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.4259299205
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.755255580
Short name T674
Test name
Test status
Simulation time 46981014 ps
CPU time 0.64 seconds
Started May 26 12:48:04 PM PDT 24
Finished May 26 12:48:05 PM PDT 24
Peak memory 204196 kb
Host smart-b66742ef-e2d9-47d9-bcda-b1dbdaf135dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755255580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.755255580
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1020797417
Short name T41
Test name
Test status
Simulation time 156701597 ps
CPU time 6.3 seconds
Started May 26 12:47:55 PM PDT 24
Finished May 26 12:48:02 PM PDT 24
Peak memory 236284 kb
Host smart-a68b55e7-d159-4219-becc-42dc1bb46165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020797417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1020797417
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3152115265
Short name T820
Test name
Test status
Simulation time 868136550 ps
CPU time 11.75 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:14 PM PDT 24
Peak memory 246892 kb
Host smart-da7fa369-3cd1-4b81-80c6-7ba72635785d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152115265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3152115265
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4276458841
Short name T794
Test name
Test status
Simulation time 2987896175 ps
CPU time 112.37 seconds
Started May 26 12:47:53 PM PDT 24
Finished May 26 12:49:46 PM PDT 24
Peak memory 904256 kb
Host smart-2ce27552-8bc3-46ae-8f56-35dd458ae622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276458841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4276458841
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2077559186
Short name T855
Test name
Test status
Simulation time 4075532141 ps
CPU time 75.87 seconds
Started May 26 12:47:48 PM PDT 24
Finished May 26 12:49:04 PM PDT 24
Peak memory 702140 kb
Host smart-7d5a7459-7471-4aef-84c5-f8c0e19b32d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077559186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2077559186
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2356633899
Short name T1143
Test name
Test status
Simulation time 258985621 ps
CPU time 0.96 seconds
Started May 26 12:47:46 PM PDT 24
Finished May 26 12:47:48 PM PDT 24
Peak memory 204212 kb
Host smart-0260c3e7-e294-4d6a-befb-4eeedaebb44e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356633899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2356633899
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1239755456
Short name T525
Test name
Test status
Simulation time 136994807 ps
CPU time 3.37 seconds
Started May 26 12:48:00 PM PDT 24
Finished May 26 12:48:04 PM PDT 24
Peak memory 222524 kb
Host smart-f032c057-f4a3-49c8-86fe-3e62086aa990
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239755456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1239755456
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2658673191
Short name T1445
Test name
Test status
Simulation time 2963820623 ps
CPU time 212.58 seconds
Started May 26 12:47:45 PM PDT 24
Finished May 26 12:51:18 PM PDT 24
Peak memory 907604 kb
Host smart-fa054e51-de9a-4789-bcf7-7280f19f2841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658673191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2658673191
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2757435655
Short name T1152
Test name
Test status
Simulation time 2582410076 ps
CPU time 4.07 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:07 PM PDT 24
Peak memory 204568 kb
Host smart-6decfc7c-9341-49cf-998c-a4621a0197a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757435655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2757435655
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3151107914
Short name T1436
Test name
Test status
Simulation time 26694418840 ps
CPU time 64.5 seconds
Started May 26 12:48:05 PM PDT 24
Finished May 26 12:49:10 PM PDT 24
Peak memory 294644 kb
Host smart-2a8f7b11-0a7a-43af-b38b-5ff553d8a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151107914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3151107914
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1548455724
Short name T1061
Test name
Test status
Simulation time 36719916 ps
CPU time 0.64 seconds
Started May 26 12:47:48 PM PDT 24
Finished May 26 12:47:49 PM PDT 24
Peak memory 204212 kb
Host smart-facab566-a5f5-44a6-ad44-c3633befbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548455724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1548455724
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1962499077
Short name T656
Test name
Test status
Simulation time 12000894885 ps
CPU time 414.42 seconds
Started May 26 12:47:54 PM PDT 24
Finished May 26 12:54:49 PM PDT 24
Peak memory 204512 kb
Host smart-a49738f0-e29b-4a10-b6b1-91ad2a1185a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962499077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1962499077
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2650774383
Short name T1065
Test name
Test status
Simulation time 8591829890 ps
CPU time 36.56 seconds
Started May 26 12:47:48 PM PDT 24
Finished May 26 12:48:25 PM PDT 24
Peak memory 345288 kb
Host smart-de086be7-dbe7-4980-85dc-95e08b53a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650774383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2650774383
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.4218009626
Short name T257
Test name
Test status
Simulation time 1251887433 ps
CPU time 29 seconds
Started May 26 12:47:52 PM PDT 24
Finished May 26 12:48:22 PM PDT 24
Peak memory 212576 kb
Host smart-815f6440-86be-46e1-aecb-ee61d31a3d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218009626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.4218009626
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.353714533
Short name T1008
Test name
Test status
Simulation time 4501888819 ps
CPU time 5.72 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:08 PM PDT 24
Peak memory 204560 kb
Host smart-99675146-e4b2-4bab-a5c6-899396b03168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353714533 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.353714533
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.452447400
Short name T1067
Test name
Test status
Simulation time 10157674588 ps
CPU time 12.39 seconds
Started May 26 12:48:04 PM PDT 24
Finished May 26 12:48:17 PM PDT 24
Peak memory 255324 kb
Host smart-af99a04c-3272-4cfa-9b38-1ab6e0461048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452447400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.452447400
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2580593448
Short name T528
Test name
Test status
Simulation time 10207311391 ps
CPU time 69.2 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:49:12 PM PDT 24
Peak memory 514784 kb
Host smart-44e4a12c-c3c0-4fc1-bfdd-6ef93724e8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580593448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2580593448
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.3703010226
Short name T1255
Test name
Test status
Simulation time 1108403737 ps
CPU time 4.81 seconds
Started May 26 12:48:03 PM PDT 24
Finished May 26 12:48:09 PM PDT 24
Peak memory 204608 kb
Host smart-a0901031-1218-4f29-b22f-a8f538215147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703010226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.3703010226
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.2446847310
Short name T1335
Test name
Test status
Simulation time 1074211939 ps
CPU time 6.36 seconds
Started May 26 12:48:04 PM PDT 24
Finished May 26 12:48:11 PM PDT 24
Peak memory 204428 kb
Host smart-4ebcef30-7724-4235-8624-48ebe0296f44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446847310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.2446847310
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2599517228
Short name T280
Test name
Test status
Simulation time 1756167288 ps
CPU time 2.71 seconds
Started May 26 12:48:04 PM PDT 24
Finished May 26 12:48:08 PM PDT 24
Peak memory 204520 kb
Host smart-e5736996-ad8c-4fd7-b150-579708239e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599517228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2599517228
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2724214517
Short name T326
Test name
Test status
Simulation time 605289450 ps
CPU time 3.6 seconds
Started May 26 12:47:54 PM PDT 24
Finished May 26 12:47:58 PM PDT 24
Peak memory 204468 kb
Host smart-fadfa07b-a3cd-4068-9ae6-8c4f5abd9f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724214517 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2724214517
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1976497578
Short name T977
Test name
Test status
Simulation time 12154287740 ps
CPU time 27.2 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:30 PM PDT 24
Peak memory 754188 kb
Host smart-e97f36cd-ceb2-4b98-94f0-c42d08b2f6a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976497578 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1976497578
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.634203975
Short name T845
Test name
Test status
Simulation time 1362903759 ps
CPU time 22.32 seconds
Started May 26 12:47:52 PM PDT 24
Finished May 26 12:48:15 PM PDT 24
Peak memory 204548 kb
Host smart-9beaf3cd-e473-4e6a-bbbb-2e7c92907534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634203975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.634203975
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1084141538
Short name T572
Test name
Test status
Simulation time 631496579 ps
CPU time 11.28 seconds
Started May 26 12:47:53 PM PDT 24
Finished May 26 12:48:04 PM PDT 24
Peak memory 210792 kb
Host smart-fc699bc3-d8c1-477f-814e-821ec0acca62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084141538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1084141538
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3617004627
Short name T741
Test name
Test status
Simulation time 9911798274 ps
CPU time 4.74 seconds
Started May 26 12:48:01 PM PDT 24
Finished May 26 12:48:06 PM PDT 24
Peak memory 204520 kb
Host smart-cce533f0-9b7b-4be0-a5cb-f9302137f01a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617004627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3617004627
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1358275596
Short name T733
Test name
Test status
Simulation time 996581116 ps
CPU time 15.19 seconds
Started May 26 12:47:54 PM PDT 24
Finished May 26 12:48:09 PM PDT 24
Peak memory 340664 kb
Host smart-30eaa89a-82ef-41e6-b026-32b16f48a598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358275596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1358275596
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3938999854
Short name T514
Test name
Test status
Simulation time 5768199755 ps
CPU time 6.81 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:09 PM PDT 24
Peak memory 204452 kb
Host smart-8c8d431f-8536-4447-92a7-16493a3d9ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938999854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3938999854
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.553807933
Short name T606
Test name
Test status
Simulation time 43620801 ps
CPU time 0.63 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:21 PM PDT 24
Peak memory 204056 kb
Host smart-c81974f0-ecbd-4c04-afcd-12d7e7d21d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553807933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.553807933
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2652586801
Short name T1099
Test name
Test status
Simulation time 1013653379 ps
CPU time 4.15 seconds
Started May 26 12:48:12 PM PDT 24
Finished May 26 12:48:17 PM PDT 24
Peak memory 247364 kb
Host smart-521a1990-e6d6-4cc1-9baa-b7dc2fb1b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652586801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2652586801
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3684588180
Short name T475
Test name
Test status
Simulation time 2175096517 ps
CPU time 21.67 seconds
Started May 26 12:48:14 PM PDT 24
Finished May 26 12:48:37 PM PDT 24
Peak memory 278164 kb
Host smart-a60b3aef-7919-45a8-a0b1-7ebc8ea4a471
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684588180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3684588180
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2854504423
Short name T1012
Test name
Test status
Simulation time 2476846092 ps
CPU time 92.95 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:49:47 PM PDT 24
Peak memory 821248 kb
Host smart-b4c6340d-4e0d-4947-82f3-921c88b235fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854504423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2854504423
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2602782314
Short name T697
Test name
Test status
Simulation time 1919540044 ps
CPU time 58.36 seconds
Started May 26 12:48:12 PM PDT 24
Finished May 26 12:49:11 PM PDT 24
Peak memory 664332 kb
Host smart-ee1e2116-efd0-4ea3-8ff2-eac084ff1399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602782314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2602782314
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1429715708
Short name T1042
Test name
Test status
Simulation time 227102655 ps
CPU time 1.12 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:48:13 PM PDT 24
Peak memory 204408 kb
Host smart-acc41e1f-f136-4b13-aeb3-2148154b7a75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429715708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1429715708
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.826362114
Short name T788
Test name
Test status
Simulation time 507043144 ps
CPU time 6.72 seconds
Started May 26 12:48:14 PM PDT 24
Finished May 26 12:48:21 PM PDT 24
Peak memory 221096 kb
Host smart-c77f677e-bfe1-48da-b725-6c9a8428b98e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826362114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
826362114
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.868985149
Short name T758
Test name
Test status
Simulation time 4648661736 ps
CPU time 137.69 seconds
Started May 26 12:48:03 PM PDT 24
Finished May 26 12:50:21 PM PDT 24
Peak memory 1315224 kb
Host smart-a041f86b-cbc0-431b-b805-192058c0bd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868985149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.868985149
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3658815725
Short name T239
Test name
Test status
Simulation time 4309540270 ps
CPU time 5.43 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:48:18 PM PDT 24
Peak memory 204568 kb
Host smart-59394507-2eb4-4767-875d-6a1f1308164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658815725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3658815725
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1680916393
Short name T1112
Test name
Test status
Simulation time 4886600865 ps
CPU time 35.01 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:48:48 PM PDT 24
Peak memory 384452 kb
Host smart-e4bec39b-ad21-401c-b8df-84fea885dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680916393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1680916393
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2090382933
Short name T135
Test name
Test status
Simulation time 46435216 ps
CPU time 0.65 seconds
Started May 26 12:48:02 PM PDT 24
Finished May 26 12:48:04 PM PDT 24
Peak memory 204124 kb
Host smart-fefcf24b-62e2-42eb-8b2e-af2c406358c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090382933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2090382933
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1102239240
Short name T947
Test name
Test status
Simulation time 18324037747 ps
CPU time 87.7 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:49:41 PM PDT 24
Peak memory 502496 kb
Host smart-d01c62ac-7736-45e0-b990-78aa8e1030d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102239240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1102239240
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.954304377
Short name T518
Test name
Test status
Simulation time 5482217324 ps
CPU time 24.69 seconds
Started May 26 12:48:03 PM PDT 24
Finished May 26 12:48:28 PM PDT 24
Peak memory 281148 kb
Host smart-3358f7e2-5af7-461e-8066-101835cf7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954304377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.954304377
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.394630895
Short name T835
Test name
Test status
Simulation time 2095074088 ps
CPU time 24.14 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:48:36 PM PDT 24
Peak memory 212708 kb
Host smart-34975457-a5fa-4328-a184-400cf7ebfac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394630895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.394630895
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1374134898
Short name T1181
Test name
Test status
Simulation time 1203073252 ps
CPU time 3.7 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:48:17 PM PDT 24
Peak memory 204484 kb
Host smart-8d839246-2d3e-48a7-90a4-ec78e4526661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374134898 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1374134898
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.968837208
Short name T589
Test name
Test status
Simulation time 10250489030 ps
CPU time 13.12 seconds
Started May 26 12:48:15 PM PDT 24
Finished May 26 12:48:28 PM PDT 24
Peak memory 262588 kb
Host smart-8857b0b8-f08e-4e12-a84e-b2416ee23f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968837208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.968837208
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3811891108
Short name T917
Test name
Test status
Simulation time 10137451164 ps
CPU time 66.57 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:49:18 PM PDT 24
Peak memory 508992 kb
Host smart-5c028ab7-96d4-410f-9156-6e0556316548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811891108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3811891108
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.1465491082
Short name T848
Test name
Test status
Simulation time 1122896229 ps
CPU time 5.44 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:27 PM PDT 24
Peak memory 204436 kb
Host smart-226982cc-0f3f-401a-9f13-5e7e28d9de45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465491082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.1465491082
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.868467460
Short name T591
Test name
Test status
Simulation time 1263842045 ps
CPU time 2.05 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:23 PM PDT 24
Peak memory 204588 kb
Host smart-b27989af-95ec-4781-aa77-c5c069beba14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868467460 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.868467460
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2965184495
Short name T1071
Test name
Test status
Simulation time 3431872595 ps
CPU time 2.41 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:48:16 PM PDT 24
Peak memory 204632 kb
Host smart-64c16314-c7df-4aa5-a8b3-b915a658f060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965184495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2965184495
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.672146913
Short name T668
Test name
Test status
Simulation time 841631874 ps
CPU time 5.03 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:48:19 PM PDT 24
Peak memory 212644 kb
Host smart-6250f98c-cef1-4b5a-b7d0-5a33646c2c6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672146913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.672146913
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1618306875
Short name T918
Test name
Test status
Simulation time 11881321932 ps
CPU time 12 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:48:24 PM PDT 24
Peak memory 339928 kb
Host smart-45ff703d-3852-48fb-9e12-8d295e7ca555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618306875 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1618306875
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3014990256
Short name T1201
Test name
Test status
Simulation time 3363250647 ps
CPU time 13.57 seconds
Started May 26 12:48:12 PM PDT 24
Finished May 26 12:48:26 PM PDT 24
Peak memory 204520 kb
Host smart-1fbcae61-21df-4cdd-852b-2d4a714e07c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014990256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3014990256
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2493531906
Short name T570
Test name
Test status
Simulation time 4376981034 ps
CPU time 19.13 seconds
Started May 26 12:48:12 PM PDT 24
Finished May 26 12:48:32 PM PDT 24
Peak memory 215688 kb
Host smart-be256421-b814-4cb2-96cc-b5a4e92eeb04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493531906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2493531906
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.4116211513
Short name T946
Test name
Test status
Simulation time 34200924862 ps
CPU time 48.8 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:49:00 PM PDT 24
Peak memory 966284 kb
Host smart-145fa7a5-afc9-4fcc-a274-8c5728f70c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116211513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.4116211513
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1508227789
Short name T300
Test name
Test status
Simulation time 23847215556 ps
CPU time 152.48 seconds
Started May 26 12:48:11 PM PDT 24
Finished May 26 12:50:44 PM PDT 24
Peak memory 1465632 kb
Host smart-54575fac-a944-455c-82ab-8970d578e423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508227789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1508227789
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1304434418
Short name T346
Test name
Test status
Simulation time 1364278637 ps
CPU time 7.92 seconds
Started May 26 12:48:13 PM PDT 24
Finished May 26 12:48:22 PM PDT 24
Peak memory 220744 kb
Host smart-6f8ee029-d11a-4d1f-9a51-eea35c7753f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304434418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1304434418
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3180682232
Short name T618
Test name
Test status
Simulation time 16974803 ps
CPU time 0.63 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:32 PM PDT 24
Peak memory 204084 kb
Host smart-3a5d620a-8119-45ac-a13e-3e033a1b726c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180682232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3180682232
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2931751906
Short name T1357
Test name
Test status
Simulation time 239161579 ps
CPU time 3.8 seconds
Started May 26 12:48:22 PM PDT 24
Finished May 26 12:48:26 PM PDT 24
Peak memory 204520 kb
Host smart-4156183d-54be-4320-b0fc-14fa8ce936be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931751906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2931751906
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.518255196
Short name T331
Test name
Test status
Simulation time 314390480 ps
CPU time 5.73 seconds
Started May 26 12:48:21 PM PDT 24
Finished May 26 12:48:28 PM PDT 24
Peak memory 266520 kb
Host smart-872ca837-148e-4546-b57f-e1959318e8f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518255196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.518255196
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1757979221
Short name T689
Test name
Test status
Simulation time 7949544043 ps
CPU time 90.75 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:49:51 PM PDT 24
Peak memory 820288 kb
Host smart-9eab99a8-a9a9-4bb3-b902-8badc6406d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757979221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1757979221
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2803848753
Short name T1435
Test name
Test status
Simulation time 3836380542 ps
CPU time 65.28 seconds
Started May 26 12:48:19 PM PDT 24
Finished May 26 12:49:25 PM PDT 24
Peak memory 670920 kb
Host smart-d7c90020-b7c3-459e-8c43-9624fd49680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803848753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2803848753
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2283383622
Short name T1323
Test name
Test status
Simulation time 445120217 ps
CPU time 0.92 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:22 PM PDT 24
Peak memory 204192 kb
Host smart-de2067fc-3fca-4563-b6fd-ef1d3cd44447
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283383622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2283383622
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2587349975
Short name T639
Test name
Test status
Simulation time 200635861 ps
CPU time 10.05 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:31 PM PDT 24
Peak memory 204392 kb
Host smart-b986c6e9-9523-4d83-a147-2eac3bb4ff7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587349975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2587349975
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3704437963
Short name T1352
Test name
Test status
Simulation time 2884603629 ps
CPU time 189.84 seconds
Started May 26 12:48:22 PM PDT 24
Finished May 26 12:51:33 PM PDT 24
Peak memory 889600 kb
Host smart-6125f0ad-8043-4635-8e0e-fd79147d7924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704437963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3704437963
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2345223068
Short name T379
Test name
Test status
Simulation time 390130269 ps
CPU time 15.92 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:46 PM PDT 24
Peak memory 204488 kb
Host smart-447756cb-8aa4-4ff2-846c-adc51cc7102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345223068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2345223068
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3862093773
Short name T68
Test name
Test status
Simulation time 12251039062 ps
CPU time 37.24 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:49:08 PM PDT 24
Peak memory 335368 kb
Host smart-965f3d4d-b32c-472e-8eb6-c8d84b91b467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862093773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3862093773
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.734665801
Short name T423
Test name
Test status
Simulation time 36742628 ps
CPU time 0.62 seconds
Started May 26 12:48:19 PM PDT 24
Finished May 26 12:48:20 PM PDT 24
Peak memory 204120 kb
Host smart-216e73d6-9c3e-42c2-ada7-b9b8275cee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734665801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.734665801
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2661875224
Short name T1405
Test name
Test status
Simulation time 17810547165 ps
CPU time 410.6 seconds
Started May 26 12:48:21 PM PDT 24
Finished May 26 12:55:13 PM PDT 24
Peak memory 1807804 kb
Host smart-5d1e1565-6cc6-459e-9ae2-b820d1752088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661875224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2661875224
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1650472049
Short name T796
Test name
Test status
Simulation time 1173340386 ps
CPU time 20.6 seconds
Started May 26 12:48:21 PM PDT 24
Finished May 26 12:48:43 PM PDT 24
Peak memory 332068 kb
Host smart-f5d2d033-c27f-4dbc-b1d0-9d705cdb1055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650472049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1650472049
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2393452874
Short name T1155
Test name
Test status
Simulation time 14349458457 ps
CPU time 1236.47 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 01:08:58 PM PDT 24
Peak memory 3039688 kb
Host smart-b8aec2ba-315c-4fc5-813a-3b6d5276fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393452874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2393452874
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.977781558
Short name T963
Test name
Test status
Simulation time 1004601874 ps
CPU time 48.56 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:49:09 PM PDT 24
Peak memory 212656 kb
Host smart-3d30c44b-3c5d-433a-8396-ae92bfd1cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977781558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.977781558
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.144376941
Short name T27
Test name
Test status
Simulation time 847993487 ps
CPU time 2.55 seconds
Started May 26 12:48:32 PM PDT 24
Finished May 26 12:48:35 PM PDT 24
Peak memory 204540 kb
Host smart-137f2d56-bfa5-4135-a484-f63d5d4817c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144376941 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.144376941
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4179760520
Short name T394
Test name
Test status
Simulation time 10580338812 ps
CPU time 6.53 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:48:36 PM PDT 24
Peak memory 216744 kb
Host smart-7b927b56-bb34-461f-ade3-4d2e4f791d6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179760520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4179760520
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.342434943
Short name T86
Test name
Test status
Simulation time 10110757848 ps
CPU time 82.63 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:49:54 PM PDT 24
Peak memory 620556 kb
Host smart-52cc455f-f570-4b30-9614-5125100a0268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342434943 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.342434943
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3278744304
Short name T886
Test name
Test status
Simulation time 1113735821 ps
CPU time 4.95 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:48:35 PM PDT 24
Peak memory 204512 kb
Host smart-a44f7aac-b8e7-451c-ba68-efc64848de82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278744304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3278744304
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.3495536008
Short name T1175
Test name
Test status
Simulation time 1485480989 ps
CPU time 1.91 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:32 PM PDT 24
Peak memory 204456 kb
Host smart-2a6167a4-4506-43a8-b335-56b97f0095e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495536008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3495536008
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1895780723
Short name T1301
Test name
Test status
Simulation time 772781783 ps
CPU time 2.81 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:33 PM PDT 24
Peak memory 204568 kb
Host smart-b069a8c1-d2dd-4236-bc15-fb1361040834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895780723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1895780723
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3239822470
Short name T166
Test name
Test status
Simulation time 1408071519 ps
CPU time 3.46 seconds
Started May 26 12:48:19 PM PDT 24
Finished May 26 12:48:23 PM PDT 24
Peak memory 204512 kb
Host smart-1ef05948-f9c3-47cb-8dc2-61548bc8527b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239822470 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3239822470
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1227170668
Short name T1398
Test name
Test status
Simulation time 17855661140 ps
CPU time 47.77 seconds
Started May 26 12:48:23 PM PDT 24
Finished May 26 12:49:12 PM PDT 24
Peak memory 1049384 kb
Host smart-1cabaf60-6df4-4d23-9a55-cbda55eb9be3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227170668 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1227170668
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1906892389
Short name T704
Test name
Test status
Simulation time 8476922480 ps
CPU time 5.7 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:27 PM PDT 24
Peak memory 204428 kb
Host smart-822f81e8-87c8-4450-b5b4-870a06febcbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906892389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1906892389
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2969254710
Short name T286
Test name
Test status
Simulation time 1748864978 ps
CPU time 25.64 seconds
Started May 26 12:48:20 PM PDT 24
Finished May 26 12:48:46 PM PDT 24
Peak memory 231080 kb
Host smart-28be2c02-3044-48cf-b04e-81a9f20b2655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969254710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2969254710
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2668224562
Short name T444
Test name
Test status
Simulation time 46775935056 ps
CPU time 311.18 seconds
Started May 26 12:48:21 PM PDT 24
Finished May 26 12:53:33 PM PDT 24
Peak memory 3391672 kb
Host smart-1ef9781e-27ee-4476-830f-5d589c09fd68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668224562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2668224562
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.37153390
Short name T1257
Test name
Test status
Simulation time 17921649065 ps
CPU time 76.16 seconds
Started May 26 12:48:23 PM PDT 24
Finished May 26 12:49:40 PM PDT 24
Peak memory 900280 kb
Host smart-5c51aec8-2352-4162-8acc-458af86b4b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37153390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_stretch.37153390
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.101880549
Short name T482
Test name
Test status
Simulation time 1539631590 ps
CPU time 8.4 seconds
Started May 26 12:48:23 PM PDT 24
Finished May 26 12:48:32 PM PDT 24
Peak memory 218472 kb
Host smart-480ff850-cb07-4084-8355-668fd190221f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101880549 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.101880549
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2439481850
Short name T179
Test name
Test status
Simulation time 65576380 ps
CPU time 0.61 seconds
Started May 26 12:48:42 PM PDT 24
Finished May 26 12:48:43 PM PDT 24
Peak memory 204156 kb
Host smart-744d09ba-1eb6-4f9e-aae0-55727e9788af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439481850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2439481850
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3110998070
Short name T1275
Test name
Test status
Simulation time 83473580 ps
CPU time 1.64 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:48:31 PM PDT 24
Peak memory 212716 kb
Host smart-ed2df200-d07d-4fa6-a939-bc06a0ce81cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110998070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3110998070
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1118359166
Short name T581
Test name
Test status
Simulation time 469092397 ps
CPU time 26.5 seconds
Started May 26 12:48:28 PM PDT 24
Finished May 26 12:48:55 PM PDT 24
Peak memory 311024 kb
Host smart-577afcbb-2c77-40b4-b02b-f4d3f663b6f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118359166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1118359166
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1753225691
Short name T1374
Test name
Test status
Simulation time 4622398956 ps
CPU time 170.42 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:51:22 PM PDT 24
Peak memory 769244 kb
Host smart-94f556b3-632b-4c40-b94c-61cd7cf31e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753225691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1753225691
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.68243585
Short name T422
Test name
Test status
Simulation time 2309608607 ps
CPU time 174.78 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:51:25 PM PDT 24
Peak memory 717728 kb
Host smart-046c4fc9-562a-4019-bb16-721419012629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68243585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.68243585
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4036220595
Short name T1060
Test name
Test status
Simulation time 112801642 ps
CPU time 1.07 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:48:33 PM PDT 24
Peak memory 204232 kb
Host smart-cb34aa27-c22e-47f3-9985-3e26d0023b38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036220595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4036220595
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.785292576
Short name T1297
Test name
Test status
Simulation time 223283503 ps
CPU time 5.33 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:36 PM PDT 24
Peak memory 204412 kb
Host smart-809d6329-94ba-4502-8a27-504417050819
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785292576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.
785292576
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1072938484
Short name T1172
Test name
Test status
Simulation time 24315852981 ps
CPU time 189.33 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:51:41 PM PDT 24
Peak memory 1530664 kb
Host smart-859014be-a65d-4964-8013-3cc8457584bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072938484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1072938484
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.693047682
Short name T879
Test name
Test status
Simulation time 2132373607 ps
CPU time 9.62 seconds
Started May 26 12:48:41 PM PDT 24
Finished May 26 12:48:51 PM PDT 24
Peak memory 204432 kb
Host smart-76e5d182-33b4-4126-a676-6ee17cbd4a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693047682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.693047682
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.3964853337
Short name T404
Test name
Test status
Simulation time 45693757 ps
CPU time 0.69 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:48:31 PM PDT 24
Peak memory 204100 kb
Host smart-08de6299-b9e5-4843-97ff-9b6f5e21d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964853337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3964853337
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2075280538
Short name T651
Test name
Test status
Simulation time 7694648912 ps
CPU time 41.41 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:49:13 PM PDT 24
Peak memory 586088 kb
Host smart-7f39d31b-f480-4aac-ac4f-e2d43b22a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075280538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2075280538
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3433395843
Short name T580
Test name
Test status
Simulation time 7377214951 ps
CPU time 36.15 seconds
Started May 26 12:48:28 PM PDT 24
Finished May 26 12:49:05 PM PDT 24
Peak memory 330472 kb
Host smart-f626214c-465a-43a2-8fd6-1c8dfdcb9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433395843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3433395843
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2980805432
Short name T1337
Test name
Test status
Simulation time 13681733366 ps
CPU time 970.29 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 01:04:42 PM PDT 24
Peak memory 3343524 kb
Host smart-cb6318ee-1038-492e-ae42-6b3255b23939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980805432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2980805432
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.4030028973
Short name T624
Test name
Test status
Simulation time 644604026 ps
CPU time 9.63 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:48:39 PM PDT 24
Peak memory 217372 kb
Host smart-aea8efc8-f8b7-44c6-939e-e6c38ab00fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030028973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4030028973
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2638846184
Short name T1208
Test name
Test status
Simulation time 1295931046 ps
CPU time 3.65 seconds
Started May 26 12:48:42 PM PDT 24
Finished May 26 12:48:46 PM PDT 24
Peak memory 204408 kb
Host smart-fa31a8d6-cfd7-4b39-b492-e9cde8e2fe37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638846184 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2638846184
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3641304034
Short name T539
Test name
Test status
Simulation time 10233201211 ps
CPU time 45.49 seconds
Started May 26 12:48:43 PM PDT 24
Finished May 26 12:49:29 PM PDT 24
Peak memory 366096 kb
Host smart-564b144c-0230-44fa-9805-3e3d5c97cf34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641304034 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3641304034
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2391303217
Short name T1362
Test name
Test status
Simulation time 10321890576 ps
CPU time 36.28 seconds
Started May 26 12:48:41 PM PDT 24
Finished May 26 12:49:18 PM PDT 24
Peak memory 467332 kb
Host smart-7d4193ab-a7c4-40e1-99e4-35feb0586f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391303217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2391303217
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1992061067
Short name T1412
Test name
Test status
Simulation time 4868837951 ps
CPU time 2.49 seconds
Started May 26 12:48:42 PM PDT 24
Finished May 26 12:48:45 PM PDT 24
Peak memory 204492 kb
Host smart-801d51d4-ded3-4269-85d2-ab5dc751098f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992061067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1992061067
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.627849648
Short name T359
Test name
Test status
Simulation time 1118173704 ps
CPU time 1.53 seconds
Started May 26 12:48:41 PM PDT 24
Finished May 26 12:48:43 PM PDT 24
Peak memory 204440 kb
Host smart-49f7ccf0-d742-4bbf-9ba1-3e2d2e07b5e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627849648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.627849648
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2363802015
Short name T1209
Test name
Test status
Simulation time 449046458 ps
CPU time 2.47 seconds
Started May 26 12:48:44 PM PDT 24
Finished May 26 12:48:47 PM PDT 24
Peak memory 204520 kb
Host smart-9f14a6bf-2030-4b89-be12-26b620f76b45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363802015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2363802015
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1660829872
Short name T491
Test name
Test status
Simulation time 842452426 ps
CPU time 4.54 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:48:36 PM PDT 24
Peak memory 204500 kb
Host smart-4f87297f-04a2-4d9b-a4fb-2622e3b74539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660829872 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1660829872
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2973446343
Short name T509
Test name
Test status
Simulation time 16922843335 ps
CPU time 32.11 seconds
Started May 26 12:48:31 PM PDT 24
Finished May 26 12:49:03 PM PDT 24
Peak memory 606268 kb
Host smart-cfc92067-5589-4ded-bc23-7ed01e9d878d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973446343 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2973446343
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.971612993
Short name T494
Test name
Test status
Simulation time 770877216 ps
CPU time 32.58 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:49:03 PM PDT 24
Peak memory 204472 kb
Host smart-3704ebaa-4e11-46d7-a18b-7426decd0552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971612993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.971612993
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.556794100
Short name T853
Test name
Test status
Simulation time 1721604137 ps
CPU time 28.07 seconds
Started May 26 12:48:29 PM PDT 24
Finished May 26 12:48:58 PM PDT 24
Peak memory 204460 kb
Host smart-cb67cf7a-46e8-4188-9ff0-4779ed8a35f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556794100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.556794100
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.4093568118
Short name T1227
Test name
Test status
Simulation time 39971835037 ps
CPU time 531.91 seconds
Started May 26 12:48:30 PM PDT 24
Finished May 26 12:57:23 PM PDT 24
Peak memory 4869296 kb
Host smart-67046147-a6f7-42ce-80e4-ad41ddd73fff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093568118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.4093568118
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.180994645
Short name T316
Test name
Test status
Simulation time 10744189939 ps
CPU time 1404.95 seconds
Started May 26 12:48:32 PM PDT 24
Finished May 26 01:11:58 PM PDT 24
Peak memory 2655380 kb
Host smart-aa47d07d-3fae-49eb-841e-cfc9c7414ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180994645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.180994645
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1564941132
Short name T32
Test name
Test status
Simulation time 1479691804 ps
CPU time 7.5 seconds
Started May 26 12:48:41 PM PDT 24
Finished May 26 12:48:49 PM PDT 24
Peak memory 204816 kb
Host smart-a6d359d6-fffc-44f0-ba81-0e5052bfe09d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564941132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1564941132
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3512979484
Short name T574
Test name
Test status
Simulation time 46612306 ps
CPU time 0.65 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 12:49:02 PM PDT 24
Peak memory 204044 kb
Host smart-b49054da-cba0-4c84-aaab-c64afef70674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512979484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3512979484
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2111761342
Short name T1011
Test name
Test status
Simulation time 732054491 ps
CPU time 3.44 seconds
Started May 26 12:48:52 PM PDT 24
Finished May 26 12:48:55 PM PDT 24
Peak memory 216888 kb
Host smart-73675416-cd22-4746-80ee-d4c89515debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111761342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2111761342
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3716041149
Short name T72
Test name
Test status
Simulation time 625880429 ps
CPU time 7.33 seconds
Started May 26 12:48:56 PM PDT 24
Finished May 26 12:49:04 PM PDT 24
Peak memory 265980 kb
Host smart-c5df4d87-60ce-499b-8529-a1a2862aea0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716041149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3716041149
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2286634476
Short name T1358
Test name
Test status
Simulation time 8939299706 ps
CPU time 67.87 seconds
Started May 26 12:48:58 PM PDT 24
Finished May 26 12:50:06 PM PDT 24
Peak memory 562764 kb
Host smart-5332d2b8-27ac-4d80-8f26-ddafbd377378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286634476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2286634476
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1588796137
Short name T1005
Test name
Test status
Simulation time 2134941952 ps
CPU time 159.62 seconds
Started May 26 12:48:55 PM PDT 24
Finished May 26 12:51:36 PM PDT 24
Peak memory 732288 kb
Host smart-94fa6f2c-ccf0-484b-8ddf-39a82c0e8041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588796137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1588796137
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1902974672
Short name T1318
Test name
Test status
Simulation time 138509779 ps
CPU time 1.09 seconds
Started May 26 12:48:55 PM PDT 24
Finished May 26 12:48:56 PM PDT 24
Peak memory 204424 kb
Host smart-5e3b7ce1-d019-4b40-a231-6e357bc5a7f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902974672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1902974672
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3916409923
Short name T1118
Test name
Test status
Simulation time 204406226 ps
CPU time 5.34 seconds
Started May 26 12:48:50 PM PDT 24
Finished May 26 12:48:56 PM PDT 24
Peak memory 204468 kb
Host smart-e0075214-c914-4b55-a9c2-fe95a6b65022
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916409923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3916409923
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2142310323
Short name T321
Test name
Test status
Simulation time 3955955789 ps
CPU time 255.24 seconds
Started May 26 12:48:58 PM PDT 24
Finished May 26 12:53:14 PM PDT 24
Peak memory 949748 kb
Host smart-36f2f3ef-9fae-4755-b59c-fc231b9eda18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142310323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2142310323
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.2280574355
Short name T981
Test name
Test status
Simulation time 494974119 ps
CPU time 19.42 seconds
Started May 26 12:48:57 PM PDT 24
Finished May 26 12:49:17 PM PDT 24
Peak memory 204448 kb
Host smart-457e0402-3473-4edd-a865-a7781d27058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280574355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2280574355
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2638716223
Short name T1125
Test name
Test status
Simulation time 6640309509 ps
CPU time 24.03 seconds
Started May 26 12:48:56 PM PDT 24
Finished May 26 12:49:20 PM PDT 24
Peak memory 334424 kb
Host smart-58ef4840-092a-4f96-bac2-747100ca974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638716223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2638716223
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3345802761
Short name T1341
Test name
Test status
Simulation time 26912171 ps
CPU time 0.72 seconds
Started May 26 12:48:43 PM PDT 24
Finished May 26 12:48:44 PM PDT 24
Peak memory 204160 kb
Host smart-82fe0cea-76d7-4ccc-abe7-02148519fb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345802761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3345802761
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1058511146
Short name T1380
Test name
Test status
Simulation time 386251646 ps
CPU time 3.81 seconds
Started May 26 12:48:59 PM PDT 24
Finished May 26 12:49:03 PM PDT 24
Peak memory 220744 kb
Host smart-c6934efd-0217-434a-8fa3-e11782118de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058511146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1058511146
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2665094575
Short name T1369
Test name
Test status
Simulation time 3768058352 ps
CPU time 25.92 seconds
Started May 26 12:48:42 PM PDT 24
Finished May 26 12:49:08 PM PDT 24
Peak memory 315376 kb
Host smart-69fbf006-e1c2-4fc0-97f9-2947887b3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665094575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2665094575
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3506258214
Short name T52
Test name
Test status
Simulation time 78175207301 ps
CPU time 1091.3 seconds
Started May 26 12:48:53 PM PDT 24
Finished May 26 01:07:05 PM PDT 24
Peak memory 1630936 kb
Host smart-559c9bb7-beea-4a26-b4d9-8bebd251c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506258214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3506258214
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1094412926
Short name T360
Test name
Test status
Simulation time 663553843 ps
CPU time 10.64 seconds
Started May 26 12:48:50 PM PDT 24
Finished May 26 12:49:01 PM PDT 24
Peak memory 212652 kb
Host smart-e3812165-bfda-451a-9307-b8468d1c690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094412926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1094412926
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1118505675
Short name T466
Test name
Test status
Simulation time 11316061942 ps
CPU time 3.12 seconds
Started May 26 12:48:52 PM PDT 24
Finished May 26 12:48:56 PM PDT 24
Peak memory 204496 kb
Host smart-7752482c-803b-4a94-930e-5bec55bd6dce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118505675 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1118505675
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1253707672
Short name T271
Test name
Test status
Simulation time 10095180131 ps
CPU time 41.65 seconds
Started May 26 12:48:54 PM PDT 24
Finished May 26 12:49:36 PM PDT 24
Peak memory 347524 kb
Host smart-4b175a9d-c38a-4a89-91f6-51a373384b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253707672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1253707672
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2174224950
Short name T1229
Test name
Test status
Simulation time 10153587470 ps
CPU time 60.67 seconds
Started May 26 12:48:53 PM PDT 24
Finished May 26 12:49:54 PM PDT 24
Peak memory 567432 kb
Host smart-5a267767-0c98-43b5-b87f-53a13c45cecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174224950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2174224950
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.3407859055
Short name T1139
Test name
Test status
Simulation time 5367188298 ps
CPU time 2.49 seconds
Started May 26 12:48:57 PM PDT 24
Finished May 26 12:49:00 PM PDT 24
Peak memory 204532 kb
Host smart-1d504ae9-5ee7-42b9-ba25-80e072dadf86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407859055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3407859055
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.3520800447
Short name T388
Test name
Test status
Simulation time 1053828952 ps
CPU time 5.21 seconds
Started May 26 12:49:04 PM PDT 24
Finished May 26 12:49:10 PM PDT 24
Peak memory 204448 kb
Host smart-38dc1090-17e0-49ea-8f33-ad18f696ce93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520800447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.3520800447
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.132054196
Short name T20
Test name
Test status
Simulation time 2031344378 ps
CPU time 2.61 seconds
Started May 26 12:48:56 PM PDT 24
Finished May 26 12:49:00 PM PDT 24
Peak memory 204524 kb
Host smart-891eff05-5159-4574-88b1-5a6db0640715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132054196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.132054196
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3583094479
Short name T986
Test name
Test status
Simulation time 1344069711 ps
CPU time 6.13 seconds
Started May 26 12:48:54 PM PDT 24
Finished May 26 12:49:01 PM PDT 24
Peak memory 213920 kb
Host smart-e8209951-7148-48bd-bc7c-23e007b97fc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583094479 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3583094479
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2673615551
Short name T270
Test name
Test status
Simulation time 11334734698 ps
CPU time 33.69 seconds
Started May 26 12:48:57 PM PDT 24
Finished May 26 12:49:31 PM PDT 24
Peak memory 204532 kb
Host smart-6e7f3ed0-0821-4945-b259-c4dbb05c3312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673615551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2673615551
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.21354176
Short name T147
Test name
Test status
Simulation time 823454935 ps
CPU time 18.36 seconds
Started May 26 12:48:55 PM PDT 24
Finished May 26 12:49:15 PM PDT 24
Peak memory 204512 kb
Host smart-81e94a3d-3dd8-4ae7-9ea5-a278a6ff7dba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_rd.21354176
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2732287136
Short name T896
Test name
Test status
Simulation time 26565256974 ps
CPU time 50.48 seconds
Started May 26 12:48:51 PM PDT 24
Finished May 26 12:49:42 PM PDT 24
Peak memory 936976 kb
Host smart-03113e55-aebb-47cc-afe8-9cf7d26d4104
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732287136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2732287136
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.4049029263
Short name T680
Test name
Test status
Simulation time 20634466705 ps
CPU time 2379.38 seconds
Started May 26 12:48:57 PM PDT 24
Finished May 26 01:28:37 PM PDT 24
Peak memory 4537852 kb
Host smart-01b92c52-311e-4d23-b6a7-e7c358029cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049029263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.4049029263
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2816355822
Short name T343
Test name
Test status
Simulation time 1336735734 ps
CPU time 7.46 seconds
Started May 26 12:48:57 PM PDT 24
Finished May 26 12:49:05 PM PDT 24
Peak memory 220736 kb
Host smart-97817ef8-084f-44ab-9453-a17263336a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816355822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2816355822
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2038165999
Short name T493
Test name
Test status
Simulation time 54621974 ps
CPU time 0.62 seconds
Started May 26 12:49:07 PM PDT 24
Finished May 26 12:49:09 PM PDT 24
Peak memory 204384 kb
Host smart-c30d7540-5dea-4256-b92a-4ac654554d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038165999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2038165999
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2523262767
Short name T164
Test name
Test status
Simulation time 119836767 ps
CPU time 1.5 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 12:49:03 PM PDT 24
Peak memory 212852 kb
Host smart-c49106f4-dfd8-4654-b7fe-3d6bf849ed1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523262767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2523262767
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3582369295
Short name T1117
Test name
Test status
Simulation time 344202899 ps
CPU time 16.53 seconds
Started May 26 12:49:05 PM PDT 24
Finished May 26 12:49:22 PM PDT 24
Peak memory 271728 kb
Host smart-ce820263-7bb9-466b-a7fe-06ab3d6d6089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582369295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3582369295
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1891258100
Short name T85
Test name
Test status
Simulation time 4384854691 ps
CPU time 110.91 seconds
Started May 26 12:49:04 PM PDT 24
Finished May 26 12:50:56 PM PDT 24
Peak memory 894092 kb
Host smart-4916e7c8-f0c5-446a-89ae-1b97f8578a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891258100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1891258100
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1014890350
Short name T1006
Test name
Test status
Simulation time 6987546012 ps
CPU time 53.56 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:55 PM PDT 24
Peak memory 620456 kb
Host smart-f8f71afa-950b-4dc7-b45b-a8858cf5224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014890350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1014890350
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2050267787
Short name T1018
Test name
Test status
Simulation time 2340319061 ps
CPU time 1.01 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 12:49:02 PM PDT 24
Peak memory 204300 kb
Host smart-1d8c8ab5-5f5d-4d83-a47d-16dde6abe0f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050267787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2050267787
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2258545412
Short name T596
Test name
Test status
Simulation time 234451867 ps
CPU time 14.81 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:15 PM PDT 24
Peak memory 250152 kb
Host smart-120b1a59-89ab-420e-aa44-03f26496bf65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258545412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2258545412
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1216431846
Short name T953
Test name
Test status
Simulation time 4182076843 ps
CPU time 295.79 seconds
Started May 26 12:48:59 PM PDT 24
Finished May 26 12:53:56 PM PDT 24
Peak memory 1204636 kb
Host smart-22c59ab4-d145-460f-87b1-3ed1b9e73ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216431846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1216431846
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.831430251
Short name T46
Test name
Test status
Simulation time 1267128152 ps
CPU time 14.03 seconds
Started May 26 12:49:08 PM PDT 24
Finished May 26 12:49:23 PM PDT 24
Peak memory 204372 kb
Host smart-bac2cede-0d37-46c1-90c1-9c014b82a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831430251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.831430251
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.4130288423
Short name T1446
Test name
Test status
Simulation time 4332415642 ps
CPU time 34.18 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:49:44 PM PDT 24
Peak memory 349420 kb
Host smart-36e2daed-f3f4-47b6-bac6-64e6762d315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130288423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.4130288423
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4035345233
Short name T350
Test name
Test status
Simulation time 79080778 ps
CPU time 0.66 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:02 PM PDT 24
Peak memory 204204 kb
Host smart-01a322b3-ba86-4f3d-829d-2031d5b79ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035345233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4035345233
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2781625158
Short name T1192
Test name
Test status
Simulation time 308912037 ps
CPU time 3.32 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 12:49:05 PM PDT 24
Peak memory 221684 kb
Host smart-7ca4568f-fac9-4986-a8ec-ef33bace8a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781625158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2781625158
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.998104850
Short name T1188
Test name
Test status
Simulation time 1748543899 ps
CPU time 87.34 seconds
Started May 26 12:49:02 PM PDT 24
Finished May 26 12:50:30 PM PDT 24
Peak memory 352236 kb
Host smart-3b390609-815b-496b-9b50-df84394c9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998104850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.998104850
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.520361704
Short name T1340
Test name
Test status
Simulation time 838756023 ps
CPU time 27.28 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:28 PM PDT 24
Peak memory 212660 kb
Host smart-98962613-aba1-4e54-867e-974460fe5f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520361704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.520361704
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.938739438
Short name T982
Test name
Test status
Simulation time 1628230254 ps
CPU time 4.05 seconds
Started May 26 12:49:18 PM PDT 24
Finished May 26 12:49:23 PM PDT 24
Peak memory 204492 kb
Host smart-c34db09c-b67c-4088-8264-7a29b5af42de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938739438 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.938739438
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3674056556
Short name T795
Test name
Test status
Simulation time 10437477797 ps
CPU time 13.03 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:14 PM PDT 24
Peak memory 250456 kb
Host smart-f143900a-7962-403c-9595-854eb7a061cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674056556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3674056556
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3953966476
Short name T578
Test name
Test status
Simulation time 11573930252 ps
CPU time 3.76 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 12:49:04 PM PDT 24
Peak memory 231268 kb
Host smart-496a40db-c714-42ca-98a4-ecf3ab7e50ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953966476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3953966476
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.159355585
Short name T161
Test name
Test status
Simulation time 1451037279 ps
CPU time 1.9 seconds
Started May 26 12:49:11 PM PDT 24
Finished May 26 12:49:13 PM PDT 24
Peak memory 204452 kb
Host smart-da71e5e0-ec38-44ce-9d7e-56ced28b64e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159355585 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.159355585
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2479220243
Short name T1377
Test name
Test status
Simulation time 1382018187 ps
CPU time 2.22 seconds
Started May 26 12:49:18 PM PDT 24
Finished May 26 12:49:21 PM PDT 24
Peak memory 204500 kb
Host smart-0ae26477-5d50-49ab-a04b-afd85f2bc08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479220243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2479220243
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1465692705
Short name T1017
Test name
Test status
Simulation time 1551551314 ps
CPU time 2.4 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:49:12 PM PDT 24
Peak memory 204548 kb
Host smart-6058cb4e-3548-4359-8f6f-cecb69b1cbe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465692705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1465692705
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3793475158
Short name T295
Test name
Test status
Simulation time 701009654 ps
CPU time 4.16 seconds
Started May 26 12:49:04 PM PDT 24
Finished May 26 12:49:09 PM PDT 24
Peak memory 206352 kb
Host smart-8da810ba-550d-4689-a8e6-f23c2a3bc624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793475158 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3793475158
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3197323951
Short name T18
Test name
Test status
Simulation time 12891205652 ps
CPU time 37.16 seconds
Started May 26 12:49:04 PM PDT 24
Finished May 26 12:49:42 PM PDT 24
Peak memory 780900 kb
Host smart-6e87db6a-0d1c-485d-9a41-ae29c013d282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197323951 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3197323951
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2018284929
Short name T1046
Test name
Test status
Simulation time 4388328856 ps
CPU time 20.17 seconds
Started May 26 12:49:03 PM PDT 24
Finished May 26 12:49:24 PM PDT 24
Peak memory 204528 kb
Host smart-93bf9d22-d04c-4c6c-9c41-33617eca83a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018284929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2018284929
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.167152516
Short name T309
Test name
Test status
Simulation time 1027942882 ps
CPU time 10.14 seconds
Started May 26 12:49:02 PM PDT 24
Finished May 26 12:49:13 PM PDT 24
Peak memory 204440 kb
Host smart-63600c02-3388-4340-ba62-84ca610f1f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167152516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.167152516
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1189182812
Short name T1348
Test name
Test status
Simulation time 54281534767 ps
CPU time 1352.82 seconds
Started May 26 12:49:00 PM PDT 24
Finished May 26 01:11:34 PM PDT 24
Peak memory 8412340 kb
Host smart-5af5b6d2-88b1-4261-95b1-235e1d24f6ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189182812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1189182812
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.2039651313
Short name T864
Test name
Test status
Simulation time 32609084731 ps
CPU time 2747.59 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 01:34:49 PM PDT 24
Peak memory 7733968 kb
Host smart-bf20d5cb-030c-445b-803e-e605e3607c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039651313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.2039651313
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2959046248
Short name T358
Test name
Test status
Simulation time 1337062251 ps
CPU time 7.36 seconds
Started May 26 12:49:01 PM PDT 24
Finished May 26 12:49:09 PM PDT 24
Peak memory 219276 kb
Host smart-7c1b5ab1-b806-4c12-835b-0cfa88b4e521
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959046248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2959046248
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3809800159
Short name T1288
Test name
Test status
Simulation time 23313221 ps
CPU time 0.65 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:49:26 PM PDT 24
Peak memory 204092 kb
Host smart-44b31a33-ec10-4c0c-b859-4112fac4067a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809800159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3809800159
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.4267390403
Short name T531
Test name
Test status
Simulation time 680937306 ps
CPU time 4.63 seconds
Started May 26 12:49:10 PM PDT 24
Finished May 26 12:49:15 PM PDT 24
Peak memory 224324 kb
Host smart-e6fda6a9-7a58-4de7-9f45-a10b3be298e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267390403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.4267390403
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3790569087
Short name T1215
Test name
Test status
Simulation time 394407670 ps
CPU time 16.55 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:49:27 PM PDT 24
Peak memory 270728 kb
Host smart-38336bdb-c907-4547-8d8e-fba572ee2516
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790569087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3790569087
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2698310842
Short name T1314
Test name
Test status
Simulation time 13891589788 ps
CPU time 100.45 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:50:50 PM PDT 24
Peak memory 896308 kb
Host smart-15c78883-90b2-4b85-92ac-e4ca827e564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698310842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2698310842
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1749257643
Short name T532
Test name
Test status
Simulation time 10816005565 ps
CPU time 219.36 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:52:49 PM PDT 24
Peak memory 848892 kb
Host smart-4d2bf4e4-46d9-406e-b15b-58dd07c0e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749257643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1749257643
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.4139342383
Short name T234
Test name
Test status
Simulation time 1015281078 ps
CPU time 1.05 seconds
Started May 26 12:49:07 PM PDT 24
Finished May 26 12:49:09 PM PDT 24
Peak memory 204416 kb
Host smart-9487141e-4729-4a76-a045-d0bf83a767c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139342383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.4139342383
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1762742845
Short name T1195
Test name
Test status
Simulation time 764581669 ps
CPU time 9.34 seconds
Started May 26 12:49:18 PM PDT 24
Finished May 26 12:49:28 PM PDT 24
Peak memory 204440 kb
Host smart-a70d2880-7300-425c-9746-19f5399cc933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762742845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1762742845
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1535620987
Short name T109
Test name
Test status
Simulation time 7073062193 ps
CPU time 101.52 seconds
Started May 26 12:49:10 PM PDT 24
Finished May 26 12:50:52 PM PDT 24
Peak memory 1084792 kb
Host smart-1af0f6eb-077c-478e-90b0-371e65642577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535620987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1535620987
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4238202426
Short name T1384
Test name
Test status
Simulation time 532268177 ps
CPU time 6.32 seconds
Started May 26 12:49:19 PM PDT 24
Finished May 26 12:49:26 PM PDT 24
Peak memory 204500 kb
Host smart-eddcc2ba-7dea-4f03-a021-13badebfeffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238202426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4238202426
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1264639079
Short name T1177
Test name
Test status
Simulation time 3858383836 ps
CPU time 101.84 seconds
Started May 26 12:49:16 PM PDT 24
Finished May 26 12:50:58 PM PDT 24
Peak memory 430212 kb
Host smart-c464f5ed-2911-4530-affc-3044072aff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264639079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1264639079
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1906520051
Short name T1320
Test name
Test status
Simulation time 134965896 ps
CPU time 0.64 seconds
Started May 26 12:49:08 PM PDT 24
Finished May 26 12:49:10 PM PDT 24
Peak memory 204156 kb
Host smart-7de7b4a5-9df1-4061-bcb4-f8bd15954c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906520051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1906520051
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2183825802
Short name T432
Test name
Test status
Simulation time 12310729662 ps
CPU time 289.13 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:53:59 PM PDT 24
Peak memory 1321916 kb
Host smart-434d1335-7001-445f-89d1-4ef9ad06cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183825802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2183825802
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.329369249
Short name T749
Test name
Test status
Simulation time 1219025982 ps
CPU time 21.71 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:49:31 PM PDT 24
Peak memory 334812 kb
Host smart-4e260dc1-0b09-4412-8683-95ddd6b134e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329369249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.329369249
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3724483155
Short name T327
Test name
Test status
Simulation time 10126474315 ps
CPU time 28.21 seconds
Started May 26 12:49:09 PM PDT 24
Finished May 26 12:49:38 PM PDT 24
Peak memory 212756 kb
Host smart-731b7c87-881d-4b9f-b9aa-f411a10daf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724483155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3724483155
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2240838239
Short name T460
Test name
Test status
Simulation time 12782952772 ps
CPU time 3.35 seconds
Started May 26 12:49:17 PM PDT 24
Finished May 26 12:49:21 PM PDT 24
Peak memory 204560 kb
Host smart-4f099fee-2bc9-4403-874e-7f51e6a5e5ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240838239 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2240838239
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.899954254
Short name T450
Test name
Test status
Simulation time 11355525672 ps
CPU time 3.12 seconds
Started May 26 12:49:16 PM PDT 24
Finished May 26 12:49:19 PM PDT 24
Peak memory 213812 kb
Host smart-2894db07-396f-4d22-b34e-627e967456b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899954254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.899954254
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3387205781
Short name T1424
Test name
Test status
Simulation time 10163399636 ps
CPU time 32.87 seconds
Started May 26 12:49:16 PM PDT 24
Finished May 26 12:49:50 PM PDT 24
Peak memory 358312 kb
Host smart-ae3819d0-2d10-4759-8046-13eee70d7c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387205781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3387205781
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.307421142
Short name T237
Test name
Test status
Simulation time 1489626536 ps
CPU time 6.73 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:49:33 PM PDT 24
Peak memory 204456 kb
Host smart-0a62bb17-dc00-4d75-881a-f6a53e61974f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307421142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.307421142
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2113494336
Short name T1104
Test name
Test status
Simulation time 1377750648 ps
CPU time 1.98 seconds
Started May 26 12:49:36 PM PDT 24
Finished May 26 12:49:38 PM PDT 24
Peak memory 204452 kb
Host smart-60e0f1ba-6758-437f-812b-e43d56ec577f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113494336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2113494336
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.487072680
Short name T22
Test name
Test status
Simulation time 1020103214 ps
CPU time 3.27 seconds
Started May 26 12:49:21 PM PDT 24
Finished May 26 12:49:25 PM PDT 24
Peak memory 204528 kb
Host smart-aaa85c41-1170-4eeb-9334-33114682c551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487072680 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.487072680
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.152166686
Short name T1025
Test name
Test status
Simulation time 2178131549 ps
CPU time 5.56 seconds
Started May 26 12:49:16 PM PDT 24
Finished May 26 12:49:22 PM PDT 24
Peak memory 210404 kb
Host smart-da143d83-2b1d-4832-b60b-30a7f61fb410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152166686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.152166686
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2828474073
Short name T659
Test name
Test status
Simulation time 11470193377 ps
CPU time 4.47 seconds
Started May 26 12:49:19 PM PDT 24
Finished May 26 12:49:24 PM PDT 24
Peak memory 204544 kb
Host smart-3d79a56b-b695-493b-82ea-3c9522a3993d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828474073 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2828474073
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.726933883
Short name T1211
Test name
Test status
Simulation time 6606263677 ps
CPU time 21.76 seconds
Started May 26 12:49:10 PM PDT 24
Finished May 26 12:49:32 PM PDT 24
Peak memory 204544 kb
Host smart-75846781-a52e-4bf2-8fbf-52a9cfd6745f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726933883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.726933883
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3835279437
Short name T1031
Test name
Test status
Simulation time 2362249777 ps
CPU time 26.77 seconds
Started May 26 12:49:10 PM PDT 24
Finished May 26 12:49:38 PM PDT 24
Peak memory 204544 kb
Host smart-9ebe47d6-ff2b-40ac-8011-04d3572bf4a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835279437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3835279437
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.476413244
Short name T383
Test name
Test status
Simulation time 51279247621 ps
CPU time 146.79 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:52:01 PM PDT 24
Peak memory 1893224 kb
Host smart-8113016d-cc85-4128-ab28-3a7956fe2dc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476413244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.476413244
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.4161474548
Short name T275
Test name
Test status
Simulation time 15938937011 ps
CPU time 1132.91 seconds
Started May 26 12:49:17 PM PDT 24
Finished May 26 01:08:11 PM PDT 24
Peak memory 2522068 kb
Host smart-0baf58ab-d49d-4680-b8d9-a36fcdba9a7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161474548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.4161474548
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3108393686
Short name T442
Test name
Test status
Simulation time 9269956702 ps
CPU time 6.8 seconds
Started May 26 12:49:16 PM PDT 24
Finished May 26 12:49:24 PM PDT 24
Peak memory 220844 kb
Host smart-113f7dd2-9f59-4335-bab0-1b0a1c0c4525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108393686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3108393686
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1460844863
Short name T979
Test name
Test status
Simulation time 19730284 ps
CPU time 0.63 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 12:49:44 PM PDT 24
Peak memory 204084 kb
Host smart-3660d996-44e2-437d-9b7d-8a9999e94f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460844863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1460844863
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2567875758
Short name T995
Test name
Test status
Simulation time 712617330 ps
CPU time 2.91 seconds
Started May 26 12:49:36 PM PDT 24
Finished May 26 12:49:39 PM PDT 24
Peak memory 212704 kb
Host smart-9c5165dd-98aa-4df0-8dbc-acb8bfc21669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567875758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2567875758
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1115324154
Short name T313
Test name
Test status
Simulation time 988606606 ps
CPU time 10.84 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:49:36 PM PDT 24
Peak memory 309068 kb
Host smart-206f7f16-5908-4633-8441-a9eba11b12a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115324154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1115324154
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3696766513
Short name T1186
Test name
Test status
Simulation time 25869532129 ps
CPU time 49.09 seconds
Started May 26 12:49:26 PM PDT 24
Finished May 26 12:50:16 PM PDT 24
Peak memory 589904 kb
Host smart-793f0977-1825-412f-be45-f96023cf449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696766513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3696766513
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3054073563
Short name T1178
Test name
Test status
Simulation time 6200288265 ps
CPU time 49.68 seconds
Started May 26 12:49:24 PM PDT 24
Finished May 26 12:50:14 PM PDT 24
Peak memory 515676 kb
Host smart-c2580a7c-d6bc-4987-8e07-8b932f0065f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054073563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3054073563
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2116267634
Short name T498
Test name
Test status
Simulation time 477271882 ps
CPU time 1.04 seconds
Started May 26 12:49:31 PM PDT 24
Finished May 26 12:49:33 PM PDT 24
Peak memory 204464 kb
Host smart-5f28d451-851c-424b-bbac-c3e67f278ea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116267634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2116267634
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1445519700
Short name T1393
Test name
Test status
Simulation time 681023717 ps
CPU time 4.3 seconds
Started May 26 12:49:26 PM PDT 24
Finished May 26 12:49:31 PM PDT 24
Peak memory 204436 kb
Host smart-328da976-1613-4c61-ba74-44f2e15d8d29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445519700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1445519700
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2711037013
Short name T984
Test name
Test status
Simulation time 3291683816 ps
CPU time 62.31 seconds
Started May 26 12:49:24 PM PDT 24
Finished May 26 12:50:27 PM PDT 24
Peak memory 881484 kb
Host smart-9ac3c189-a0a6-48e2-b189-452eaf1305d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711037013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2711037013
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1038589510
Short name T546
Test name
Test status
Simulation time 536678262 ps
CPU time 22.57 seconds
Started May 26 12:49:42 PM PDT 24
Finished May 26 12:50:06 PM PDT 24
Peak memory 204512 kb
Host smart-dbaa52d5-71ee-446b-8e93-5c047c945ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038589510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1038589510
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3797875298
Short name T1120
Test name
Test status
Simulation time 1503650472 ps
CPU time 70.96 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:50:45 PM PDT 24
Peak memory 285648 kb
Host smart-b3699bc3-c7f0-495a-8ef7-cfe601a51053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797875298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3797875298
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.880791387
Short name T140
Test name
Test status
Simulation time 19942795 ps
CPU time 0.68 seconds
Started May 26 12:49:24 PM PDT 24
Finished May 26 12:49:25 PM PDT 24
Peak memory 204116 kb
Host smart-d3436926-1679-4e00-92cb-2d6c29809091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880791387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.880791387
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.4107574094
Short name T39
Test name
Test status
Simulation time 7639895735 ps
CPU time 283.55 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:54:18 PM PDT 24
Peak memory 225532 kb
Host smart-0a95b7ee-82cb-432a-9b1b-b58a275c7a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107574094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4107574094
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2546062892
Short name T554
Test name
Test status
Simulation time 1827349129 ps
CPU time 36.51 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:50:02 PM PDT 24
Peak memory 327428 kb
Host smart-6114b7dd-9e16-4800-963a-7f85dbe80935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546062892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2546062892
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.905239187
Short name T507
Test name
Test status
Simulation time 1524913591 ps
CPU time 11.93 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:49:38 PM PDT 24
Peak memory 220856 kb
Host smart-a101886f-7174-47b6-8759-2010d932aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905239187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.905239187
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.111758412
Short name T364
Test name
Test status
Simulation time 1782779952 ps
CPU time 4.51 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:49:39 PM PDT 24
Peak memory 204584 kb
Host smart-279634a6-99ad-4ac1-b643-bb78206a17ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111758412 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.111758412
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3978777163
Short name T907
Test name
Test status
Simulation time 10124769140 ps
CPU time 17.15 seconds
Started May 26 12:49:33 PM PDT 24
Finished May 26 12:49:51 PM PDT 24
Peak memory 246580 kb
Host smart-d117f7c3-ead7-4616-9044-02d792675b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978777163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3978777163
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2447569878
Short name T699
Test name
Test status
Simulation time 10268928396 ps
CPU time 15.91 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:49:51 PM PDT 24
Peak memory 328784 kb
Host smart-27eaf6c1-eae3-47c5-a8d4-fe7b13f28cf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447569878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2447569878
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3553400016
Short name T873
Test name
Test status
Simulation time 1074527681 ps
CPU time 5.34 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 12:49:49 PM PDT 24
Peak memory 204536 kb
Host smart-474a59d9-9555-451d-accc-f0325397449a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553400016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3553400016
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2953240410
Short name T558
Test name
Test status
Simulation time 1065225627 ps
CPU time 5.94 seconds
Started May 26 12:49:41 PM PDT 24
Finished May 26 12:49:47 PM PDT 24
Peak memory 204512 kb
Host smart-636b0141-c058-451c-9511-1e4fee55494b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953240410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2953240410
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1978032966
Short name T1115
Test name
Test status
Simulation time 261711049 ps
CPU time 1.84 seconds
Started May 26 12:49:35 PM PDT 24
Finished May 26 12:49:37 PM PDT 24
Peak memory 204452 kb
Host smart-04a96c0d-48e0-46c0-9f54-8aac811fe4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978032966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1978032966
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2814222725
Short name T565
Test name
Test status
Simulation time 4102356046 ps
CPU time 6.51 seconds
Started May 26 12:49:34 PM PDT 24
Finished May 26 12:49:41 PM PDT 24
Peak memory 220784 kb
Host smart-cebd7cb3-6c02-4391-8ec3-ef413b69ff51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814222725 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2814222725
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3100158550
Short name T485
Test name
Test status
Simulation time 16963601271 ps
CPU time 204.63 seconds
Started May 26 12:49:33 PM PDT 24
Finished May 26 12:52:59 PM PDT 24
Peak memory 2931984 kb
Host smart-a1be51ee-fdfb-43f0-9784-5f7df3697fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100158550 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3100158550
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4104418787
Short name T406
Test name
Test status
Simulation time 910197497 ps
CPU time 34.41 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:50:00 PM PDT 24
Peak memory 204420 kb
Host smart-be40ba26-d480-4eb0-8d8d-f1f62ee2d8c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104418787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4104418787
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2011576434
Short name T303
Test name
Test status
Simulation time 1738007688 ps
CPU time 18.58 seconds
Started May 26 12:49:25 PM PDT 24
Finished May 26 12:49:44 PM PDT 24
Peak memory 212656 kb
Host smart-cb5296aa-1fd4-4075-836c-e767c4042858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011576434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2011576434
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1894139818
Short name T1280
Test name
Test status
Simulation time 40011709342 ps
CPU time 138.04 seconds
Started May 26 12:49:26 PM PDT 24
Finished May 26 12:51:45 PM PDT 24
Peak memory 1732072 kb
Host smart-5c929755-8c15-4f09-9153-3e601fac9eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894139818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1894139818
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3692908869
Short name T1290
Test name
Test status
Simulation time 22014918495 ps
CPU time 117.84 seconds
Started May 26 12:49:36 PM PDT 24
Finished May 26 12:51:34 PM PDT 24
Peak memory 1265872 kb
Host smart-391d6df2-a32b-4ba1-bc33-edf6ad58f260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692908869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3692908869
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2437156221
Short name T829
Test name
Test status
Simulation time 2481948232 ps
CPU time 6.81 seconds
Started May 26 12:49:41 PM PDT 24
Finished May 26 12:49:49 PM PDT 24
Peak memory 218636 kb
Host smart-3f691db0-25d7-446b-9296-98c9ebe2c95e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437156221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2437156221
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3829387443
Short name T1133
Test name
Test status
Simulation time 16671399 ps
CPU time 0.71 seconds
Started May 26 12:42:04 PM PDT 24
Finished May 26 12:42:05 PM PDT 24
Peak memory 204088 kb
Host smart-82b5bf60-7194-4428-bb25-858c87153614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829387443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3829387443
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.997674829
Short name T863
Test name
Test status
Simulation time 296522064 ps
CPU time 1.63 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:56 PM PDT 24
Peak memory 212676 kb
Host smart-3f9dfe46-1cca-433b-aa18-c1e6a72daf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997674829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.997674829
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.613922196
Short name T368
Test name
Test status
Simulation time 2070052511 ps
CPU time 16.75 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:42:12 PM PDT 24
Peak memory 254944 kb
Host smart-25f76db3-529e-4ae0-a51f-ab1f1e502552
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613922196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.613922196
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.533601610
Short name T1426
Test name
Test status
Simulation time 10099914032 ps
CPU time 167.55 seconds
Started May 26 12:41:52 PM PDT 24
Finished May 26 12:44:40 PM PDT 24
Peak memory 632444 kb
Host smart-d702dd15-183a-4fc9-8554-488cf74b0840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533601610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.533601610
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1950101965
Short name T1415
Test name
Test status
Simulation time 2280275906 ps
CPU time 79.82 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 710756 kb
Host smart-a5e96839-7d69-4dc7-a06d-7f15d1d989bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950101965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1950101965
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3279241017
Short name T1447
Test name
Test status
Simulation time 78644726 ps
CPU time 0.94 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:55 PM PDT 24
Peak memory 204236 kb
Host smart-e9c4867b-8160-4d18-8deb-c9966b288320
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279241017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3279241017
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1266215575
Short name T1027
Test name
Test status
Simulation time 176849081 ps
CPU time 10.13 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:42:05 PM PDT 24
Peak memory 234360 kb
Host smart-3c2a2e6e-4aa9-4c82-9a1a-eb594a42aedd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266215575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1266215575
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.4106208827
Short name T718
Test name
Test status
Simulation time 18997608848 ps
CPU time 138.13 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:44:12 PM PDT 24
Peak memory 1387892 kb
Host smart-4ec9ffcd-16d4-47d6-b9bb-1826d1a6f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106208827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.4106208827
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1929687796
Short name T1289
Test name
Test status
Simulation time 3539460591 ps
CPU time 88.41 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:43:34 PM PDT 24
Peak memory 405460 kb
Host smart-5eb58355-b3d7-4c17-a0b5-9584a10ee437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929687796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1929687796
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3176383474
Short name T1395
Test name
Test status
Simulation time 31586112 ps
CPU time 0.69 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:41:55 PM PDT 24
Peak memory 204236 kb
Host smart-42351ee6-5734-4c58-8c44-41db37640a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176383474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3176383474
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1371519734
Short name T996
Test name
Test status
Simulation time 6187116116 ps
CPU time 198.86 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:45:12 PM PDT 24
Peak memory 1516872 kb
Host smart-469a823e-18e7-4769-ba09-0ff34e8e0d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371519734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1371519734
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2639950338
Short name T919
Test name
Test status
Simulation time 1003645988 ps
CPU time 21.51 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:42:16 PM PDT 24
Peak memory 335468 kb
Host smart-2a497dc0-2dc8-4543-80ca-257ee7243c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639950338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2639950338
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.353031316
Short name T1023
Test name
Test status
Simulation time 723577172 ps
CPU time 14.65 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:09 PM PDT 24
Peak memory 213728 kb
Host smart-6198c694-5760-4411-a004-7ebb4005de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353031316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.353031316
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3151418450
Short name T178
Test name
Test status
Simulation time 76639094 ps
CPU time 0.84 seconds
Started May 26 12:42:07 PM PDT 24
Finished May 26 12:42:08 PM PDT 24
Peak memory 221676 kb
Host smart-c7626c0a-a46c-4097-a18c-d30319d221db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151418450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3151418450
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.18885363
Short name T859
Test name
Test status
Simulation time 797783708 ps
CPU time 4.73 seconds
Started May 26 12:42:06 PM PDT 24
Finished May 26 12:42:11 PM PDT 24
Peak memory 204520 kb
Host smart-d2fb9efb-e03d-4072-94aa-a1fd614ce4f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885363 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_bad_addr.18885363
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1948412609
Short name T650
Test name
Test status
Simulation time 10232141150 ps
CPU time 14.06 seconds
Started May 26 12:41:55 PM PDT 24
Finished May 26 12:42:09 PM PDT 24
Peak memory 248128 kb
Host smart-51b7f88a-8b14-4a4d-a7af-09484b1d8e77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948412609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1948412609
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2212616011
Short name T649
Test name
Test status
Simulation time 10071793969 ps
CPU time 71 seconds
Started May 26 12:41:58 PM PDT 24
Finished May 26 12:43:09 PM PDT 24
Peak memory 515616 kb
Host smart-137acfdf-b214-458b-8284-f2eacc27a6d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212616011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2212616011
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.995419885
Short name T1198
Test name
Test status
Simulation time 2024240609 ps
CPU time 5.09 seconds
Started May 26 12:42:07 PM PDT 24
Finished May 26 12:42:13 PM PDT 24
Peak memory 204596 kb
Host smart-270e341b-0e42-41ef-b58b-00c48f632cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995419885 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.995419885
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.984505450
Short name T891
Test name
Test status
Simulation time 1027697143 ps
CPU time 6.63 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:42:12 PM PDT 24
Peak memory 204496 kb
Host smart-111ed203-efd0-4a61-88da-6119e4d9dda1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984505450 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.984505450
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3345301245
Short name T602
Test name
Test status
Simulation time 3279554854 ps
CPU time 2.01 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:42:07 PM PDT 24
Peak memory 204592 kb
Host smart-d4a1e60f-1710-4838-ae3a-907deb1c765b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345301245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3345301245
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1406621393
Short name T672
Test name
Test status
Simulation time 2030945311 ps
CPU time 5.99 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:00 PM PDT 24
Peak memory 220684 kb
Host smart-9e710ff9-e165-4406-9024-c10794a8c77d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406621393 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1406621393
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2228565313
Short name T1093
Test name
Test status
Simulation time 15744025185 ps
CPU time 176.01 seconds
Started May 26 12:41:55 PM PDT 24
Finished May 26 12:44:51 PM PDT 24
Peak memory 2222240 kb
Host smart-0a948689-258f-431c-8bfc-c7e3698854c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228565313 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2228565313
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.226906885
Short name T547
Test name
Test status
Simulation time 4720730040 ps
CPU time 15.2 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:09 PM PDT 24
Peak memory 204496 kb
Host smart-0c3301e7-daa0-4e3a-8c0c-c6589497a8ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226906885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.226906885
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3545714583
Short name T667
Test name
Test status
Simulation time 2065476111 ps
CPU time 10.8 seconds
Started May 26 12:41:54 PM PDT 24
Finished May 26 12:42:06 PM PDT 24
Peak memory 205712 kb
Host smart-50e3fc5d-17fc-47f4-b42d-bb0507461b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545714583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3545714583
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.80130556
Short name T955
Test name
Test status
Simulation time 62469588681 ps
CPU time 392.39 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:48:26 PM PDT 24
Peak memory 3739300 kb
Host smart-349842ab-e77b-4a61-b983-3bb4df51823b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80130556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stress_wr.80130556
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.4020795268
Short name T492
Test name
Test status
Simulation time 28034933500 ps
CPU time 178.74 seconds
Started May 26 12:41:52 PM PDT 24
Finished May 26 12:44:51 PM PDT 24
Peak memory 1679124 kb
Host smart-5faa136b-7dcd-43fb-ad53-800e2b393b98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020795268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.4020795268
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.111125912
Short name T348
Test name
Test status
Simulation time 15491304733 ps
CPU time 8.02 seconds
Started May 26 12:41:53 PM PDT 24
Finished May 26 12:42:03 PM PDT 24
Peak memory 219412 kb
Host smart-f56646c5-402e-40e2-8393-8f8a53642e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111125912 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.111125912
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2173685684
Short name T504
Test name
Test status
Simulation time 35070875 ps
CPU time 0.63 seconds
Started May 26 12:49:50 PM PDT 24
Finished May 26 12:49:52 PM PDT 24
Peak memory 204056 kb
Host smart-96c85e40-8fd7-4bb7-8f74-b12ed771c26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173685684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2173685684
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.849476131
Short name T496
Test name
Test status
Simulation time 462925014 ps
CPU time 8.28 seconds
Started May 26 12:49:41 PM PDT 24
Finished May 26 12:49:50 PM PDT 24
Peak memory 286280 kb
Host smart-f36a1ff8-90ca-42de-afb7-1b9195062072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849476131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.849476131
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2357808344
Short name T1052
Test name
Test status
Simulation time 758518424 ps
CPU time 6.45 seconds
Started May 26 12:49:44 PM PDT 24
Finished May 26 12:49:51 PM PDT 24
Peak memory 275216 kb
Host smart-6aa5f470-3c96-4ef5-bc20-6b8a3eaf8b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357808344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2357808344
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.4134547332
Short name T1213
Test name
Test status
Simulation time 9865825660 ps
CPU time 151.78 seconds
Started May 26 12:49:47 PM PDT 24
Finished May 26 12:52:19 PM PDT 24
Peak memory 556664 kb
Host smart-0ef0be83-6ecc-4d89-89c7-448d16f66ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134547332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4134547332
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3851362791
Short name T833
Test name
Test status
Simulation time 46373341041 ps
CPU time 88.17 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:51:14 PM PDT 24
Peak memory 784080 kb
Host smart-92d1878d-067d-4025-8f6f-a48f3285dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851362791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3851362791
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3322912464
Short name T231
Test name
Test status
Simulation time 431392890 ps
CPU time 0.97 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:49:46 PM PDT 24
Peak memory 204188 kb
Host smart-77bbbef1-f8a7-45f0-8353-d20359c81a27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322912464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3322912464
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1251233445
Short name T847
Test name
Test status
Simulation time 1363621237 ps
CPU time 4.86 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 12:49:49 PM PDT 24
Peak memory 233472 kb
Host smart-a1c29d78-07e3-41ba-8712-ad9dea7dc702
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251233445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1251233445
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2685093031
Short name T148
Test name
Test status
Simulation time 5081434721 ps
CPU time 161.39 seconds
Started May 26 12:49:40 PM PDT 24
Finished May 26 12:52:22 PM PDT 24
Peak memory 1447188 kb
Host smart-cc1adc86-bbb5-456b-abc0-515a4483455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685093031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2685093031
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2625040110
Short name T44
Test name
Test status
Simulation time 8119737144 ps
CPU time 9.16 seconds
Started May 26 12:49:54 PM PDT 24
Finished May 26 12:50:04 PM PDT 24
Peak memory 204536 kb
Host smart-0d475167-a936-4308-b622-689da12d98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625040110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2625040110
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.236246285
Short name T965
Test name
Test status
Simulation time 6916885759 ps
CPU time 38.81 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:50:33 PM PDT 24
Peak memory 397740 kb
Host smart-dd5811eb-5c46-4ea2-8aba-0c3be5a6d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236246285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.236246285
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.680573899
Short name T985
Test name
Test status
Simulation time 45371997 ps
CPU time 0.68 seconds
Started May 26 12:49:42 PM PDT 24
Finished May 26 12:49:44 PM PDT 24
Peak memory 204128 kb
Host smart-bae073fe-c23b-4ead-a3d8-8cbaf6f4f33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680573899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.680573899
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.178799890
Short name T479
Test name
Test status
Simulation time 963745134 ps
CPU time 45.77 seconds
Started May 26 12:49:44 PM PDT 24
Finished May 26 12:50:30 PM PDT 24
Peak memory 288712 kb
Host smart-9185f4a0-ba25-4909-9249-93d521f10e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178799890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.178799890
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3135527126
Short name T55
Test name
Test status
Simulation time 19836043426 ps
CPU time 819.21 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 01:03:23 PM PDT 24
Peak memory 1352172 kb
Host smart-e2b7b29b-e5af-47be-a886-d7e44dff4c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135527126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3135527126
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2127397851
Short name T70
Test name
Test status
Simulation time 1256439660 ps
CPU time 30.9 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:50:16 PM PDT 24
Peak memory 212680 kb
Host smart-1894582f-f366-4975-b136-f52e50b6b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127397851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2127397851
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3496742607
Short name T435
Test name
Test status
Simulation time 3552075100 ps
CPU time 4.42 seconds
Started May 26 12:49:42 PM PDT 24
Finished May 26 12:49:47 PM PDT 24
Peak memory 212712 kb
Host smart-b79bcade-0174-4196-9b78-76226abf51a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496742607 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3496742607
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.273036717
Short name T1000
Test name
Test status
Simulation time 10525445428 ps
CPU time 8.88 seconds
Started May 26 12:49:42 PM PDT 24
Finished May 26 12:49:52 PM PDT 24
Peak memory 232728 kb
Host smart-68a533a1-cf98-4c18-9aba-d4ee5a228556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273036717 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.273036717
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.4170994539
Short name T253
Test name
Test status
Simulation time 10225807843 ps
CPU time 62.36 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 12:50:47 PM PDT 24
Peak memory 486836 kb
Host smart-2accf372-ec9c-4b17-b446-4f100556b152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170994539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.4170994539
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.901542646
Short name T1106
Test name
Test status
Simulation time 1460895084 ps
CPU time 6.63 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:50:01 PM PDT 24
Peak memory 204604 kb
Host smart-740456d6-8eda-4583-9eac-e8304ced0403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901542646 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.901542646
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.1980993480
Short name T115
Test name
Test status
Simulation time 1074094681 ps
CPU time 5.33 seconds
Started May 26 12:49:51 PM PDT 24
Finished May 26 12:49:57 PM PDT 24
Peak memory 204508 kb
Host smart-2d3d8f55-a067-464a-ab67-d7ee9ef2fb80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980993480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.1980993480
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1571958624
Short name T812
Test name
Test status
Simulation time 4836127030 ps
CPU time 2.58 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:49:48 PM PDT 24
Peak memory 204600 kb
Host smart-62b24531-01bf-45c8-981a-a673728c387e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571958624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1571958624
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.4208587549
Short name T805
Test name
Test status
Simulation time 4087098999 ps
CPU time 5.42 seconds
Started May 26 12:49:47 PM PDT 24
Finished May 26 12:49:53 PM PDT 24
Peak memory 214728 kb
Host smart-c88180a6-461c-41e0-82f4-cdaca647dcea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208587549 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.4208587549
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.537289665
Short name T601
Test name
Test status
Simulation time 26234240470 ps
CPU time 45.72 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:50:32 PM PDT 24
Peak memory 1020460 kb
Host smart-397512ea-1b51-41f1-ad16-c96235134b99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537289665 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.537289665
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.280267039
Short name T908
Test name
Test status
Simulation time 1572354648 ps
CPU time 30.4 seconds
Started May 26 12:49:44 PM PDT 24
Finished May 26 12:50:15 PM PDT 24
Peak memory 204472 kb
Host smart-26a23fd8-271d-4965-aec3-4382e1b8771f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280267039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.280267039
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3119812474
Short name T1336
Test name
Test status
Simulation time 1799790142 ps
CPU time 27.85 seconds
Started May 26 12:49:42 PM PDT 24
Finished May 26 12:50:10 PM PDT 24
Peak memory 230644 kb
Host smart-8900ee2d-8e2a-4854-b09e-4d4b23b79faa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119812474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3119812474
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3668965681
Short name T1376
Test name
Test status
Simulation time 30938352361 ps
CPU time 10.84 seconds
Started May 26 12:49:43 PM PDT 24
Finished May 26 12:49:55 PM PDT 24
Peak memory 290864 kb
Host smart-ca9ea1ac-a172-49c4-bcdc-67b6248aadd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668965681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3668965681
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1779990305
Short name T131
Test name
Test status
Simulation time 22429658149 ps
CPU time 1991.83 seconds
Started May 26 12:49:41 PM PDT 24
Finished May 26 01:22:54 PM PDT 24
Peak memory 5304360 kb
Host smart-c899107b-1ad9-4156-ad09-06b4f6b4f4af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779990305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1779990305
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.288610325
Short name T481
Test name
Test status
Simulation time 12755317210 ps
CPU time 7.49 seconds
Started May 26 12:49:45 PM PDT 24
Finished May 26 12:49:53 PM PDT 24
Peak memory 212728 kb
Host smart-95399be5-94b6-4141-9a9a-2e1d6db0972d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288610325 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.288610325
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3539001608
Short name T1164
Test name
Test status
Simulation time 18531412 ps
CPU time 0.7 seconds
Started May 26 12:50:01 PM PDT 24
Finished May 26 12:50:02 PM PDT 24
Peak memory 204028 kb
Host smart-c22ef6fe-1927-4193-a937-c54296ad131d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539001608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3539001608
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3316282673
Short name T1116
Test name
Test status
Simulation time 50719299 ps
CPU time 1.33 seconds
Started May 26 12:49:52 PM PDT 24
Finished May 26 12:49:54 PM PDT 24
Peak memory 212728 kb
Host smart-882c0c29-49b8-4440-9954-9e1e4919d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316282673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3316282673
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1688186107
Short name T2
Test name
Test status
Simulation time 162426803 ps
CPU time 9.13 seconds
Started May 26 12:49:51 PM PDT 24
Finished May 26 12:50:01 PM PDT 24
Peak memory 232860 kb
Host smart-a0ba23b9-2091-43b6-81d5-d627a521b168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688186107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1688186107
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2129684351
Short name T377
Test name
Test status
Simulation time 2950280881 ps
CPU time 47.75 seconds
Started May 26 12:49:51 PM PDT 24
Finished May 26 12:50:40 PM PDT 24
Peak memory 494068 kb
Host smart-13d6f67a-8d72-43fe-b732-10b6519a7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129684351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2129684351
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.4274675793
Short name T1246
Test name
Test status
Simulation time 2796985450 ps
CPU time 82.72 seconds
Started May 26 12:49:54 PM PDT 24
Finished May 26 12:51:18 PM PDT 24
Peak memory 803556 kb
Host smart-969be799-6902-4991-bef0-6b20a24a5626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274675793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.4274675793
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1727549707
Short name T768
Test name
Test status
Simulation time 204495131 ps
CPU time 1.11 seconds
Started May 26 12:49:52 PM PDT 24
Finished May 26 12:49:53 PM PDT 24
Peak memory 204484 kb
Host smart-2d334fe9-54e8-4509-acf3-f08d70e62a2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727549707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1727549707
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4122685839
Short name T745
Test name
Test status
Simulation time 576518187 ps
CPU time 3.29 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:49:57 PM PDT 24
Peak memory 204560 kb
Host smart-be5a3556-b658-4a4b-9db5-c34d37c71201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122685839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4122685839
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1548037601
Short name T511
Test name
Test status
Simulation time 11231947325 ps
CPU time 74.69 seconds
Started May 26 12:49:52 PM PDT 24
Finished May 26 12:51:08 PM PDT 24
Peak memory 807672 kb
Host smart-11fb6176-0631-46c6-8a86-beca07a4f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548037601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1548037601
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1436556519
Short name T885
Test name
Test status
Simulation time 1874299797 ps
CPU time 5.57 seconds
Started May 26 12:49:58 PM PDT 24
Finished May 26 12:50:05 PM PDT 24
Peak memory 204504 kb
Host smart-55fceb6c-a965-4a39-bc1f-fe3f5e64a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436556519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1436556519
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3155835686
Short name T980
Test name
Test status
Simulation time 7696434108 ps
CPU time 28.61 seconds
Started May 26 12:50:00 PM PDT 24
Finished May 26 12:50:29 PM PDT 24
Peak memory 319572 kb
Host smart-2a8eadfb-66d9-443d-b8d2-6331ab536aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155835686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3155835686
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.63327130
Short name T80
Test name
Test status
Simulation time 28930750 ps
CPU time 0.68 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:49:55 PM PDT 24
Peak memory 204112 kb
Host smart-f2dc8c04-1960-4ff3-83e0-b932eed7dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63327130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.63327130
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2175123257
Short name T471
Test name
Test status
Simulation time 7089700430 ps
CPU time 26.26 seconds
Started May 26 12:49:49 PM PDT 24
Finished May 26 12:50:16 PM PDT 24
Peak memory 212796 kb
Host smart-1f40a5e3-ddbd-474e-947a-609101e16758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175123257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2175123257
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3627351440
Short name T134
Test name
Test status
Simulation time 2672064067 ps
CPU time 21.19 seconds
Started May 26 12:49:51 PM PDT 24
Finished May 26 12:50:13 PM PDT 24
Peak memory 333992 kb
Host smart-f64e1cec-fddd-4afd-a313-ff4b516ee3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627351440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3627351440
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.821145871
Short name T1370
Test name
Test status
Simulation time 1374142237 ps
CPU time 12.41 seconds
Started May 26 12:49:54 PM PDT 24
Finished May 26 12:50:07 PM PDT 24
Peak memory 216540 kb
Host smart-b9ac1f67-ecac-4152-b47c-7375f7e1717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821145871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.821145871
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3475294225
Short name T975
Test name
Test status
Simulation time 2545584731 ps
CPU time 3.56 seconds
Started May 26 12:50:02 PM PDT 24
Finished May 26 12:50:07 PM PDT 24
Peak memory 204480 kb
Host smart-e35e0a00-4c78-4761-8808-78838f38e45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475294225 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3475294225
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3693360346
Short name T94
Test name
Test status
Simulation time 10333143982 ps
CPU time 17.5 seconds
Started May 26 12:50:01 PM PDT 24
Finished May 26 12:50:19 PM PDT 24
Peak memory 271676 kb
Host smart-479ae1a8-625c-4746-92d5-e77b01f2e1e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693360346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3693360346
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3882486904
Short name T93
Test name
Test status
Simulation time 10104164916 ps
CPU time 60.95 seconds
Started May 26 12:49:59 PM PDT 24
Finished May 26 12:51:01 PM PDT 24
Peak memory 470140 kb
Host smart-6e9df35b-d7dd-4d65-87c3-f981e3c9ddc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882486904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3882486904
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.692009847
Short name T238
Test name
Test status
Simulation time 1657358889 ps
CPU time 4.37 seconds
Started May 26 12:50:03 PM PDT 24
Finished May 26 12:50:08 PM PDT 24
Peak memory 204480 kb
Host smart-ab19d3f0-0709-4136-9a4c-6a526a0a2a0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692009847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.692009847
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.2268298157
Short name T826
Test name
Test status
Simulation time 1048577418 ps
CPU time 5.78 seconds
Started May 26 12:50:04 PM PDT 24
Finished May 26 12:50:10 PM PDT 24
Peak memory 204428 kb
Host smart-a08fc107-0b76-4863-ade1-861da1c1359e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268298157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.2268298157
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3315896202
Short name T1427
Test name
Test status
Simulation time 1425632058 ps
CPU time 3.1 seconds
Started May 26 12:50:01 PM PDT 24
Finished May 26 12:50:05 PM PDT 24
Peak memory 204632 kb
Host smart-c88101d5-7dec-458b-b57a-6183d97a0479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315896202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3315896202
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2027829992
Short name T407
Test name
Test status
Simulation time 5173122456 ps
CPU time 4.57 seconds
Started May 26 12:49:52 PM PDT 24
Finished May 26 12:49:57 PM PDT 24
Peak memory 204512 kb
Host smart-404c691f-d443-47bf-98e9-d0d3296bb82c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027829992 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2027829992
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2542933972
Short name T579
Test name
Test status
Simulation time 18554483341 ps
CPU time 10.33 seconds
Started May 26 12:49:54 PM PDT 24
Finished May 26 12:50:05 PM PDT 24
Peak memory 356268 kb
Host smart-e7b69f2f-39fc-41cc-8c3d-6e4806503dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542933972 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2542933972
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.599425556
Short name T1166
Test name
Test status
Simulation time 1318013252 ps
CPU time 16.82 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:50:11 PM PDT 24
Peak memory 204492 kb
Host smart-434abd10-6f4d-4dfd-89c1-47b22e865670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599425556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.599425556
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1606442089
Short name T29
Test name
Test status
Simulation time 2434231667 ps
CPU time 20.79 seconds
Started May 26 12:49:53 PM PDT 24
Finished May 26 12:50:15 PM PDT 24
Peak memory 227624 kb
Host smart-1397ff12-181d-481c-a1f0-16667661ea2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606442089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1606442089
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3151201004
Short name T416
Test name
Test status
Simulation time 37198544836 ps
CPU time 223.8 seconds
Started May 26 12:49:52 PM PDT 24
Finished May 26 12:53:36 PM PDT 24
Peak memory 2006456 kb
Host smart-a6f2a6d9-93fe-4921-b4af-fc4160b7699a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151201004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3151201004
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1262871969
Short name T391
Test name
Test status
Simulation time 1348670598 ps
CPU time 7.89 seconds
Started May 26 12:49:55 PM PDT 24
Finished May 26 12:50:03 PM PDT 24
Peak memory 216636 kb
Host smart-6efb6467-9296-42dc-98e8-54cf3b6b33bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262871969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1262871969
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2371819910
Short name T413
Test name
Test status
Simulation time 46094807 ps
CPU time 0.64 seconds
Started May 26 12:50:16 PM PDT 24
Finished May 26 12:50:18 PM PDT 24
Peak memory 204056 kb
Host smart-f925a840-e8a2-4bbc-8b90-5cebcb26c358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371819910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2371819910
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1337491804
Short name T1329
Test name
Test status
Simulation time 744475379 ps
CPU time 3.89 seconds
Started May 26 12:50:02 PM PDT 24
Finished May 26 12:50:07 PM PDT 24
Peak memory 239808 kb
Host smart-425ab7d2-beba-4df5-8552-847e7d3115fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337491804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1337491804
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2830592226
Short name T698
Test name
Test status
Simulation time 11368461139 ps
CPU time 110.16 seconds
Started May 26 12:49:59 PM PDT 24
Finished May 26 12:51:50 PM PDT 24
Peak memory 878664 kb
Host smart-7e099652-a9ac-4865-b169-162314eaf232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830592226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2830592226
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2698647145
Short name T459
Test name
Test status
Simulation time 1960759161 ps
CPU time 131.22 seconds
Started May 26 12:50:01 PM PDT 24
Finished May 26 12:52:13 PM PDT 24
Peak memory 593344 kb
Host smart-0cd5776a-c2af-4594-8905-a78e55ea4433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698647145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2698647145
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3022982645
Short name T1136
Test name
Test status
Simulation time 141169740 ps
CPU time 1.15 seconds
Started May 26 12:49:59 PM PDT 24
Finished May 26 12:50:01 PM PDT 24
Peak memory 204468 kb
Host smart-f519d042-7b9e-4df1-ab73-f5999a3580e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022982645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3022982645
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2415979613
Short name T373
Test name
Test status
Simulation time 275641682 ps
CPU time 4.24 seconds
Started May 26 12:50:02 PM PDT 24
Finished May 26 12:50:07 PM PDT 24
Peak memory 224696 kb
Host smart-af847e0d-aea7-4bf5-9c64-2ec29f8b162b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415979613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2415979613
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3652652116
Short name T628
Test name
Test status
Simulation time 4380788419 ps
CPU time 129.77 seconds
Started May 26 12:50:02 PM PDT 24
Finished May 26 12:52:12 PM PDT 24
Peak memory 1194312 kb
Host smart-153b10fd-efe5-4a79-9dfe-67c0fb5f6a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652652116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3652652116
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3436569326
Short name T1349
Test name
Test status
Simulation time 594576133 ps
CPU time 8.32 seconds
Started May 26 12:50:17 PM PDT 24
Finished May 26 12:50:26 PM PDT 24
Peak memory 204520 kb
Host smart-fb6f3afc-707e-4b7d-ac63-2c90785cb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436569326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3436569326
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2559736672
Short name T640
Test name
Test status
Simulation time 8720460491 ps
CPU time 30.95 seconds
Started May 26 12:50:07 PM PDT 24
Finished May 26 12:50:39 PM PDT 24
Peak memory 330084 kb
Host smart-822684ff-3c39-4308-97ec-e1e8dc10a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559736672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2559736672
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1484236279
Short name T412
Test name
Test status
Simulation time 65239535 ps
CPU time 0.65 seconds
Started May 26 12:49:58 PM PDT 24
Finished May 26 12:50:00 PM PDT 24
Peak memory 204104 kb
Host smart-74f376b5-e412-4e1b-b215-34b5a2a91954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484236279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1484236279
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3812703244
Short name T1278
Test name
Test status
Simulation time 6601985026 ps
CPU time 19.39 seconds
Started May 26 12:50:01 PM PDT 24
Finished May 26 12:50:21 PM PDT 24
Peak memory 316480 kb
Host smart-38adcd7a-85c8-4dd4-8d28-3699fa834f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812703244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3812703244
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1132207571
Short name T1309
Test name
Test status
Simulation time 5465972346 ps
CPU time 26.05 seconds
Started May 26 12:49:59 PM PDT 24
Finished May 26 12:50:26 PM PDT 24
Peak memory 351028 kb
Host smart-f955f364-9f93-4972-89fe-5cb3cc4240d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132207571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1132207571
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3545331380
Short name T268
Test name
Test status
Simulation time 97378977901 ps
CPU time 1712.15 seconds
Started May 26 12:50:11 PM PDT 24
Finished May 26 01:18:45 PM PDT 24
Peak memory 3775136 kb
Host smart-0bad49d8-1242-4314-87bb-6f180da9e3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545331380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3545331380
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.698621447
Short name T1226
Test name
Test status
Simulation time 618232980 ps
CPU time 12.9 seconds
Started May 26 12:50:00 PM PDT 24
Finished May 26 12:50:14 PM PDT 24
Peak memory 212700 kb
Host smart-dcf773ba-e6ed-46aa-ae8b-9d6532151d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698621447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.698621447
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2511828672
Short name T777
Test name
Test status
Simulation time 2004091358 ps
CPU time 2.87 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:50:13 PM PDT 24
Peak memory 204488 kb
Host smart-e83e91c4-22a1-489c-9add-66bede1babaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511828672 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2511828672
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.788448180
Short name T146
Test name
Test status
Simulation time 10197873709 ps
CPU time 47.43 seconds
Started May 26 12:50:16 PM PDT 24
Finished May 26 12:51:04 PM PDT 24
Peak memory 322980 kb
Host smart-05e75b8b-53cc-4b22-b56b-7666d08d551e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788448180 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.788448180
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.206098559
Short name T436
Test name
Test status
Simulation time 10250410359 ps
CPU time 35.9 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:50:46 PM PDT 24
Peak memory 462756 kb
Host smart-9ad665a8-c41a-42f7-8a58-e1ff240e6122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206098559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.206098559
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.3526908945
Short name T605
Test name
Test status
Simulation time 3539165735 ps
CPU time 2.56 seconds
Started May 26 12:50:08 PM PDT 24
Finished May 26 12:50:11 PM PDT 24
Peak memory 204552 kb
Host smart-4888b94e-d58e-423c-bfa1-66bb1e807578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526908945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.3526908945
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3530662939
Short name T1225
Test name
Test status
Simulation time 1064871381 ps
CPU time 3.29 seconds
Started May 26 12:50:08 PM PDT 24
Finished May 26 12:50:12 PM PDT 24
Peak memory 204484 kb
Host smart-b8750452-fc90-4b61-8050-278fd5c40f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530662939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3530662939
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.799849232
Short name T1344
Test name
Test status
Simulation time 298388589 ps
CPU time 2.23 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:50:12 PM PDT 24
Peak memory 204564 kb
Host smart-b1b93088-0f3d-4d55-9b77-b2810ba47a25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799849232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.799849232
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2334330847
Short name T440
Test name
Test status
Simulation time 1774672680 ps
CPU time 4.7 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:50:14 PM PDT 24
Peak memory 204448 kb
Host smart-ac178a9a-310c-4cba-a6fc-52f2cfe7e03e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334330847 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2334330847
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3565074425
Short name T1266
Test name
Test status
Simulation time 8393229962 ps
CPU time 5.68 seconds
Started May 26 12:50:10 PM PDT 24
Finished May 26 12:50:16 PM PDT 24
Peak memory 204472 kb
Host smart-4efc98bd-0ef7-40e5-b1c5-63a2f5536fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565074425 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3565074425
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3675102693
Short name T334
Test name
Test status
Simulation time 17804862815 ps
CPU time 41.74 seconds
Started May 26 12:50:17 PM PDT 24
Finished May 26 12:50:59 PM PDT 24
Peak memory 204552 kb
Host smart-7bdc4d13-7e3b-43fc-9f2f-8cf22f320cf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675102693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3675102693
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2148990525
Short name T290
Test name
Test status
Simulation time 1559498332 ps
CPU time 6.34 seconds
Started May 26 12:50:08 PM PDT 24
Finished May 26 12:50:15 PM PDT 24
Peak memory 205348 kb
Host smart-6ba00589-a39b-4a34-b525-3115231eaec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148990525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2148990525
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2166066984
Short name T813
Test name
Test status
Simulation time 40871360351 ps
CPU time 79.44 seconds
Started May 26 12:50:09 PM PDT 24
Finished May 26 12:51:29 PM PDT 24
Peak memory 1349264 kb
Host smart-d7fd961c-4c8a-4ad0-9295-195f1018c279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166066984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2166066984
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_alert_test.518371510
Short name T646
Test name
Test status
Simulation time 36519724 ps
CPU time 0.62 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:28 PM PDT 24
Peak memory 204132 kb
Host smart-43ee3a92-01ac-42b6-935d-2c274e2d36a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518371510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.518371510
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4207599256
Short name T1267
Test name
Test status
Simulation time 474436883 ps
CPU time 3.6 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:50:22 PM PDT 24
Peak memory 212772 kb
Host smart-a9be5923-c145-46bb-b8f6-1c3c3582e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207599256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4207599256
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2190475310
Short name T339
Test name
Test status
Simulation time 338610787 ps
CPU time 18.2 seconds
Started May 26 12:50:17 PM PDT 24
Finished May 26 12:50:36 PM PDT 24
Peak memory 276012 kb
Host smart-66836bb3-7849-4490-98e1-b56492e3a8e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190475310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2190475310
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2877269285
Short name T566
Test name
Test status
Simulation time 1791489429 ps
CPU time 50.87 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:51:10 PM PDT 24
Peak memory 646744 kb
Host smart-5be0c936-eb89-459a-bada-e72fb7f22ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877269285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2877269285
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3788848645
Short name T661
Test name
Test status
Simulation time 6797666300 ps
CPU time 59.98 seconds
Started May 26 12:50:20 PM PDT 24
Finished May 26 12:51:21 PM PDT 24
Peak memory 645848 kb
Host smart-c101fd28-19e2-430a-8cdd-e0f80e244bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788848645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3788848645
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3975909905
Short name T1237
Test name
Test status
Simulation time 552223756 ps
CPU time 1.11 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:50:20 PM PDT 24
Peak memory 204496 kb
Host smart-fd47870b-ba04-4313-9805-d1d5dd3ff025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975909905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3975909905
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.4228307665
Short name T1190
Test name
Test status
Simulation time 4274663919 ps
CPU time 11.93 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:50:30 PM PDT 24
Peak memory 204492 kb
Host smart-f04254c5-9dcb-4f23-8d18-7a863deb732c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228307665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.4228307665
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3224518289
Short name T105
Test name
Test status
Simulation time 4472418866 ps
CPU time 127.56 seconds
Started May 26 12:50:19 PM PDT 24
Finished May 26 12:52:27 PM PDT 24
Peak memory 1269152 kb
Host smart-71ac9fff-5fb8-4868-8421-a687e30de5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224518289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3224518289
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.480478191
Short name T682
Test name
Test status
Simulation time 2717935523 ps
CPU time 5.65 seconds
Started May 26 12:50:30 PM PDT 24
Finished May 26 12:50:36 PM PDT 24
Peak memory 204492 kb
Host smart-51a17615-72bb-41c9-9e8a-75fa3164508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480478191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.480478191
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.851573869
Short name T1082
Test name
Test status
Simulation time 1922477568 ps
CPU time 85.31 seconds
Started May 26 12:50:29 PM PDT 24
Finished May 26 12:51:55 PM PDT 24
Peak memory 345096 kb
Host smart-d68e83f7-2cba-4bf6-a989-b9eb1e7eda1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851573869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.851573869
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1371843664
Short name T1343
Test name
Test status
Simulation time 82482753 ps
CPU time 0.71 seconds
Started May 26 12:50:15 PM PDT 24
Finished May 26 12:50:17 PM PDT 24
Peak memory 204124 kb
Host smart-5f61b938-dcdc-4423-8b0e-aef4ec81f5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371843664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1371843664
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2864623997
Short name T827
Test name
Test status
Simulation time 12643781512 ps
CPU time 1177.39 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 01:09:56 PM PDT 24
Peak memory 2049408 kb
Host smart-a1e2b898-2d02-430e-bcad-8878954c2f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864623997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2864623997
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.435854802
Short name T497
Test name
Test status
Simulation time 15531171682 ps
CPU time 61.11 seconds
Started May 26 12:50:19 PM PDT 24
Finished May 26 12:51:20 PM PDT 24
Peak memory 299184 kb
Host smart-fbf168cf-7a94-4109-b463-b52012358bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435854802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.435854802
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3741295845
Short name T151
Test name
Test status
Simulation time 84787254494 ps
CPU time 989.75 seconds
Started May 26 12:50:17 PM PDT 24
Finished May 26 01:06:48 PM PDT 24
Peak memory 2238944 kb
Host smart-30282a79-79de-4036-826e-2106bda12102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741295845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3741295845
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3625066950
Short name T333
Test name
Test status
Simulation time 2700620398 ps
CPU time 34.94 seconds
Started May 26 12:50:16 PM PDT 24
Finished May 26 12:50:52 PM PDT 24
Peak memory 212840 kb
Host smart-208fa9c0-377b-4a8f-ac27-95a214ceddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625066950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3625066950
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.951619946
Short name T691
Test name
Test status
Simulation time 892228966 ps
CPU time 4.25 seconds
Started May 26 12:50:27 PM PDT 24
Finished May 26 12:50:32 PM PDT 24
Peak memory 212644 kb
Host smart-b493cbe3-ee18-4e86-af12-58918d40482d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951619946 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.951619946
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2593900266
Short name T1016
Test name
Test status
Simulation time 10415061301 ps
CPU time 15.25 seconds
Started May 26 12:50:30 PM PDT 24
Finished May 26 12:50:46 PM PDT 24
Peak memory 248424 kb
Host smart-85ed364b-58bb-487c-b52b-850f67f7f05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593900266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2593900266
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3299307617
Short name T825
Test name
Test status
Simulation time 10489696855 ps
CPU time 12.08 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:39 PM PDT 24
Peak memory 277612 kb
Host smart-86d97683-b15a-4434-9194-88d5d6506485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299307617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3299307617
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.1286764223
Short name T1361
Test name
Test status
Simulation time 2381757516 ps
CPU time 2.87 seconds
Started May 26 12:50:30 PM PDT 24
Finished May 26 12:50:33 PM PDT 24
Peak memory 204536 kb
Host smart-00f26b1c-9b87-498b-8ece-18bcb76c0706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286764223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.1286764223
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.626379688
Short name T305
Test name
Test status
Simulation time 1380128342 ps
CPU time 2.2 seconds
Started May 26 12:50:25 PM PDT 24
Finished May 26 12:50:27 PM PDT 24
Peak memory 204436 kb
Host smart-c5a995db-0a2b-40e7-87a9-d5e0c895d616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626379688 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.626379688
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1049361314
Short name T1039
Test name
Test status
Simulation time 1917208650 ps
CPU time 3.14 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:30 PM PDT 24
Peak memory 204428 kb
Host smart-b554a208-83fe-45a9-92b4-73e3d49b3925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049361314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1049361314
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1319846926
Short name T535
Test name
Test status
Simulation time 973688903 ps
CPU time 5.51 seconds
Started May 26 12:50:17 PM PDT 24
Finished May 26 12:50:23 PM PDT 24
Peak memory 205312 kb
Host smart-e596f7d1-be1e-412e-8648-ea28ab0de840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319846926 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1319846926
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1424296073
Short name T671
Test name
Test status
Simulation time 10490710390 ps
CPU time 178.68 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:53:18 PM PDT 24
Peak memory 2665956 kb
Host smart-ec5b2867-7b84-42e7-a80d-1e80931c3ffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424296073 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1424296073
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3524695672
Short name T926
Test name
Test status
Simulation time 6492779790 ps
CPU time 7.76 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:50:26 PM PDT 24
Peak memory 204520 kb
Host smart-4a70fd40-1b83-409a-ae7a-9c2c7cb5bad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524695672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3524695672
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2705445971
Short name T1109
Test name
Test status
Simulation time 988667468 ps
CPU time 39.63 seconds
Started May 26 12:50:16 PM PDT 24
Finished May 26 12:50:57 PM PDT 24
Peak memory 204476 kb
Host smart-8c64b86a-b188-401f-b802-ef11cfe58957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705445971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2705445971
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1794195329
Short name T973
Test name
Test status
Simulation time 21667897917 ps
CPU time 24.72 seconds
Started May 26 12:50:19 PM PDT 24
Finished May 26 12:50:44 PM PDT 24
Peak memory 292636 kb
Host smart-e27e8997-b438-424d-8de0-0c7972715580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794195329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1794195329
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1640158768
Short name T695
Test name
Test status
Simulation time 12967023589 ps
CPU time 64.65 seconds
Started May 26 12:50:19 PM PDT 24
Finished May 26 12:51:24 PM PDT 24
Peak memory 812180 kb
Host smart-c817d504-88a8-4c5b-9559-771834f3b2c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640158768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1640158768
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.177208642
Short name T960
Test name
Test status
Simulation time 2720451712 ps
CPU time 7.94 seconds
Started May 26 12:50:18 PM PDT 24
Finished May 26 12:50:27 PM PDT 24
Peak memory 220780 kb
Host smart-857054b4-8901-4b87-b562-7a98a1aaacf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177208642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.177208642
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2833611468
Short name T1431
Test name
Test status
Simulation time 23504308 ps
CPU time 0.62 seconds
Started May 26 12:50:34 PM PDT 24
Finished May 26 12:50:35 PM PDT 24
Peak memory 204092 kb
Host smart-058cbde0-4eab-4528-ac18-b55e994ed370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833611468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2833611468
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2313116732
Short name T322
Test name
Test status
Simulation time 66761445 ps
CPU time 1.33 seconds
Started May 26 12:50:27 PM PDT 24
Finished May 26 12:50:29 PM PDT 24
Peak memory 212740 kb
Host smart-5d2c4bcd-7474-4899-92c6-91de273cace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313116732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2313116732
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3885928239
Short name T1244
Test name
Test status
Simulation time 284646397 ps
CPU time 14.5 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:41 PM PDT 24
Peak memory 259192 kb
Host smart-d41be2ff-ae0c-42ec-8c27-4cc210a2a0f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885928239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3885928239
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3408511575
Short name T677
Test name
Test status
Simulation time 2244035155 ps
CPU time 58.73 seconds
Started May 26 12:50:28 PM PDT 24
Finished May 26 12:51:27 PM PDT 24
Peak memory 618492 kb
Host smart-7e528e12-6c80-42fd-b7a9-4ad900b075cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408511575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3408511575
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.146659062
Short name T71
Test name
Test status
Simulation time 1418905982 ps
CPU time 34.45 seconds
Started May 26 12:50:25 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 447068 kb
Host smart-473af0ed-2248-463b-a01d-6ff6ce06e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146659062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.146659062
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3250056226
Short name T1119
Test name
Test status
Simulation time 312523132 ps
CPU time 0.76 seconds
Started May 26 12:50:25 PM PDT 24
Finished May 26 12:50:26 PM PDT 24
Peak memory 204300 kb
Host smart-1417adba-e6d7-4915-80f1-34c32ed231c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250056226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3250056226
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3445772059
Short name T228
Test name
Test status
Simulation time 169116608 ps
CPU time 3.59 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:30 PM PDT 24
Peak memory 204492 kb
Host smart-a93eab50-f350-4ebd-b25a-26fabb2119f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445772059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3445772059
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3914408396
Short name T506
Test name
Test status
Simulation time 5477684986 ps
CPU time 181.94 seconds
Started May 26 12:50:25 PM PDT 24
Finished May 26 12:53:28 PM PDT 24
Peak memory 1536856 kb
Host smart-43e2d778-6173-498e-ae6a-a00865713262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914408396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3914408396
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3453679072
Short name T425
Test name
Test status
Simulation time 528549077 ps
CPU time 21.1 seconds
Started May 26 12:50:36 PM PDT 24
Finished May 26 12:50:58 PM PDT 24
Peak memory 204624 kb
Host smart-af554f79-8051-4097-8031-dfb8b769a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453679072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3453679072
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3344452176
Short name T604
Test name
Test status
Simulation time 1682709441 ps
CPU time 85.42 seconds
Started May 26 12:50:39 PM PDT 24
Finished May 26 12:52:04 PM PDT 24
Peak memory 387044 kb
Host smart-4481f1c6-9c69-4425-bb0b-91874fc23d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344452176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3344452176
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3614249007
Short name T524
Test name
Test status
Simulation time 28013299 ps
CPU time 0.71 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:28 PM PDT 24
Peak memory 204140 kb
Host smart-ec177619-f981-4c5d-9f87-13d5455e77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614249007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3614249007
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.514956059
Short name T1205
Test name
Test status
Simulation time 6687356939 ps
CPU time 615.6 seconds
Started May 26 12:50:28 PM PDT 24
Finished May 26 01:00:44 PM PDT 24
Peak memory 1571552 kb
Host smart-f8306ff9-1118-4020-8da8-b449899fff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514956059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.514956059
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1441003073
Short name T983
Test name
Test status
Simulation time 5090073447 ps
CPU time 19.9 seconds
Started May 26 12:50:29 PM PDT 24
Finished May 26 12:50:50 PM PDT 24
Peak memory 326328 kb
Host smart-449cc4c1-0476-4ea2-b97b-3296ffeacc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441003073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1441003073
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3374964729
Short name T267
Test name
Test status
Simulation time 52723848889 ps
CPU time 581.28 seconds
Started May 26 12:50:28 PM PDT 24
Finished May 26 01:00:10 PM PDT 24
Peak memory 2415660 kb
Host smart-fc52ce41-848a-4398-a3bb-bca79223f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374964729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3374964729
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2114814517
Short name T114
Test name
Test status
Simulation time 790231565 ps
CPU time 13.04 seconds
Started May 26 12:50:27 PM PDT 24
Finished May 26 12:50:41 PM PDT 24
Peak memory 218956 kb
Host smart-a8111c8f-2de6-4eb2-9848-eeb9efd81f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114814517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2114814517
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2552736622
Short name T1176
Test name
Test status
Simulation time 1648506045 ps
CPU time 2.7 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:50:39 PM PDT 24
Peak memory 204388 kb
Host smart-5684862d-6c65-45c1-8feb-6b890f371e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552736622 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2552736622
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1224229255
Short name T1197
Test name
Test status
Simulation time 10381155542 ps
CPU time 8.04 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:50:44 PM PDT 24
Peak memory 225288 kb
Host smart-d17c60cf-f964-4cd5-ac80-c7e6272fcbc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224229255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1224229255
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2007060212
Short name T92
Test name
Test status
Simulation time 10207430481 ps
CPU time 71.88 seconds
Started May 26 12:50:37 PM PDT 24
Finished May 26 12:51:50 PM PDT 24
Peak memory 634484 kb
Host smart-eb9bc701-6f63-4a21-bb44-c723193949bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007060212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2007060212
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.1108580817
Short name T1443
Test name
Test status
Simulation time 1108944818 ps
CPU time 3.55 seconds
Started May 26 12:50:34 PM PDT 24
Finished May 26 12:50:38 PM PDT 24
Peak memory 204440 kb
Host smart-1bc160dd-2db0-427a-a6ff-51ae027a528e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108580817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.1108580817
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.159489950
Short name T185
Test name
Test status
Simulation time 1068233743 ps
CPU time 3.88 seconds
Started May 26 12:50:34 PM PDT 24
Finished May 26 12:50:38 PM PDT 24
Peak memory 204488 kb
Host smart-77fb5866-e024-483b-9bf9-abddfdfb9e78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159489950 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.159489950
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.4168704818
Short name T24
Test name
Test status
Simulation time 349715107 ps
CPU time 2.54 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:50:38 PM PDT 24
Peak memory 204572 kb
Host smart-055bc977-96f4-4397-857a-f3bddf9fce4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168704818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.4168704818
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3506533223
Short name T409
Test name
Test status
Simulation time 5191076281 ps
CPU time 4.4 seconds
Started May 26 12:50:37 PM PDT 24
Finished May 26 12:50:42 PM PDT 24
Peak memory 204476 kb
Host smart-2f8e0a17-b3dd-4f7a-97b7-6768a8fb14a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506533223 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3506533223
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.4121808561
Short name T399
Test name
Test status
Simulation time 9442540958 ps
CPU time 127.65 seconds
Started May 26 12:50:37 PM PDT 24
Finished May 26 12:52:46 PM PDT 24
Peak memory 2399408 kb
Host smart-22c190b5-e3c4-4927-909d-c3cc59955b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121808561 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.4121808561
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.4227653455
Short name T304
Test name
Test status
Simulation time 2548868593 ps
CPU time 16.49 seconds
Started May 26 12:50:26 PM PDT 24
Finished May 26 12:50:44 PM PDT 24
Peak memory 204816 kb
Host smart-1a7ebaf0-8f87-47f9-9620-0bfdef28bdba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227653455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.4227653455
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.564262806
Short name T631
Test name
Test status
Simulation time 414686208 ps
CPU time 7 seconds
Started May 26 12:50:34 PM PDT 24
Finished May 26 12:50:41 PM PDT 24
Peak memory 204468 kb
Host smart-b834c61a-fdaa-4635-8442-aae4149037d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564262806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.564262806
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3572708957
Short name T1410
Test name
Test status
Simulation time 37908184092 ps
CPU time 490.93 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:58:47 PM PDT 24
Peak memory 4372460 kb
Host smart-0d8f3801-f4cc-4a26-aa7a-f4d6fe59b2da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572708957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3572708957
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3062513976
Short name T299
Test name
Test status
Simulation time 4555596323 ps
CPU time 15.23 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:50:51 PM PDT 24
Peak memory 369112 kb
Host smart-15549703-85ca-4214-ad8e-e69fb84cf1b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062513976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3062513976
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2863810010
Short name T1004
Test name
Test status
Simulation time 3103146792 ps
CPU time 8.17 seconds
Started May 26 12:50:36 PM PDT 24
Finished May 26 12:50:45 PM PDT 24
Peak memory 210372 kb
Host smart-7c1e8afb-566d-4aa4-a052-eff3b7e2f14a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863810010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2863810010
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3512254001
Short name T676
Test name
Test status
Simulation time 49483695 ps
CPU time 0.62 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:50:59 PM PDT 24
Peak memory 204092 kb
Host smart-c7428eaa-f95b-40fc-8606-0c09573f673d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512254001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3512254001
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3127791482
Short name T1286
Test name
Test status
Simulation time 1503178052 ps
CPU time 2.33 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:50:50 PM PDT 24
Peak memory 212708 kb
Host smart-f212fc78-62d1-4524-afbc-724e2a1c8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127791482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3127791482
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.481283008
Short name T1367
Test name
Test status
Simulation time 456710709 ps
CPU time 9.85 seconds
Started May 26 12:50:50 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 270384 kb
Host smart-a7632441-1ed5-410d-a5dc-80df041cc18d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481283008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.481283008
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2655948536
Short name T1092
Test name
Test status
Simulation time 2546172046 ps
CPU time 209.09 seconds
Started May 26 12:50:50 PM PDT 24
Finished May 26 12:54:20 PM PDT 24
Peak memory 810008 kb
Host smart-204fe86f-77a4-4b23-ab9a-61e7fb000c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655948536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2655948536
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.737946633
Short name T1130
Test name
Test status
Simulation time 2532183756 ps
CPU time 106.6 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:52:34 PM PDT 24
Peak memory 832492 kb
Host smart-53d93216-6540-4b0b-a8f7-2ac359381952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737946633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.737946633
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3879705081
Short name T233
Test name
Test status
Simulation time 2176609653 ps
CPU time 0.97 seconds
Started May 26 12:50:48 PM PDT 24
Finished May 26 12:50:50 PM PDT 24
Peak memory 204260 kb
Host smart-c96d3525-ea0e-4d0e-a4bf-27316ebc86a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879705081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3879705081
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2416470267
Short name T636
Test name
Test status
Simulation time 141133645 ps
CPU time 3.65 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:50:53 PM PDT 24
Peak memory 204540 kb
Host smart-1564c59a-7434-4593-882d-2fd455044334
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416470267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2416470267
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.874121163
Short name T108
Test name
Test status
Simulation time 2601290336 ps
CPU time 52.38 seconds
Started May 26 12:50:35 PM PDT 24
Finished May 26 12:51:28 PM PDT 24
Peak memory 841620 kb
Host smart-59ded1ff-ad6c-421c-a2c5-08efcd05359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874121163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.874121163
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3379243586
Short name T372
Test name
Test status
Simulation time 2932178018 ps
CPU time 5.77 seconds
Started May 26 12:51:02 PM PDT 24
Finished May 26 12:51:08 PM PDT 24
Peak memory 204528 kb
Host smart-e38bc5ee-48a7-421e-9f2c-ec1de5d2ccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379243586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3379243586
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2904483643
Short name T900
Test name
Test status
Simulation time 5402148782 ps
CPU time 26.01 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:51:13 PM PDT 24
Peak memory 381800 kb
Host smart-d4f9c59e-ad7a-4512-b96e-9d22e27e637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904483643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2904483643
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3255612549
Short name T1174
Test name
Test status
Simulation time 44605128 ps
CPU time 0.6 seconds
Started May 26 12:50:36 PM PDT 24
Finished May 26 12:50:37 PM PDT 24
Peak memory 204260 kb
Host smart-ad5235fc-df26-4fcb-a7aa-ee866f670a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255612549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3255612549
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.489201607
Short name T945
Test name
Test status
Simulation time 13644440011 ps
CPU time 182.61 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:53:50 PM PDT 24
Peak memory 835716 kb
Host smart-4a578378-4392-47b8-91f0-9e014441d9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489201607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.489201607
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.786048217
Short name T625
Test name
Test status
Simulation time 9604273037 ps
CPU time 42.61 seconds
Started May 26 12:50:36 PM PDT 24
Finished May 26 12:51:20 PM PDT 24
Peak memory 404936 kb
Host smart-8760d7c6-b4f7-4402-b0b9-0b38f50bacea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786048217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.786048217
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.4211200071
Short name T262
Test name
Test status
Simulation time 81429189093 ps
CPU time 953.93 seconds
Started May 26 12:50:50 PM PDT 24
Finished May 26 01:06:44 PM PDT 24
Peak memory 2799756 kb
Host smart-c6f599c8-50ea-4fb4-9201-140fef41472c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211200071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.4211200071
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.996634142
Short name T990
Test name
Test status
Simulation time 2840450720 ps
CPU time 12.34 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:51:02 PM PDT 24
Peak memory 220404 kb
Host smart-4cbf72d6-484e-44a5-88b3-b191fa8d7347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996634142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.996634142
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1749311281
Short name T1158
Test name
Test status
Simulation time 4070240836 ps
CPU time 5.07 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:50:55 PM PDT 24
Peak memory 212732 kb
Host smart-b3fc32f2-83ed-4b50-abf5-836adab77795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749311281 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1749311281
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2945863207
Short name T1364
Test name
Test status
Simulation time 10107874638 ps
CPU time 24.1 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:51:11 PM PDT 24
Peak memory 291692 kb
Host smart-71fede1e-42d5-4332-ba09-f58f0d6a1401
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945863207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2945863207
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.290006928
Short name T330
Test name
Test status
Simulation time 10753789320 ps
CPU time 7.95 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:50:58 PM PDT 24
Peak memory 253328 kb
Host smart-0703c96f-0175-4241-b74d-0e1846fe1530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290006928 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.290006928
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.2758595006
Short name T510
Test name
Test status
Simulation time 1201811532 ps
CPU time 3.59 seconds
Started May 26 12:51:01 PM PDT 24
Finished May 26 12:51:05 PM PDT 24
Peak memory 204432 kb
Host smart-79876e93-2a47-48d8-9122-5b3f7ce12517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758595006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.2758595006
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.2522736604
Short name T1167
Test name
Test status
Simulation time 1091457833 ps
CPU time 3.08 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:01 PM PDT 24
Peak memory 204484 kb
Host smart-f80d0f44-9682-4cab-b0c4-f2bd03691b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522736604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.2522736604
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1106017416
Short name T804
Test name
Test status
Simulation time 307616962 ps
CPU time 2.33 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:50:50 PM PDT 24
Peak memory 204544 kb
Host smart-7bfac4e1-0dfa-40c1-93fc-8d84a38441d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106017416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1106017416
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3264173522
Short name T780
Test name
Test status
Simulation time 12526369808 ps
CPU time 3.83 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:50:54 PM PDT 24
Peak memory 204464 kb
Host smart-c4dc82f6-2f34-4e51-8f67-aca5f33e7e6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264173522 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3264173522
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3914124264
Short name T314
Test name
Test status
Simulation time 17191520218 ps
CPU time 8.55 seconds
Started May 26 12:50:51 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 237972 kb
Host smart-72466bb5-23df-416e-8f85-ff53fb2246ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914124264 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3914124264
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4223248958
Short name T989
Test name
Test status
Simulation time 704511623 ps
CPU time 21.71 seconds
Started May 26 12:50:48 PM PDT 24
Finished May 26 12:51:10 PM PDT 24
Peak memory 204552 kb
Host smart-5cfb25a7-cb6d-4a92-8792-ce02c3bb9997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223248958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4223248958
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3663589485
Short name T1206
Test name
Test status
Simulation time 2020306130 ps
CPU time 38.97 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:51:27 PM PDT 24
Peak memory 204708 kb
Host smart-55730512-5e2b-45b4-bd27-99473da24ef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663589485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3663589485
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2208616797
Short name T1007
Test name
Test status
Simulation time 52311191600 ps
CPU time 159.09 seconds
Started May 26 12:50:47 PM PDT 24
Finished May 26 12:53:26 PM PDT 24
Peak memory 2043144 kb
Host smart-3502b6af-2c01-4dc6-9802-fcff548ccbaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208616797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2208616797
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3217925590
Short name T806
Test name
Test status
Simulation time 7003160663 ps
CPU time 186.47 seconds
Started May 26 12:50:49 PM PDT 24
Finished May 26 12:53:56 PM PDT 24
Peak memory 1875256 kb
Host smart-916e01fc-890a-4eb0-a889-6a3a8fd1da3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217925590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3217925590
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1163514870
Short name T515
Test name
Test status
Simulation time 22698944783 ps
CPU time 6.74 seconds
Started May 26 12:50:48 PM PDT 24
Finished May 26 12:50:56 PM PDT 24
Peak memory 215184 kb
Host smart-7daf9a45-f0f2-4fd5-af06-06807fcc8af1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163514870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1163514870
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1815338090
Short name T716
Test name
Test status
Simulation time 18969649 ps
CPU time 0.66 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:50:58 PM PDT 24
Peak memory 204088 kb
Host smart-3040dec9-5bb7-4432-a11e-fc49b74633fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815338090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1815338090
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3703460189
Short name T705
Test name
Test status
Simulation time 295938767 ps
CPU time 1.62 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 212736 kb
Host smart-3707a082-f1fe-43da-b02e-f231ffb90d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703460189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3703460189
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.949171281
Short name T841
Test name
Test status
Simulation time 1018634077 ps
CPU time 15.31 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:15 PM PDT 24
Peak memory 259232 kb
Host smart-8b1fc94f-f0f8-4a58-a2b7-a8239cf70ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949171281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.949171281
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4244555792
Short name T770
Test name
Test status
Simulation time 2905694909 ps
CPU time 206.6 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:54:24 PM PDT 24
Peak memory 787616 kb
Host smart-ac96e346-24d1-4530-8d43-f18064843da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244555792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4244555792
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.849757675
Short name T320
Test name
Test status
Simulation time 16554497751 ps
CPU time 92.81 seconds
Started May 26 12:50:59 PM PDT 24
Finished May 26 12:52:33 PM PDT 24
Peak memory 532692 kb
Host smart-ec5e5001-ed62-426b-88b6-18aad87b72a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849757675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.849757675
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3838162275
Short name T876
Test name
Test status
Simulation time 140214169 ps
CPU time 1.25 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 204512 kb
Host smart-22dddcb8-a0d2-4593-aac4-691608c29efe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838162275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3838162275
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.4291742993
Short name T964
Test name
Test status
Simulation time 502168548 ps
CPU time 5.27 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:04 PM PDT 24
Peak memory 235792 kb
Host smart-49473351-cd28-4f86-8aed-f2fc162a5761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291742993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.4291742993
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2452762163
Short name T1144
Test name
Test status
Simulation time 14354156305 ps
CPU time 93.72 seconds
Started May 26 12:51:01 PM PDT 24
Finished May 26 12:52:36 PM PDT 24
Peak memory 991440 kb
Host smart-0ace78ec-dfc0-4756-aa91-914c0db61d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452762163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2452762163
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.945572992
Short name T240
Test name
Test status
Simulation time 1840238134 ps
CPU time 5.06 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:02 PM PDT 24
Peak memory 204440 kb
Host smart-e3efd048-cd7b-44ce-9ce4-638bb9a92719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945572992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.945572992
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.958699425
Short name T351
Test name
Test status
Simulation time 13536004108 ps
CPU time 25.97 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:24 PM PDT 24
Peak memory 308768 kb
Host smart-c733f265-efce-4ae2-9c2b-a281af783876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958699425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.958699425
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2955663771
Short name T341
Test name
Test status
Simulation time 25443126 ps
CPU time 0.7 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:00 PM PDT 24
Peak memory 204160 kb
Host smart-2b1822e5-3631-4fc1-9c5e-aeee4bea6e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955663771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2955663771
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.4169606772
Short name T1291
Test name
Test status
Simulation time 8405349612 ps
CPU time 10.1 seconds
Started May 26 12:51:03 PM PDT 24
Finished May 26 12:51:14 PM PDT 24
Peak memory 298868 kb
Host smart-15a27974-bacc-416c-8342-3d06e6d382d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169606772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.4169606772
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3358324241
Short name T888
Test name
Test status
Simulation time 6114137138 ps
CPU time 39.01 seconds
Started May 26 12:51:00 PM PDT 24
Finished May 26 12:51:39 PM PDT 24
Peak memory 356724 kb
Host smart-1cedc2cd-5db8-44c0-a8cd-a13dafdeaebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358324241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3358324241
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3248456621
Short name T857
Test name
Test status
Simulation time 20311607668 ps
CPU time 450.8 seconds
Started May 26 12:51:02 PM PDT 24
Finished May 26 12:58:33 PM PDT 24
Peak memory 1315364 kb
Host smart-393a41e7-af2b-41e7-9e76-01e78f6a9dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248456621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3248456621
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1398213697
Short name T652
Test name
Test status
Simulation time 1574255506 ps
CPU time 13.51 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:12 PM PDT 24
Peak memory 220520 kb
Host smart-fb3607d5-6300-428a-8a79-be7fe2ba6c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398213697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1398213697
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.4284203004
Short name T1251
Test name
Test status
Simulation time 3359619671 ps
CPU time 3.52 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:02 PM PDT 24
Peak memory 204512 kb
Host smart-a917c99a-0466-492a-b225-82f716d2a713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284203004 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.4284203004
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.55195598
Short name T1135
Test name
Test status
Simulation time 10485278587 ps
CPU time 12.28 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:11 PM PDT 24
Peak memory 242160 kb
Host smart-395e077c-f288-4791-85e0-06d39931dee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55195598 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_acq.55195598
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1789366644
Short name T169
Test name
Test status
Simulation time 10132708597 ps
CPU time 31.93 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:31 PM PDT 24
Peak memory 448384 kb
Host smart-b5a4854c-b7cc-4e65-827a-c81bf58e8c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789366644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1789366644
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.3417617119
Short name T893
Test name
Test status
Simulation time 1072513237 ps
CPU time 4.81 seconds
Started May 26 12:50:59 PM PDT 24
Finished May 26 12:51:04 PM PDT 24
Peak memory 204552 kb
Host smart-4a2372ec-a037-4862-ae8e-3e902a958ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417617119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.3417617119
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.1382479755
Short name T874
Test name
Test status
Simulation time 1120097356 ps
CPU time 6.05 seconds
Started May 26 12:51:02 PM PDT 24
Finished May 26 12:51:09 PM PDT 24
Peak memory 204444 kb
Host smart-86070cc8-1f58-48f4-a39e-154e77c17a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382479755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.1382479755
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3443553234
Short name T731
Test name
Test status
Simulation time 1533649573 ps
CPU time 2.53 seconds
Started May 26 12:50:59 PM PDT 24
Finished May 26 12:51:02 PM PDT 24
Peak memory 204536 kb
Host smart-26e821e3-0c4b-46f0-b68f-9c5c06637213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443553234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3443553234
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.692790005
Short name T1033
Test name
Test status
Simulation time 3681237989 ps
CPU time 5.09 seconds
Started May 26 12:51:01 PM PDT 24
Finished May 26 12:51:07 PM PDT 24
Peak memory 204464 kb
Host smart-6ae87e68-4d5e-46f2-aa63-99cd7d135de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692790005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.692790005
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3024568651
Short name T1051
Test name
Test status
Simulation time 5951245082 ps
CPU time 7.37 seconds
Started May 26 12:50:57 PM PDT 24
Finished May 26 12:51:05 PM PDT 24
Peak memory 204488 kb
Host smart-417ffb53-aaa8-4a70-9493-fd2f34f36604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024568651 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3024568651
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1174028540
Short name T336
Test name
Test status
Simulation time 2060489801 ps
CPU time 15.47 seconds
Started May 26 12:50:56 PM PDT 24
Finished May 26 12:51:13 PM PDT 24
Peak memory 204456 kb
Host smart-d535722c-5937-430e-88e9-9b914103f16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174028540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1174028540
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1043645148
Short name T663
Test name
Test status
Simulation time 273389861 ps
CPU time 9.44 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:08 PM PDT 24
Peak memory 204456 kb
Host smart-8a039889-2a06-40d0-bb19-7823e50d7421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043645148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1043645148
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1657363475
Short name T282
Test name
Test status
Simulation time 16122922351 ps
CPU time 8.02 seconds
Started May 26 12:50:59 PM PDT 24
Finished May 26 12:51:08 PM PDT 24
Peak memory 204556 kb
Host smart-9d8fc60b-c484-4eb1-a993-091328ea34e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657363475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1657363475
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1543745283
Short name T347
Test name
Test status
Simulation time 4746219783 ps
CPU time 274.81 seconds
Started May 26 12:51:02 PM PDT 24
Finished May 26 12:55:37 PM PDT 24
Peak memory 1150704 kb
Host smart-b2089a39-85c6-4dd8-ba54-b5ec3512d13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543745283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1543745283
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2535797628
Short name T1048
Test name
Test status
Simulation time 2472515226 ps
CPU time 6.92 seconds
Started May 26 12:50:58 PM PDT 24
Finished May 26 12:51:06 PM PDT 24
Peak memory 217120 kb
Host smart-8e971a51-ca04-428e-a18b-5a80bee4a60b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535797628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2535797628
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.856806553
Short name T465
Test name
Test status
Simulation time 33731938 ps
CPU time 0.63 seconds
Started May 26 12:51:20 PM PDT 24
Finished May 26 12:51:21 PM PDT 24
Peak memory 204032 kb
Host smart-2ec9bfc0-8b3d-432b-9afb-637d2972b5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856806553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.856806553
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2214220244
Short name T1083
Test name
Test status
Simulation time 248065523 ps
CPU time 1.31 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:51:12 PM PDT 24
Peak memory 216288 kb
Host smart-7d2a212e-d461-4f1a-a144-a48fc3c918ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214220244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2214220244
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2923757684
Short name T600
Test name
Test status
Simulation time 322989820 ps
CPU time 4.84 seconds
Started May 26 12:51:12 PM PDT 24
Finished May 26 12:51:18 PM PDT 24
Peak memory 213204 kb
Host smart-d60b659c-5386-4729-861b-2fc0b05c0c9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923757684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2923757684
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2170413732
Short name T183
Test name
Test status
Simulation time 2350670517 ps
CPU time 164.39 seconds
Started May 26 12:51:20 PM PDT 24
Finished May 26 12:54:05 PM PDT 24
Peak memory 671312 kb
Host smart-2ae3875f-61d4-4678-bb1d-2faf0d4feed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170413732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2170413732
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.937284368
Short name T809
Test name
Test status
Simulation time 5146752499 ps
CPU time 92.72 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:52:44 PM PDT 24
Peak memory 794880 kb
Host smart-4f6a87f9-a4e0-478f-89be-e3ca1d2ab578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937284368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.937284368
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2936944187
Short name T1368
Test name
Test status
Simulation time 534251432 ps
CPU time 0.85 seconds
Started May 26 12:51:12 PM PDT 24
Finished May 26 12:51:13 PM PDT 24
Peak memory 204192 kb
Host smart-0c95f93f-2d93-4e9b-932a-fb83f1cf6f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936944187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2936944187
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1855716740
Short name T297
Test name
Test status
Simulation time 438870495 ps
CPU time 4.55 seconds
Started May 26 12:51:19 PM PDT 24
Finished May 26 12:51:25 PM PDT 24
Peak memory 204416 kb
Host smart-ffd5355b-656b-40bd-82e2-8f3eac92c346
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855716740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1855716740
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.3761624866
Short name T107
Test name
Test status
Simulation time 3826996100 ps
CPU time 101.79 seconds
Started May 26 12:51:13 PM PDT 24
Finished May 26 12:52:56 PM PDT 24
Peak memory 1153452 kb
Host smart-42ffcf90-6749-479e-8240-4b0e21f182fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761624866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3761624866
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1880904967
Short name T836
Test name
Test status
Simulation time 208799296 ps
CPU time 8.37 seconds
Started May 26 12:51:20 PM PDT 24
Finished May 26 12:51:29 PM PDT 24
Peak memory 204448 kb
Host smart-7b37180c-e854-42bc-aaf1-45b16146b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880904967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1880904967
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3656456738
Short name T462
Test name
Test status
Simulation time 1662599157 ps
CPU time 30.24 seconds
Started May 26 12:51:20 PM PDT 24
Finished May 26 12:51:51 PM PDT 24
Peak memory 292208 kb
Host smart-1d0d38fb-7c93-4627-a9e9-f68b68a7cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656456738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3656456738
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2870685798
Short name T338
Test name
Test status
Simulation time 81517051 ps
CPU time 0.73 seconds
Started May 26 12:51:09 PM PDT 24
Finished May 26 12:51:11 PM PDT 24
Peak memory 204128 kb
Host smart-073ddeb9-67b3-4b58-bd98-ca8e194190b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870685798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2870685798
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.868109282
Short name T159
Test name
Test status
Simulation time 2638808680 ps
CPU time 29.01 seconds
Started May 26 12:51:09 PM PDT 24
Finished May 26 12:51:38 PM PDT 24
Peak memory 499768 kb
Host smart-be5678b6-67fe-44cf-b11e-40a921404520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868109282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.868109282
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1968226254
Short name T988
Test name
Test status
Simulation time 2103664661 ps
CPU time 48.96 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:52:00 PM PDT 24
Peak memory 421752 kb
Host smart-ef37a897-53a6-4f65-aff8-29352eaede8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968226254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1968226254
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3789560556
Short name T57
Test name
Test status
Simulation time 46036350747 ps
CPU time 575.65 seconds
Started May 26 12:51:11 PM PDT 24
Finished May 26 01:00:48 PM PDT 24
Peak memory 2023164 kb
Host smart-5dc8f84a-0077-4996-9161-6095a178289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789560556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3789560556
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1064704003
Short name T58
Test name
Test status
Simulation time 3224505904 ps
CPU time 37.68 seconds
Started May 26 12:51:09 PM PDT 24
Finished May 26 12:51:47 PM PDT 24
Peak memory 212964 kb
Host smart-863a0a89-8457-4d66-9d28-e17d03639403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064704003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1064704003
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1137457006
Short name T369
Test name
Test status
Simulation time 4913502927 ps
CPU time 4.01 seconds
Started May 26 12:51:16 PM PDT 24
Finished May 26 12:51:20 PM PDT 24
Peak memory 212652 kb
Host smart-f85e0884-f51e-487d-aeea-102b74758a78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137457006 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1137457006
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1002258949
Short name T1390
Test name
Test status
Simulation time 10191438174 ps
CPU time 12.33 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:51:24 PM PDT 24
Peak memory 256568 kb
Host smart-01397263-3db2-4493-b8e3-f72f1c80aa1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002258949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1002258949
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3402896172
Short name T1179
Test name
Test status
Simulation time 10235155050 ps
CPU time 14.33 seconds
Started May 26 12:51:15 PM PDT 24
Finished May 26 12:51:30 PM PDT 24
Peak memory 292800 kb
Host smart-47ddab29-ad4f-4482-8c78-3f55a4d4c189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402896172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3402896172
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.1373652697
Short name T521
Test name
Test status
Simulation time 1435392333 ps
CPU time 2.11 seconds
Started May 26 12:51:20 PM PDT 24
Finished May 26 12:51:22 PM PDT 24
Peak memory 204432 kb
Host smart-b8f4759b-e545-49e4-b3a6-ecf69ee1c11e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373652697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.1373652697
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1023455714
Short name T276
Test name
Test status
Simulation time 1051564742 ps
CPU time 5.48 seconds
Started May 26 12:51:16 PM PDT 24
Finished May 26 12:51:22 PM PDT 24
Peak memory 204332 kb
Host smart-14a82cec-971a-4aa4-8f01-1b87ac99b9e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023455714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1023455714
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.930118562
Short name T335
Test name
Test status
Simulation time 1553071410 ps
CPU time 2.55 seconds
Started May 26 12:51:14 PM PDT 24
Finished May 26 12:51:17 PM PDT 24
Peak memory 204476 kb
Host smart-ed385de9-02e6-4696-993a-5f1bbf276288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930118562 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.930118562
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3344085995
Short name T127
Test name
Test status
Simulation time 817261137 ps
CPU time 4.39 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:51:16 PM PDT 24
Peak memory 204372 kb
Host smart-b617b52f-4ecb-4a11-ad2d-69173b90397e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344085995 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3344085995
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1378588680
Short name T575
Test name
Test status
Simulation time 14262385697 ps
CPU time 283.16 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:55:54 PM PDT 24
Peak memory 3600956 kb
Host smart-d04e5b05-ac26-4240-8727-350e7f131ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378588680 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1378588680
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.858227043
Short name T30
Test name
Test status
Simulation time 1860819263 ps
CPU time 14.48 seconds
Started May 26 12:51:11 PM PDT 24
Finished May 26 12:51:26 PM PDT 24
Peak memory 204604 kb
Host smart-a1af3d5a-c340-49f3-855b-cdaf181c8243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858227043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.858227043
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.445719268
Short name T352
Test name
Test status
Simulation time 428903569 ps
CPU time 8.21 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:51:19 PM PDT 24
Peak memory 204412 kb
Host smart-12f87d7d-66e1-4e15-894d-8bcd1af8296a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445719268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.445719268
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.3740001135
Short name T454
Test name
Test status
Simulation time 39589748056 ps
CPU time 537.42 seconds
Started May 26 12:51:09 PM PDT 24
Finished May 26 01:00:07 PM PDT 24
Peak memory 4906316 kb
Host smart-eeadccf1-c457-42e7-855f-b11ddc8f01fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740001135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.3740001135
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1793814668
Short name T1035
Test name
Test status
Simulation time 9167347723 ps
CPU time 407.56 seconds
Started May 26 12:51:10 PM PDT 24
Finished May 26 12:57:58 PM PDT 24
Peak memory 1501896 kb
Host smart-9618c098-bef2-4965-9d1e-0642c327085f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793814668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1793814668
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.796655170
Short name T709
Test name
Test status
Simulation time 1374406832 ps
CPU time 7.34 seconds
Started May 26 12:51:11 PM PDT 24
Finished May 26 12:51:19 PM PDT 24
Peak memory 217344 kb
Host smart-f227d0b5-04cd-4339-a751-27519c2f31b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796655170 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.796655170
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2015976398
Short name T665
Test name
Test status
Simulation time 90268328 ps
CPU time 0.65 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:35 PM PDT 24
Peak memory 204088 kb
Host smart-297f6983-e5e7-4ed2-bcb8-a6690a0e14db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015976398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2015976398
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.731828603
Short name T467
Test name
Test status
Simulation time 63212107 ps
CPU time 1.63 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:51:27 PM PDT 24
Peak memory 212624 kb
Host smart-58dd8c03-7c67-4fe7-90c6-7b7b07173b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731828603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.731828603
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2314727005
Short name T287
Test name
Test status
Simulation time 2291671106 ps
CPU time 11.43 seconds
Started May 26 12:51:15 PM PDT 24
Finished May 26 12:51:27 PM PDT 24
Peak memory 323792 kb
Host smart-29391988-158a-4778-a134-13a1cb6179a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314727005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2314727005
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2021743922
Short name T118
Test name
Test status
Simulation time 8802182385 ps
CPU time 75.41 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 12:52:41 PM PDT 24
Peak memory 730100 kb
Host smart-f102aed2-bc77-4048-820a-56aa19181dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021743922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2021743922
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1235177159
Short name T1406
Test name
Test status
Simulation time 4788156447 ps
CPU time 87.76 seconds
Started May 26 12:51:14 PM PDT 24
Finished May 26 12:52:43 PM PDT 24
Peak memory 758680 kb
Host smart-e8b16496-f46b-4e3c-81ea-8aab4ca2025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235177159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1235177159
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2454249133
Short name T1392
Test name
Test status
Simulation time 293154823 ps
CPU time 1.11 seconds
Started May 26 12:51:14 PM PDT 24
Finished May 26 12:51:16 PM PDT 24
Peak memory 204228 kb
Host smart-71deeec3-8408-4c23-a2ed-14f84a54646e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454249133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2454249133
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.2402899673
Short name T921
Test name
Test status
Simulation time 648459079 ps
CPU time 8.65 seconds
Started May 26 12:51:13 PM PDT 24
Finished May 26 12:51:23 PM PDT 24
Peak memory 204488 kb
Host smart-9e486de2-b2da-49b3-af0a-2d86cc4c9ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402899673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.2402899673
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.3021753511
Short name T810
Test name
Test status
Simulation time 2758870995 ps
CPU time 172.31 seconds
Started May 26 12:51:13 PM PDT 24
Finished May 26 12:54:06 PM PDT 24
Peak memory 849140 kb
Host smart-c9d4e3f2-7488-4284-bee7-92a6a1041ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021753511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3021753511
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2763633145
Short name T1271
Test name
Test status
Simulation time 264068480 ps
CPU time 3.66 seconds
Started May 26 12:51:32 PM PDT 24
Finished May 26 12:51:36 PM PDT 24
Peak memory 204448 kb
Host smart-67d668b4-7b6b-4885-adde-b2652e3393ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763633145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2763633145
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1170716254
Short name T520
Test name
Test status
Simulation time 12079692434 ps
CPU time 80.13 seconds
Started May 26 12:51:32 PM PDT 24
Finished May 26 12:52:53 PM PDT 24
Peak memory 310272 kb
Host smart-881b0854-9e87-4251-b0c9-4fd1cfc3807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170716254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1170716254
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1261696377
Short name T495
Test name
Test status
Simulation time 27515010 ps
CPU time 0.69 seconds
Started May 26 12:51:13 PM PDT 24
Finished May 26 12:51:14 PM PDT 24
Peak memory 204132 kb
Host smart-da27a8d9-1d45-48fc-b933-befdca9e7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261696377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1261696377
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.696819885
Short name T1009
Test name
Test status
Simulation time 6594448760 ps
CPU time 203.27 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:54:48 PM PDT 24
Peak memory 1586136 kb
Host smart-cc8c27a0-6b32-47b8-9b7f-ebec2f90c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696819885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.696819885
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3092011902
Short name T613
Test name
Test status
Simulation time 8073027324 ps
CPU time 37.29 seconds
Started May 26 12:51:14 PM PDT 24
Finished May 26 12:51:52 PM PDT 24
Peak memory 286528 kb
Host smart-2b3ee7ec-549c-4224-a6ec-4f53374e4cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092011902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3092011902
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2093845016
Short name T120
Test name
Test status
Simulation time 16747783057 ps
CPU time 79.84 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:52:45 PM PDT 24
Peak memory 490568 kb
Host smart-b158c32e-86aa-4b11-9689-745881b6c425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093845016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2093845016
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3301268367
Short name T301
Test name
Test status
Simulation time 574034473 ps
CPU time 24.93 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:51:49 PM PDT 24
Peak memory 212648 kb
Host smart-959c6cbe-330f-44f0-b3a2-69d359c9dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301268367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3301268367
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1042496209
Short name T839
Test name
Test status
Simulation time 4187642262 ps
CPU time 5.17 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:39 PM PDT 24
Peak memory 212664 kb
Host smart-c5b7046c-5a4c-43e0-91cc-31084170e95d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042496209 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1042496209
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.485994109
Short name T449
Test name
Test status
Simulation time 10369941836 ps
CPU time 13.14 seconds
Started May 26 12:51:23 PM PDT 24
Finished May 26 12:51:36 PM PDT 24
Peak memory 248964 kb
Host smart-4a042229-60c1-4076-a022-46c9717c8e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485994109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.485994109
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1863825199
Short name T828
Test name
Test status
Simulation time 10302132990 ps
CPU time 39.06 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 12:52:05 PM PDT 24
Peak memory 451140 kb
Host smart-cfbf8987-f863-4769-b130-acbadcf5b6ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863825199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1863825199
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2113806284
Short name T657
Test name
Test status
Simulation time 1152720772 ps
CPU time 5.36 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:40 PM PDT 24
Peak memory 204404 kb
Host smart-5e3c9b4b-9d74-4937-8add-a9dec496ba3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113806284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2113806284
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3571011825
Short name T1372
Test name
Test status
Simulation time 2075966839 ps
CPU time 1.83 seconds
Started May 26 12:51:32 PM PDT 24
Finished May 26 12:51:35 PM PDT 24
Peak memory 204508 kb
Host smart-c8847577-67ee-4f64-b491-509592e0172b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571011825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3571011825
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.142249137
Short name T942
Test name
Test status
Simulation time 3331111890 ps
CPU time 2.56 seconds
Started May 26 12:51:31 PM PDT 24
Finished May 26 12:51:34 PM PDT 24
Peak memory 204712 kb
Host smart-978e774d-cab9-4365-aeda-ea0813e1fabf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142249137 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.142249137
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2874606625
Short name T165
Test name
Test status
Simulation time 4582866315 ps
CPU time 6.03 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 12:51:31 PM PDT 24
Peak memory 204472 kb
Host smart-61c8daae-659b-4d65-a74b-dbcdf2775e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874606625 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2874606625
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.4087400984
Short name T569
Test name
Test status
Simulation time 10992785163 ps
CPU time 58.24 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:52:22 PM PDT 24
Peak memory 1067752 kb
Host smart-e744f7f0-a67b-468d-b0b1-49a41733da7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087400984 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4087400984
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2103446222
Short name T862
Test name
Test status
Simulation time 3402186081 ps
CPU time 13.31 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 12:51:39 PM PDT 24
Peak memory 204480 kb
Host smart-096b6e09-7798-4ce7-acdb-9b2975d0e740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103446222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2103446222
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.789050051
Short name T585
Test name
Test status
Simulation time 15794265507 ps
CPU time 25.87 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 12:51:51 PM PDT 24
Peak memory 222192 kb
Host smart-db8277bd-06b0-444e-8765-886a19dfe439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789050051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.789050051
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2708401322
Short name T852
Test name
Test status
Simulation time 41408019254 ps
CPU time 680.77 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 01:02:46 PM PDT 24
Peak memory 5457832 kb
Host smart-63f20528-b8cd-4cb4-b133-793e5ac02444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708401322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2708401322
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.4201459124
Short name T887
Test name
Test status
Simulation time 33783150572 ps
CPU time 2426.24 seconds
Started May 26 12:51:25 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 3951876 kb
Host smart-4517edb2-a9df-458c-a658-4adb3d23bbb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201459124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.4201459124
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3633868015
Short name T577
Test name
Test status
Simulation time 12541321652 ps
CPU time 8.13 seconds
Started May 26 12:51:24 PM PDT 24
Finished May 26 12:51:33 PM PDT 24
Peak memory 214300 kb
Host smart-7519a687-fdf2-4893-b0aa-9ec00d3b4805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633868015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3633868015
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1599676209
Short name T1359
Test name
Test status
Simulation time 49819384 ps
CPU time 0.65 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:43 PM PDT 24
Peak memory 204088 kb
Host smart-0b10ba5f-4ec8-4e43-a688-536c42e062fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599676209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1599676209
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2597701217
Short name T184
Test name
Test status
Simulation time 87080993 ps
CPU time 1.6 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:45 PM PDT 24
Peak memory 212720 kb
Host smart-585df485-3f67-484b-a83c-d844ba594073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597701217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2597701217
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.719989079
Short name T968
Test name
Test status
Simulation time 268125311 ps
CPU time 9.64 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:44 PM PDT 24
Peak memory 204424 kb
Host smart-524000f5-a0ea-4770-8232-654decb85fa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719989079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.719989079
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1824171669
Short name T701
Test name
Test status
Simulation time 15549304878 ps
CPU time 102.27 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:53:16 PM PDT 24
Peak memory 825860 kb
Host smart-c8f55679-b0fb-4180-88ca-077edf8bc6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824171669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1824171669
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1478597119
Short name T1247
Test name
Test status
Simulation time 7650845103 ps
CPU time 39.3 seconds
Started May 26 12:51:37 PM PDT 24
Finished May 26 12:52:17 PM PDT 24
Peak memory 431856 kb
Host smart-b540102f-3e2c-43c6-98b2-fafe4bdab1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478597119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1478597119
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3031623818
Short name T882
Test name
Test status
Simulation time 171730165 ps
CPU time 0.91 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:34 PM PDT 24
Peak memory 204212 kb
Host smart-26f98bed-e9b3-4ff8-97ab-e0b8c39d2265
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031623818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3031623818
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2367168548
Short name T180
Test name
Test status
Simulation time 985964172 ps
CPU time 5.91 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:39 PM PDT 24
Peak memory 241160 kb
Host smart-be56ea88-99c8-42c3-b7c6-6cdf28876755
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367168548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2367168548
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.722420953
Short name T1087
Test name
Test status
Simulation time 5465781545 ps
CPU time 182.33 seconds
Started May 26 12:51:31 PM PDT 24
Finished May 26 12:54:34 PM PDT 24
Peak memory 1593628 kb
Host smart-b7eceec3-8b40-4e92-9e23-c1cdc336cf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722420953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.722420953
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.794755016
Short name T1015
Test name
Test status
Simulation time 361345675 ps
CPU time 6.24 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:48 PM PDT 24
Peak memory 204436 kb
Host smart-f3c14c66-e3d7-4ee7-8aa8-a9c43e3412bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794755016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.794755016
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2518361606
Short name T75
Test name
Test status
Simulation time 1654346488 ps
CPU time 81.66 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:53:04 PM PDT 24
Peak memory 334220 kb
Host smart-3e3d644b-e0a7-4e00-85a1-942ea203d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518361606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2518361606
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1702356873
Short name T1319
Test name
Test status
Simulation time 39692260 ps
CPU time 0.67 seconds
Started May 26 12:51:33 PM PDT 24
Finished May 26 12:51:34 PM PDT 24
Peak memory 204136 kb
Host smart-9ebe9228-e940-401e-ab4f-4ec4a18606bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702356873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1702356873
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.4201117667
Short name T772
Test name
Test status
Simulation time 7223232192 ps
CPU time 97.01 seconds
Started May 26 12:51:32 PM PDT 24
Finished May 26 12:53:10 PM PDT 24
Peak memory 215120 kb
Host smart-0f10de28-73aa-41bb-958d-974128ce7a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201117667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4201117667
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.881418127
Short name T60
Test name
Test status
Simulation time 7357386398 ps
CPU time 37.36 seconds
Started May 26 12:51:31 PM PDT 24
Finished May 26 12:52:09 PM PDT 24
Peak memory 405000 kb
Host smart-48313ccd-5a1b-43cf-8d49-4d5194f2ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881418127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.881418127
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2608545228
Short name T924
Test name
Test status
Simulation time 69738782078 ps
CPU time 1714.48 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 01:20:17 PM PDT 24
Peak memory 1889304 kb
Host smart-d9dc944f-aca6-4190-9e92-68646d6a68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608545228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2608545228
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.467456802
Short name T130
Test name
Test status
Simulation time 3442329269 ps
CPU time 20.28 seconds
Started May 26 12:51:32 PM PDT 24
Finished May 26 12:51:53 PM PDT 24
Peak memory 212780 kb
Host smart-eb633033-2388-4f21-b7a8-404d28ae1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467456802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.467456802
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.525838464
Short name T126
Test name
Test status
Simulation time 3058052724 ps
CPU time 4.7 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:48 PM PDT 24
Peak memory 204476 kb
Host smart-5d8277c4-7961-4e0a-befc-a4cebace0e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525838464 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.525838464
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2148112153
Short name T753
Test name
Test status
Simulation time 10150780296 ps
CPU time 44.84 seconds
Started May 26 12:51:40 PM PDT 24
Finished May 26 12:52:26 PM PDT 24
Peak memory 387044 kb
Host smart-27927063-162f-497f-a7e6-85d50ce0bbe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148112153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2148112153
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3086927896
Short name T608
Test name
Test status
Simulation time 10568268359 ps
CPU time 24.72 seconds
Started May 26 12:51:40 PM PDT 24
Finished May 26 12:52:06 PM PDT 24
Peak memory 432796 kb
Host smart-20c88cc3-8e2a-4dec-89aa-72b4dd39a04c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086927896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3086927896
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.3500517486
Short name T948
Test name
Test status
Simulation time 1438227756 ps
CPU time 3.24 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:46 PM PDT 24
Peak memory 204552 kb
Host smart-76c2584a-893d-4270-bd8a-948eaa09590d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500517486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.3500517486
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.716729176
Short name T357
Test name
Test status
Simulation time 1146662744 ps
CPU time 1.94 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:44 PM PDT 24
Peak memory 204476 kb
Host smart-3954c371-33a8-4e49-a12f-b97ad079eb81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716729176 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.716729176
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2036347540
Short name T21
Test name
Test status
Simulation time 448850858 ps
CPU time 2.78 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:46 PM PDT 24
Peak memory 204644 kb
Host smart-19169b85-8ef6-4405-b88c-9e8fa68e6cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036347540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2036347540
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3002310130
Short name T371
Test name
Test status
Simulation time 4913844454 ps
CPU time 6.3 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:48 PM PDT 24
Peak memory 214612 kb
Host smart-19b2998a-dbd0-4ae1-ac55-bd8171779653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002310130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3002310130
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.983855495
Short name T622
Test name
Test status
Simulation time 4035429047 ps
CPU time 14.68 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:57 PM PDT 24
Peak memory 627028 kb
Host smart-ec7f4769-e5d3-4444-b6c1-09fd58f42331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983855495 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.983855495
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3471602501
Short name T549
Test name
Test status
Simulation time 947125458 ps
CPU time 15.95 seconds
Started May 26 12:51:50 PM PDT 24
Finished May 26 12:52:07 PM PDT 24
Peak memory 204476 kb
Host smart-114bee21-0092-4069-8cdc-699f902783d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471602501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3471602501
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1914825696
Short name T1162
Test name
Test status
Simulation time 402137691 ps
CPU time 16.96 seconds
Started May 26 12:51:43 PM PDT 24
Finished May 26 12:52:00 PM PDT 24
Peak memory 204480 kb
Host smart-05822ee6-5ad0-4ce2-a6d0-aed8bd30287e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914825696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1914825696
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.858223176
Short name T250
Test name
Test status
Simulation time 29467606933 ps
CPU time 7.57 seconds
Started May 26 12:51:42 PM PDT 24
Finished May 26 12:51:50 PM PDT 24
Peak memory 204496 kb
Host smart-3fa80fb0-2f1d-41c6-a16c-e772f43470c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858223176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.858223176
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1196406903
Short name T269
Test name
Test status
Simulation time 4091758712 ps
CPU time 6.67 seconds
Started May 26 12:51:41 PM PDT 24
Finished May 26 12:51:48 PM PDT 24
Peak memory 217504 kb
Host smart-cdf738d3-de13-4df4-93d0-e4dfefd24593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196406903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1196406903
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.631024134
Short name T170
Test name
Test status
Simulation time 16060552 ps
CPU time 0.64 seconds
Started May 26 12:42:12 PM PDT 24
Finished May 26 12:42:13 PM PDT 24
Peak memory 204072 kb
Host smart-c1884e7d-7122-45f6-bec0-8da702d1a329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631024134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.631024134
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2660114291
Short name T53
Test name
Test status
Simulation time 924583131 ps
CPU time 2.14 seconds
Started May 26 12:42:15 PM PDT 24
Finished May 26 12:42:18 PM PDT 24
Peak memory 212756 kb
Host smart-38c00298-f6ff-4a7f-ab3e-bb1b7d285f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660114291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2660114291
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.261265026
Short name T421
Test name
Test status
Simulation time 378733443 ps
CPU time 20.08 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:42:26 PM PDT 24
Peak memory 282580 kb
Host smart-6296e442-802f-462f-861d-d5a4de80b248
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261265026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.261265026
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.536312301
Short name T1108
Test name
Test status
Simulation time 9274962773 ps
CPU time 72.87 seconds
Started May 26 12:42:06 PM PDT 24
Finished May 26 12:43:19 PM PDT 24
Peak memory 655632 kb
Host smart-6c8cc779-a862-419d-b087-f1dd9a40f4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536312301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.536312301
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3877298790
Short name T633
Test name
Test status
Simulation time 2950072606 ps
CPU time 112.57 seconds
Started May 26 12:42:06 PM PDT 24
Finished May 26 12:43:59 PM PDT 24
Peak memory 579092 kb
Host smart-ddad363a-0df1-4a9c-a530-793857aed219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877298790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3877298790
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1467055585
Short name T832
Test name
Test status
Simulation time 97123553 ps
CPU time 0.92 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:42:06 PM PDT 24
Peak memory 204240 kb
Host smart-d7fb1887-0491-4be3-a163-5378c5dd57d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467055585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1467055585
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1567039824
Short name T156
Test name
Test status
Simulation time 716253392 ps
CPU time 4.47 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:42:10 PM PDT 24
Peak memory 204520 kb
Host smart-4ac60e1f-a085-41ca-a964-3050699c6adc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567039824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1567039824
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.249200600
Short name T767
Test name
Test status
Simulation time 3946808792 ps
CPU time 104.96 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:43:51 PM PDT 24
Peak memory 1164140 kb
Host smart-164a4069-0de6-49f8-a697-41491158964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249200600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.249200600
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2055309799
Short name T512
Test name
Test status
Simulation time 4777552813 ps
CPU time 6.13 seconds
Started May 26 12:42:12 PM PDT 24
Finished May 26 12:42:19 PM PDT 24
Peak memory 204456 kb
Host smart-f7b26f7b-0149-4658-97fe-050f02ae49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055309799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2055309799
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.652867267
Short name T1217
Test name
Test status
Simulation time 1535885689 ps
CPU time 31.8 seconds
Started May 26 12:42:16 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 359400 kb
Host smart-693b8452-cc52-4012-98f5-c929c57d2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652867267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.652867267
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.4068379142
Short name T1234
Test name
Test status
Simulation time 24989116 ps
CPU time 0.68 seconds
Started May 26 12:42:08 PM PDT 24
Finished May 26 12:42:09 PM PDT 24
Peak memory 204096 kb
Host smart-1f8440dc-07bd-4c1e-8594-0366edd1027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068379142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.4068379142
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.211570366
Short name T225
Test name
Test status
Simulation time 75880491751 ps
CPU time 1507.57 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 01:07:22 PM PDT 24
Peak memory 204520 kb
Host smart-8fc02101-764d-4f4e-813f-d28e5e0bd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211570366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.211570366
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.825887933
Short name T762
Test name
Test status
Simulation time 3542967389 ps
CPU time 89.12 seconds
Started May 26 12:42:05 PM PDT 24
Finished May 26 12:43:35 PM PDT 24
Peak memory 368052 kb
Host smart-b2980948-79cf-4873-ac6e-005d5b6f7ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825887933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.825887933
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.1441292317
Short name T1425
Test name
Test status
Simulation time 97175953298 ps
CPU time 2741.08 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 01:27:57 PM PDT 24
Peak memory 3632392 kb
Host smart-b01a3779-5b17-45d2-926c-8a6d02faf817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441292317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1441292317
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3355821113
Short name T1132
Test name
Test status
Simulation time 1608954697 ps
CPU time 6.04 seconds
Started May 26 12:42:16 PM PDT 24
Finished May 26 12:42:23 PM PDT 24
Peak memory 212620 kb
Host smart-f58b3050-9b3b-464e-ac77-daaa6b58db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355821113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3355821113
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1153284514
Short name T851
Test name
Test status
Simulation time 2781054477 ps
CPU time 3.88 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 12:42:18 PM PDT 24
Peak memory 212772 kb
Host smart-ec52171e-53ad-47fb-9521-b67d184b59d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153284514 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1153284514
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2831843176
Short name T1242
Test name
Test status
Simulation time 10128270580 ps
CPU time 44.76 seconds
Started May 26 12:42:17 PM PDT 24
Finished May 26 12:43:03 PM PDT 24
Peak memory 302096 kb
Host smart-1b73dd50-b3fb-4c9d-853e-6e3a38a69b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831843176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2831843176
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.4047544504
Short name T797
Test name
Test status
Simulation time 10134683062 ps
CPU time 71.28 seconds
Started May 26 12:42:18 PM PDT 24
Finished May 26 12:43:30 PM PDT 24
Peak memory 678952 kb
Host smart-548e3c36-b10a-4c69-a00b-8a9cacc3027e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047544504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.4047544504
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3521160112
Short name T1089
Test name
Test status
Simulation time 1056305750 ps
CPU time 5.44 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 12:42:19 PM PDT 24
Peak memory 204436 kb
Host smart-3998725c-b285-42e2-a471-b4a069d4a084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521160112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3521160112
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2775767886
Short name T999
Test name
Test status
Simulation time 1466017010 ps
CPU time 1.42 seconds
Started May 26 12:42:15 PM PDT 24
Finished May 26 12:42:17 PM PDT 24
Peak memory 204420 kb
Host smart-35cc2de8-35c3-499e-b9cd-e15b0b51e3c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775767886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2775767886
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3218464822
Short name T1169
Test name
Test status
Simulation time 372461530 ps
CPU time 2.66 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 12:42:17 PM PDT 24
Peak memory 204516 kb
Host smart-0edca8fc-f090-4314-996d-f101066c1d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218464822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3218464822
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.333833792
Short name T502
Test name
Test status
Simulation time 9737198849 ps
CPU time 5.19 seconds
Started May 26 12:42:18 PM PDT 24
Finished May 26 12:42:24 PM PDT 24
Peak memory 204516 kb
Host smart-f2389cd8-3979-4a9d-a255-e119758143fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333833792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.333833792
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2471554441
Short name T943
Test name
Test status
Simulation time 16166163315 ps
CPU time 117.17 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 12:44:12 PM PDT 24
Peak memory 2061568 kb
Host smart-2be0f183-d3e9-463a-b9e5-df3b1a7ea4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471554441 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2471554441
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1901517813
Short name T543
Test name
Test status
Simulation time 1471023255 ps
CPU time 47.01 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 12:43:01 PM PDT 24
Peak memory 204420 kb
Host smart-6dd8f60e-c684-4976-a790-a9a7e8f037d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901517813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1901517813
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3203401174
Short name T542
Test name
Test status
Simulation time 3315050809 ps
CPU time 30.88 seconds
Started May 26 12:42:17 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 221276 kb
Host smart-948982df-f597-45c8-b125-f423d0d15f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203401174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3203401174
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.372850613
Short name T429
Test name
Test status
Simulation time 71659961121 ps
CPU time 2793.41 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 01:28:48 PM PDT 24
Peak memory 12988020 kb
Host smart-f40ba0d7-1085-47bf-9f3e-b609e45b0ff5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372850613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.372850613
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.538440217
Short name T428
Test name
Test status
Simulation time 17936100678 ps
CPU time 918.6 seconds
Started May 26 12:42:13 PM PDT 24
Finished May 26 12:57:32 PM PDT 24
Peak memory 3837612 kb
Host smart-b4a1652c-3e2e-48e1-b247-1576f7c06974
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538440217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ta
rget_stretch.538440217
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2328852952
Short name T1308
Test name
Test status
Simulation time 2440250836 ps
CPU time 7.37 seconds
Started May 26 12:42:15 PM PDT 24
Finished May 26 12:42:24 PM PDT 24
Peak memory 220140 kb
Host smart-690a54f7-1fbd-4d92-b7d2-ad50282bca43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328852952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2328852952
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2295968562
Short name T557
Test name
Test status
Simulation time 41421997 ps
CPU time 0.61 seconds
Started May 26 12:42:29 PM PDT 24
Finished May 26 12:42:30 PM PDT 24
Peak memory 204172 kb
Host smart-2f2036e3-dd91-437b-89b2-5bde3c50a9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295968562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2295968562
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3136170117
Short name T354
Test name
Test status
Simulation time 591219380 ps
CPU time 2.59 seconds
Started May 26 12:42:23 PM PDT 24
Finished May 26 12:42:26 PM PDT 24
Peak memory 228952 kb
Host smart-eae90c7a-84b6-44aa-99ce-9357db3a40c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136170117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3136170117
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3924328253
Short name T687
Test name
Test status
Simulation time 311453820 ps
CPU time 5.66 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:42:29 PM PDT 24
Peak memory 253020 kb
Host smart-3eb45153-3be9-4d8c-b717-893d312e62db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924328253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3924328253
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3545451574
Short name T627
Test name
Test status
Simulation time 5662840549 ps
CPU time 215.53 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:45:59 PM PDT 24
Peak memory 851444 kb
Host smart-cd102fe1-3676-4085-83fa-748bf4fc665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545451574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3545451574
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1081608914
Short name T932
Test name
Test status
Simulation time 7381334822 ps
CPU time 141.64 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 12:44:36 PM PDT 24
Peak memory 644180 kb
Host smart-e4298367-6526-4b70-9fe7-71de83193fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081608914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1081608914
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3385149277
Short name T915
Test name
Test status
Simulation time 380551617 ps
CPU time 0.96 seconds
Started May 26 12:42:17 PM PDT 24
Finished May 26 12:42:18 PM PDT 24
Peak memory 204172 kb
Host smart-91009af9-a9b1-41e2-ac27-8d02296f93c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385149277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3385149277
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.4243590844
Short name T73
Test name
Test status
Simulation time 582034046 ps
CPU time 8.1 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:42:31 PM PDT 24
Peak memory 204408 kb
Host smart-387e7569-cc9f-480c-9c6c-aad95ddd7851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243590844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
4243590844
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2875610265
Short name T291
Test name
Test status
Simulation time 15548154544 ps
CPU time 285.12 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 12:47:00 PM PDT 24
Peak memory 1131900 kb
Host smart-1a4963ae-97d6-43de-8bfe-8346a6b25307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875610265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2875610265
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3400511082
Short name T439
Test name
Test status
Simulation time 606519968 ps
CPU time 25.33 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 12:42:51 PM PDT 24
Peak memory 204564 kb
Host smart-5f0f4f51-a767-42c3-97dd-64a988cfe05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400511082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3400511082
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.820089165
Short name T1282
Test name
Test status
Simulation time 13271390792 ps
CPU time 30.93 seconds
Started May 26 12:42:24 PM PDT 24
Finished May 26 12:42:56 PM PDT 24
Peak memory 300456 kb
Host smart-5360d4d9-7f60-4d22-9a6c-8b9a84b7f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820089165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.820089165
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.970968866
Short name T540
Test name
Test status
Simulation time 46991023 ps
CPU time 0.65 seconds
Started May 26 12:42:14 PM PDT 24
Finished May 26 12:42:16 PM PDT 24
Peak memory 204160 kb
Host smart-729f2d5d-3060-400f-b7cd-092e88b1fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970968866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.970968866
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.694282890
Short name T187
Test name
Test status
Simulation time 4783803283 ps
CPU time 89.39 seconds
Started May 26 12:42:23 PM PDT 24
Finished May 26 12:43:53 PM PDT 24
Peak memory 734060 kb
Host smart-b86cbef7-723b-4261-9e2d-58c1a3e8982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694282890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.694282890
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.681098522
Short name T426
Test name
Test status
Simulation time 2896130543 ps
CPU time 31.83 seconds
Started May 26 12:42:15 PM PDT 24
Finished May 26 12:42:47 PM PDT 24
Peak memory 382108 kb
Host smart-d41ebd43-eb9a-4378-b8aa-a4ed23d13021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681098522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.681098522
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1208474478
Short name T263
Test name
Test status
Simulation time 60893446492 ps
CPU time 229.1 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:46:12 PM PDT 24
Peak memory 1523200 kb
Host smart-3898e4a7-7c1e-4339-b938-0b64de26663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208474478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1208474478
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2994040567
Short name T1138
Test name
Test status
Simulation time 899476073 ps
CPU time 14.9 seconds
Started May 26 12:42:21 PM PDT 24
Finished May 26 12:42:37 PM PDT 24
Peak memory 220868 kb
Host smart-349a7e97-9981-45ae-86c2-e13d69e6e411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994040567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2994040567
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.874442283
Short name T719
Test name
Test status
Simulation time 656534905 ps
CPU time 3.7 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 12:42:29 PM PDT 24
Peak memory 204408 kb
Host smart-393e9310-a1f7-4e93-a432-f2d8f324f614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874442283 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.874442283
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1298163499
Short name T1224
Test name
Test status
Simulation time 10137943335 ps
CPU time 24.17 seconds
Started May 26 12:42:26 PM PDT 24
Finished May 26 12:42:50 PM PDT 24
Peak memory 283620 kb
Host smart-8c1c66cf-8801-4136-afbb-01a03df16d68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298163499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1298163499
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.566830970
Short name T91
Test name
Test status
Simulation time 10084893380 ps
CPU time 73.09 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 12:43:39 PM PDT 24
Peak memory 535880 kb
Host smart-ef14b310-4271-4d94-9197-4c8c85fa2603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566830970 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.566830970
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.571120826
Short name T1193
Test name
Test status
Simulation time 1146780481 ps
CPU time 5.61 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:42:39 PM PDT 24
Peak memory 204732 kb
Host smart-66faf546-a94f-4f4e-8af8-dc4bb9c83616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571120826 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.571120826
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.1220019708
Short name T929
Test name
Test status
Simulation time 1073891838 ps
CPU time 1.85 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:42:33 PM PDT 24
Peak memory 204580 kb
Host smart-89dac46c-a1f0-4dca-a741-de33abe111d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220019708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.1220019708
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3770154869
Short name T332
Test name
Test status
Simulation time 473725232 ps
CPU time 2.73 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 12:42:29 PM PDT 24
Peak memory 204492 kb
Host smart-4a867fc6-e968-4efe-8ba7-edc5fad282bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770154869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3770154869
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2901757963
Short name T675
Test name
Test status
Simulation time 4971030273 ps
CPU time 6.67 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 12:42:32 PM PDT 24
Peak memory 218696 kb
Host smart-7b8e7706-2c9b-4682-bd8b-e295471512c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901757963 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2901757963
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.334124320
Short name T7
Test name
Test status
Simulation time 4960815307 ps
CPU time 51.43 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:43:14 PM PDT 24
Peak memory 1345456 kb
Host smart-b2759f11-d573-4307-8106-d9c56b310ec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334124320 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.334124320
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1904020432
Short name T1069
Test name
Test status
Simulation time 685205311 ps
CPU time 24.09 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:42:47 PM PDT 24
Peak memory 204456 kb
Host smart-adb8b64a-b7aa-4ee5-9d7f-69a9e38bc9f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904020432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1904020432
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2224077577
Short name T1402
Test name
Test status
Simulation time 1742715900 ps
CPU time 42.98 seconds
Started May 26 12:42:21 PM PDT 24
Finished May 26 12:43:04 PM PDT 24
Peak memory 204516 kb
Host smart-bb607aae-3941-4f60-94a2-760e54a370a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224077577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2224077577
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3367000384
Short name T427
Test name
Test status
Simulation time 7853232487 ps
CPU time 14.39 seconds
Started May 26 12:42:24 PM PDT 24
Finished May 26 12:42:40 PM PDT 24
Peak memory 204656 kb
Host smart-6a804a48-0a42-4c10-8eb0-df43c5c40bd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367000384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3367000384
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.889625257
Short name T246
Test name
Test status
Simulation time 21893344832 ps
CPU time 1178.31 seconds
Started May 26 12:42:25 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 2646192 kb
Host smart-b10e8c42-f396-4b6b-bbf7-7819d42a5744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889625257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.889625257
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1378589459
Short name T738
Test name
Test status
Simulation time 4102636275 ps
CPU time 6.6 seconds
Started May 26 12:42:22 PM PDT 24
Finished May 26 12:42:29 PM PDT 24
Peak memory 220844 kb
Host smart-23303e29-a939-4f6c-862b-363ab542f9ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378589459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1378589459
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1089188428
Short name T556
Test name
Test status
Simulation time 47576870 ps
CPU time 0.63 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:42:41 PM PDT 24
Peak memory 204132 kb
Host smart-9890e971-0a14-4402-a9f6-20cbab0efb60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089188428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1089188428
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2674151283
Short name T854
Test name
Test status
Simulation time 129678098 ps
CPU time 3.03 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:42:35 PM PDT 24
Peak memory 212696 kb
Host smart-66d807ce-8535-4f9c-8451-08a56ffcdfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674151283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2674151283
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2409647011
Short name T1094
Test name
Test status
Simulation time 440100721 ps
CPU time 10.47 seconds
Started May 26 12:42:30 PM PDT 24
Finished May 26 12:42:41 PM PDT 24
Peak memory 291964 kb
Host smart-eb2b297d-a60a-4780-bc18-9199d51a1f1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409647011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2409647011
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1010655849
Short name T620
Test name
Test status
Simulation time 1589507327 ps
CPU time 106.48 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:44:19 PM PDT 24
Peak memory 589016 kb
Host smart-72c3ad36-9d5b-4d5b-bf37-6027a67ab381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010655849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1010655849
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.4151751471
Short name T723
Test name
Test status
Simulation time 2682884310 ps
CPU time 206.69 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:45:58 PM PDT 24
Peak memory 814792 kb
Host smart-b27f2879-e3c0-4240-b508-96ffa580a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151751471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.4151751471
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2276584218
Short name T167
Test name
Test status
Simulation time 81029376 ps
CPU time 0.96 seconds
Started May 26 12:42:30 PM PDT 24
Finished May 26 12:42:32 PM PDT 24
Peak memory 204244 kb
Host smart-56a0080a-82b7-47f6-980f-dbc282dfab8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276584218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2276584218
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2406260447
Short name T729
Test name
Test status
Simulation time 174751894 ps
CPU time 4.77 seconds
Started May 26 12:42:29 PM PDT 24
Finished May 26 12:42:35 PM PDT 24
Peak memory 236208 kb
Host smart-0fb29055-98ea-41a0-b9b1-ba6a3a05c589
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406260447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2406260447
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1691229761
Short name T260
Test name
Test status
Simulation time 24128435688 ps
CPU time 241.94 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:46:34 PM PDT 24
Peak memory 1043820 kb
Host smart-97108667-838d-46c0-9fdb-6f71e1cc59b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691229761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1691229761
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1808374521
Short name T792
Test name
Test status
Simulation time 463144032 ps
CPU time 9.58 seconds
Started May 26 12:42:42 PM PDT 24
Finished May 26 12:42:52 PM PDT 24
Peak memory 204436 kb
Host smart-f1b08ecf-0ce2-4410-9b08-d4e60140e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808374521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1808374521
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2814245739
Short name T966
Test name
Test status
Simulation time 2086877148 ps
CPU time 40.01 seconds
Started May 26 12:42:40 PM PDT 24
Finished May 26 12:43:21 PM PDT 24
Peak memory 357100 kb
Host smart-95ffc434-1f5a-4c35-bca0-6631b57f7518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814245739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2814245739
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.884698668
Short name T142
Test name
Test status
Simulation time 91769377 ps
CPU time 0.71 seconds
Started May 26 12:42:33 PM PDT 24
Finished May 26 12:42:34 PM PDT 24
Peak memory 203820 kb
Host smart-d1ec4f6c-63cb-4b61-ac1f-9e3efc7f4a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884698668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.884698668
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2691116471
Short name T387
Test name
Test status
Simulation time 51127620167 ps
CPU time 423.04 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:49:35 PM PDT 24
Peak memory 2080580 kb
Host smart-f63c87df-37d9-45b9-99ab-8abbb1ce8386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691116471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2691116471
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2061657543
Short name T484
Test name
Test status
Simulation time 16753513102 ps
CPU time 30.01 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:43:03 PM PDT 24
Peak memory 357264 kb
Host smart-39fa7b54-4aa2-4182-b483-c565e1886ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061657543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2061657543
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1037191001
Short name T1200
Test name
Test status
Simulation time 10852195374 ps
CPU time 19.16 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:42:52 PM PDT 24
Peak memory 220988 kb
Host smart-42937ffd-0e95-46f7-b913-591cec72ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037191001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1037191001
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3308699797
Short name T1316
Test name
Test status
Simulation time 3782528053 ps
CPU time 4.69 seconds
Started May 26 12:42:41 PM PDT 24
Finished May 26 12:42:47 PM PDT 24
Peak memory 212748 kb
Host smart-780b3ea8-719e-4714-9866-d2aeb41479f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308699797 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3308699797
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2935124368
Short name T1332
Test name
Test status
Simulation time 10222566311 ps
CPU time 23.63 seconds
Started May 26 12:42:41 PM PDT 24
Finished May 26 12:43:06 PM PDT 24
Peak memory 278392 kb
Host smart-b48df03d-cc9f-4042-aee3-5418d0aa9817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935124368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2935124368
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.881936864
Short name T158
Test name
Test status
Simulation time 10416601858 ps
CPU time 18.89 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:42:59 PM PDT 24
Peak memory 326836 kb
Host smart-85a85ae8-95c5-4d9a-ab1f-b2b9aba9a9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881936864 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.881936864
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.783257563
Short name T1022
Test name
Test status
Simulation time 1274324704 ps
CPU time 6.12 seconds
Started May 26 12:42:41 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 204516 kb
Host smart-89e15d3b-665a-476c-99e7-6b9a1bf44d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783257563 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.783257563
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.2029212168
Short name T1382
Test name
Test status
Simulation time 1068701404 ps
CPU time 6.22 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:42:47 PM PDT 24
Peak memory 204420 kb
Host smart-b69c931a-4d04-4ea0-8148-81da7f9175e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029212168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2029212168
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.197933816
Short name T1160
Test name
Test status
Simulation time 1890613437 ps
CPU time 2.84 seconds
Started May 26 12:42:40 PM PDT 24
Finished May 26 12:42:44 PM PDT 24
Peak memory 204508 kb
Host smart-e51609ee-0539-48e7-b2d3-fc868536c2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197933816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.197933816
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1425251727
Short name T1124
Test name
Test status
Simulation time 1223213076 ps
CPU time 6.61 seconds
Started May 26 12:42:30 PM PDT 24
Finished May 26 12:42:37 PM PDT 24
Peak memory 218732 kb
Host smart-2ca786c0-a9d8-4120-a41b-ec6faa72cf21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425251727 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1425251727
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3570778323
Short name T418
Test name
Test status
Simulation time 10564849868 ps
CPU time 8.8 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:42:41 PM PDT 24
Peak memory 268728 kb
Host smart-2b23ef3b-8ba0-4af7-9f6a-9fadc1e3532b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570778323 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3570778323
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.4186070547
Short name T927
Test name
Test status
Simulation time 9947628809 ps
CPU time 28.33 seconds
Started May 26 12:42:32 PM PDT 24
Finished May 26 12:43:01 PM PDT 24
Peak memory 204508 kb
Host smart-bd9dea2f-43af-4b2a-a4cb-4582a36c74aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186070547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.4186070547
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3385948343
Short name T1235
Test name
Test status
Simulation time 404618035 ps
CPU time 7.37 seconds
Started May 26 12:42:31 PM PDT 24
Finished May 26 12:42:39 PM PDT 24
Peak memory 204520 kb
Host smart-54412f75-4d16-4d91-8361-6d5e771151c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385948343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3385948343
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3879962523
Short name T488
Test name
Test status
Simulation time 43025985377 ps
CPU time 98.7 seconds
Started May 26 12:42:30 PM PDT 24
Finished May 26 12:44:09 PM PDT 24
Peak memory 1455352 kb
Host smart-996d0c27-46ff-4f36-aa06-7fd4da926c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879962523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3879962523
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3834113072
Short name T764
Test name
Test status
Simulation time 11543300347 ps
CPU time 54.57 seconds
Started May 26 12:42:33 PM PDT 24
Finished May 26 12:43:28 PM PDT 24
Peak memory 837176 kb
Host smart-16e857c2-8159-4f2a-bed1-4e5fb6dbaf78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834113072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3834113072
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2183909775
Short name T386
Test name
Test status
Simulation time 5300125778 ps
CPU time 7.22 seconds
Started May 26 12:42:41 PM PDT 24
Finished May 26 12:42:49 PM PDT 24
Peak memory 204536 kb
Host smart-8c9a4e97-7fb8-49f8-ac53-325ae169eb2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183909775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2183909775
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.4211175068
Short name T541
Test name
Test status
Simulation time 68514218 ps
CPU time 0.61 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:42:49 PM PDT 24
Peak memory 204092 kb
Host smart-0e5cacf4-a79c-4ad5-93a8-ee352a19914e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211175068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.4211175068
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.503835271
Short name T1417
Test name
Test status
Simulation time 396122903 ps
CPU time 3.15 seconds
Started May 26 12:42:49 PM PDT 24
Finished May 26 12:42:53 PM PDT 24
Peak memory 212692 kb
Host smart-58c78e91-8647-4f61-a5f4-15ded777f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503835271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.503835271
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3467441966
Short name T284
Test name
Test status
Simulation time 344772917 ps
CPU time 17.6 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:42:58 PM PDT 24
Peak memory 276836 kb
Host smart-b9289628-1003-4b42-b949-8d320d602cf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467441966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3467441966
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3750036445
Short name T824
Test name
Test status
Simulation time 10896836474 ps
CPU time 177.33 seconds
Started May 26 12:42:42 PM PDT 24
Finished May 26 12:45:40 PM PDT 24
Peak memory 682328 kb
Host smart-baf0cf68-1269-4290-86c1-4a3b42de1f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750036445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3750036445
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2567909361
Short name T487
Test name
Test status
Simulation time 1486965620 ps
CPU time 42.62 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:43:23 PM PDT 24
Peak memory 522292 kb
Host smart-3886e123-51da-4558-ad97-579edfdc9bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567909361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2567909361
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1299196953
Short name T1363
Test name
Test status
Simulation time 310086468 ps
CPU time 0.92 seconds
Started May 26 12:42:40 PM PDT 24
Finished May 26 12:42:42 PM PDT 24
Peak memory 204228 kb
Host smart-3eb17c84-ddeb-4e0e-80c6-001093abc70e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299196953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1299196953
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2076772103
Short name T469
Test name
Test status
Simulation time 502876788 ps
CPU time 7.09 seconds
Started May 26 12:42:40 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 256768 kb
Host smart-8233da19-e90a-4275-b71f-71f2476b2481
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076772103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2076772103
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3642006991
Short name T913
Test name
Test status
Simulation time 4511823031 ps
CPU time 342.74 seconds
Started May 26 12:42:43 PM PDT 24
Finished May 26 12:48:26 PM PDT 24
Peak memory 1301896 kb
Host smart-9390e62e-4417-4920-a57b-2890ffeea542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642006991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3642006991
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.506135403
Short name T834
Test name
Test status
Simulation time 3988459150 ps
CPU time 6.78 seconds
Started May 26 12:42:46 PM PDT 24
Finished May 26 12:42:54 PM PDT 24
Peak memory 204536 kb
Host smart-4b6bab3d-e5a7-43fc-a223-63765326e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506135403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.506135403
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3525339705
Short name T958
Test name
Test status
Simulation time 1700320722 ps
CPU time 39.7 seconds
Started May 26 12:42:49 PM PDT 24
Finished May 26 12:43:29 PM PDT 24
Peak memory 436408 kb
Host smart-43a80c43-5fc9-43bb-9fa4-c5c77e83519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525339705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3525339705
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2909378010
Short name T1180
Test name
Test status
Simulation time 40558674 ps
CPU time 0.62 seconds
Started May 26 12:42:39 PM PDT 24
Finished May 26 12:42:41 PM PDT 24
Peak memory 204236 kb
Host smart-1a5f8989-965e-4612-b799-5f33e4d706cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909378010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2909378010
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.249912203
Short name T789
Test name
Test status
Simulation time 1660692387 ps
CPU time 9.13 seconds
Started May 26 12:42:38 PM PDT 24
Finished May 26 12:42:48 PM PDT 24
Peak memory 239884 kb
Host smart-b039a80e-ea45-4c2c-bfbc-2684a7a2935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249912203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.249912203
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1129535161
Short name T708
Test name
Test status
Simulation time 2110856842 ps
CPU time 40.87 seconds
Started May 26 12:42:40 PM PDT 24
Finished May 26 12:43:22 PM PDT 24
Peak memory 364980 kb
Host smart-e6ea64b3-531e-4638-9d71-56042b87ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129535161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1129535161
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1412718439
Short name T1149
Test name
Test status
Simulation time 77757210128 ps
CPU time 1587.71 seconds
Started May 26 12:42:46 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 4234612 kb
Host smart-1b366569-7ce8-4fd6-b0aa-39a198ab931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412718439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1412718439
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.905320761
Short name T261
Test name
Test status
Simulation time 1539673214 ps
CPU time 33.79 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:43:22 PM PDT 24
Peak memory 212668 kb
Host smart-bd50d81f-69d5-4fb9-ae90-0fbda8e49dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905320761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.905320761
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3196487072
Short name T952
Test name
Test status
Simulation time 3207007326 ps
CPU time 4.16 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:42:53 PM PDT 24
Peak memory 204552 kb
Host smart-c8a12e47-38d0-4690-8b5f-cec89f110ad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196487072 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3196487072
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.175600150
Short name T693
Test name
Test status
Simulation time 10398329976 ps
CPU time 18.98 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:43:08 PM PDT 24
Peak memory 358692 kb
Host smart-12dce993-d9c4-477d-9faa-1f1d5ba1e665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175600150 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.175600150
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2477213522
Short name T311
Test name
Test status
Simulation time 1468356511 ps
CPU time 1.9 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:42:49 PM PDT 24
Peak memory 204384 kb
Host smart-cf8f1218-3543-4667-b45b-48a7bd81c720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477213522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2477213522
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3608816946
Short name T610
Test name
Test status
Simulation time 1054228875 ps
CPU time 5.74 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:42:55 PM PDT 24
Peak memory 204472 kb
Host smart-96bafe95-7d49-44bb-b83f-794b4f216dfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608816946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3608816946
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3218157055
Short name T869
Test name
Test status
Simulation time 1567749140 ps
CPU time 2.39 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:42:50 PM PDT 24
Peak memory 204504 kb
Host smart-ba1b4e58-aa1e-44d7-9886-3b7fb76a0127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218157055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3218157055
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2213571531
Short name T1328
Test name
Test status
Simulation time 971057826 ps
CPU time 6.14 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:42:54 PM PDT 24
Peak memory 217928 kb
Host smart-a2d9dbf6-5014-4eab-a055-f6fb32ae0b53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213571531 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2213571531
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.754434177
Short name T356
Test name
Test status
Simulation time 9590353532 ps
CPU time 7.41 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:42:55 PM PDT 24
Peak memory 212048 kb
Host smart-e9a03c73-a9b5-45c2-96ed-ade2a6eda4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754434177 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.754434177
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2892520994
Short name T1232
Test name
Test status
Simulation time 1158772168 ps
CPU time 32.51 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:43:20 PM PDT 24
Peak memory 204520 kb
Host smart-63282cf7-56e6-49ab-831f-4a10c1b72988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892520994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2892520994
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2561577261
Short name T1216
Test name
Test status
Simulation time 4526113911 ps
CPU time 30.53 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:43:19 PM PDT 24
Peak memory 230552 kb
Host smart-545cf97e-5ef2-4b88-ba2d-61a3d70d3ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561577261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2561577261
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2741481275
Short name T1096
Test name
Test status
Simulation time 54370360661 ps
CPU time 1415.86 seconds
Started May 26 12:42:49 PM PDT 24
Finished May 26 01:06:26 PM PDT 24
Peak memory 8570244 kb
Host smart-6e16d44d-5f7e-4414-91fd-da22136676bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741481275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2741481275
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1099856570
Short name T1183
Test name
Test status
Simulation time 10392575482 ps
CPU time 29.6 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:43:18 PM PDT 24
Peak memory 476504 kb
Host smart-e8d72844-9c18-47f5-a5c7-8c83a74b0bfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099856570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1099856570
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2016100448
Short name T1076
Test name
Test status
Simulation time 1366051801 ps
CPU time 7.65 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:42:56 PM PDT 24
Peak memory 217672 kb
Host smart-126954e0-c646-4585-8950-fb578e6152e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016100448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2016100448
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.752853253
Short name T1066
Test name
Test status
Simulation time 21587107 ps
CPU time 0.62 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:06 PM PDT 24
Peak memory 204100 kb
Host smart-a2459039-32e7-4dd5-aeb0-195e47e83f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752853253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.752853253
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2559156672
Short name T1142
Test name
Test status
Simulation time 621734996 ps
CPU time 1.56 seconds
Started May 26 12:42:57 PM PDT 24
Finished May 26 12:43:00 PM PDT 24
Peak memory 212636 kb
Host smart-cdb09afb-ac9d-4a93-8704-b9c36794ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559156672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2559156672
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2109145145
Short name T1121
Test name
Test status
Simulation time 683170015 ps
CPU time 16.84 seconds
Started May 26 12:42:59 PM PDT 24
Finished May 26 12:43:17 PM PDT 24
Peak memory 272916 kb
Host smart-2e31c4c0-cea6-4172-bbb0-03e9cb95fa2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109145145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2109145145
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1970144339
Short name T673
Test name
Test status
Simulation time 8116588083 ps
CPU time 50.56 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:43:50 PM PDT 24
Peak memory 286400 kb
Host smart-bbf13a96-6af6-4375-953b-5116ff01e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970144339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1970144339
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.847824398
Short name T417
Test name
Test status
Simulation time 9112242404 ps
CPU time 88.54 seconds
Started May 26 12:42:59 PM PDT 24
Finished May 26 12:44:29 PM PDT 24
Peak memory 817216 kb
Host smart-b4e4d44f-587c-42bd-94b1-e2f6cbd7e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847824398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.847824398
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3608948368
Short name T1429
Test name
Test status
Simulation time 70239006 ps
CPU time 0.76 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:43:01 PM PDT 24
Peak memory 204200 kb
Host smart-ce3c4964-491c-49fb-b9f9-442200012fea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608948368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3608948368
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.4139735468
Short name T890
Test name
Test status
Simulation time 409077650 ps
CPU time 4.46 seconds
Started May 26 12:42:57 PM PDT 24
Finished May 26 12:43:03 PM PDT 24
Peak memory 226112 kb
Host smart-d324b92b-18d7-4728-8764-062a941b842d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139735468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
4139735468
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.649032996
Short name T112
Test name
Test status
Simulation time 15084161969 ps
CPU time 60.46 seconds
Started May 26 12:42:59 PM PDT 24
Finished May 26 12:44:00 PM PDT 24
Peak memory 782188 kb
Host smart-7eceafb9-cf99-4687-a197-5cba12b12d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649032996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.649032996
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2810350732
Short name T1303
Test name
Test status
Simulation time 547232310 ps
CPU time 7.49 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 204416 kb
Host smart-4a8439c1-cb7d-4f29-9242-572f14feacdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810350732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2810350732
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2294961917
Short name T1249
Test name
Test status
Simulation time 5091673903 ps
CPU time 138.24 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:45:24 PM PDT 24
Peak memory 512668 kb
Host smart-d38f3a10-a547-41ce-87ac-35298560c3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294961917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2294961917
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3955774368
Short name T1442
Test name
Test status
Simulation time 17747984 ps
CPU time 0.66 seconds
Started May 26 12:42:48 PM PDT 24
Finished May 26 12:42:49 PM PDT 24
Peak memory 204148 kb
Host smart-7cf8bf2d-925d-4672-8ab8-fdea73394218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955774368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3955774368
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.614231754
Short name T791
Test name
Test status
Simulation time 550810275 ps
CPU time 24.48 seconds
Started May 26 12:42:57 PM PDT 24
Finished May 26 12:43:23 PM PDT 24
Peak memory 237160 kb
Host smart-455015e2-8662-4292-bfd9-10891806890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614231754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.614231754
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1625630072
Short name T822
Test name
Test status
Simulation time 1940830287 ps
CPU time 35.6 seconds
Started May 26 12:42:47 PM PDT 24
Finished May 26 12:43:24 PM PDT 24
Peak memory 333416 kb
Host smart-35cd4bf3-1ff8-4c1b-8c39-d0a4d5997f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625630072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1625630072
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1357701421
Short name T519
Test name
Test status
Simulation time 21517031420 ps
CPU time 1012.91 seconds
Started May 26 12:42:54 PM PDT 24
Finished May 26 12:59:48 PM PDT 24
Peak memory 2691612 kb
Host smart-2843063e-b7e4-4ead-ab51-3d97b097a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357701421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1357701421
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.394397538
Short name T954
Test name
Test status
Simulation time 520567309 ps
CPU time 10.47 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:43:07 PM PDT 24
Peak memory 220268 kb
Host smart-2740d497-9b0e-40f8-a6d2-43aada68a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394397538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.394397538
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2733680333
Short name T424
Test name
Test status
Simulation time 2814818668 ps
CPU time 3.73 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:43:01 PM PDT 24
Peak memory 204624 kb
Host smart-d5bb208c-6279-4c33-8138-bd3483a30ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733680333 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2733680333
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.464576800
Short name T1298
Test name
Test status
Simulation time 10361585695 ps
CPU time 9.28 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:43:09 PM PDT 24
Peak memory 234540 kb
Host smart-4328e41a-dc15-4702-8bc2-1a3d26450517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464576800 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.464576800
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3933962877
Short name T920
Test name
Test status
Simulation time 10377189617 ps
CPU time 15.09 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 311908 kb
Host smart-c33df45a-334b-4fa0-85aa-795210abb132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933962877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3933962877
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.1469365931
Short name T242
Test name
Test status
Simulation time 1229273935 ps
CPU time 5.7 seconds
Started May 26 12:43:07 PM PDT 24
Finished May 26 12:43:13 PM PDT 24
Peak memory 204468 kb
Host smart-06d8acbd-96b5-43a6-987d-4b567072304d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469365931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1469365931
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3956145623
Short name T818
Test name
Test status
Simulation time 1539706480 ps
CPU time 1.68 seconds
Started May 26 12:43:05 PM PDT 24
Finished May 26 12:43:08 PM PDT 24
Peak memory 204476 kb
Host smart-179ff4b1-48c6-477d-9e75-30de1d3473c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956145623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3956145623
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2296007000
Short name T1259
Test name
Test status
Simulation time 607832487 ps
CPU time 2.3 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:42:58 PM PDT 24
Peak memory 204620 kb
Host smart-cbb6c6fa-f582-4bc5-91d4-718ce6113492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296007000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2296007000
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3052390069
Short name T1299
Test name
Test status
Simulation time 2243393343 ps
CPU time 3.54 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:43:01 PM PDT 24
Peak memory 204552 kb
Host smart-48300a9e-8cd3-4871-830e-4a6833fac9c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052390069 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3052390069
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3623300646
Short name T688
Test name
Test status
Simulation time 13961688390 ps
CPU time 131.25 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:45:10 PM PDT 24
Peak memory 1891656 kb
Host smart-dd3b1503-2026-4028-a44d-96844690fb68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623300646 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3623300646
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.29818224
Short name T974
Test name
Test status
Simulation time 2927988031 ps
CPU time 18.25 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:43:15 PM PDT 24
Peak memory 204536 kb
Host smart-05967c4d-54f5-4dce-a7af-4dede024d1e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29818224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targe
t_smoke.29818224
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2909412674
Short name T513
Test name
Test status
Simulation time 1825323862 ps
CPU time 17.26 seconds
Started May 26 12:42:56 PM PDT 24
Finished May 26 12:43:14 PM PDT 24
Peak memory 211516 kb
Host smart-43f3f71d-578d-48d1-ba56-353b40529a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909412674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2909412674
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.744730901
Short name T527
Test name
Test status
Simulation time 40590256353 ps
CPU time 79.45 seconds
Started May 26 12:42:57 PM PDT 24
Finished May 26 12:44:18 PM PDT 24
Peak memory 1343292 kb
Host smart-32b01e47-a154-4c6f-8388-d573e4da1a8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744730901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.744730901
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3124677620
Short name T692
Test name
Test status
Simulation time 27100317712 ps
CPU time 188.14 seconds
Started May 26 12:42:58 PM PDT 24
Finished May 26 12:46:08 PM PDT 24
Peak memory 1696296 kb
Host smart-6c986ef4-9557-4e33-82f6-4af55ac70a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124677620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3124677620
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1584881513
Short name T1373
Test name
Test status
Simulation time 1429313033 ps
CPU time 7.72 seconds
Started May 26 12:42:57 PM PDT 24
Finished May 26 12:43:06 PM PDT 24
Peak memory 216852 kb
Host smart-acdc0391-6b34-4b4e-8193-c988967368c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584881513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1584881513
Directory /workspace/9.i2c_target_timeout/latest
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