Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	859122	1			T1	3		T2	3		T3	232
all_values[1]	859122	1			T1	3		T2	3		T3	232
all_values[2]	859122	1			T1	3		T2	3		T3	232
all_values[3]	859122	1			T1	3		T2	3		T3	232
all_values[4]	859122	1			T1	3		T2	3		T3	232
all_values[5]	859122	1			T1	3		T2	3		T3	232
all_values[6]	859122	1			T1	3		T2	3		T3	232
all_values[7]	859122	1			T1	3		T2	3		T3	232
all_values[8]	859122	1			T1	3		T2	3		T3	232
all_values[9]	859122	1			T1	3		T2	3		T3	232
all_values[10]	859122	1			T1	3		T2	3		T3	232
all_values[11]	859122	1			T1	3		T2	3		T3	232
all_values[12]	859122	1			T1	3		T2	3		T3	232
all_values[13]	859122	1			T1	3		T2	3		T3	232
all_values[14]	859122	1			T1	3		T2	3		T3	232

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10534212

1

T1

38

T2

40

T3

3020

auto[1]

2352618

1

T1

7

T2

5

T3

460

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11310595

1

T1

45

T2

45

T3

3480

auto[1]

1576235

1

T46

151111

T122

4299

T54

164011

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80734	1			T2	1		T3	27		T4	173
all_values[0]	auto[0]	auto[1]	8836	1			T122	18		T54	350		T123	1669
all_values[0]	auto[1]	auto[0]	685115	1			T1	3		T2	2		T3	205
all_values[0]	auto[1]	auto[1]	84437	1			T122	290		T54	13317		T123	3816
all_values[1]	auto[0]	auto[0]	744570	1			T1	3		T2	3		T3	232
all_values[1]	auto[0]	auto[1]	114094	1			T46	12591		T122	301		T54	13657
all_values[1]	auto[1]	auto[0]	217	1			T117	25		T44	1		T49	1
all_values[1]	auto[1]	auto[1]	241	1			T46	2		T122	4		T54	11
all_values[2]	auto[0]	auto[0]	738600	1			T1	3		T2	3		T3	232
all_values[2]	auto[0]	auto[1]	120190	1			T46	12590		T122	304		T54	13667
all_values[2]	auto[1]	auto[0]	116	1			T20	1		T21	1		T258	1
all_values[2]	auto[1]	auto[1]	216	1			T46	3		T122	3		T54	1
all_values[3]	auto[0]	auto[0]	738438	1			T1	3		T2	3		T3	232
all_values[3]	auto[0]	auto[1]	120429	1			T46	12591		T122	304		T54	13664
all_values[3]	auto[1]	auto[1]	255	1			T46	2		T122	4		T54	4
all_values[4]	auto[0]	auto[0]	752099	1			T1	3		T2	3		T3	232
all_values[4]	auto[0]	auto[1]	106792	1			T46	12590		T122	304		T156	14810
all_values[4]	auto[1]	auto[0]	16	1			T250	1		T259	1		T260	1
all_values[4]	auto[1]	auto[1]	215	1			T46	3		T122	3		T156	1
all_values[5]	auto[0]	auto[0]	739554	1			T1	3		T2	3		T3	232
all_values[5]	auto[0]	auto[1]	119288	1			T46	12591		T122	303		T54	13664
all_values[5]	auto[1]	auto[1]	280	1			T46	1		T122	3		T54	3
all_values[6]	auto[0]	auto[0]	779105	1			T1	3		T2	3		T3	232
all_values[6]	auto[0]	auto[1]	79712	1			T46	12589		T122	306		T156	14810
all_values[6]	auto[1]	auto[1]	305	1			T46	3		T122	2		T156	3
all_values[7]	auto[0]	auto[0]	720329	1			T1	3		T2	3		T3	217
all_values[7]	auto[0]	auto[1]	110016	1			T46	12363		T122	246		T54	13497
all_values[7]	auto[1]	auto[0]	24837	1			T3	15		T4	132		T5	44
all_values[7]	auto[1]	auto[1]	3940	1			T46	230		T122	62		T54	170
all_values[8]	auto[0]	auto[0]	739318	1			T1	3		T2	3		T3	232
all_values[8]	auto[0]	auto[1]	119533	1			T46	12590		T122	307		T54	13665
all_values[8]	auto[1]	auto[1]	271	1			T46	3		T122	1		T54	3
all_values[9]	auto[0]	auto[0]	143616	1			T1	2		T2	2		T3	222
all_values[9]	auto[0]	auto[1]	20293	1			T122	285		T54	183		T156	1866
all_values[9]	auto[1]	auto[0]	645669	1			T1	1		T2	1		T3	10
all_values[9]	auto[1]	auto[1]	49544	1			T122	23		T54	13485		T156	12945
all_values[10]	auto[0]	auto[0]	748934	1			T1	3		T2	3		T3	232
all_values[10]	auto[0]	auto[1]	109965	1			T46	12590		T122	304		T54	13666
all_values[10]	auto[1]	auto[1]	223	1			T46	2		T122	2		T54	1
all_values[11]	auto[0]	auto[0]	2621	1			T2	1		T3	2		T4	9
all_values[11]	auto[0]	auto[1]	572	1			T46	16		T54	21		T123	24
all_values[11]	auto[1]	auto[0]	750943	1			T1	3		T2	2		T3	230
all_values[11]	auto[1]	auto[1]	104986	1			T46	12576		T54	13647		T123	5461
all_values[12]	auto[0]	auto[0]	769442	1			T1	3		T2	3		T3	232
all_values[12]	auto[0]	auto[1]	89422	1			T46	12590		T122	302		T54	13666
all_values[12]	auto[1]	auto[0]	22	1			T20	1		T21	1		T147	1
all_values[12]	auto[1]	auto[1]	236	1			T46	3		T122	4		T54	2
all_values[13]	auto[0]	auto[0]	751372	1			T1	3		T2	3		T3	232
all_values[13]	auto[0]	auto[1]	107485	1			T122	304		T54	13664		T156	14809
all_values[13]	auto[1]	auto[1]	265	1			T122	3		T54	3		T156	4
all_values[14]	auto[0]	auto[0]	754928	1			T1	3		T2	3		T3	232
all_values[14]	auto[0]	auto[1]	103925	1			T46	12589		T122	307		T156	14813
all_values[14]	auto[1]	auto[1]	269	1			T46	3		T123	4		T64	3