Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	859122	1			T1	3		T2	3		T3	232
all_pins[1]	859122	1			T1	3		T2	3		T3	232
all_pins[2]	859122	1			T1	3		T2	3		T3	232
all_pins[3]	859122	1			T1	3		T2	3		T3	232
all_pins[4]	859122	1			T1	3		T2	3		T3	232
all_pins[5]	859122	1			T1	3		T2	3		T3	232
all_pins[6]	859122	1			T1	3		T2	3		T3	232
all_pins[7]	859122	1			T1	3		T2	3		T3	232
all_pins[8]	859122	1			T1	3		T2	3		T3	232
all_pins[9]	859122	1			T1	3		T2	3		T3	232
all_pins[10]	859122	1			T1	3		T2	3		T3	232
all_pins[11]	859122	1			T1	3		T2	3		T3	232
all_pins[12]	859122	1			T1	3		T2	3		T3	232
all_pins[13]	859122	1			T1	3		T2	3		T3	232
all_pins[14]	859122	1			T1	3		T2	3		T3	232

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10540046	1			T1	38		T2	40		T3	3018
values[0x1]	2346784	1			T1	7		T2	5		T3	462
transitions[0x0=>0x1]	2345974	1			T1	7		T2	5		T3	462
transitions[0x1=>0x0]	2344811	1			T1	6		T2	4		T3	461

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92978	1			T2	1		T3	27		T4	173
all_pins[0]	values[0x1]	766144	1			T1	3		T2	2		T3	205
all_pins[0]	transitions[0x0=>0x1]	765816	1			T1	3		T2	2		T3	205
all_pins[0]	transitions[0x1=>0x0]	61	1			T54	1		T123	1		T64	1
all_pins[1]	values[0x0]	858733	1			T1	3		T2	3		T3	232
all_pins[1]	values[0x1]	389	1			T117	25		T44	1		T49	1
all_pins[1]	transitions[0x0=>0x1]	370	1			T117	25		T44	1		T49	1
all_pins[1]	transitions[0x1=>0x0]	196	1			T20	1		T21	1		T46	2
all_pins[2]	values[0x0]	858907	1			T1	3		T2	3		T3	232
all_pins[2]	values[0x1]	215	1			T20	1		T21	1		T46	2
all_pins[2]	transitions[0x0=>0x1]	194	1			T20	1		T21	1		T46	1
all_pins[2]	transitions[0x1=>0x0]	104	1			T122	1		T64	2		T235	4
all_pins[3]	values[0x0]	858997	1			T1	3		T2	3		T3	232
all_pins[3]	values[0x1]	125	1			T46	1		T122	1		T123	1
all_pins[3]	transitions[0x0=>0x1]	99	1			T122	1		T123	1		T64	2
all_pins[3]	transitions[0x1=>0x0]	107	1			T122	2		T250	1		T259	1
all_pins[4]	values[0x0]	858989	1			T1	3		T2	3		T3	232
all_pins[4]	values[0x1]	133	1			T46	1		T122	2		T250	1
all_pins[4]	transitions[0x0=>0x1]	96	1			T46	1		T122	1		T250	1
all_pins[4]	transitions[0x1=>0x0]	113	1			T54	3		T156	1		T123	4
all_pins[5]	values[0x0]	858972	1			T1	3		T2	3		T3	232
all_pins[5]	values[0x1]	150	1			T122	1		T54	3		T156	1
all_pins[5]	transitions[0x0=>0x1]	103	1			T54	3		T156	1		T123	3
all_pins[5]	transitions[0x1=>0x0]	108	1			T46	3		T156	2		T123	2
all_pins[6]	values[0x0]	858967	1			T1	3		T2	3		T3	232
all_pins[6]	values[0x1]	155	1			T46	3		T122	1		T156	2
all_pins[6]	transitions[0x0=>0x1]	121	1			T46	3		T122	1		T156	2
all_pins[6]	transitions[0x1=>0x0]	31469	1			T3	17		T4	149		T5	46
all_pins[7]	values[0x0]	827619	1			T1	3		T2	3		T3	215
all_pins[7]	values[0x1]	31503	1			T3	17		T4	149		T5	46
all_pins[7]	transitions[0x0=>0x1]	31471	1			T3	17		T4	149		T5	46
all_pins[7]	transitions[0x1=>0x0]	100	1			T54	2		T156	2		T123	1
all_pins[8]	values[0x0]	858990	1			T1	3		T2	3		T3	232
all_pins[8]	values[0x1]	132	1			T54	3		T156	2		T123	1
all_pins[8]	transitions[0x0=>0x1]	108	1			T54	3		T64	2		T124	4
all_pins[8]	transitions[0x1=>0x0]	695129	1			T1	1		T2	1		T3	10
all_pins[9]	values[0x0]	163969	1			T1	2		T2	2		T3	222
all_pins[9]	values[0x1]	695153	1			T1	1		T2	1		T3	10
all_pins[9]	transitions[0x0=>0x1]	695138	1			T1	1		T2	1		T3	10
all_pins[9]	transitions[0x1=>0x0]	90	1			T122	1		T54	1		T64	1
all_pins[10]	values[0x0]	859017	1			T1	3		T2	3		T3	232
all_pins[10]	values[0x1]	105	1			T122	1		T54	1		T123	1
all_pins[10]	transitions[0x0=>0x1]	73	1			T122	1		T54	1		T82	1
all_pins[10]	transitions[0x1=>0x0]	852116	1			T1	3		T2	2		T3	230
all_pins[11]	values[0x0]	6974	1			T2	1		T3	2		T4	9
all_pins[11]	values[0x1]	852148	1			T1	3		T2	2		T3	230
all_pins[11]	transitions[0x0=>0x1]	852083	1			T1	3		T2	2		T3	230
all_pins[11]	transitions[0x1=>0x0]	84	1			T46	2		T122	4		T156	2
all_pins[12]	values[0x0]	858973	1			T1	3		T2	3		T3	232
all_pins[12]	values[0x1]	149	1			T20	1		T21	1		T46	2
all_pins[12]	transitions[0x0=>0x1]	123	1			T20	1		T21	1		T46	2
all_pins[12]	transitions[0x1=>0x0]	109	1			T54	1		T156	2		T123	2
all_pins[13]	values[0x0]	858987	1			T1	3		T2	3		T3	232
all_pins[13]	values[0x1]	135	1			T122	2		T54	1		T156	2
all_pins[13]	transitions[0x0=>0x1]	86	1			T122	2		T54	1		T156	2
all_pins[13]	transitions[0x1=>0x0]	99	1			T46	1		T123	3		T82	1
all_pins[14]	values[0x0]	858974	1			T1	3		T2	3		T3	232
all_pins[14]	values[0x1]	148	1			T46	1		T123	3		T82	1
all_pins[14]	transitions[0x0=>0x1]	93	1			T46	1		T123	2		T279	1
all_pins[14]	transitions[0x1=>0x0]	764926	1			T1	2		T2	1		T3	204