Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	535	1			T46	4		T122	7		T54	4
all_values[1]	535	1			T46	4		T122	7		T54	4
all_values[2]	535	1			T46	4		T122	7		T54	4
all_values[3]	535	1			T46	4		T122	7		T54	4
all_values[4]	535	1			T46	4		T122	7		T54	4
all_values[5]	535	1			T46	4		T122	7		T54	4
all_values[6]	535	1			T46	4		T122	7		T54	4
all_values[7]	535	1			T46	4		T122	7		T54	4
all_values[8]	535	1			T46	4		T122	7		T54	4
all_values[9]	535	1			T46	4		T122	7		T54	4
all_values[10]	535	1			T46	4		T122	7		T54	4
all_values[11]	535	1			T46	4		T122	7		T54	4
all_values[12]	535	1			T46	4		T122	7		T54	4
all_values[13]	535	1			T46	4		T122	7		T54	4
all_values[14]	535	1			T46	4		T122	7		T54	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4131

1

T46

42

T122

50

T54

29

auto[1]

3894

1

T46

18

T122

55

T54

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1296

1

T46

17

T122

20

T54

17

auto[1]

6729

1

T46

43

T122

85

T54

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4723

1

T46

35

T122

65

T54

37

auto[1]

3302

1

T46

25

T122

40

T54

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	41	1			T46	3		T156	2		T84	2
all_values[0]	auto[0]	auto[0]	auto[1]	116	1			T122	2		T54	1		T123	3
all_values[0]	auto[0]	auto[1]	auto[0]	38	1			T46	1		T54	1		T156	2
all_values[0]	auto[0]	auto[1]	auto[1]	116	1			T122	1		T123	1		T82	2
all_values[0]	auto[1]	auto[0]	auto[1]	108	1			T122	2		T123	3		T64	1
all_values[0]	auto[1]	auto[1]	auto[1]	116	1			T122	2		T54	2		T123	4
all_values[1]	auto[0]	auto[0]	auto[0]	58	1			T122	3		T235	2		T124	2
all_values[1]	auto[0]	auto[0]	auto[1]	116	1			T46	1		T122	2		T123	3
all_values[1]	auto[0]	auto[1]	auto[0]	39	1			T123	2		T64	1		T280	1
all_values[1]	auto[0]	auto[1]	auto[1]	117	1			T46	1		T122	1		T54	2
all_values[1]	auto[1]	auto[0]	auto[1]	124	1			T46	2		T122	1		T123	1
all_values[1]	auto[1]	auto[1]	auto[1]	81	1			T54	2		T156	1		T123	2
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T235	1		T279	3		T281	1
all_values[2]	auto[0]	auto[0]	auto[1]	112	1			T46	1		T122	2		T54	3
all_values[2]	auto[0]	auto[1]	auto[0]	35	1			T122	1		T123	1		T279	1
all_values[2]	auto[0]	auto[1]	auto[1]	123	1			T122	1		T156	1		T64	2
all_values[2]	auto[1]	auto[0]	auto[1]	114	1			T46	2		T122	2		T54	1
all_values[2]	auto[1]	auto[1]	auto[1]	102	1			T46	1		T122	1		T156	1
all_values[3]	auto[0]	auto[0]	auto[0]	34	1			T281	1		T282	1		T269	1
all_values[3]	auto[0]	auto[0]	auto[1]	124	1			T122	1		T54	1		T156	1
all_values[3]	auto[0]	auto[1]	auto[0]	36	1			T156	1		T123	2		T124	1
all_values[3]	auto[0]	auto[1]	auto[1]	124	1			T46	2		T122	1		T123	2
all_values[3]	auto[1]	auto[0]	auto[1]	115	1			T46	1		T122	2		T54	3
all_values[3]	auto[1]	auto[1]	auto[1]	102	1			T46	1		T122	3		T123	2
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T54	3		T123	1		T84	1
all_values[4]	auto[0]	auto[0]	auto[1]	123	1			T46	1		T122	2		T156	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1			T122	1		T54	1		T156	2
all_values[4]	auto[0]	auto[1]	auto[1]	118	1			T122	1		T123	1		T235	2
all_values[4]	auto[1]	auto[0]	auto[1]	103	1			T46	2		T122	1		T123	4
all_values[4]	auto[1]	auto[1]	auto[1]	112	1			T46	1		T122	2		T156	1
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T46	1		T235	1		T279	1
all_values[5]	auto[0]	auto[0]	auto[1]	113	1			T46	2		T122	1		T156	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1			T122	2		T54	1		T123	3
all_values[5]	auto[0]	auto[1]	auto[1]	106	1			T122	2		T54	1		T123	1
all_values[5]	auto[1]	auto[0]	auto[1]	122	1			T46	1		T123	1		T64	2
all_values[5]	auto[1]	auto[1]	auto[1]	111	1			T122	2		T54	2		T156	3
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T46	1		T54	1		T64	3
all_values[6]	auto[0]	auto[0]	auto[1]	119	1			T122	1		T156	1		T123	2
all_values[6]	auto[0]	auto[1]	auto[0]	28	1			T54	3		T64	1		T82	1
all_values[6]	auto[0]	auto[1]	auto[1]	103	1			T46	1		T122	3		T156	1
all_values[6]	auto[1]	auto[0]	auto[1]	121	1			T122	1		T156	1		T123	3
all_values[6]	auto[1]	auto[1]	auto[1]	107	1			T46	2		T122	2		T156	1
all_values[7]	auto[0]	auto[0]	auto[0]	55	1			T54	1		T82	3		T235	2
all_values[7]	auto[0]	auto[0]	auto[1]	113	1			T46	3		T122	4		T54	1
all_values[7]	auto[0]	auto[1]	auto[0]	36	1			T156	1		T123	2		T82	1
all_values[7]	auto[0]	auto[1]	auto[1]	97	1			T156	1		T123	2		T64	2
all_values[7]	auto[1]	auto[0]	auto[1]	130	1			T46	1		T122	3		T54	1
all_values[7]	auto[1]	auto[1]	auto[1]	104	1			T54	1		T156	1		T123	1
all_values[8]	auto[0]	auto[0]	auto[0]	52	1			T235	6		T84	3		T279	2
all_values[8]	auto[0]	auto[0]	auto[1]	103	1			T46	2		T156	1		T123	4
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T64	1		T235	1		T84	2
all_values[8]	auto[0]	auto[1]	auto[1]	115	1			T122	4		T54	1		T156	1
all_values[8]	auto[1]	auto[0]	auto[1]	112	1			T46	2		T122	2		T156	1
all_values[8]	auto[1]	auto[1]	auto[1]	122	1			T122	1		T54	3		T156	1
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T46	3		T82	1		T281	1
all_values[9]	auto[0]	auto[0]	auto[1]	110	1			T122	3		T54	2		T123	2
all_values[9]	auto[0]	auto[1]	auto[0]	52	1			T46	1		T156	2		T64	4
all_values[9]	auto[0]	auto[1]	auto[1]	123	1			T122	2		T156	1		T123	3
all_values[9]	auto[1]	auto[0]	auto[1]	96	1			T123	2		T235	1		T124	2
all_values[9]	auto[1]	auto[1]	auto[1]	98	1			T122	2		T54	2		T156	1
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T46	1		T122	1		T54	1
all_values[10]	auto[0]	auto[0]	auto[1]	120	1			T46	1		T122	2		T156	1
all_values[10]	auto[0]	auto[1]	auto[0]	36	1			T122	1		T156	2		T64	1
all_values[10]	auto[0]	auto[1]	auto[1]	117	1			T122	1		T54	2		T123	2
all_values[10]	auto[1]	auto[0]	auto[1]	119	1			T46	2		T54	1		T82	1
all_values[10]	auto[1]	auto[1]	auto[1]	104	1			T122	2		T156	1		T123	2
all_values[11]	auto[0]	auto[0]	auto[0]	39	1			T46	1		T122	5		T156	3
all_values[11]	auto[0]	auto[0]	auto[1]	111	1			T54	1		T123	4		T82	1
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T122	2		T156	1		T64	1
all_values[11]	auto[0]	auto[1]	auto[1]	128	1			T46	1		T54	2		T123	2
all_values[11]	auto[1]	auto[0]	auto[1]	118	1			T46	1		T123	3		T82	1
all_values[11]	auto[1]	auto[1]	auto[1]	95	1			T46	1		T54	1		T123	2
all_values[12]	auto[0]	auto[0]	auto[0]	46	1			T64	1		T84	1		T279	3
all_values[12]	auto[0]	auto[0]	auto[1]	105	1			T46	1		T54	2		T123	5
all_values[12]	auto[0]	auto[1]	auto[0]	39	1			T122	2		T64	3		T279	1
all_values[12]	auto[0]	auto[1]	auto[1]	109	1			T122	1		T156	2		T123	3
all_values[12]	auto[1]	auto[0]	auto[1]	116	1			T46	2		T54	2		T235	1
all_values[12]	auto[1]	auto[1]	auto[1]	120	1			T46	1		T122	4		T156	2
all_values[13]	auto[0]	auto[0]	auto[0]	51	1			T46	1		T122	1		T124	2
all_values[13]	auto[0]	auto[0]	auto[1]	120	1			T122	1		T54	1		T123	2
all_values[13]	auto[0]	auto[1]	auto[0]	45	1			T46	3		T54	1		T123	2
all_values[13]	auto[0]	auto[1]	auto[1]	111	1			T122	3		T156	1		T123	3
all_values[13]	auto[1]	auto[0]	auto[1]	103	1			T122	1		T156	2		T123	4
all_values[13]	auto[1]	auto[1]	auto[1]	105	1			T122	1		T54	2		T156	1
all_values[14]	auto[0]	auto[0]	auto[0]	54	1			T46	1		T122	1		T54	3
all_values[14]	auto[0]	auto[0]	auto[1]	103	1			T46	1		T122	2		T156	1
all_values[14]	auto[0]	auto[1]	auto[0]	44	1			T54	1		T124	1		T84	6
all_values[14]	auto[0]	auto[1]	auto[1]	112	1			T122	1		T156	1		T123	1
all_values[14]	auto[1]	auto[0]	auto[1]	114	1			T46	1		T122	1		T156	1
all_values[14]	auto[1]	auto[1]	auto[1]	108	1			T46	1		T122	2		T156	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal