Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.08 96.60 90.18 97.67 70.24 93.62 98.44 90.84


Total test records in report: 1609
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html
T1527 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3866178042 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:15 PM PDT 24 15568101 ps
T215 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2195623649 Jun 05 03:49:22 PM PDT 24 Jun 05 03:49:23 PM PDT 24 59514414 ps
T108 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.374894266 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:16 PM PDT 24 160156807 ps
T198 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3713791462 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:14 PM PDT 24 91368276 ps
T1528 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3498222741 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:13 PM PDT 24 35234424 ps
T1529 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3116637923 Jun 05 03:49:27 PM PDT 24 Jun 05 03:49:28 PM PDT 24 20463173 ps
T1530 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.4131030241 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 51871020 ps
T1531 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3055177984 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:30 PM PDT 24 17499973 ps
T1532 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.858919224 Jun 05 03:49:21 PM PDT 24 Jun 05 03:49:23 PM PDT 24 53919348 ps
T1533 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2133546902 Jun 05 03:49:32 PM PDT 24 Jun 05 03:49:36 PM PDT 24 146225004 ps
T1534 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1497711599 Jun 05 03:49:23 PM PDT 24 Jun 05 03:49:25 PM PDT 24 18438597 ps
T1535 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.537875000 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:30 PM PDT 24 803901017 ps
T1536 /workspace/coverage/cover_reg_top/45.i2c_intr_test.98866338 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:42 PM PDT 24 42683851 ps
T1537 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.27680388 Jun 05 03:49:24 PM PDT 24 Jun 05 03:49:26 PM PDT 24 158789608 ps
T1538 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.656586185 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:16 PM PDT 24 29599856 ps
T216 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1821330881 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 146314243 ps
T217 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1023947049 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:19 PM PDT 24 448839526 ps
T1539 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2476559741 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:15 PM PDT 24 71844248 ps
T207 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3000723976 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 170329517 ps
T203 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.592565074 Jun 05 03:49:09 PM PDT 24 Jun 05 03:49:13 PM PDT 24 53172387 ps
T1540 /workspace/coverage/cover_reg_top/33.i2c_intr_test.327952833 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:41 PM PDT 24 54004023 ps
T1541 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.152337440 Jun 05 03:49:04 PM PDT 24 Jun 05 03:49:06 PM PDT 24 75973909 ps
T218 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.929951392 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:15 PM PDT 24 71802041 ps
T1542 /workspace/coverage/cover_reg_top/9.i2c_intr_test.234275623 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:43 PM PDT 24 24597886 ps
T1543 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1343733506 Jun 05 03:49:08 PM PDT 24 Jun 05 03:49:10 PM PDT 24 33189968 ps
T1544 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1761682393 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:22 PM PDT 24 19709556 ps
T1545 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2649163301 Jun 05 03:49:09 PM PDT 24 Jun 05 03:49:12 PM PDT 24 42367380 ps
T1546 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1677967692 Jun 05 03:49:40 PM PDT 24 Jun 05 03:49:42 PM PDT 24 80257901 ps
T1547 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3791964086 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:40 PM PDT 24 44342194 ps
T219 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1425682376 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:13 PM PDT 24 25610770 ps
T1548 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3084212025 Jun 05 03:49:14 PM PDT 24 Jun 05 03:49:17 PM PDT 24 65563671 ps
T261 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1942304357 Jun 05 03:49:12 PM PDT 24 Jun 05 03:49:15 PM PDT 24 299650504 ps
T220 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1106166812 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:19 PM PDT 24 528633031 ps
T221 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1615726540 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 50474244 ps
T1549 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3882133622 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 20704097 ps
T1550 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2938931858 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:32 PM PDT 24 27832660 ps
T1551 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2810298207 Jun 05 03:49:12 PM PDT 24 Jun 05 03:49:14 PM PDT 24 27091461 ps
T1552 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2456875537 Jun 05 03:49:24 PM PDT 24 Jun 05 03:49:26 PM PDT 24 56939237 ps
T1553 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2919128910 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:22 PM PDT 24 97112699 ps
T1554 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.4054991412 Jun 05 03:49:23 PM PDT 24 Jun 05 03:49:25 PM PDT 24 42207796 ps
T1555 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1464925884 Jun 05 03:49:26 PM PDT 24 Jun 05 03:49:28 PM PDT 24 20045192 ps
T1556 /workspace/coverage/cover_reg_top/24.i2c_intr_test.994513405 Jun 05 03:49:45 PM PDT 24 Jun 05 03:49:46 PM PDT 24 45182574 ps
T1557 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2029854386 Jun 05 03:49:22 PM PDT 24 Jun 05 03:49:24 PM PDT 24 52011631 ps
T222 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1452731545 Jun 05 03:49:09 PM PDT 24 Jun 05 03:49:11 PM PDT 24 18957613 ps
T223 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2172454520 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:13 PM PDT 24 55060233 ps
T200 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1650768322 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:23 PM PDT 24 1543966377 ps
T1558 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.990251067 Jun 05 03:49:25 PM PDT 24 Jun 05 03:49:28 PM PDT 24 73356313 ps
T1559 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2274964398 Jun 05 03:49:43 PM PDT 24 Jun 05 03:49:45 PM PDT 24 22064728 ps
T224 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3803750269 Jun 05 03:49:09 PM PDT 24 Jun 05 03:49:12 PM PDT 24 52475603 ps
T1560 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3868298266 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:12 PM PDT 24 27041997 ps
T1561 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3802311721 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:39 PM PDT 24 23707358 ps
T1562 /workspace/coverage/cover_reg_top/23.i2c_intr_test.195191904 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:32 PM PDT 24 19932905 ps
T1563 /workspace/coverage/cover_reg_top/12.i2c_intr_test.257947706 Jun 05 03:49:21 PM PDT 24 Jun 05 03:49:22 PM PDT 24 21536475 ps
T1564 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2931606921 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:16 PM PDT 24 44812115 ps
T1565 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3870515533 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:14 PM PDT 24 119581962 ps
T206 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4003413064 Jun 05 03:49:33 PM PDT 24 Jun 05 03:49:35 PM PDT 24 301009641 ps
T1566 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2426306418 Jun 05 03:49:26 PM PDT 24 Jun 05 03:49:27 PM PDT 24 27788170 ps
T208 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.737964172 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:23 PM PDT 24 48071992 ps
T1567 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1002749142 Jun 05 03:49:47 PM PDT 24 Jun 05 03:49:49 PM PDT 24 75373322 ps
T199 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2825720003 Jun 05 03:49:18 PM PDT 24 Jun 05 03:49:22 PM PDT 24 167187158 ps
T1568 /workspace/coverage/cover_reg_top/31.i2c_intr_test.647854198 Jun 05 03:49:43 PM PDT 24 Jun 05 03:49:45 PM PDT 24 39546379 ps
T1569 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.735160009 Jun 05 03:49:12 PM PDT 24 Jun 05 03:49:14 PM PDT 24 21386279 ps
T1570 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3794266026 Jun 05 03:49:23 PM PDT 24 Jun 05 03:49:25 PM PDT 24 27271985 ps
T1571 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1629278987 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:14 PM PDT 24 67299516 ps
T1572 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1378832347 Jun 05 03:49:16 PM PDT 24 Jun 05 03:49:18 PM PDT 24 58851831 ps
T1573 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.753914502 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:43 PM PDT 24 117102508 ps
T209 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1506873897 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:24 PM PDT 24 1871632058 ps
T1574 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3687333112 Jun 05 03:49:14 PM PDT 24 Jun 05 03:49:16 PM PDT 24 16428644 ps
T1575 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2061917950 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:30 PM PDT 24 36016888 ps
T1576 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1071177432 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:13 PM PDT 24 73738257 ps
T1577 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.349359947 Jun 05 03:49:24 PM PDT 24 Jun 05 03:49:26 PM PDT 24 53907608 ps
T204 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3202474661 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:14 PM PDT 24 252408261 ps
T1578 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3163610457 Jun 05 03:49:18 PM PDT 24 Jun 05 03:49:20 PM PDT 24 17851500 ps
T1579 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2041342295 Jun 05 03:49:21 PM PDT 24 Jun 05 03:49:23 PM PDT 24 18936939 ps
T1580 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3652294388 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:42 PM PDT 24 122445828 ps
T1581 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2894289718 Jun 05 03:49:13 PM PDT 24 Jun 05 03:49:15 PM PDT 24 97138109 ps
T1582 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2557050052 Jun 05 03:49:48 PM PDT 24 Jun 05 03:49:50 PM PDT 24 27039919 ps
T1583 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2138489407 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:43 PM PDT 24 89199411 ps
T1584 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4074253515 Jun 05 03:49:17 PM PDT 24 Jun 05 03:49:20 PM PDT 24 217386676 ps
T1585 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1997960594 Jun 05 03:49:23 PM PDT 24 Jun 05 03:49:25 PM PDT 24 25270169 ps
T225 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4226611372 Jun 05 03:49:23 PM PDT 24 Jun 05 03:49:25 PM PDT 24 51969473 ps
T1586 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3386048910 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:33 PM PDT 24 29747222 ps
T226 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2216819622 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:12 PM PDT 24 67706818 ps
T1587 /workspace/coverage/cover_reg_top/35.i2c_intr_test.892230969 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:29 PM PDT 24 25099245 ps
T205 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.391344138 Jun 05 03:49:24 PM PDT 24 Jun 05 03:49:27 PM PDT 24 83035815 ps
T1588 /workspace/coverage/cover_reg_top/47.i2c_intr_test.955133811 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:29 PM PDT 24 18047730 ps
T1589 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2913449062 Jun 05 03:49:14 PM PDT 24 Jun 05 03:49:16 PM PDT 24 68518645 ps
T1590 /workspace/coverage/cover_reg_top/48.i2c_intr_test.4195140090 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:33 PM PDT 24 19470567 ps
T1591 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2754015579 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:20 PM PDT 24 50784507 ps
T1592 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1837239057 Jun 05 03:49:09 PM PDT 24 Jun 05 03:49:10 PM PDT 24 27024467 ps
T1593 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3813846622 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:12 PM PDT 24 17730994 ps
T227 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1214211293 Jun 05 03:49:20 PM PDT 24 Jun 05 03:49:21 PM PDT 24 23569486 ps
T1594 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3367680065 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:14 PM PDT 24 43704030 ps
T1595 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3026566565 Jun 05 03:49:24 PM PDT 24 Jun 05 03:49:26 PM PDT 24 27383327 ps
T1596 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2483995611 Jun 05 03:49:14 PM PDT 24 Jun 05 03:49:22 PM PDT 24 46955837 ps
T1597 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1097683237 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:14 PM PDT 24 20173514 ps
T1598 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3403356412 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:38 PM PDT 24 16202157 ps
T1599 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3659474649 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:31 PM PDT 24 55158663 ps
T202 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3548003451 Jun 05 03:49:11 PM PDT 24 Jun 05 03:49:15 PM PDT 24 134671154 ps
T1600 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1014765942 Jun 05 03:49:50 PM PDT 24 Jun 05 03:49:52 PM PDT 24 51731829 ps
T1601 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2097733562 Jun 05 03:49:10 PM PDT 24 Jun 05 03:49:14 PM PDT 24 635746280 ps
T1602 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3682214494 Jun 05 03:49:12 PM PDT 24 Jun 05 03:49:14 PM PDT 24 56540199 ps
T1603 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2122626234 Jun 05 03:49:12 PM PDT 24 Jun 05 03:49:16 PM PDT 24 804180078 ps
T1604 /workspace/coverage/cover_reg_top/13.i2c_intr_test.864327039 Jun 05 03:49:40 PM PDT 24 Jun 05 03:49:41 PM PDT 24 18300267 ps
T1605 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.377676138 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:40 PM PDT 24 33184388 ps
T1606 /workspace/coverage/cover_reg_top/46.i2c_intr_test.30137297 Jun 05 03:49:27 PM PDT 24 Jun 05 03:49:28 PM PDT 24 18234085 ps
T1607 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2744929466 Jun 05 03:49:46 PM PDT 24 Jun 05 03:49:48 PM PDT 24 75467588 ps
T1608 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2150688764 Jun 05 03:49:19 PM PDT 24 Jun 05 03:49:21 PM PDT 24 25291811 ps
T1609 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4230559881 Jun 05 03:49:16 PM PDT 24 Jun 05 03:49:18 PM PDT 24 21231194 ps

Test location /workspace/coverage/default/5.i2c_host_may_nack.3563720276
Short name T9
Test name
Test status
Simulation time 745223220 ps
CPU time 16.16 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:35:27 PM PDT 24
Peak memory 205032 kb
Host smart-e8c0e737-dbb6-49a4-933b-245a8ce5bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563720276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3563720276
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1009479234
Short name T13
Test name
Test status
Simulation time 10193634459 ps
CPU time 12.95 seconds
Started Jun 05 04:37:33 PM PDT 24
Finished Jun 05 04:37:47 PM PDT 24
Peak memory 245172 kb
Host smart-2e4094f0-e088-4774-a5c1-c9651c89194c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009479234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1009479234
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.351987367
Short name T46
Test name
Test status
Simulation time 8271538398 ps
CPU time 757.59 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:49:25 PM PDT 24
Peak memory 1350168 kb
Host smart-359d12b4-d9a7-44ac-ae24-fe01312b0cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351987367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.351987367
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.660593657
Short name T17
Test name
Test status
Simulation time 38969361628 ps
CPU time 10.77 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:34:36 PM PDT 24
Peak memory 213476 kb
Host smart-bebc3e5e-daec-461e-a963-21307922f332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660593657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.660593657
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3907923553
Short name T99
Test name
Test status
Simulation time 110107356 ps
CPU time 1.64 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 203504 kb
Host smart-714261ff-1230-4b18-ba3e-032c2029b4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907923553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3907923553
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3515859619
Short name T6
Test name
Test status
Simulation time 10676972381 ps
CPU time 51.93 seconds
Started Jun 05 04:35:57 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 980228 kb
Host smart-27a76b3e-2bc1-47b8-b679-f42280faf5f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515859619 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3515859619
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1276981695
Short name T123
Test name
Test status
Simulation time 30736847469 ps
CPU time 218.43 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:40:58 PM PDT 24
Peak memory 999144 kb
Host smart-d3d32c56-b17b-4301-8645-56f04e647d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276981695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1276981695
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1729156935
Short name T8
Test name
Test status
Simulation time 9317992245 ps
CPU time 149.1 seconds
Started Jun 05 04:36:37 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 616796 kb
Host smart-5dc72bcb-de89-4a8b-a044-7e9fb4d12c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729156935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1729156935
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1684521944
Short name T187
Test name
Test status
Simulation time 68035024 ps
CPU time 0.98 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:34:48 PM PDT 24
Peak memory 222904 kb
Host smart-50ebb9d4-aa71-418e-bd22-39cc47d218dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684521944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1684521944
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/31.i2c_host_override.237829989
Short name T79
Test name
Test status
Simulation time 34438286 ps
CPU time 0.68 seconds
Started Jun 05 04:37:22 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 204784 kb
Host smart-9b947a90-c98f-4aa8-9877-7ea318f92d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237829989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.237829989
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4201896920
Short name T154
Test name
Test status
Simulation time 74935412 ps
CPU time 1.59 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203784 kb
Host smart-6f21547a-006a-4417-afcb-102ec8f3fca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201896920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4201896920
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3950050575
Short name T64
Test name
Test status
Simulation time 28628967448 ps
CPU time 3271.1 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 05:29:06 PM PDT 24
Peak memory 2099248 kb
Host smart-d45d3179-c188-43b3-b1c2-f91b792d9393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950050575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3950050575
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1197023115
Short name T101
Test name
Test status
Simulation time 43440028 ps
CPU time 0.87 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 202600 kb
Host smart-4802131d-bec6-40da-b4d0-b27e90cb9a84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197023115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1197023115
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.926605380
Short name T262
Test name
Test status
Simulation time 1060345541 ps
CPU time 19.9 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:38:36 PM PDT 24
Peak memory 205116 kb
Host smart-72b5574f-c681-44cb-b191-091fe4687ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926605380 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.926605380
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2640884917
Short name T77
Test name
Test status
Simulation time 1335290245 ps
CPU time 6.72 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:39:10 PM PDT 24
Peak memory 213464 kb
Host smart-e089b7d6-fe95-4d51-b120-77eae0278539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640884917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2640884917
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3597412774
Short name T923
Test name
Test status
Simulation time 11750919007 ps
CPU time 342.66 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:42:40 PM PDT 24
Peak memory 1896124 kb
Host smart-8f9a1a5a-9a36-4274-9944-f0baef4d1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597412774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3597412774
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1128322512
Short name T58
Test name
Test status
Simulation time 8614313436 ps
CPU time 9.48 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:35:56 PM PDT 24
Peak memory 297560 kb
Host smart-dc6dd517-4b52-4592-aee2-266bc944e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128322512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1128322512
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.203691145
Short name T59
Test name
Test status
Simulation time 246299989 ps
CPU time 1.71 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:23 PM PDT 24
Peak memory 213296 kb
Host smart-4cc31fc2-9931-425e-b871-b42ef7bd9be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203691145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.203691145
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1388602518
Short name T14
Test name
Test status
Simulation time 1129964161 ps
CPU time 5.81 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:35:14 PM PDT 24
Peak memory 213368 kb
Host smart-4546c375-b0d8-466c-b81a-f59ffe32c8fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388602518 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1388602518
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.749808130
Short name T61
Test name
Test status
Simulation time 321596496 ps
CPU time 0.85 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:38 PM PDT 24
Peak memory 204896 kb
Host smart-f18acad3-e6f1-48ca-93b8-c06f169512ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749808130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.749808130
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2134392785
Short name T759
Test name
Test status
Simulation time 396093637 ps
CPU time 2.72 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:34 PM PDT 24
Peak memory 205076 kb
Host smart-0149a26a-957f-42e3-a3cf-f3133f4b366c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134392785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2134392785
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.786861469
Short name T125
Test name
Test status
Simulation time 58853850943 ps
CPU time 469.25 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:46:01 PM PDT 24
Peak memory 1969056 kb
Host smart-c7da7242-b8ae-49f7-b6e7-cffc60b302b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786861469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.786861469
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1071254955
Short name T72
Test name
Test status
Simulation time 81644364 ps
CPU time 1.96 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 213292 kb
Host smart-e48cda63-9a6e-45ae-b377-620deb270b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071254955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1071254955
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.3386364845
Short name T47
Test name
Test status
Simulation time 72544758090 ps
CPU time 1161.92 seconds
Started Jun 05 04:36:28 PM PDT 24
Finished Jun 05 04:55:50 PM PDT 24
Peak memory 3768100 kb
Host smart-362ddba9-4cef-41f6-ab1f-383dd1ec3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386364845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.3386364845
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1448175583
Short name T185
Test name
Test status
Simulation time 18931777 ps
CPU time 0.62 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 204748 kb
Host smart-cf9631a8-495b-42ef-8123-1414596fc7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448175583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1448175583
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4036003316
Short name T195
Test name
Test status
Simulation time 54312148 ps
CPU time 2.67 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203776 kb
Host smart-1b866550-d4a0-47db-bd0a-bad5e68a032b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036003316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4036003316
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.4253866226
Short name T354
Test name
Test status
Simulation time 10149186531 ps
CPU time 25.32 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:34:57 PM PDT 24
Peak memory 283592 kb
Host smart-61ae2aa3-fc56-4522-99fc-75b65d1a4d9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253866226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.4253866226
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3115887380
Short name T246
Test name
Test status
Simulation time 371077856 ps
CPU time 1.24 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 205152 kb
Host smart-f42ad9af-c960-4c4d-a2b9-3130a51bcb34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115887380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3115887380
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.669847810
Short name T73
Test name
Test status
Simulation time 1359368994 ps
CPU time 19.58 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:19 PM PDT 24
Peak memory 315516 kb
Host smart-77cd685d-791d-4d86-b16c-f5efb5fea916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669847810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.669847810
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1453642604
Short name T335
Test name
Test status
Simulation time 407589146 ps
CPU time 4.78 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 230944 kb
Host smart-04778ecd-617a-49a8-895e-74857d0b0e9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453642604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1453642604
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2986597960
Short name T269
Test name
Test status
Simulation time 18763582777 ps
CPU time 3111.89 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 05:28:50 PM PDT 24
Peak memory 3116168 kb
Host smart-de23d646-0f7b-4911-9db2-0983688b2efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986597960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2986597960
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2641476043
Short name T242
Test name
Test status
Simulation time 89997464052 ps
CPU time 609.55 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:45:08 PM PDT 24
Peak memory 3080484 kb
Host smart-38521c13-e3d4-407f-88fa-a632558354fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641476043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2641476043
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1414504444
Short name T193
Test name
Test status
Simulation time 59157462 ps
CPU time 1.44 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:30 PM PDT 24
Peak memory 203812 kb
Host smart-ccfdbb4b-0453-4853-941b-c4be9262b54f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414504444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1414504444
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3628732033
Short name T239
Test name
Test status
Simulation time 10280662299 ps
CPU time 14.16 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:37:12 PM PDT 24
Peak memory 256908 kb
Host smart-d4c21c55-af41-46a5-aa42-2ad8febfe3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628732033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3628732033
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.4215094601
Short name T180
Test name
Test status
Simulation time 8949324914 ps
CPU time 122.71 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:40:19 PM PDT 24
Peak memory 940156 kb
Host smart-3b4d7dd2-f80e-4f14-9314-cb1183d863f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215094601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4215094601
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.1716361742
Short name T20
Test name
Test status
Simulation time 2153479920 ps
CPU time 2.93 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:40 PM PDT 24
Peak memory 205116 kb
Host smart-f9bd498d-1c14-48db-aab8-12c28d80b349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716361742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.1716361742
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.297517107
Short name T286
Test name
Test status
Simulation time 1198617370 ps
CPU time 7.13 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:35:52 PM PDT 24
Peak memory 221388 kb
Host smart-a8d2d9a0-182c-482a-9204-7d23ff0fe2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297517107 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.297517107
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.742149741
Short name T70
Test name
Test status
Simulation time 3891667499 ps
CPU time 34.96 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 378664 kb
Host smart-f0ea6dda-19d1-419e-8193-edeb1f7757ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742149741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.742149741
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.391344138
Short name T205
Test name
Test status
Simulation time 83035815 ps
CPU time 1.48 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:27 PM PDT 24
Peak memory 203732 kb
Host smart-f42a0c03-5310-44a8-ad89-dfda15e2be1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391344138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.391344138
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3548003451
Short name T202
Test name
Test status
Simulation time 134671154 ps
CPU time 2.29 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 202952 kb
Host smart-82bd7a24-d2e3-474e-81b7-f29a4cd1019e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548003451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3548003451
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2925251480
Short name T1444
Test name
Test status
Simulation time 10112338222 ps
CPU time 15.37 seconds
Started Jun 05 04:34:36 PM PDT 24
Finished Jun 05 04:34:54 PM PDT 24
Peak memory 335240 kb
Host smart-ea82063e-f365-49ab-b1d6-c56f5413b55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925251480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2925251480
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1069073508
Short name T1441
Test name
Test status
Simulation time 4547653591 ps
CPU time 2.5 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:34:42 PM PDT 24
Peak memory 205180 kb
Host smart-d7faeec8-00ab-4791-8d34-5e4d64c52645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069073508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1069073508
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.880636944
Short name T264
Test name
Test status
Simulation time 7788078782 ps
CPU time 41.63 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:35:19 PM PDT 24
Peak memory 205172 kb
Host smart-f05aad8d-1c13-4d8f-a439-0634b571865f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880636944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.880636944
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2291991935
Short name T84
Test name
Test status
Simulation time 20776718015 ps
CPU time 240.87 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:39:26 PM PDT 24
Peak memory 1196716 kb
Host smart-b20bde4a-1ef5-4d78-8a8f-16b178e4cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291991935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2291991935
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.4187836419
Short name T259
Test name
Test status
Simulation time 1235308620 ps
CPU time 4.27 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 205064 kb
Host smart-401c8039-0674-491b-975b-cc7a644aba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187836419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.4187836419
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3527164080
Short name T248
Test name
Test status
Simulation time 2744072032 ps
CPU time 63.45 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:36:28 PM PDT 24
Peak memory 276092 kb
Host smart-ae05e562-40a0-4be6-891d-8a42d853d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527164080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3527164080
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_perf.838824101
Short name T45
Test name
Test status
Simulation time 48672509369 ps
CPU time 321.55 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:40:42 PM PDT 24
Peak memory 205144 kb
Host smart-e325b60d-5e5f-4159-a4a8-05cdb6f481e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838824101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.838824101
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3074835835
Short name T253
Test name
Test status
Simulation time 9652765473 ps
CPU time 66.06 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:36:27 PM PDT 24
Peak memory 207368 kb
Host smart-8225710b-b8a9-4cd2-a985-6106386c9992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074835835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3074835835
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3784267287
Short name T277
Test name
Test status
Simulation time 4116364659 ps
CPU time 129.89 seconds
Started Jun 05 04:36:08 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 570852 kb
Host smart-e4c22a45-361e-4c1c-bf4a-8bfc08b3d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784267287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3784267287
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1906252218
Short name T85
Test name
Test status
Simulation time 4916721398 ps
CPU time 189.62 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:39:37 PM PDT 24
Peak memory 794200 kb
Host smart-0a8b48b3-f928-4ba3-976d-a4f57ded9b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906252218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1906252218
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3713791462
Short name T198
Test name
Test status
Simulation time 91368276 ps
CPU time 2.33 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 202924 kb
Host smart-6a5a8a07-9166-43c7-9f56-c9bbd958b23c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713791462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3713791462
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.737964172
Short name T208
Test name
Test status
Simulation time 48071992 ps
CPU time 1.55 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 202648 kb
Host smart-23fe23f6-7fd0-417b-a4f8-7341fbc390f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737964172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.737964172
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1506873897
Short name T209
Test name
Test status
Simulation time 1871632058 ps
CPU time 2.99 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:24 PM PDT 24
Peak memory 203496 kb
Host smart-6ee865b2-eef6-47c0-8ed5-f9070dd260f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506873897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1506873897
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2894289718
Short name T1581
Test name
Test status
Simulation time 97138109 ps
CPU time 1.42 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 203624 kb
Host smart-a1439cd5-49b9-4611-80d0-7f4a94a9eff1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894289718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2894289718
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2629052007
Short name T1517
Test name
Test status
Simulation time 244488804 ps
CPU time 3.2 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 203320 kb
Host smart-27324c58-fdf7-47b6-bc8a-1b2bf4b0d6dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629052007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2629052007
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.589262587
Short name T106
Test name
Test status
Simulation time 70376464 ps
CPU time 0.77 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:10 PM PDT 24
Peak memory 203488 kb
Host smart-74b40e1d-f4fa-4293-9579-29ea0ef85ec0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589262587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.589262587
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4024117729
Short name T194
Test name
Test status
Simulation time 115511910 ps
CPU time 1.49 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 211776 kb
Host smart-66da7047-9268-48d4-b02a-79406979523d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024117729 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4024117729
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1452731545
Short name T222
Test name
Test status
Simulation time 18957613 ps
CPU time 0.82 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:11 PM PDT 24
Peak memory 203412 kb
Host smart-5e43c969-cbdf-4260-b5fb-686477cbc87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452731545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1452731545
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3866178042
Short name T1527
Test name
Test status
Simulation time 15568101 ps
CPU time 0.66 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 203372 kb
Host smart-d646d296-e3fa-49e4-8b61-1d8d9f82aec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866178042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3866178042
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.152337440
Short name T1541
Test name
Test status
Simulation time 75973909 ps
CPU time 2.08 seconds
Started Jun 05 03:49:04 PM PDT 24
Finished Jun 05 03:49:06 PM PDT 24
Peak memory 204212 kb
Host smart-6989fe09-1adb-4e85-abc0-f462e673d9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152337440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.152337440
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2483995611
Short name T1596
Test name
Test status
Simulation time 46955837 ps
CPU time 2.14 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203688 kb
Host smart-d674a8e4-80ff-41be-9858-4806860c0c1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483995611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2483995611
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1106166812
Short name T220
Test name
Test status
Simulation time 528633031 ps
CPU time 6.05 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:19 PM PDT 24
Peak memory 202896 kb
Host smart-f4e326c2-cabb-4f5a-b9a0-ae192b483c8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106166812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1106166812
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2172454520
Short name T223
Test name
Test status
Simulation time 55060233 ps
CPU time 0.66 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 203416 kb
Host smart-c1bc163d-2bab-4208-a773-2bb6f5b7546c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172454520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2172454520
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1071177432
Short name T1576
Test name
Test status
Simulation time 73738257 ps
CPU time 0.81 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 204016 kb
Host smart-5db9d61c-b720-419a-a0bb-9c973c608e3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071177432 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1071177432
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.929951392
Short name T218
Test name
Test status
Simulation time 71802041 ps
CPU time 0.79 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 202736 kb
Host smart-591ea100-af27-4c02-a38a-e8dd973a7fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929951392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.929951392
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3813846622
Short name T1593
Test name
Test status
Simulation time 17730994 ps
CPU time 0.78 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 202688 kb
Host smart-03937767-2964-46e0-950e-582228dd1fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813846622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3813846622
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3682214494
Short name T1602
Test name
Test status
Simulation time 56540199 ps
CPU time 0.86 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203428 kb
Host smart-ac92e4d2-e21b-4d5d-99c9-e62c865bb005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682214494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3682214494
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2115520697
Short name T121
Test name
Test status
Simulation time 441581821 ps
CPU time 2.45 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 202964 kb
Host smart-106f05ba-fe27-45c4-8fad-f90bf4d93b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115520697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2115520697
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2754015579
Short name T1591
Test name
Test status
Simulation time 50784507 ps
CPU time 0.9 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:20 PM PDT 24
Peak memory 203572 kb
Host smart-a6945565-8667-4d50-af64-b39f3869d72c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754015579 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2754015579
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1464925884
Short name T1555
Test name
Test status
Simulation time 20045192 ps
CPU time 0.82 seconds
Started Jun 05 03:49:26 PM PDT 24
Finished Jun 05 03:49:28 PM PDT 24
Peak memory 203432 kb
Host smart-95470297-7cd0-4792-b7ca-af4b3cdc90a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464925884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1464925884
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3978528307
Short name T1513
Test name
Test status
Simulation time 23402770 ps
CPU time 0.66 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203468 kb
Host smart-0131e8da-b39e-4ce2-aafc-db14e1652ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978528307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3978528307
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.349359947
Short name T1577
Test name
Test status
Simulation time 53907608 ps
CPU time 0.9 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:26 PM PDT 24
Peak memory 203472 kb
Host smart-58852275-2563-45a6-8800-181f0946c280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349359947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.349359947
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1650768322
Short name T200
Test name
Test status
Simulation time 1543966377 ps
CPU time 2.54 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203752 kb
Host smart-eab05554-5520-484b-b7dd-acd0d4fe3e44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650768322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1650768322
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1677967692
Short name T1546
Test name
Test status
Simulation time 80257901 ps
CPU time 1.12 seconds
Started Jun 05 03:49:40 PM PDT 24
Finished Jun 05 03:49:42 PM PDT 24
Peak memory 203596 kb
Host smart-58981629-ee4a-455e-84ce-532ef369a39a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677967692 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1677967692
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.4054991412
Short name T1554
Test name
Test status
Simulation time 42207796 ps
CPU time 0.73 seconds
Started Jun 05 03:49:23 PM PDT 24
Finished Jun 05 03:49:25 PM PDT 24
Peak memory 202852 kb
Host smart-d9ca37cb-f629-4c76-908b-56e1859bae13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054991412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.4054991412
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2029854386
Short name T1557
Test name
Test status
Simulation time 52011631 ps
CPU time 0.67 seconds
Started Jun 05 03:49:22 PM PDT 24
Finished Jun 05 03:49:24 PM PDT 24
Peak memory 203460 kb
Host smart-e444e50d-01d3-4374-8cf9-6b56b8ee5759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029854386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2029854386
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2456875537
Short name T1552
Test name
Test status
Simulation time 56939237 ps
CPU time 0.98 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:26 PM PDT 24
Peak memory 202744 kb
Host smart-0ba3fa96-1768-4bbf-a5ec-a95c84b530cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456875537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2456875537
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.4131030241
Short name T1530
Test name
Test status
Simulation time 51871020 ps
CPU time 1.34 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203064 kb
Host smart-f4eb698c-9116-4a7a-883c-010bf9db64d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131030241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.4131030241
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3794266026
Short name T1570
Test name
Test status
Simulation time 27271985 ps
CPU time 1.16 seconds
Started Jun 05 03:49:23 PM PDT 24
Finished Jun 05 03:49:25 PM PDT 24
Peak memory 212000 kb
Host smart-2d7df65a-0c90-4ce8-b480-dc2d0298cd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794266026 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3794266026
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3882133622
Short name T1549
Test name
Test status
Simulation time 20704097 ps
CPU time 0.74 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203496 kb
Host smart-299761d5-daf3-4287-8d08-51abedc836b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882133622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3882133622
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.257947706
Short name T1563
Test name
Test status
Simulation time 21536475 ps
CPU time 0.73 seconds
Started Jun 05 03:49:21 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203488 kb
Host smart-386697ec-19e7-4592-9abc-70d67a5c158f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257947706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.257947706
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.956690846
Short name T233
Test name
Test status
Simulation time 108763330 ps
CPU time 0.95 seconds
Started Jun 05 03:49:22 PM PDT 24
Finished Jun 05 03:49:24 PM PDT 24
Peak memory 203472 kb
Host smart-3635da68-b29f-4f70-a6bb-b3e58247ecd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956690846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.956690846
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4074253515
Short name T1584
Test name
Test status
Simulation time 217386676 ps
CPU time 1.68 seconds
Started Jun 05 03:49:17 PM PDT 24
Finished Jun 05 03:49:20 PM PDT 24
Peak memory 203600 kb
Host smart-653f8aed-73ce-4c17-8903-93085b601462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074253515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4074253515
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1774123122
Short name T104
Test name
Test status
Simulation time 27471760 ps
CPU time 0.91 seconds
Started Jun 05 03:49:25 PM PDT 24
Finished Jun 05 03:49:27 PM PDT 24
Peak memory 203304 kb
Host smart-d0643d6e-8cc6-4659-a9cd-ecac2496ebfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774123122 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1774123122
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2041342295
Short name T1579
Test name
Test status
Simulation time 18936939 ps
CPU time 0.84 seconds
Started Jun 05 03:49:21 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203524 kb
Host smart-46c42ae8-f578-4bc9-9e3d-3f7471ca7ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041342295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2041342295
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.864327039
Short name T1604
Test name
Test status
Simulation time 18300267 ps
CPU time 0.75 seconds
Started Jun 05 03:49:40 PM PDT 24
Finished Jun 05 03:49:41 PM PDT 24
Peak memory 203448 kb
Host smart-3d3500da-7068-40b7-9a92-9b134bed76fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864327039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.864327039
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.377676138
Short name T1605
Test name
Test status
Simulation time 33184388 ps
CPU time 1.23 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:40 PM PDT 24
Peak memory 203748 kb
Host smart-ce395f7c-801a-48b8-b688-8ae2e659289a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377676138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.377676138
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1613430955
Short name T1511
Test name
Test status
Simulation time 290722413 ps
CPU time 1.87 seconds
Started Jun 05 03:49:18 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203804 kb
Host smart-91e4ac4b-e3bb-4757-bca1-2418b40cbbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613430955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1613430955
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.190530865
Short name T102
Test name
Test status
Simulation time 615291514 ps
CPU time 2.56 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:36 PM PDT 24
Peak memory 203732 kb
Host smart-a6cff1cf-83d7-49b9-9d98-2e9954d1d7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190530865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.190530865
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2919128910
Short name T1553
Test name
Test status
Simulation time 97112699 ps
CPU time 1.44 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203824 kb
Host smart-14348e33-747c-4c60-a049-de52b06d606a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919128910 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2919128910
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4226611372
Short name T225
Test name
Test status
Simulation time 51969473 ps
CPU time 0.9 seconds
Started Jun 05 03:49:23 PM PDT 24
Finished Jun 05 03:49:25 PM PDT 24
Peak memory 202644 kb
Host smart-c57eabcb-1621-46a1-8ad6-1d5e7dbfff2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226611372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4226611372
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2150688764
Short name T1608
Test name
Test status
Simulation time 25291811 ps
CPU time 0.73 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 202700 kb
Host smart-508299bb-88be-4a6d-8c64-849c4658d052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150688764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2150688764
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.193309797
Short name T103
Test name
Test status
Simulation time 188155263 ps
CPU time 2.1 seconds
Started Jun 05 03:49:29 PM PDT 24
Finished Jun 05 03:49:32 PM PDT 24
Peak memory 203764 kb
Host smart-f050ed9a-a842-4ffd-9e65-013a3cb27d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193309797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.193309797
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3022523957
Short name T153
Test name
Test status
Simulation time 46594056 ps
CPU time 1.08 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:34 PM PDT 24
Peak memory 203808 kb
Host smart-eb2344b3-ee20-4006-9498-e7974a191ace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022523957 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3022523957
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1680707002
Short name T232
Test name
Test status
Simulation time 43083772 ps
CPU time 0.68 seconds
Started Jun 05 03:49:34 PM PDT 24
Finished Jun 05 03:49:35 PM PDT 24
Peak memory 203496 kb
Host smart-5d8b53d2-66b4-4381-9091-9df0ca26bf44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680707002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1680707002
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3163610457
Short name T1578
Test name
Test status
Simulation time 17851500 ps
CPU time 0.75 seconds
Started Jun 05 03:49:18 PM PDT 24
Finished Jun 05 03:49:20 PM PDT 24
Peak memory 202700 kb
Host smart-1315e5b1-aad2-42de-8622-c733de4aeebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163610457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3163610457
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2453678092
Short name T107
Test name
Test status
Simulation time 74782531 ps
CPU time 0.96 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203480 kb
Host smart-635fda09-8b10-49c1-a097-ec58c9449b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453678092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2453678092
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3026566565
Short name T1595
Test name
Test status
Simulation time 27383327 ps
CPU time 1.31 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:26 PM PDT 24
Peak memory 203828 kb
Host smart-0069acd0-dd8d-4a70-9195-876282c163d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026566565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3026566565
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.537875000
Short name T1535
Test name
Test status
Simulation time 803901017 ps
CPU time 1.61 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:30 PM PDT 24
Peak memory 203772 kb
Host smart-21a1687c-79c4-40ce-8e25-6b45293d7aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537875000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.537875000
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1529333219
Short name T155
Test name
Test status
Simulation time 119883645 ps
CPU time 1.07 seconds
Started Jun 05 03:49:17 PM PDT 24
Finished Jun 05 03:49:19 PM PDT 24
Peak memory 203996 kb
Host smart-eb22eeeb-dd3a-4f5c-9144-6b59cd1c10ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529333219 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1529333219
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1761682393
Short name T1544
Test name
Test status
Simulation time 19709556 ps
CPU time 0.74 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 202260 kb
Host smart-e00f6168-c40c-4d5c-b8ed-d4879b82d25a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761682393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1761682393
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2938931858
Short name T1550
Test name
Test status
Simulation time 27832660 ps
CPU time 0.67 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:32 PM PDT 24
Peak memory 203384 kb
Host smart-98cfe089-daa8-4494-9bfd-2740ab771f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938931858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2938931858
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.763261367
Short name T228
Test name
Test status
Simulation time 47718187 ps
CPU time 1.11 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:33 PM PDT 24
Peak memory 203720 kb
Host smart-32f0bd13-a3c4-4d5f-ba32-a10b491b8804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763261367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.763261367
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1618882732
Short name T1522
Test name
Test status
Simulation time 42233247 ps
CPU time 1.31 seconds
Started Jun 05 03:49:21 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203820 kb
Host smart-690bd745-01e2-4422-a6cf-56049b6047d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618882732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1618882732
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2672948576
Short name T212
Test name
Test status
Simulation time 28789552 ps
CPU time 1.19 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 203768 kb
Host smart-9b10971a-17aa-46e4-8589-17d25e62011d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672948576 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2672948576
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3545293183
Short name T230
Test name
Test status
Simulation time 78266213 ps
CPU time 0.8 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 203508 kb
Host smart-8c79d9bb-c512-440b-8da4-5f38fe62251a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545293183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3545293183
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2426306418
Short name T1566
Test name
Test status
Simulation time 27788170 ps
CPU time 0.68 seconds
Started Jun 05 03:49:26 PM PDT 24
Finished Jun 05 03:49:27 PM PDT 24
Peak memory 203476 kb
Host smart-f5b9b7af-fffe-44b0-8b0e-0f220ba3edd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426306418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2426306418
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2292263145
Short name T234
Test name
Test status
Simulation time 30978086 ps
CPU time 1.16 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:27 PM PDT 24
Peak memory 203552 kb
Host smart-9b79f501-3cc5-440c-934a-b885d0bf0883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292263145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2292263145
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2133546902
Short name T1533
Test name
Test status
Simulation time 146225004 ps
CPU time 2.06 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:36 PM PDT 24
Peak memory 203008 kb
Host smart-3483bbb7-f543-4260-8c54-b8cbfc8d369b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133546902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2133546902
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4003413064
Short name T206
Test name
Test status
Simulation time 301009641 ps
CPU time 1.6 seconds
Started Jun 05 03:49:33 PM PDT 24
Finished Jun 05 03:49:35 PM PDT 24
Peak memory 203796 kb
Host smart-068b9d13-0946-47ee-a7fd-0632dce84f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003413064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.4003413064
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3380097458
Short name T213
Test name
Test status
Simulation time 51269438 ps
CPU time 1.24 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 203772 kb
Host smart-55f6f321-1e11-4ce6-bb01-bea09b3033d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380097458 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3380097458
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1214211293
Short name T227
Test name
Test status
Simulation time 23569486 ps
CPU time 0.71 seconds
Started Jun 05 03:49:20 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203144 kb
Host smart-86aa4d2f-ea26-4173-87a8-042a5a5560c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214211293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1214211293
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3063478753
Short name T1515
Test name
Test status
Simulation time 48930558 ps
CPU time 0.62 seconds
Started Jun 05 03:49:40 PM PDT 24
Finished Jun 05 03:49:41 PM PDT 24
Peak memory 203468 kb
Host smart-7ef81629-ce32-4206-9453-0a717b26278b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063478753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3063478753
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.998369560
Short name T105
Test name
Test status
Simulation time 43649007 ps
CPU time 0.97 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203108 kb
Host smart-150e865d-c7e5-417b-b06b-7c093e24adf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998369560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.998369560
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3950121935
Short name T100
Test name
Test status
Simulation time 309669397 ps
CPU time 1.33 seconds
Started Jun 05 03:49:36 PM PDT 24
Finished Jun 05 03:49:38 PM PDT 24
Peak memory 203836 kb
Host smart-a1e65f08-a716-445f-adfa-d16ffb8c73aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950121935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3950121935
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3000723976
Short name T207
Test name
Test status
Simulation time 170329517 ps
CPU time 1.45 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203792 kb
Host smart-7be1cafe-e2b6-49af-afbf-74e2d1194e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000723976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3000723976
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2744929466
Short name T1607
Test name
Test status
Simulation time 75467588 ps
CPU time 0.81 seconds
Started Jun 05 03:49:46 PM PDT 24
Finished Jun 05 03:49:48 PM PDT 24
Peak memory 203556 kb
Host smart-883d935b-b422-45ad-b3d1-8a22bad91c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744929466 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2744929466
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1497711599
Short name T1534
Test name
Test status
Simulation time 18438597 ps
CPU time 0.77 seconds
Started Jun 05 03:49:23 PM PDT 24
Finished Jun 05 03:49:25 PM PDT 24
Peak memory 203176 kb
Host smart-0435ae21-57bb-4d41-90a6-bb83e9a4cd3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497711599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1497711599
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3652294388
Short name T1580
Test name
Test status
Simulation time 122445828 ps
CPU time 0.65 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:42 PM PDT 24
Peak memory 203460 kb
Host smart-6798e090-02f0-4eee-a1ff-01e30d459452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652294388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3652294388
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2138489407
Short name T1583
Test name
Test status
Simulation time 89199411 ps
CPU time 1.09 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 203520 kb
Host smart-3f7ec9fc-1ef9-4ef3-b79f-28394a752cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138489407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2138489407
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.753914502
Short name T1573
Test name
Test status
Simulation time 117102508 ps
CPU time 1.63 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 203796 kb
Host smart-58377e7e-15ea-4cec-ae2b-13d35e5e4bae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753914502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.753914502
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.858919224
Short name T1532
Test name
Test status
Simulation time 53919348 ps
CPU time 1.65 seconds
Started Jun 05 03:49:21 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203796 kb
Host smart-c479aa28-315e-4bdf-bc6b-b7963e14e93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858919224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.858919224
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2097733562
Short name T1601
Test name
Test status
Simulation time 635746280 ps
CPU time 2.24 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 202192 kb
Host smart-e7ab6dbc-45cf-46df-bc79-f35233a5d954
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097733562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2097733562
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1023947049
Short name T217
Test name
Test status
Simulation time 448839526 ps
CPU time 6 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:19 PM PDT 24
Peak memory 203292 kb
Host smart-ab10c7c5-495d-4c0c-a7b3-c4bb7e85ffb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023947049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1023947049
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2195623649
Short name T215
Test name
Test status
Simulation time 59514414 ps
CPU time 0.82 seconds
Started Jun 05 03:49:22 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203488 kb
Host smart-b104d58f-759c-4fb8-81ad-a85a131e9b28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195623649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2195623649
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1837239057
Short name T1592
Test name
Test status
Simulation time 27024467 ps
CPU time 0.93 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:10 PM PDT 24
Peak memory 203520 kb
Host smart-262f7d52-60f8-4fda-85b0-aff2dd68cc4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837239057 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1837239057
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3868298266
Short name T1560
Test name
Test status
Simulation time 27041997 ps
CPU time 0.81 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 203544 kb
Host smart-9635f687-f588-414a-955b-f97aa4525b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868298266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3868298266
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1343733506
Short name T1543
Test name
Test status
Simulation time 33189968 ps
CPU time 0.68 seconds
Started Jun 05 03:49:08 PM PDT 24
Finished Jun 05 03:49:10 PM PDT 24
Peak memory 203416 kb
Host smart-7955273c-e976-4382-9825-9728dcc77962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343733506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1343733506
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2476559741
Short name T1539
Test name
Test status
Simulation time 71844248 ps
CPU time 1.25 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 204148 kb
Host smart-f93786fa-95d4-42a4-ad34-5eecf0559f79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476559741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2476559741
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.374894266
Short name T108
Test name
Test status
Simulation time 160156807 ps
CPU time 2.92 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 202996 kb
Host smart-4cd130e8-fbef-4c6a-a714-3db459c33d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374894266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.374894266
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2825720003
Short name T199
Test name
Test status
Simulation time 167187158 ps
CPU time 2.33 seconds
Started Jun 05 03:49:18 PM PDT 24
Finished Jun 05 03:49:22 PM PDT 24
Peak memory 202952 kb
Host smart-124f2ce5-0b71-4ff9-bf16-921e4e8960fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825720003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2825720003
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2274964398
Short name T1559
Test name
Test status
Simulation time 22064728 ps
CPU time 0.68 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:45 PM PDT 24
Peak memory 203456 kb
Host smart-5bc5248b-b058-4541-a538-92a4d61259a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274964398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2274964398
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3485297361
Short name T1507
Test name
Test status
Simulation time 18459888 ps
CPU time 0.81 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:41 PM PDT 24
Peak memory 202700 kb
Host smart-ef320804-4139-4aa6-91f5-853906c1915d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485297361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3485297361
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4230559881
Short name T1609
Test name
Test status
Simulation time 21231194 ps
CPU time 0.63 seconds
Started Jun 05 03:49:16 PM PDT 24
Finished Jun 05 03:49:18 PM PDT 24
Peak memory 203496 kb
Host smart-350af859-ca45-4fb0-bf8b-84d18f5ff763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230559881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4230559881
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.195191904
Short name T1562
Test name
Test status
Simulation time 19932905 ps
CPU time 0.64 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:32 PM PDT 24
Peak memory 203460 kb
Host smart-a8e0eb85-1019-4a24-9f1a-b8293dd19b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195191904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.195191904
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.994513405
Short name T1556
Test name
Test status
Simulation time 45182574 ps
CPU time 0.67 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 203472 kb
Host smart-21aba826-2f1b-4541-b8ab-b22147e310fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994513405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.994513405
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3659474649
Short name T1599
Test name
Test status
Simulation time 55158663 ps
CPU time 0.66 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:31 PM PDT 24
Peak memory 203460 kb
Host smart-0b54db94-6c86-4a77-9412-0ac204985884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659474649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3659474649
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3448340763
Short name T1521
Test name
Test status
Simulation time 63242405 ps
CPU time 0.68 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 203356 kb
Host smart-0de38243-9ee8-4adc-a7c6-e7dde15ff324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448340763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3448340763
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.42813370
Short name T1512
Test name
Test status
Simulation time 16899920 ps
CPU time 0.81 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:33 PM PDT 24
Peak memory 202688 kb
Host smart-81787b44-dcb1-4a21-999b-e749d176caec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.42813370
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2452471167
Short name T1525
Test name
Test status
Simulation time 53143773 ps
CPU time 0.68 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:31 PM PDT 24
Peak memory 203452 kb
Host smart-46d1f0ea-aa73-4574-814a-1d69ed2fd424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452471167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2452471167
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.970462845
Short name T1506
Test name
Test status
Simulation time 20398248 ps
CPU time 0.69 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:40 PM PDT 24
Peak memory 203448 kb
Host smart-4d4d1702-13fa-4d5c-a84d-b5266711f4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970462845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.970462845
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2419297056
Short name T214
Test name
Test status
Simulation time 65388201 ps
CPU time 1.44 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 203776 kb
Host smart-6f64cbdd-5c36-41f9-9cd5-5043396573f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419297056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2419297056
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.735160009
Short name T1569
Test name
Test status
Simulation time 21386279 ps
CPU time 0.73 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203512 kb
Host smart-a03b8ecd-0dd5-437a-9f14-e897b25b76b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735160009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.735160009
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1885594185
Short name T1518
Test name
Test status
Simulation time 26518004 ps
CPU time 0.8 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:11 PM PDT 24
Peak memory 203448 kb
Host smart-b77d8e91-50b4-44e4-aa09-a7cb0aceb35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885594185 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1885594185
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3803750269
Short name T224
Test name
Test status
Simulation time 52475603 ps
CPU time 0.9 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 202712 kb
Host smart-b563cb8a-8fb8-4abe-ae7e-b38e2e920bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803750269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3803750269
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2638142102
Short name T1524
Test name
Test status
Simulation time 16104323 ps
CPU time 0.73 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 201908 kb
Host smart-62e30fc0-b8ca-470e-bd8d-5f1fc74618b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638142102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2638142102
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2649163301
Short name T1545
Test name
Test status
Simulation time 42367380 ps
CPU time 1.02 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 201292 kb
Host smart-d7641b5b-4d4e-46a1-873b-f3fa4e0a1083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649163301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2649163301
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2155784459
Short name T1520
Test name
Test status
Simulation time 54971863 ps
CPU time 2.96 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:19 PM PDT 24
Peak memory 202956 kb
Host smart-9a3d588f-0378-440a-9ec9-f2e7fe8403ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155784459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2155784459
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.592565074
Short name T203
Test name
Test status
Simulation time 53172387 ps
CPU time 1.43 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 202944 kb
Host smart-a9ee4153-4728-4fe5-a01b-ab2ffd5fc4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592565074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.592565074
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2557050052
Short name T1582
Test name
Test status
Simulation time 27039919 ps
CPU time 0.68 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 203448 kb
Host smart-ccb0653c-264e-4159-be47-46b9d2b3e4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557050052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2557050052
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.647854198
Short name T1568
Test name
Test status
Simulation time 39546379 ps
CPU time 0.65 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:45 PM PDT 24
Peak memory 203272 kb
Host smart-cee5963d-332c-4794-a2c6-74de6320b3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647854198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.647854198
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2061917950
Short name T1575
Test name
Test status
Simulation time 36016888 ps
CPU time 0.76 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:30 PM PDT 24
Peak memory 203432 kb
Host smart-df201c9e-22b4-4b07-9f1b-06c2baaf4b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061917950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2061917950
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.327952833
Short name T1540
Test name
Test status
Simulation time 54004023 ps
CPU time 0.69 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:41 PM PDT 24
Peak memory 203456 kb
Host smart-c60edd17-ba39-484d-8697-716256793b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327952833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.327952833
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3116637923
Short name T1529
Test name
Test status
Simulation time 20463173 ps
CPU time 0.66 seconds
Started Jun 05 03:49:27 PM PDT 24
Finished Jun 05 03:49:28 PM PDT 24
Peak memory 203444 kb
Host smart-4e65d964-0891-4692-b9ef-cee8cdcce939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116637923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3116637923
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.892230969
Short name T1587
Test name
Test status
Simulation time 25099245 ps
CPU time 0.66 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:29 PM PDT 24
Peak memory 203456 kb
Host smart-7f80d16e-75ce-45d5-b009-4c05ba15cc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892230969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.892230969
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3423258088
Short name T1509
Test name
Test status
Simulation time 14537476 ps
CPU time 0.7 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:34 PM PDT 24
Peak memory 203476 kb
Host smart-bfffc194-f745-495c-b16d-df2f182d9b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423258088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3423258088
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3403356412
Short name T1598
Test name
Test status
Simulation time 16202157 ps
CPU time 0.65 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:38 PM PDT 24
Peak memory 203464 kb
Host smart-8bf91339-842e-4ec1-94f5-41f9b92a01b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403356412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3403356412
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1014765942
Short name T1600
Test name
Test status
Simulation time 51731829 ps
CPU time 0.67 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:49:52 PM PDT 24
Peak memory 203432 kb
Host smart-aabf6708-9750-4839-8c93-5742ecfc263d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014765942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1014765942
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1750774552
Short name T1519
Test name
Test status
Simulation time 39478179 ps
CPU time 0.68 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:45 PM PDT 24
Peak memory 203468 kb
Host smart-06fcb08c-15c6-4bed-86ad-9da60ee462d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750774552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1750774552
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3250674323
Short name T1516
Test name
Test status
Simulation time 30649523 ps
CPU time 1.31 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:11 PM PDT 24
Peak memory 203656 kb
Host smart-0dc1078c-83fb-41dd-a5bd-aa6a48f10cde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250674323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3250674323
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3412278055
Short name T1523
Test name
Test status
Simulation time 157111229 ps
CPU time 5.6 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:18 PM PDT 24
Peak memory 203720 kb
Host smart-a7d32315-b0b0-403b-8c1d-3c2aea7fda88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412278055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3412278055
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1097683237
Short name T1597
Test name
Test status
Simulation time 20173514 ps
CPU time 0.75 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 202892 kb
Host smart-2e764ec6-03dc-410e-b4d2-eec0956b17b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097683237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1097683237
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2931606921
Short name T1564
Test name
Test status
Simulation time 44812115 ps
CPU time 1.38 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 202996 kb
Host smart-c519564e-17bc-4e94-980b-077f00328a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931606921 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2931606921
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1425682376
Short name T219
Test name
Test status
Simulation time 25610770 ps
CPU time 0.79 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 203520 kb
Host smart-5b862007-52cf-4e9d-b659-44d2e1faf8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425682376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1425682376
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3065455110
Short name T1514
Test name
Test status
Simulation time 23201213 ps
CPU time 0.67 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 203396 kb
Host smart-ec02b8ce-e349-4f2b-92f4-a2222a9479bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065455110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3065455110
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2802053891
Short name T229
Test name
Test status
Simulation time 47486716 ps
CPU time 0.9 seconds
Started Jun 05 03:49:09 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 201384 kb
Host smart-162efc68-a7c1-4cb7-b60e-8cc2aeefc822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802053891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2802053891
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3367680065
Short name T1594
Test name
Test status
Simulation time 43704030 ps
CPU time 2.23 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203784 kb
Host smart-681fe5e0-4c35-4e19-bdd4-77a07aef0f35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367680065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3367680065
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3202474661
Short name T204
Test name
Test status
Simulation time 252408261 ps
CPU time 2.55 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203756 kb
Host smart-3c99d9a5-e364-401d-94fa-c0438bbf5415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202474661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3202474661
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.508815025
Short name T1510
Test name
Test status
Simulation time 35343098 ps
CPU time 0.64 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:40 PM PDT 24
Peak memory 203456 kb
Host smart-7960e4f8-d539-4173-8771-134287eac9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508815025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.508815025
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3802311721
Short name T1561
Test name
Test status
Simulation time 23707358 ps
CPU time 0.64 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:39 PM PDT 24
Peak memory 203496 kb
Host smart-7a70ce33-c888-4f01-bb85-4247391dca77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802311721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3802311721
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1002749142
Short name T1567
Test name
Test status
Simulation time 75373322 ps
CPU time 0.67 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 203392 kb
Host smart-e88cff09-e938-4010-98ac-844e76bfa247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002749142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1002749142
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3055177984
Short name T1531
Test name
Test status
Simulation time 17499973 ps
CPU time 0.66 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:30 PM PDT 24
Peak memory 203516 kb
Host smart-a5edfe4c-81ac-4b61-9cdf-8394ea5ef774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055177984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3055177984
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3791964086
Short name T1547
Test name
Test status
Simulation time 44342194 ps
CPU time 0.7 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:40 PM PDT 24
Peak memory 203500 kb
Host smart-d1846fbd-4f47-4f79-87fb-9e385af5c055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791964086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3791964086
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.98866338
Short name T1536
Test name
Test status
Simulation time 42683851 ps
CPU time 0.75 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:42 PM PDT 24
Peak memory 203448 kb
Host smart-3641651c-0b07-46b9-a3af-c0e66b9a2989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98866338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.98866338
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.30137297
Short name T1606
Test name
Test status
Simulation time 18234085 ps
CPU time 0.64 seconds
Started Jun 05 03:49:27 PM PDT 24
Finished Jun 05 03:49:28 PM PDT 24
Peak memory 203448 kb
Host smart-b8c93f98-9f6b-4942-9bc4-ca2d5eec8366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.30137297
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.955133811
Short name T1588
Test name
Test status
Simulation time 18047730 ps
CPU time 0.68 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:29 PM PDT 24
Peak memory 203424 kb
Host smart-dcfe69e1-2480-4afd-906b-c40225d77b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955133811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.955133811
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.4195140090
Short name T1590
Test name
Test status
Simulation time 19470567 ps
CPU time 0.69 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:33 PM PDT 24
Peak memory 203420 kb
Host smart-3fcf843c-af4e-450d-afcf-4b3c10cb6fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195140090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.4195140090
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2955506083
Short name T1508
Test name
Test status
Simulation time 16995121 ps
CPU time 0.66 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 203516 kb
Host smart-9df14c62-e27a-4cdf-8348-8e536e3bc778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955506083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2955506083
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3498222741
Short name T1528
Test name
Test status
Simulation time 35234424 ps
CPU time 1.67 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:13 PM PDT 24
Peak memory 214160 kb
Host smart-dd019a98-73fa-428e-9b8a-bbd78d805b10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498222741 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3498222741
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2810298207
Short name T1551
Test name
Test status
Simulation time 27091461 ps
CPU time 0.69 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203480 kb
Host smart-e88749b1-9ea4-4af4-99bf-6a945a989333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810298207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2810298207
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1184748102
Short name T231
Test name
Test status
Simulation time 99174598 ps
CPU time 1.18 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203748 kb
Host smart-82f2fe77-ee28-4458-bd91-0dc150bbd49a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184748102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1184748102
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1629278987
Short name T1571
Test name
Test status
Simulation time 67299516 ps
CPU time 1.45 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203860 kb
Host smart-131076f0-21fe-4220-9439-8d7fd0e9150f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629278987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1629278987
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2122626234
Short name T1603
Test name
Test status
Simulation time 804180078 ps
CPU time 2.62 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 202948 kb
Host smart-6f7e0616-aa33-4d56-8c52-9373628caeae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122626234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2122626234
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3115386586
Short name T196
Test name
Test status
Simulation time 23226575 ps
CPU time 1.14 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 202828 kb
Host smart-ed467ad4-9b62-43fc-8e90-59a85315b12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115386586 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3115386586
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2216819622
Short name T226
Test name
Test status
Simulation time 67706818 ps
CPU time 0.79 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:12 PM PDT 24
Peak memory 202748 kb
Host smart-3d24513e-fd00-4ebd-9e54-61ee885ab16d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216819622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2216819622
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3687333112
Short name T1574
Test name
Test status
Simulation time 16428644 ps
CPU time 0.7 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 203484 kb
Host smart-38ccbbd8-f0ae-40c8-9ad5-4d086873cc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687333112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3687333112
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.656586185
Short name T1538
Test name
Test status
Simulation time 29599856 ps
CPU time 1.19 seconds
Started Jun 05 03:49:13 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 203740 kb
Host smart-a10a287e-5859-4edd-a1ef-9243d6fae45d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656586185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.656586185
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1298484117
Short name T197
Test name
Test status
Simulation time 221844898 ps
CPU time 1.58 seconds
Started Jun 05 03:49:11 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203164 kb
Host smart-ed42fbef-592e-4cba-ad99-ea3bea17088e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298484117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1298484117
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2145546347
Short name T210
Test name
Test status
Simulation time 221898865 ps
CPU time 1.49 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:17 PM PDT 24
Peak memory 203728 kb
Host smart-754c1166-f317-4113-a331-920667d6b29e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145546347 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2145546347
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1821330881
Short name T216
Test name
Test status
Simulation time 146314243 ps
CPU time 0.85 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203532 kb
Host smart-cd3cf489-c95c-4bf3-8dbe-1c41b6eeb119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821330881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1821330881
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2913449062
Short name T1589
Test name
Test status
Simulation time 68518645 ps
CPU time 0.72 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:16 PM PDT 24
Peak memory 203488 kb
Host smart-a35e85e7-b288-4132-9f3f-4fbac308bdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913449062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2913449062
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3084212025
Short name T1548
Test name
Test status
Simulation time 65563671 ps
CPU time 1.28 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:17 PM PDT 24
Peak memory 202872 kb
Host smart-64c46d60-4ac6-4c53-bc6f-9f1a755e967e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084212025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3084212025
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3870515533
Short name T1565
Test name
Test status
Simulation time 119581962 ps
CPU time 2.65 seconds
Started Jun 05 03:49:10 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203436 kb
Host smart-840e76a1-7bf0-47cc-a381-42d46786d1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870515533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3870515533
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1942304357
Short name T261
Test name
Test status
Simulation time 299650504 ps
CPU time 1.64 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:15 PM PDT 24
Peak memory 203076 kb
Host smart-6a7b710b-b60f-4276-85f1-21852574c587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942304357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1942304357
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1708144427
Short name T201
Test name
Test status
Simulation time 32773820 ps
CPU time 1.01 seconds
Started Jun 05 03:49:21 PM PDT 24
Finished Jun 05 03:49:23 PM PDT 24
Peak memory 203604 kb
Host smart-69644107-0090-4eea-8585-bae984f62b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708144427 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1708144427
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1615726540
Short name T221
Test name
Test status
Simulation time 50474244 ps
CPU time 0.76 seconds
Started Jun 05 03:49:19 PM PDT 24
Finished Jun 05 03:49:21 PM PDT 24
Peak memory 203532 kb
Host smart-d1d1b6be-ad68-465f-9dd7-ec378892715b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615726540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1615726540
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.623660762
Short name T1526
Test name
Test status
Simulation time 23153410 ps
CPU time 0.66 seconds
Started Jun 05 03:49:12 PM PDT 24
Finished Jun 05 03:49:14 PM PDT 24
Peak memory 203484 kb
Host smart-505a86b0-b6a3-46c5-ac9b-40dd2f479224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623660762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.623660762
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1378832347
Short name T1572
Test name
Test status
Simulation time 58851831 ps
CPU time 0.89 seconds
Started Jun 05 03:49:16 PM PDT 24
Finished Jun 05 03:49:18 PM PDT 24
Peak memory 203492 kb
Host smart-6a7196cb-a7a8-43e1-adc6-16b28b60a71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378832347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1378832347
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1131361427
Short name T120
Test name
Test status
Simulation time 994980622 ps
CPU time 2.7 seconds
Started Jun 05 03:49:14 PM PDT 24
Finished Jun 05 03:49:18 PM PDT 24
Peak memory 203380 kb
Host smart-5973d01a-0d2d-4f60-8947-ef2885a919f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131361427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1131361427
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1997960594
Short name T1585
Test name
Test status
Simulation time 25270169 ps
CPU time 1.08 seconds
Started Jun 05 03:49:23 PM PDT 24
Finished Jun 05 03:49:25 PM PDT 24
Peak memory 203596 kb
Host smart-23e4e145-2648-45d0-9970-dfbf66025537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997960594 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1997960594
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3386048910
Short name T1586
Test name
Test status
Simulation time 29747222 ps
CPU time 0.84 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:33 PM PDT 24
Peak memory 203504 kb
Host smart-4e932b44-6fc3-4380-bd86-c458d86ff1d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386048910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3386048910
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.234275623
Short name T1542
Test name
Test status
Simulation time 24597886 ps
CPU time 0.68 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 203460 kb
Host smart-a0d39a16-b189-4b12-bb1b-a43f17265c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234275623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.234275623
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.27680388
Short name T1537
Test name
Test status
Simulation time 158789608 ps
CPU time 0.91 seconds
Started Jun 05 03:49:24 PM PDT 24
Finished Jun 05 03:49:26 PM PDT 24
Peak memory 203552 kb
Host smart-99527524-4126-4f1b-8b22-f58fa19ca62a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outs
tanding.27680388
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.990251067
Short name T1558
Test name
Test status
Simulation time 73356313 ps
CPU time 1.89 seconds
Started Jun 05 03:49:25 PM PDT 24
Finished Jun 05 03:49:28 PM PDT 24
Peak memory 203792 kb
Host smart-dabacf6f-87f9-4fcf-b526-9e4b7a31cfc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990251067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.990251067
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1766087152
Short name T192
Test name
Test status
Simulation time 187365333 ps
CPU time 1.57 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:34 PM PDT 24
Peak memory 204156 kb
Host smart-dce10878-7791-4704-8732-c2c1d95caabd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766087152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1766087152
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1799007520
Short name T758
Test name
Test status
Simulation time 17469344 ps
CPU time 0.67 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:34:36 PM PDT 24
Peak memory 204752 kb
Host smart-4cfed23e-e794-4f83-a8ec-dc9ebfc10d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799007520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1799007520
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3240119169
Short name T1144
Test name
Test status
Simulation time 644524959 ps
CPU time 2.25 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 221264 kb
Host smart-7d603169-c182-475e-9ede-96dba5f8a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240119169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3240119169
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1953522465
Short name T939
Test name
Test status
Simulation time 261845571 ps
CPU time 13.86 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 255032 kb
Host smart-155a6715-4c33-4455-8734-89745c552762
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953522465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1953522465
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.521350382
Short name T1456
Test name
Test status
Simulation time 2537971795 ps
CPU time 86.4 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:36:02 PM PDT 24
Peak memory 518756 kb
Host smart-24579989-d2d3-4684-9ba7-32f242d19aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521350382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.521350382
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.807633197
Short name T1074
Test name
Test status
Simulation time 3759763203 ps
CPU time 142.01 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:37:02 PM PDT 24
Peak memory 642068 kb
Host smart-87518966-4095-484f-a5bb-6a5022a547a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807633197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.807633197
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3677626711
Short name T595
Test name
Test status
Simulation time 123249462 ps
CPU time 1.16 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 205008 kb
Host smart-503be367-ab92-466f-9926-fc2c8aad835f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677626711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3677626711
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.820759440
Short name T949
Test name
Test status
Simulation time 1377488580 ps
CPU time 6.11 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:34:42 PM PDT 24
Peak memory 205028 kb
Host smart-47804ab8-d37d-41ed-b4c5-077386b4a47a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820759440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.820759440
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1703436149
Short name T1445
Test name
Test status
Simulation time 22364908875 ps
CPU time 119.11 seconds
Started Jun 05 04:34:21 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 1293096 kb
Host smart-5d2c7a2a-9ea7-463e-9206-606283ba2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703436149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1703436149
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.827208744
Short name T877
Test name
Test status
Simulation time 297929623 ps
CPU time 4.03 seconds
Started Jun 05 04:34:20 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 205100 kb
Host smart-e04af130-be93-41f9-bec2-836f7a9a99a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827208744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.827208744
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.2833887516
Short name T80
Test name
Test status
Simulation time 77537633 ps
CPU time 0.69 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:40 PM PDT 24
Peak memory 204716 kb
Host smart-6f51988e-8eda-4435-b6d1-4c394d4beb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833887516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2833887516
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3151486609
Short name T852
Test name
Test status
Simulation time 18160891000 ps
CPU time 1191.83 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:54:18 PM PDT 24
Peak memory 3458464 kb
Host smart-981c6dbb-5331-4613-bcbf-9f484ef8e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151486609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3151486609
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2894920492
Short name T846
Test name
Test status
Simulation time 5311026649 ps
CPU time 25.77 seconds
Started Jun 05 04:34:26 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 302272 kb
Host smart-e6929c69-b1be-46da-b331-ef0253f32aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894920492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2894920492
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3440007744
Short name T986
Test name
Test status
Simulation time 30780612576 ps
CPU time 873.83 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:49:13 PM PDT 24
Peak memory 1567308 kb
Host smart-798b7aee-8b8d-448f-888c-be9656e244a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440007744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3440007744
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2284634074
Short name T968
Test name
Test status
Simulation time 2535662476 ps
CPU time 6.28 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:34:48 PM PDT 24
Peak memory 219716 kb
Host smart-a224902b-4bda-480f-b75f-e557eb52b5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284634074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2284634074
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.208402082
Short name T188
Test name
Test status
Simulation time 78664931 ps
CPU time 0.93 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:34:35 PM PDT 24
Peak memory 222144 kb
Host smart-4a8abcf9-1bab-44e3-82b1-cb2b44e9de8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208402082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.208402082
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2681678519
Short name T849
Test name
Test status
Simulation time 955952861 ps
CPU time 4.32 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:45 PM PDT 24
Peak memory 213328 kb
Host smart-6e65c395-1cd9-4cce-a7b4-84f06f8f67b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681678519 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2681678519
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3453843953
Short name T735
Test name
Test status
Simulation time 10791555208 ps
CPU time 4.48 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 248972 kb
Host smart-5c9b7c92-ffe9-4817-89e1-8471b183a757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453843953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3453843953
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.4292932675
Short name T1161
Test name
Test status
Simulation time 1071422335 ps
CPU time 5.18 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 205052 kb
Host smart-cb54338d-754c-4311-8325-6edf0156e040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292932675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.4292932675
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.599299774
Short name T1093
Test name
Test status
Simulation time 1121572483 ps
CPU time 4.14 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 205136 kb
Host smart-e088f0d5-878a-42f5-b898-7f625999c7a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599299774 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.599299774
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1896221321
Short name T1152
Test name
Test status
Simulation time 2575237287 ps
CPU time 6.97 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:50 PM PDT 24
Peak memory 213396 kb
Host smart-bab3e79f-b9a1-4225-9c62-2c196668bb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896221321 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1896221321
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.361405272
Short name T171
Test name
Test status
Simulation time 15702131736 ps
CPU time 104.15 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:36:14 PM PDT 24
Peak memory 1799060 kb
Host smart-f8cadc62-1c4f-4445-b653-d061b4847dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361405272 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.361405272
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.64546036
Short name T695
Test name
Test status
Simulation time 720433258 ps
CPU time 11.74 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 205068 kb
Host smart-969f36e6-f57e-480a-be9b-613ad034fe66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64546036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targe
t_smoke.64546036
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1569512717
Short name T661
Test name
Test status
Simulation time 2407265327 ps
CPU time 53.47 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 206380 kb
Host smart-92fe5a1c-04ca-4953-9efe-58961fec8394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569512717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1569512717
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.4056619353
Short name T169
Test name
Test status
Simulation time 49805337083 ps
CPU time 1212.24 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:55:00 PM PDT 24
Peak memory 7462392 kb
Host smart-9f827a98-28dd-46c7-b610-482cf31c0905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056619353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.4056619353
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3550015053
Short name T1065
Test name
Test status
Simulation time 15213495457 ps
CPU time 875.43 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:49:17 PM PDT 24
Peak memory 3713336 kb
Host smart-6d505205-44ea-469c-b39f-d5ce9feebd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550015053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3550015053
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.2550978960
Short name T940
Test name
Test status
Simulation time 1595676642 ps
CPU time 7.22 seconds
Started Jun 05 04:34:43 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 221280 kb
Host smart-f2f19458-6d4a-4762-9738-d5a5df529449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550978960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.2550978960
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.2628168603
Short name T1118
Test name
Test status
Simulation time 1623587412 ps
CPU time 19.62 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 205080 kb
Host smart-b3fa7d8e-ed83-4332-ab8a-f9a145087b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628168603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2628168603
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3489931047
Short name T857
Test name
Test status
Simulation time 782521292 ps
CPU time 2.76 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 213332 kb
Host smart-62621a42-cd5e-4ad9-89e0-8675952adef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489931047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3489931047
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2440912332
Short name T579
Test name
Test status
Simulation time 574593455 ps
CPU time 7.53 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 228820 kb
Host smart-a5194622-d124-4a01-9a86-b19ad8907f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440912332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2440912332
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.4206323702
Short name T1023
Test name
Test status
Simulation time 2638771175 ps
CPU time 230.38 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:38:27 PM PDT 24
Peak memory 841604 kb
Host smart-a1c0b058-6884-41f4-ba01-be8617358d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206323702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.4206323702
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2855958597
Short name T1000
Test name
Test status
Simulation time 3595730484 ps
CPU time 118.36 seconds
Started Jun 05 04:34:27 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 463392 kb
Host smart-f185465b-8997-4b3d-9afc-8d4d1cf88085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855958597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2855958597
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1985442678
Short name T848
Test name
Test status
Simulation time 614101866 ps
CPU time 1.07 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:42 PM PDT 24
Peak memory 204996 kb
Host smart-8e9c97b6-ee6c-45b2-9a11-761992a654a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985442678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1985442678
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1335749527
Short name T1371
Test name
Test status
Simulation time 10522642270 ps
CPU time 159.75 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:37:14 PM PDT 24
Peak memory 779776 kb
Host smart-fcee3f3e-fba5-4f5a-a37f-5d1db6067462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335749527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1335749527
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1869736250
Short name T275
Test name
Test status
Simulation time 963416102 ps
CPU time 7.46 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 205080 kb
Host smart-40cb6a74-4f12-4cb5-912c-c91d01375bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869736250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1869736250
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.2497775430
Short name T386
Test name
Test status
Simulation time 86833234 ps
CPU time 0.69 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 204720 kb
Host smart-c673421c-97d2-4ae4-867c-1442409896cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497775430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2497775430
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3461714012
Short name T1028
Test name
Test status
Simulation time 53109891273 ps
CPU time 516.98 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:43:14 PM PDT 24
Peak memory 1667596 kb
Host smart-52e55958-dd57-4a03-a48c-494fd5ce57db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461714012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3461714012
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3396303662
Short name T384
Test name
Test status
Simulation time 5592995638 ps
CPU time 22.95 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 347548 kb
Host smart-504a54a9-c6b3-4430-a25a-37f1f5c16f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396303662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3396303662
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2297320437
Short name T54
Test name
Test status
Simulation time 16980420905 ps
CPU time 930.76 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:50:16 PM PDT 24
Peak memory 1900144 kb
Host smart-77db1f8a-5dde-4d22-b76e-89ab05b431b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297320437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2297320437
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2223543056
Short name T743
Test name
Test status
Simulation time 2435029504 ps
CPU time 29.08 seconds
Started Jun 05 04:34:48 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 213412 kb
Host smart-ae290e54-af96-490d-a573-6bafe5eb957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223543056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2223543056
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2402964610
Short name T300
Test name
Test status
Simulation time 2889323166 ps
CPU time 4.06 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:34:51 PM PDT 24
Peak memory 213392 kb
Host smart-91cbd242-938b-49c5-8e62-87df356a3c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402964610 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2402964610
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2444907781
Short name T1313
Test name
Test status
Simulation time 10196262685 ps
CPU time 11.98 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:35:04 PM PDT 24
Peak memory 234488 kb
Host smart-3a487a57-9fc0-4e11-884a-5ccba89dedf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444907781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2444907781
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1214480625
Short name T1435
Test name
Test status
Simulation time 10303833956 ps
CPU time 16.71 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:55 PM PDT 24
Peak memory 310900 kb
Host smart-2ed24b83-5005-4149-bdbf-eb848b53e1ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214480625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1214480625
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.4266978456
Short name T439
Test name
Test status
Simulation time 1096307861 ps
CPU time 3.26 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:39 PM PDT 24
Peak memory 205136 kb
Host smart-c2f442bc-f34f-4fb5-8ff4-56abb32ec82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266978456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.4266978456
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.686980006
Short name T19
Test name
Test status
Simulation time 7040068869 ps
CPU time 10.39 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 213428 kb
Host smart-ddf7eb60-b055-4c6b-b132-2c3d6b3d5749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686980006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.686980006
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.4077989291
Short name T266
Test name
Test status
Simulation time 574411147 ps
CPU time 2.05 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 205112 kb
Host smart-9215c8bb-3fda-4bbf-b835-28711393eec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077989291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.4077989291
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.947343859
Short name T1078
Test name
Test status
Simulation time 1365045580 ps
CPU time 7.24 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 219240 kb
Host smart-a4af99a5-0f36-47ce-944a-c9f85cc7bca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947343859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.947343859
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3816395368
Short name T368
Test name
Test status
Simulation time 8595808585 ps
CPU time 16.17 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:35:03 PM PDT 24
Peak memory 567644 kb
Host smart-37231cb2-a20a-4977-91f3-02efeebae37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816395368 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3816395368
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3259518538
Short name T1035
Test name
Test status
Simulation time 6105391998 ps
CPU time 24.68 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:35:06 PM PDT 24
Peak memory 235448 kb
Host smart-3e0c4af9-7bca-4688-bc65-87565cd5c366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259518538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3259518538
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.4259675357
Short name T969
Test name
Test status
Simulation time 35716275097 ps
CPU time 59.19 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 1063320 kb
Host smart-97dc7d53-f944-4408-9369-eb2f941050b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259675357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.4259675357
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1366322300
Short name T1431
Test name
Test status
Simulation time 9539739793 ps
CPU time 306.24 seconds
Started Jun 05 04:34:56 PM PDT 24
Finished Jun 05 04:40:03 PM PDT 24
Peak memory 1207332 kb
Host smart-31109239-260b-4af1-a4a7-b88c1226d22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366322300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1366322300
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3493657749
Short name T1298
Test name
Test status
Simulation time 1270551434 ps
CPU time 6.93 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:34:58 PM PDT 24
Peak memory 213336 kb
Host smart-4dc63898-1ffd-4bcc-b39f-be951f19dfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493657749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3493657749
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.193523663
Short name T24
Test name
Test status
Simulation time 1030390534 ps
CPU time 19.38 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:35:07 PM PDT 24
Peak memory 205108 kb
Host smart-45b88c23-c97a-4d8c-a7c6-2aca072863ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193523663 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.193523663
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1914972881
Short name T1233
Test name
Test status
Simulation time 21733574 ps
CPU time 0.68 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 204756 kb
Host smart-9badede3-7c33-4e4b-82c5-547612756b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914972881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1914972881
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2511237136
Short name T1409
Test name
Test status
Simulation time 178461589 ps
CPU time 2.26 seconds
Started Jun 05 04:35:14 PM PDT 24
Finished Jun 05 04:35:17 PM PDT 24
Peak memory 221344 kb
Host smart-39db8bfc-e8ea-4c18-9da8-7d3cb3d2d91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511237136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2511237136
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.182247632
Short name T1228
Test name
Test status
Simulation time 360542743 ps
CPU time 18.77 seconds
Started Jun 05 04:35:25 PM PDT 24
Finished Jun 05 04:35:45 PM PDT 24
Peak memory 280352 kb
Host smart-be53e64c-7a23-479b-b6d0-07810465df2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182247632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.182247632
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2903457744
Short name T711
Test name
Test status
Simulation time 12395172826 ps
CPU time 83.34 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:36:32 PM PDT 24
Peak memory 792252 kb
Host smart-b91abe4e-4e24-468f-ac13-97690168621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903457744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2903457744
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1069333893
Short name T1050
Test name
Test status
Simulation time 2458465476 ps
CPU time 195.1 seconds
Started Jun 05 04:35:06 PM PDT 24
Finished Jun 05 04:38:22 PM PDT 24
Peak memory 758280 kb
Host smart-3930d2ce-9e54-4395-8626-4d7c61198ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069333893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1069333893
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2454671577
Short name T750
Test name
Test status
Simulation time 1066067041 ps
CPU time 0.97 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:35:13 PM PDT 24
Peak memory 204788 kb
Host smart-390284e4-b3ab-4f1e-9ac5-b9123490252f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454671577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2454671577
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3108249987
Short name T355
Test name
Test status
Simulation time 356367905 ps
CPU time 9.43 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:15 PM PDT 24
Peak memory 205000 kb
Host smart-943bc139-6b5e-495d-babe-eb7dfe35dc94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108249987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3108249987
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1282441357
Short name T737
Test name
Test status
Simulation time 20695431210 ps
CPU time 457.77 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:43:01 PM PDT 24
Peak memory 1520136 kb
Host smart-dec97fee-562a-4ac7-90c8-ca4d570e7651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282441357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1282441357
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.4086461961
Short name T1254
Test name
Test status
Simulation time 2160400269 ps
CPU time 22.54 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:47 PM PDT 24
Peak memory 205148 kb
Host smart-e7257951-64e5-473b-82f3-3321baf9c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086461961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.4086461961
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3785656894
Short name T71
Test name
Test status
Simulation time 1515145825 ps
CPU time 69.73 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:36:43 PM PDT 24
Peak memory 336556 kb
Host smart-309a4965-b096-4956-a243-b098ca5f3bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785656894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3785656894
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1098127408
Short name T1356
Test name
Test status
Simulation time 19748143 ps
CPU time 0.66 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 204748 kb
Host smart-9a40ad9a-c33d-4cdb-8a79-1bdf374e3611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098127408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1098127408
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.117036301
Short name T1017
Test name
Test status
Simulation time 25073925356 ps
CPU time 165.95 seconds
Started Jun 05 04:35:34 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 229636 kb
Host smart-93a761eb-3ffe-49ca-9adc-70d2584731fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117036301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.117036301
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1517378634
Short name T306
Test name
Test status
Simulation time 2130383711 ps
CPU time 16.43 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 284808 kb
Host smart-a9f355c1-5fd2-4086-9e02-ef354e4321d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517378634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1517378634
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.306793183
Short name T644
Test name
Test status
Simulation time 14559148761 ps
CPU time 47.93 seconds
Started Jun 05 04:35:09 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 213448 kb
Host smart-2a090c2c-f7b1-44cc-aebc-3e0246218eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306793183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.306793183
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3556554019
Short name T1440
Test name
Test status
Simulation time 3833007257 ps
CPU time 4.76 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 213356 kb
Host smart-ffedc225-7f22-4374-8854-733d2a3dddd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556554019 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3556554019
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3789558480
Short name T871
Test name
Test status
Simulation time 10078362604 ps
CPU time 44.44 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:36:03 PM PDT 24
Peak memory 347488 kb
Host smart-a735fd70-50c4-433d-b2a3-0d2a34f9ebc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789558480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3789558480
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.159644061
Short name T1502
Test name
Test status
Simulation time 10092591646 ps
CPU time 73.69 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:36:25 PM PDT 24
Peak memory 539668 kb
Host smart-bfe46539-2e10-46ae-b843-d4274f4a6494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159644061 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.159644061
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3040212801
Short name T258
Test name
Test status
Simulation time 2549599277 ps
CPU time 1.65 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:35:33 PM PDT 24
Peak memory 205184 kb
Host smart-ada344fc-bbe3-495f-aa1f-2e0542e24459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040212801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3040212801
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2970738884
Short name T951
Test name
Test status
Simulation time 1026046142 ps
CPU time 5.89 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 205064 kb
Host smart-02123fe4-e7e6-4a04-9f92-cc5c2e198e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970738884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2970738884
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1985354739
Short name T779
Test name
Test status
Simulation time 3665678130 ps
CPU time 5.05 seconds
Started Jun 05 04:35:21 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 206756 kb
Host smart-74b19029-b7ca-4c2f-b21b-6e3249b35b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985354739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1985354739
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1761042772
Short name T1432
Test name
Test status
Simulation time 22121620853 ps
CPU time 45.07 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 711360 kb
Host smart-2bdbae4c-11c8-4062-bd5a-f4c678da29c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761042772 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1761042772
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.119514714
Short name T534
Test name
Test status
Simulation time 4937188790 ps
CPU time 50.61 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:36:24 PM PDT 24
Peak memory 205176 kb
Host smart-9fbbefc8-531d-4bc6-aaf2-d687ce28101c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119514714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.119514714
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2815988449
Short name T1026
Test name
Test status
Simulation time 11176560369 ps
CPU time 75.36 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:36:27 PM PDT 24
Peak memory 210336 kb
Host smart-188a2678-ed74-48ac-888d-f71073b5af93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815988449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2815988449
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2541173888
Short name T467
Test name
Test status
Simulation time 37530379621 ps
CPU time 62.08 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:36:32 PM PDT 24
Peak memory 1134980 kb
Host smart-16a936e7-d484-4cea-b432-6c93f37d963e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541173888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2541173888
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2030771247
Short name T517
Test name
Test status
Simulation time 1096594304 ps
CPU time 6.38 seconds
Started Jun 05 04:35:14 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 218428 kb
Host smart-fb728e07-8897-4bbb-a0cd-e2a9ee2dbab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030771247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2030771247
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.1548301947
Short name T981
Test name
Test status
Simulation time 1063945539 ps
CPU time 20.42 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:35:32 PM PDT 24
Peak memory 205080 kb
Host smart-24e23e72-b09e-4a5e-9929-4037c8250b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548301947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.1548301947
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1578014385
Short name T596
Test name
Test status
Simulation time 17649570 ps
CPU time 0.63 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:20 PM PDT 24
Peak memory 204748 kb
Host smart-53308f19-e7eb-4a5c-8040-e1d2994d4648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578014385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1578014385
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1089142022
Short name T48
Test name
Test status
Simulation time 383688737 ps
CPU time 1.34 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 213360 kb
Host smart-68086e7e-e7d9-4225-bccb-20a53e851480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089142022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1089142022
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2432816721
Short name T886
Test name
Test status
Simulation time 1052265668 ps
CPU time 12.55 seconds
Started Jun 05 04:35:21 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 227296 kb
Host smart-75d24b0a-3de4-4884-a55c-99cf54e0a176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432816721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2432816721
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1226323065
Short name T765
Test name
Test status
Simulation time 1833766753 ps
CPU time 55.5 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:36:11 PM PDT 24
Peak memory 647468 kb
Host smart-477a31dd-bfe7-4013-8b44-3d5c33297fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226323065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1226323065
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2119611642
Short name T182
Test name
Test status
Simulation time 27993824429 ps
CPU time 116.09 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 533344 kb
Host smart-06e355ec-e798-45a4-8cb9-3665d885c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119611642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2119611642
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1283649140
Short name T628
Test name
Test status
Simulation time 523571197 ps
CPU time 0.98 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 204796 kb
Host smart-d201e8b7-5741-439f-8f80-d812223e2d4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283649140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1283649140
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.605613071
Short name T934
Test name
Test status
Simulation time 1222600148 ps
CPU time 4.32 seconds
Started Jun 05 04:35:13 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 232612 kb
Host smart-db253e6b-def4-4f1f-9988-a2521bcbdb6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605613071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
605613071
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2657730408
Short name T109
Test name
Test status
Simulation time 4174896266 ps
CPU time 106.08 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 1240936 kb
Host smart-da6a4c92-9862-446d-9811-c07a5ecb1735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657730408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2657730408
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1948638835
Short name T1131
Test name
Test status
Simulation time 1738939865 ps
CPU time 36.26 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 401784 kb
Host smart-341faef9-e29c-4a84-bcaf-281b049bedbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948638835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1948638835
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1431906386
Short name T753
Test name
Test status
Simulation time 18391175 ps
CPU time 0.67 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:17 PM PDT 24
Peak memory 204708 kb
Host smart-0938df8e-c0dd-4d04-b4be-3a7c88f0e7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431906386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1431906386
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2558381423
Short name T1378
Test name
Test status
Simulation time 12460086970 ps
CPU time 509.22 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:43:48 PM PDT 24
Peak memory 205128 kb
Host smart-6b8896cb-f225-42f5-b8f6-23d9e72f6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558381423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2558381423
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.4200314873
Short name T821
Test name
Test status
Simulation time 3877941321 ps
CPU time 50.23 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:36:09 PM PDT 24
Peak memory 303516 kb
Host smart-bdc1e0de-fa8b-4def-b502-664cb8873248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200314873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.4200314873
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4077601475
Short name T648
Test name
Test status
Simulation time 17426885908 ps
CPU time 387 seconds
Started Jun 05 04:35:28 PM PDT 24
Finished Jun 05 04:41:56 PM PDT 24
Peak memory 1866224 kb
Host smart-0a4bdf26-6532-4275-9bf3-6d4168d342bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077601475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4077601475
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1670333478
Short name T769
Test name
Test status
Simulation time 3172395339 ps
CPU time 14.91 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 221616 kb
Host smart-4722860a-532e-40db-b7bb-43d1616eb120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670333478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1670333478
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.401973117
Short name T808
Test name
Test status
Simulation time 2615294733 ps
CPU time 5.93 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:24 PM PDT 24
Peak memory 213528 kb
Host smart-f409f3cf-b9a4-4177-9cb8-499d40236128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401973117 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.401973117
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3372631268
Short name T160
Test name
Test status
Simulation time 10894750185 ps
CPU time 8.23 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 220592 kb
Host smart-2f7ff1db-c2c6-4868-bcfe-35acaee5803d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372631268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3372631268
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1309440342
Short name T89
Test name
Test status
Simulation time 10103554780 ps
CPU time 60.2 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 464264 kb
Host smart-832cb937-546b-4922-88b8-d9760ecc11e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309440342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1309440342
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.579102564
Short name T977
Test name
Test status
Simulation time 2138034641 ps
CPU time 2.76 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 205020 kb
Host smart-c795aa9f-5c45-4476-917a-06fc7fcaed06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579102564 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.579102564
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.623760796
Short name T358
Test name
Test status
Simulation time 1064692214 ps
CPU time 5.45 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 205128 kb
Host smart-bc424fa3-ca69-4226-bea6-db582000b2b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623760796 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.623760796
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3940560480
Short name T867
Test name
Test status
Simulation time 1807810616 ps
CPU time 3.07 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:35:33 PM PDT 24
Peak memory 204868 kb
Host smart-c961a5e3-4fa8-4df5-af50-c739738f3283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940560480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3940560480
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.75845215
Short name T343
Test name
Test status
Simulation time 4415853005 ps
CPU time 5.84 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:23 PM PDT 24
Peak memory 213388 kb
Host smart-8e83e856-4328-43a0-a75d-73519e86ae77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75845215 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.75845215
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1385769610
Short name T565
Test name
Test status
Simulation time 9197728253 ps
CPU time 21.22 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 472320 kb
Host smart-fac42211-d3b2-46db-a9e0-3f8350464679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385769610 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1385769610
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3092389090
Short name T1291
Test name
Test status
Simulation time 543072703 ps
CPU time 9.1 seconds
Started Jun 05 04:35:13 PM PDT 24
Finished Jun 05 04:35:23 PM PDT 24
Peak memory 205112 kb
Host smart-99b4ae71-db0b-434d-a78a-6610dca7a494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092389090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3092389090
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3691667652
Short name T675
Test name
Test status
Simulation time 1175412442 ps
CPU time 48.91 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:36:05 PM PDT 24
Peak memory 205140 kb
Host smart-96a8d1c8-a931-49a0-90b0-c6cb5cb030bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691667652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3691667652
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1615744314
Short name T256
Test name
Test status
Simulation time 57623332962 ps
CPU time 231.36 seconds
Started Jun 05 04:35:13 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 2510508 kb
Host smart-7d659dc3-a099-4d31-a687-b7442d78b2c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615744314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1615744314
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2519357283
Short name T825
Test name
Test status
Simulation time 27324876489 ps
CPU time 242.01 seconds
Started Jun 05 04:35:12 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 1822076 kb
Host smart-e051a316-ce1b-4af4-a880-8786b2cc0d62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519357283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2519357283
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3252747881
Short name T1094
Test name
Test status
Simulation time 2593637995 ps
CPU time 7.07 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 213380 kb
Host smart-23db3d7e-9702-4bc6-93ab-1bc674f83109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252747881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3252747881
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3171432300
Short name T22
Test name
Test status
Simulation time 1077611458 ps
CPU time 16.6 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 205068 kb
Host smart-b11de558-30e4-4fda-866f-e54ea55048eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171432300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3171432300
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2435759754
Short name T369
Test name
Test status
Simulation time 34925135 ps
CPU time 0.61 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 204744 kb
Host smart-ccb9196a-2309-4cb4-ae70-5989c45ca037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435759754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2435759754
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.262537964
Short name T919
Test name
Test status
Simulation time 125953467 ps
CPU time 1.71 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 213384 kb
Host smart-dc3e4d06-1c7f-485c-958d-d631a15ad3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262537964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.262537964
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2956557801
Short name T1211
Test name
Test status
Simulation time 1328352518 ps
CPU time 16.65 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:36 PM PDT 24
Peak memory 247920 kb
Host smart-10de4ed2-88a0-43f0-b1d1-d9b6f3888927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956557801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2956557801
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2233879239
Short name T1358
Test name
Test status
Simulation time 40681158553 ps
CPU time 65.1 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 672176 kb
Host smart-1c9e659c-6df7-4c75-af65-9a9dbf7441c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233879239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2233879239
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2493311853
Short name T1018
Test name
Test status
Simulation time 7785778927 ps
CPU time 65.89 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:36:25 PM PDT 24
Peak memory 639028 kb
Host smart-f36cfcb0-2708-4602-881d-62b0b57dcc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493311853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2493311853
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.17619933
Short name T245
Test name
Test status
Simulation time 141058756 ps
CPU time 1.2 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 204960 kb
Host smart-f08a3197-94f3-4a43-be2d-96ccc8d6c3ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17619933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt
.17619933
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1508124466
Short name T634
Test name
Test status
Simulation time 162662381 ps
CPU time 9.64 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:30 PM PDT 24
Peak memory 233100 kb
Host smart-16e4506b-797f-42a2-87ae-11cd3be0851c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508124466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1508124466
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2834717456
Short name T1283
Test name
Test status
Simulation time 5087684887 ps
CPU time 145.74 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 1470632 kb
Host smart-8598bfc1-8727-4cb3-9d80-0aafb853072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834717456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2834717456
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3944971211
Short name T958
Test name
Test status
Simulation time 2258577682 ps
CPU time 23.77 seconds
Started Jun 05 04:35:20 PM PDT 24
Finished Jun 05 04:35:45 PM PDT 24
Peak memory 205104 kb
Host smart-cbcbe31b-86b5-4d2e-b330-555df50a735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944971211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3944971211
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.691247799
Short name T887
Test name
Test status
Simulation time 19220485 ps
CPU time 0.69 seconds
Started Jun 05 04:35:27 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 204780 kb
Host smart-da17233b-5103-403f-a6dc-d61e2196fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691247799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.691247799
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2091447219
Short name T545
Test name
Test status
Simulation time 1240664583 ps
CPU time 27.69 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:49 PM PDT 24
Peak memory 397724 kb
Host smart-6938dd3c-e99e-4333-a1fe-c458043291b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091447219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2091447219
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2103925475
Short name T179
Test name
Test status
Simulation time 78851659798 ps
CPU time 684.57 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:46:45 PM PDT 24
Peak memory 2134084 kb
Host smart-27acc1ad-9a34-43e4-8c65-596c78b03f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103925475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2103925475
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3926791479
Short name T274
Test name
Test status
Simulation time 1250126140 ps
CPU time 12.16 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:46 PM PDT 24
Peak memory 213436 kb
Host smart-c7c566a5-0bfd-46cc-a8c8-5e17b3ec1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926791479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3926791479
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2685927644
Short name T552
Test name
Test status
Simulation time 889164488 ps
CPU time 3.81 seconds
Started Jun 05 04:35:34 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 205160 kb
Host smart-54b38355-a998-4340-bce7-f792645d852a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685927644 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2685927644
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3852912038
Short name T1208
Test name
Test status
Simulation time 10149697819 ps
CPU time 12.88 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 234732 kb
Host smart-b668bf67-1bd7-43b3-8113-6070e46c0a38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852912038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3852912038
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4200440088
Short name T652
Test name
Test status
Simulation time 10249188777 ps
CPU time 17.82 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 353888 kb
Host smart-8073ab73-abeb-48d1-9630-2e336cb4dde9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200440088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4200440088
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.36765136
Short name T1449
Test name
Test status
Simulation time 1170047921 ps
CPU time 5.17 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:29 PM PDT 24
Peak memory 205040 kb
Host smart-65e33239-862a-4d12-ae0a-77d862d220fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765136 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.36765136
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3728681518
Short name T1428
Test name
Test status
Simulation time 1029460026 ps
CPU time 5.99 seconds
Started Jun 05 04:35:35 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205056 kb
Host smart-c21089e2-83d4-4af6-b6ed-9a5c00362f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728681518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3728681518
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1763439306
Short name T776
Test name
Test status
Simulation time 985299572 ps
CPU time 3.2 seconds
Started Jun 05 04:35:27 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 205136 kb
Host smart-7eb45445-561f-40d0-b0b1-f3d8c2bfaff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763439306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1763439306
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2584284627
Short name T1204
Test name
Test status
Simulation time 3760225795 ps
CPU time 5.33 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:25 PM PDT 24
Peak memory 205140 kb
Host smart-714eb359-0246-48f4-a8f1-5cb4cdabe905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584284627 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2584284627
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3677659526
Short name T816
Test name
Test status
Simulation time 8654072927 ps
CPU time 6.38 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 205108 kb
Host smart-2bf5f4dc-035d-4d65-a706-3c7ddea55e38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677659526 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3677659526
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3707707147
Short name T1268
Test name
Test status
Simulation time 1672074128 ps
CPU time 14.2 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 205072 kb
Host smart-855d659a-7fda-40de-8223-fdfc570f71b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707707147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3707707147
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1643727603
Short name T1262
Test name
Test status
Simulation time 42568309026 ps
CPU time 235.34 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:39:16 PM PDT 24
Peak memory 2897752 kb
Host smart-373327ea-033a-45cd-a8e7-24c2d96ab231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643727603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1643727603
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.666377857
Short name T732
Test name
Test status
Simulation time 25855966451 ps
CPU time 1534.35 seconds
Started Jun 05 04:35:24 PM PDT 24
Finished Jun 05 05:01:00 PM PDT 24
Peak memory 3051784 kb
Host smart-3b1cec24-41f7-4a88-b4d6-e10d85c6dd6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666377857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.666377857
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2431601892
Short name T1103
Test name
Test status
Simulation time 5250818716 ps
CPU time 8.1 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 213432 kb
Host smart-4f6f1e90-8121-4bb6-b34c-20fc68d60ccb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431601892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2431601892
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2255632100
Short name T1395
Test name
Test status
Simulation time 1066975818 ps
CPU time 17.04 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 205076 kb
Host smart-c8113602-d83a-4b15-bb39-6b24516c82a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255632100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2255632100
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3282097602
Short name T1132
Test name
Test status
Simulation time 15701301 ps
CPU time 0.7 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 204728 kb
Host smart-19020f28-019e-43ad-8bf2-ee29e3370d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282097602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3282097602
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2409542240
Short name T1472
Test name
Test status
Simulation time 2203451201 ps
CPU time 4.3 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:35:37 PM PDT 24
Peak memory 221504 kb
Host smart-2e07b834-e393-4d00-8070-12db55143815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409542240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2409542240
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3272683148
Short name T767
Test name
Test status
Simulation time 1118628127 ps
CPU time 20.15 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:35:44 PM PDT 24
Peak memory 285156 kb
Host smart-7a483b4e-45d0-4263-8f31-2f7639c31d60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272683148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3272683148
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.287953358
Short name T665
Test name
Test status
Simulation time 2173103103 ps
CPU time 167.77 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 745676 kb
Host smart-7b715895-3788-4a7c-8376-8aee02839cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287953358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.287953358
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1085724140
Short name T349
Test name
Test status
Simulation time 14301973029 ps
CPU time 86.79 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 459256 kb
Host smart-45991309-0fc0-4eb8-9e92-4f34ec431beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085724140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1085724140
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.4103176627
Short name T1413
Test name
Test status
Simulation time 593604539 ps
CPU time 1.23 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 204924 kb
Host smart-cdb8aef0-cfd5-4404-826a-d8a334c4d861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103176627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.4103176627
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3693602781
Short name T1401
Test name
Test status
Simulation time 304265161 ps
CPU time 8.2 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:29 PM PDT 24
Peak memory 204944 kb
Host smart-5b1e5585-9073-45f8-8108-781884c616f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693602781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3693602781
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1880842102
Short name T113
Test name
Test status
Simulation time 11873010937 ps
CPU time 69.84 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 944564 kb
Host smart-e8194d9f-5a22-4b25-9198-c6af38110a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880842102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1880842102
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.591592082
Short name T1436
Test name
Test status
Simulation time 954348320 ps
CPU time 11.84 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205088 kb
Host smart-e75a854b-61cc-41e7-9a9c-405c76758ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591592082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.591592082
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1411153814
Short name T50
Test name
Test status
Simulation time 7047803325 ps
CPU time 87.64 seconds
Started Jun 05 04:35:50 PM PDT 24
Finished Jun 05 04:37:18 PM PDT 24
Peak memory 386460 kb
Host smart-beed691c-3bf1-4344-93a9-056214419e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411153814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1411153814
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2552425608
Short name T603
Test name
Test status
Simulation time 41868193 ps
CPU time 0.7 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 204768 kb
Host smart-7d04bd81-9022-4751-9479-d50fe0cca842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552425608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2552425608
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3306353141
Short name T493
Test name
Test status
Simulation time 5056274869 ps
CPU time 21.97 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:35:54 PM PDT 24
Peak memory 324204 kb
Host smart-f58a0667-24ca-42a2-8303-ce096b6c5c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306353141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3306353141
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3399988369
Short name T280
Test name
Test status
Simulation time 3218446896 ps
CPU time 226.41 seconds
Started Jun 05 04:35:20 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 585156 kb
Host smart-706786ee-5834-4f84-9675-f813cac28c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399988369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3399988369
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2707775855
Short name T681
Test name
Test status
Simulation time 669463956 ps
CPU time 30.07 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 213264 kb
Host smart-8cab7596-d706-4828-9faf-2198858334f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707775855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2707775855
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1924708544
Short name T1348
Test name
Test status
Simulation time 951558913 ps
CPU time 4.42 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:35:37 PM PDT 24
Peak memory 213284 kb
Host smart-ec178b38-3b83-4e6c-a047-1e99017f72da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924708544 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1924708544
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1033931960
Short name T1280
Test name
Test status
Simulation time 10651222698 ps
CPU time 5.4 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 216704 kb
Host smart-797c9ee1-6ab2-4227-bf45-cd1e2108470d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033931960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1033931960
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2042057462
Short name T1384
Test name
Test status
Simulation time 10578855846 ps
CPU time 11.12 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 292816 kb
Host smart-e30f6d0c-25d5-428b-8846-5d8a243cecce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042057462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2042057462
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.2575013293
Short name T933
Test name
Test status
Simulation time 2085492032 ps
CPU time 2.74 seconds
Started Jun 05 04:35:43 PM PDT 24
Finished Jun 05 04:35:47 PM PDT 24
Peak memory 205252 kb
Host smart-9b605eef-3aa7-43ba-b21f-75606f824eee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575013293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.2575013293
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3132472353
Short name T1477
Test name
Test status
Simulation time 1211023335 ps
CPU time 2.06 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:33 PM PDT 24
Peak memory 205076 kb
Host smart-dd604a08-f56c-480c-b00e-93b69fb2b1f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132472353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3132472353
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1147735581
Short name T1148
Test name
Test status
Simulation time 885661286 ps
CPU time 2.85 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 205040 kb
Host smart-9459a20b-9230-4532-8618-03f24634f9d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147735581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1147735581
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.408212184
Short name T882
Test name
Test status
Simulation time 7534334263 ps
CPU time 5.39 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 205060 kb
Host smart-69887210-b929-43e5-b03c-c3c7ebe4c6e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408212184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.408212184
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.106809475
Short name T683
Test name
Test status
Simulation time 17575339956 ps
CPU time 113.96 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 2000512 kb
Host smart-bd06f8da-074e-471f-8be8-5f0c18045b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106809475 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.106809475
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.4119474159
Short name T507
Test name
Test status
Simulation time 2487674749 ps
CPU time 23.52 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 205176 kb
Host smart-22e4dce8-f591-44af-a546-baa0f216d102
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119474159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.4119474159
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3763032373
Short name T817
Test name
Test status
Simulation time 824001043 ps
CPU time 35.62 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 205096 kb
Host smart-8fdb40ce-cb97-4f2f-95d7-02e97ecb1670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763032373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3763032373
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1996191326
Short name T717
Test name
Test status
Simulation time 32414326314 ps
CPU time 297 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:40:28 PM PDT 24
Peak memory 3154360 kb
Host smart-2edf204e-4660-4be4-813e-2033f276c89f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996191326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1996191326
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.4199749079
Short name T983
Test name
Test status
Simulation time 2890486850 ps
CPU time 58.87 seconds
Started Jun 05 04:35:36 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 815332 kb
Host smart-64f5ee80-e68b-4333-bc4c-86ad08da08c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199749079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.4199749079
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2135684267
Short name T434
Test name
Test status
Simulation time 2559427920 ps
CPU time 7.38 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 213424 kb
Host smart-f009641b-4f75-414f-b858-95466668e179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135684267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2135684267
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.2022152648
Short name T1341
Test name
Test status
Simulation time 1036221430 ps
CPU time 19.5 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:35:51 PM PDT 24
Peak memory 205108 kb
Host smart-a316d108-9a81-4934-b5ba-dafe18754a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022152648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2022152648
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.4054043562
Short name T1433
Test name
Test status
Simulation time 41259147 ps
CPU time 0.68 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:38 PM PDT 24
Peak memory 204708 kb
Host smart-0b7d5fb7-ccb5-4dc5-9467-6753e6d689f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054043562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.4054043562
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2708673713
Short name T1242
Test name
Test status
Simulation time 97368233 ps
CPU time 1.66 seconds
Started Jun 05 04:35:34 PM PDT 24
Finished Jun 05 04:35:36 PM PDT 24
Peak memory 213492 kb
Host smart-5ab32dba-ba9e-4dbb-ac4e-5176d9da923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708673713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2708673713
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2654146691
Short name T291
Test name
Test status
Simulation time 377382513 ps
CPU time 8.68 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 281260 kb
Host smart-e52c6e08-4b89-419f-b80d-e16cf1e5b223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654146691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2654146691
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1411785595
Short name T1095
Test name
Test status
Simulation time 12590206391 ps
CPU time 77.58 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 647004 kb
Host smart-2d6a1b59-1734-4c22-bcdf-03f0e2399af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411785595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1411785595
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3150033957
Short name T364
Test name
Test status
Simulation time 11017161489 ps
CPU time 97.52 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 862932 kb
Host smart-58226abb-188a-47e8-9e41-4fa716328ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150033957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3150033957
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.601102947
Short name T365
Test name
Test status
Simulation time 150213151 ps
CPU time 0.79 seconds
Started Jun 05 04:35:34 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 204788 kb
Host smart-53f73246-07ee-4361-9632-cb774f1f2ca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601102947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.601102947
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3044067748
Short name T599
Test name
Test status
Simulation time 184272501 ps
CPU time 10.37 seconds
Started Jun 05 04:35:34 PM PDT 24
Finished Jun 05 04:35:45 PM PDT 24
Peak memory 237504 kb
Host smart-9320fc39-1529-42eb-ae9d-65bcbd4e92c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044067748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3044067748
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.795314505
Short name T1289
Test name
Test status
Simulation time 4959259086 ps
CPU time 430.89 seconds
Started Jun 05 04:35:35 PM PDT 24
Finished Jun 05 04:42:47 PM PDT 24
Peak memory 1455580 kb
Host smart-77789a4a-a10c-4987-837d-82f1ec92abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795314505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.795314505
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2002325192
Short name T1192
Test name
Test status
Simulation time 258074804 ps
CPU time 3.34 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205060 kb
Host smart-c78e10fe-8213-4b00-8238-f5cf7cc2bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002325192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2002325192
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1141987991
Short name T491
Test name
Test status
Simulation time 1450626851 ps
CPU time 21.31 seconds
Started Jun 05 04:35:40 PM PDT 24
Finished Jun 05 04:36:02 PM PDT 24
Peak memory 311692 kb
Host smart-4ab418ab-e979-4248-a2b7-5790f2b228ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141987991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1141987991
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3332867570
Short name T1451
Test name
Test status
Simulation time 20994061 ps
CPU time 0.68 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 204752 kb
Host smart-39624423-fe2a-4f6a-94eb-07d6638e3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332867570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3332867570
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.846202838
Short name T973
Test name
Test status
Simulation time 3326609605 ps
CPU time 19.47 seconds
Started Jun 05 04:35:32 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 373100 kb
Host smart-6471da07-63d1-429c-b0f7-926338633fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846202838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.846202838
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2034617857
Short name T663
Test name
Test status
Simulation time 19394738641 ps
CPU time 64.02 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 307288 kb
Host smart-1357dcbf-3723-46f9-9f9a-d9886906b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034617857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2034617857
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2024330722
Short name T279
Test name
Test status
Simulation time 16222486044 ps
CPU time 1038.57 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:52:50 PM PDT 24
Peak memory 2488392 kb
Host smart-240d8155-4b97-415d-a2dd-9672e625142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024330722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2024330722
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.4028703727
Short name T399
Test name
Test status
Simulation time 643405991 ps
CPU time 28.09 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:36:00 PM PDT 24
Peak memory 213288 kb
Host smart-185aaf4a-ea67-4a7c-ac9c-9313b14bed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028703727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.4028703727
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.4062122425
Short name T1126
Test name
Test status
Simulation time 818495972 ps
CPU time 4.45 seconds
Started Jun 05 04:35:43 PM PDT 24
Finished Jun 05 04:35:48 PM PDT 24
Peak memory 205268 kb
Host smart-e4b6e1c9-157f-48e0-a177-dc8e86294d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062122425 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4062122425
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2117016998
Short name T741
Test name
Test status
Simulation time 10200056951 ps
CPU time 46.71 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:36:25 PM PDT 24
Peak memory 363428 kb
Host smart-7b03ce0d-fb5b-4601-b971-5786d60fae8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117016998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2117016998
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3334755074
Short name T630
Test name
Test status
Simulation time 11049872017 ps
CPU time 4.15 seconds
Started Jun 05 04:35:41 PM PDT 24
Finished Jun 05 04:35:46 PM PDT 24
Peak memory 245504 kb
Host smart-b4e097e9-f31e-4814-8853-5d37a7c30b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334755074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3334755074
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1767360488
Short name T21
Test name
Test status
Simulation time 2859648613 ps
CPU time 2.96 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 205124 kb
Host smart-9ba23fc8-9c55-460f-bc52-b21e0f097e87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767360488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1767360488
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.1690779223
Short name T626
Test name
Test status
Simulation time 1184360286 ps
CPU time 1.83 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:35:46 PM PDT 24
Peak memory 205132 kb
Host smart-6eba4a15-2fa1-4c1f-b9d8-857787f126f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690779223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.1690779223
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.659265510
Short name T906
Test name
Test status
Simulation time 486716481 ps
CPU time 2.88 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205016 kb
Host smart-ca4920f2-b590-4a00-ad70-aa0e327fa346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659265510 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.659265510
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.470451418
Short name T1138
Test name
Test status
Simulation time 3407441755 ps
CPU time 5.02 seconds
Started Jun 05 04:35:28 PM PDT 24
Finished Jun 05 04:35:34 PM PDT 24
Peak memory 205848 kb
Host smart-019c685c-71c8-4f6a-b8db-edd409dce600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470451418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.470451418
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1854635155
Short name T915
Test name
Test status
Simulation time 4235783423 ps
CPU time 8.16 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 415152 kb
Host smart-357251bc-7b57-43e0-b4a8-ce1ab43f2b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854635155 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1854635155
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3932603491
Short name T792
Test name
Test status
Simulation time 4844562937 ps
CPU time 28.92 seconds
Started Jun 05 04:35:27 PM PDT 24
Finished Jun 05 04:35:57 PM PDT 24
Peak memory 205128 kb
Host smart-32b022e7-1a5d-4e22-b983-9379f71c2594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932603491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3932603491
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3334026791
Short name T749
Test name
Test status
Simulation time 1206705452 ps
CPU time 5.07 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 204976 kb
Host smart-cb687dde-419d-40e7-89ff-105890b59625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334026791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3334026791
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.4195167593
Short name T257
Test name
Test status
Simulation time 57958922680 ps
CPU time 560.76 seconds
Started Jun 05 04:35:28 PM PDT 24
Finished Jun 05 04:44:50 PM PDT 24
Peak memory 4705916 kb
Host smart-b24a1bd2-0e15-4f0d-bbb2-a2b39e123fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195167593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.4195167593
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.241652914
Short name T999
Test name
Test status
Simulation time 20027742517 ps
CPU time 377.28 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:41:48 PM PDT 24
Peak memory 2270884 kb
Host smart-4fe01489-fdba-41e5-977c-d81ad4e0a5e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241652914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.241652914
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2784101119
Short name T721
Test name
Test status
Simulation time 1329596188 ps
CPU time 7.33 seconds
Started Jun 05 04:35:33 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 213344 kb
Host smart-76e22cc1-421a-4a1c-a71b-86728633e412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784101119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2784101119
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.2825354444
Short name T523
Test name
Test status
Simulation time 1141536124 ps
CPU time 21.91 seconds
Started Jun 05 04:35:50 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 205104 kb
Host smart-87bf3c15-447a-4e6b-936e-6f94a2649f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825354444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2825354444
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1304811058
Short name T1210
Test name
Test status
Simulation time 49712792 ps
CPU time 0.6 seconds
Started Jun 05 04:35:49 PM PDT 24
Finished Jun 05 04:35:50 PM PDT 24
Peak memory 204768 kb
Host smart-00c9020d-5643-48da-a9f9-e0717a131ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304811058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1304811058
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3570570702
Short name T449
Test name
Test status
Simulation time 410883719 ps
CPU time 2.82 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 221184 kb
Host smart-adf0aab0-a852-4778-b60d-1378fa932fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570570702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3570570702
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.159803310
Short name T1047
Test name
Test status
Simulation time 3088835589 ps
CPU time 4.38 seconds
Started Jun 05 04:35:39 PM PDT 24
Finished Jun 05 04:35:44 PM PDT 24
Peak memory 248388 kb
Host smart-039d1a4b-ef11-4630-9e22-04aa58350a05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159803310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.159803310
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3454418540
Short name T1044
Test name
Test status
Simulation time 4940781308 ps
CPU time 65.99 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:36:51 PM PDT 24
Peak memory 295100 kb
Host smart-5e5f020a-edc6-49e3-9322-78f65c58d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454418540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3454418540
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.705737511
Short name T629
Test name
Test status
Simulation time 1882515377 ps
CPU time 122.46 seconds
Started Jun 05 04:35:39 PM PDT 24
Finished Jun 05 04:37:43 PM PDT 24
Peak memory 595376 kb
Host smart-2ba6b3f1-057f-4d03-bbdd-84497079e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705737511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.705737511
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.4281357675
Short name T1214
Test name
Test status
Simulation time 750350792 ps
CPU time 9.69 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:35:56 PM PDT 24
Peak memory 205020 kb
Host smart-09493986-52d2-4a0c-a88d-3a998c60f62f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281357675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.4281357675
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2603338020
Short name T1365
Test name
Test status
Simulation time 13907600446 ps
CPU time 97.11 seconds
Started Jun 05 04:35:42 PM PDT 24
Finished Jun 05 04:37:20 PM PDT 24
Peak memory 1004248 kb
Host smart-a3bda751-0a54-47cd-abd1-7b856f81efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603338020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2603338020
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2234032718
Short name T600
Test name
Test status
Simulation time 1137963904 ps
CPU time 12.89 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:51 PM PDT 24
Peak memory 204900 kb
Host smart-7e78eeab-fa92-49b6-bc04-ccdfa0bdd8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234032718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2234032718
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1387671029
Short name T679
Test name
Test status
Simulation time 1569522597 ps
CPU time 23.01 seconds
Started Jun 05 04:35:40 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 319676 kb
Host smart-6638b07f-e5d1-486f-9f15-60b263427a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387671029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1387671029
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2934907432
Short name T898
Test name
Test status
Simulation time 31067502 ps
CPU time 0.77 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:39 PM PDT 24
Peak memory 204608 kb
Host smart-cd189af3-0924-4a82-8f89-60cbef47470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934907432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2934907432
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.34608229
Short name T42
Test name
Test status
Simulation time 6232598476 ps
CPU time 66.4 seconds
Started Jun 05 04:35:39 PM PDT 24
Finished Jun 05 04:36:46 PM PDT 24
Peak memory 213448 kb
Host smart-e5433bde-4343-4f56-8563-412df558f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34608229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.34608229
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3354146291
Short name T1111
Test name
Test status
Simulation time 938203067 ps
CPU time 15.16 seconds
Started Jun 05 04:35:39 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 278064 kb
Host smart-915c5cbb-0b55-4a13-8b7a-e1c31a5d7d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354146291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3354146291
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.168054111
Short name T1372
Test name
Test status
Simulation time 9094632530 ps
CPU time 950.21 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:51:46 PM PDT 24
Peak memory 1786676 kb
Host smart-1be9d2f7-4847-4509-ba6c-610ba70cabb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168054111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.168054111
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2265623021
Short name T118
Test name
Test status
Simulation time 8063558917 ps
CPU time 33.09 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 213324 kb
Host smart-0d685361-e656-4e07-8880-88fcc6ad39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265623021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2265623021
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.132035562
Short name T1059
Test name
Test status
Simulation time 662431415 ps
CPU time 3.76 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205152 kb
Host smart-ea832154-ace2-4367-bd29-f6f7161f5747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132035562 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.132035562
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3514037869
Short name T1319
Test name
Test status
Simulation time 10312777116 ps
CPU time 12.44 seconds
Started Jun 05 04:35:49 PM PDT 24
Finished Jun 05 04:36:02 PM PDT 24
Peak memory 231352 kb
Host smart-7d6e62b2-7deb-411e-849c-4cd8b0c00036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514037869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3514037869
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2506280382
Short name T472
Test name
Test status
Simulation time 10543272258 ps
CPU time 13.22 seconds
Started Jun 05 04:35:39 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 307604 kb
Host smart-9d7086b9-b251-4393-af39-d0ebc0e3fee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506280382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2506280382
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.3278950593
Short name T1468
Test name
Test status
Simulation time 1474248313 ps
CPU time 6.55 seconds
Started Jun 05 04:35:47 PM PDT 24
Finished Jun 05 04:35:54 PM PDT 24
Peak memory 205168 kb
Host smart-4cbd2bda-74f4-46ae-83fb-48631ed2aaea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278950593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.3278950593
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.870967242
Short name T782
Test name
Test status
Simulation time 1118572535 ps
CPU time 3.41 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 205088 kb
Host smart-bc293390-daed-4d63-af1a-59124afceed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870967242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.870967242
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1012530032
Short name T892
Test name
Test status
Simulation time 1390633915 ps
CPU time 2.51 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 205104 kb
Host smart-abdc6542-f1af-4001-90e3-ee558f900e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012530032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1012530032
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3507863014
Short name T773
Test name
Test status
Simulation time 14948133615 ps
CPU time 7.64 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 213392 kb
Host smart-d19eef53-7257-460b-904e-6f607666e7ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507863014 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3507863014
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1191202630
Short name T937
Test name
Test status
Simulation time 11964085631 ps
CPU time 191.96 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 2893424 kb
Host smart-540d951d-aa5c-4e0a-a0a3-621b4311bfe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191202630 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1191202630
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2450727444
Short name T991
Test name
Test status
Simulation time 794475481 ps
CPU time 28.29 seconds
Started Jun 05 04:35:48 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 205116 kb
Host smart-fab03000-8bcd-44bf-b6bb-0316d1fe4541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450727444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2450727444
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1683090646
Short name T551
Test name
Test status
Simulation time 8006465387 ps
CPU time 44.13 seconds
Started Jun 05 04:35:37 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 205112 kb
Host smart-6be8b4c4-c223-442f-8d3e-96840bac59f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683090646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1683090646
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3167635145
Short name T26
Test name
Test status
Simulation time 26229930758 ps
CPU time 20.31 seconds
Started Jun 05 04:35:49 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 469916 kb
Host smart-d903aedb-2d92-44a4-8fd2-4ff716808f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167635145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3167635145
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.4134673968
Short name T548
Test name
Test status
Simulation time 5041129059 ps
CPU time 19.33 seconds
Started Jun 05 04:35:40 PM PDT 24
Finished Jun 05 04:36:00 PM PDT 24
Peak memory 434384 kb
Host smart-ce18891a-5e23-4114-a408-0090fadc06b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134673968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.4134673968
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1202204562
Short name T784
Test name
Test status
Simulation time 2110287956 ps
CPU time 7.68 seconds
Started Jun 05 04:35:47 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 219276 kb
Host smart-3fc82ef5-28d1-4c10-8453-e6aba47388e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202204562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1202204562
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.3957574428
Short name T1128
Test name
Test status
Simulation time 1029193376 ps
CPU time 16.24 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 205008 kb
Host smart-fc1bb8f3-bed0-44b8-bf76-a4bd10b96585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957574428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.3957574428
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.185878090
Short name T712
Test name
Test status
Simulation time 20988403 ps
CPU time 0.6 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 204752 kb
Host smart-19c354fc-91dc-4070-a0be-111a149497b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185878090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.185878090
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2154489292
Short name T1006
Test name
Test status
Simulation time 1838341706 ps
CPU time 8.05 seconds
Started Jun 05 04:35:38 PM PDT 24
Finished Jun 05 04:35:47 PM PDT 24
Peak memory 301620 kb
Host smart-907b46a2-a473-4320-ab76-33aa1837666f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154489292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2154489292
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.936152612
Short name T1406
Test name
Test status
Simulation time 5952648083 ps
CPU time 42.54 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:36:38 PM PDT 24
Peak memory 437612 kb
Host smart-2fd793cf-94ed-4f2f-b21c-70fbdca5c61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936152612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.936152612
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.4171047606
Short name T471
Test name
Test status
Simulation time 1349179557 ps
CPU time 43.97 seconds
Started Jun 05 04:35:47 PM PDT 24
Finished Jun 05 04:36:32 PM PDT 24
Peak memory 532740 kb
Host smart-79f4742b-6739-498d-aac7-89e3efaa886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171047606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.4171047606
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3048297800
Short name T243
Test name
Test status
Simulation time 353197036 ps
CPU time 1.02 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:35:47 PM PDT 24
Peak memory 204776 kb
Host smart-f010af3b-0c31-4f6a-808b-d707405d1e3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048297800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3048297800
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.559968329
Short name T762
Test name
Test status
Simulation time 240361982 ps
CPU time 3.6 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:35:57 PM PDT 24
Peak memory 221960 kb
Host smart-b065abda-eaf8-41ec-aae5-deb4f1d8714e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559968329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
559968329
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3086759774
Short name T855
Test name
Test status
Simulation time 17064374050 ps
CPU time 105.67 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:37:31 PM PDT 24
Peak memory 1222640 kb
Host smart-89daf852-c39e-49a5-8904-b5d5efebfcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086759774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3086759774
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.4154213379
Short name T562
Test name
Test status
Simulation time 632923505 ps
CPU time 28.18 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:36:14 PM PDT 24
Peak memory 205036 kb
Host smart-766dabc0-a678-420a-925f-c84ed56d3491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154213379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.4154213379
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1565591286
Short name T506
Test name
Test status
Simulation time 3108409073 ps
CPU time 76.19 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:37:13 PM PDT 24
Peak memory 330384 kb
Host smart-f59e48ec-cd87-45e1-b3d8-448a27083612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565591286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1565591286
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3462964412
Short name T1215
Test name
Test status
Simulation time 109754549 ps
CPU time 0.72 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:35:45 PM PDT 24
Peak memory 204768 kb
Host smart-a5e82aa2-f3e4-48dc-85ac-705ed1c25f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462964412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3462964412
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.879151914
Short name T1480
Test name
Test status
Simulation time 2194211402 ps
CPU time 21.23 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:36:07 PM PDT 24
Peak memory 359708 kb
Host smart-9149dd32-ad98-4537-b0ef-23872e932d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879151914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.879151914
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.208791447
Short name T800
Test name
Test status
Simulation time 3044532427 ps
CPU time 27.35 seconds
Started Jun 05 04:35:49 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 296936 kb
Host smart-f1ba0d29-8b83-4a0a-ac6a-26b3d535483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208791447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.208791447
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2297620245
Short name T510
Test name
Test status
Simulation time 17475539884 ps
CPU time 939.11 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:51:26 PM PDT 24
Peak memory 2198320 kb
Host smart-44a36607-f179-4177-8698-db34861a88b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297620245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2297620245
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.808391106
Short name T1037
Test name
Test status
Simulation time 804670669 ps
CPU time 37.19 seconds
Started Jun 05 04:35:50 PM PDT 24
Finished Jun 05 04:36:28 PM PDT 24
Peak memory 213288 kb
Host smart-89f70493-d5ba-4c1f-b1c8-753ed5031d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808391106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.808391106
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3479995921
Short name T1248
Test name
Test status
Simulation time 1329628165 ps
CPU time 3.67 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:35:50 PM PDT 24
Peak memory 205100 kb
Host smart-b3743a0e-9420-477d-b075-bcc012be908c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479995921 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3479995921
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.346793369
Short name T1284
Test name
Test status
Simulation time 10210739429 ps
CPU time 12.67 seconds
Started Jun 05 04:35:51 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 243008 kb
Host smart-25be95a7-9eec-4d37-9fe8-0268ffda7c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346793369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.346793369
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3065845058
Short name T177
Test name
Test status
Simulation time 10256907248 ps
CPU time 16.18 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 322740 kb
Host smart-d039af2d-c241-47f7-90a6-6e8acb3b568e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065845058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3065845058
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.863184220
Short name T488
Test name
Test status
Simulation time 2029707878 ps
CPU time 5.02 seconds
Started Jun 05 04:35:48 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 205120 kb
Host smart-d3950acc-c5e5-4f9b-9a06-2b7da9a240e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863184220 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.863184220
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.2399748775
Short name T1474
Test name
Test status
Simulation time 1174941773 ps
CPU time 3.35 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 205152 kb
Host smart-2620c30e-298f-43ea-8555-646a8037e1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399748775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.2399748775
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2314718583
Short name T29
Test name
Test status
Simulation time 805727812 ps
CPU time 2.77 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:35:50 PM PDT 24
Peak memory 205016 kb
Host smart-80d697a9-8afc-4da4-8846-d58ff5ae34b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314718583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2314718583
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3772259609
Short name T955
Test name
Test status
Simulation time 5595982520 ps
CPU time 4.52 seconds
Started Jun 05 04:35:51 PM PDT 24
Finished Jun 05 04:35:56 PM PDT 24
Peak memory 205128 kb
Host smart-b3e64bbc-d313-4fa4-b0fa-2af3af10b102
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772259609 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3772259609
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.478359541
Short name T1354
Test name
Test status
Simulation time 5944872577 ps
CPU time 4.65 seconds
Started Jun 05 04:35:47 PM PDT 24
Finished Jun 05 04:35:52 PM PDT 24
Peak memory 205164 kb
Host smart-6b80f6b7-ae88-485d-8f9a-0ddb526abfe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478359541 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.478359541
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2635847633
Short name T1046
Test name
Test status
Simulation time 1475721079 ps
CPU time 57.08 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 205096 kb
Host smart-8c30fccf-a64b-411e-959c-80a99377a21f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635847633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2635847633
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1211493729
Short name T1193
Test name
Test status
Simulation time 31212389637 ps
CPU time 357.58 seconds
Started Jun 05 04:35:57 PM PDT 24
Finished Jun 05 04:41:56 PM PDT 24
Peak memory 1616164 kb
Host smart-6fdf6184-d840-41e7-9917-51a5100c4b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211493729 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1211493729
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3702097760
Short name T1494
Test name
Test status
Simulation time 12543179457 ps
CPU time 19.1 seconds
Started Jun 05 04:35:48 PM PDT 24
Finished Jun 05 04:36:08 PM PDT 24
Peak memory 214048 kb
Host smart-9e10b956-3f00-4df8-860c-f1c59b246ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702097760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3702097760
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3824885046
Short name T1136
Test name
Test status
Simulation time 15056740771 ps
CPU time 29.28 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:36:16 PM PDT 24
Peak memory 205164 kb
Host smart-c95e599b-a595-42d0-83ea-4a3c28effe43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824885046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3824885046
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.2926980019
Short name T175
Test name
Test status
Simulation time 1047980221 ps
CPU time 18.85 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:12 PM PDT 24
Peak memory 205116 kb
Host smart-42ec7a85-0f5a-4733-9568-4f7e19dabbda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926980019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2926980019
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.453811752
Short name T371
Test name
Test status
Simulation time 19709802 ps
CPU time 0.63 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:35:57 PM PDT 24
Peak memory 204708 kb
Host smart-469b3ad2-d4dd-4609-be55-a0f3c7866879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453811752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.453811752
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1417549394
Short name T598
Test name
Test status
Simulation time 235594734 ps
CPU time 1.44 seconds
Started Jun 05 04:35:47 PM PDT 24
Finished Jun 05 04:35:50 PM PDT 24
Peak memory 213368 kb
Host smart-eefa70d8-bacb-4311-809d-bd1f95ff043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417549394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1417549394
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2460898984
Short name T770
Test name
Test status
Simulation time 117832957 ps
CPU time 6.05 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 221276 kb
Host smart-4413bd09-9741-470e-a290-93f4368fe26c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460898984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2460898984
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1078004222
Short name T1325
Test name
Test status
Simulation time 4166508392 ps
CPU time 82.88 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 733472 kb
Host smart-e31e8469-2e48-4fa4-8896-e679647a1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078004222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1078004222
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3180277085
Short name T989
Test name
Test status
Simulation time 3074007917 ps
CPU time 79.71 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 742196 kb
Host smart-2b9d1238-8a63-4d3f-a6c4-4dc353db66aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180277085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3180277085
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.831089125
Short name T985
Test name
Test status
Simulation time 118121300 ps
CPU time 1.02 seconds
Started Jun 05 04:35:46 PM PDT 24
Finished Jun 05 04:35:48 PM PDT 24
Peak memory 204932 kb
Host smart-44b50f56-77e5-46ea-b607-5ef55215856a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831089125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.831089125
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1028255542
Short name T1174
Test name
Test status
Simulation time 593846767 ps
CPU time 8.16 seconds
Started Jun 05 04:35:50 PM PDT 24
Finished Jun 05 04:35:59 PM PDT 24
Peak memory 228840 kb
Host smart-e9599795-79a1-4044-b385-82ff65dd769f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028255542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1028255542
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.279977981
Short name T745
Test name
Test status
Simulation time 36541817527 ps
CPU time 93.04 seconds
Started Jun 05 04:35:48 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 1173852 kb
Host smart-4b8b0b0a-8a22-457b-957f-72c173dfdd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279977981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.279977981
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.738740318
Short name T783
Test name
Test status
Simulation time 606427225 ps
CPU time 9.7 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:36:06 PM PDT 24
Peak memory 205088 kb
Host smart-1f42f82d-bd6d-49ef-bffd-0c72d16a370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738740318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.738740318
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2572417257
Short name T1368
Test name
Test status
Simulation time 7580041269 ps
CPU time 29.32 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 342908 kb
Host smart-15ee5b61-5e90-4b5e-853d-c2104f228521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572417257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2572417257
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1430696830
Short name T1112
Test name
Test status
Simulation time 94829359 ps
CPU time 0.74 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:35:54 PM PDT 24
Peak memory 204772 kb
Host smart-1889460d-4217-4520-8c34-53a6cbfeb682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430696830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1430696830
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.505301378
Short name T1379
Test name
Test status
Simulation time 6023641940 ps
CPU time 22.55 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:36:18 PM PDT 24
Peak memory 364276 kb
Host smart-059e5b63-481d-4ba0-bc7b-1058dd38f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505301378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.505301378
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.4272920703
Short name T473
Test name
Test status
Simulation time 1524615664 ps
CPU time 31.53 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 350360 kb
Host smart-2e2532d2-ac9e-422d-9394-7cf5cd760d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272920703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.4272920703
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2022085391
Short name T1036
Test name
Test status
Simulation time 8803765441 ps
CPU time 863.09 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:50:09 PM PDT 24
Peak memory 1902964 kb
Host smart-7bd533a4-7a49-4c14-9c61-e86ae184592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022085391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2022085391
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.899704576
Short name T1007
Test name
Test status
Simulation time 1021402883 ps
CPU time 22.13 seconds
Started Jun 05 04:35:44 PM PDT 24
Finished Jun 05 04:36:07 PM PDT 24
Peak memory 213184 kb
Host smart-d2b6bc1d-7b24-4606-8f34-571bc68ead80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899704576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.899704576
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.748386110
Short name T1389
Test name
Test status
Simulation time 10020932624 ps
CPU time 2.82 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:35:59 PM PDT 24
Peak memory 205124 kb
Host smart-ef199b31-6983-4831-9253-73686d1eae06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748386110 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.748386110
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.781930845
Short name T911
Test name
Test status
Simulation time 10125220283 ps
CPU time 47.02 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 327676 kb
Host smart-86270b85-f43a-41d8-96fb-4f757e09c9ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781930845 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.781930845
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1416345755
Short name T1158
Test name
Test status
Simulation time 10211806455 ps
CPU time 32.94 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 382752 kb
Host smart-9c217ce1-bd44-4ad5-84b8-55fa20f48318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416345755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1416345755
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.2900319358
Short name T445
Test name
Test status
Simulation time 1225667944 ps
CPU time 5.8 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:36:03 PM PDT 24
Peak memory 205072 kb
Host smart-02763dbf-f120-42d0-ada1-394936d5900e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900319358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.2900319358
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2985406421
Short name T1279
Test name
Test status
Simulation time 1472846562 ps
CPU time 2.43 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:35:59 PM PDT 24
Peak memory 205124 kb
Host smart-d2dcffe1-7707-4bda-9312-992efb1a5206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985406421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2985406421
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.282238919
Short name T858
Test name
Test status
Simulation time 1537141804 ps
CPU time 2.39 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 205064 kb
Host smart-abf96a18-d43d-41d4-ae3a-6d1f31e9aa37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282238919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.282238919
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.594477954
Short name T664
Test name
Test status
Simulation time 7704969651 ps
CPU time 5.22 seconds
Started Jun 05 04:35:58 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 205176 kb
Host smart-eb0c28cb-f61d-4d40-bce3-8d54cec3a62c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594477954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.594477954
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2227783856
Short name T831
Test name
Test status
Simulation time 2725233541 ps
CPU time 21.87 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:36:14 PM PDT 24
Peak memory 809484 kb
Host smart-b132c4fb-9452-4710-9c63-b62358db22c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227783856 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2227783856
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3482282757
Short name T383
Test name
Test status
Simulation time 2334086614 ps
CPU time 13.16 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:36:08 PM PDT 24
Peak memory 205188 kb
Host smart-2e7b7cd2-8c1d-4a25-9a94-1642bb9198bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482282757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3482282757
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.740520655
Short name T778
Test name
Test status
Simulation time 1962357862 ps
CPU time 44.02 seconds
Started Jun 05 04:35:45 PM PDT 24
Finished Jun 05 04:36:30 PM PDT 24
Peak memory 205040 kb
Host smart-050e0f36-6f5d-4b02-9378-4d7d6893a618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740520655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.740520655
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1223167347
Short name T307
Test name
Test status
Simulation time 20759551902 ps
CPU time 31.36 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:36:28 PM PDT 24
Peak memory 210980 kb
Host smart-e686ca50-01c8-4ab1-a194-a227c97a6ef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223167347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1223167347
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1098169713
Short name T304
Test name
Test status
Simulation time 6004273389 ps
CPU time 401.86 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:42:39 PM PDT 24
Peak memory 1469016 kb
Host smart-448e6a75-164a-42ca-99bb-99731c401832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098169713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1098169713
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2189650115
Short name T1213
Test name
Test status
Simulation time 1153982486 ps
CPU time 6.72 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:36:02 PM PDT 24
Peak memory 218072 kb
Host smart-ef95c218-8261-4ec5-92f9-a21bff850717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189650115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2189650115
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.3616528261
Short name T930
Test name
Test status
Simulation time 1043583826 ps
CPU time 19.6 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 205108 kb
Host smart-35c67d82-5c69-45df-b084-2686b9552c3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616528261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3616528261
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.804950400
Short name T622
Test name
Test status
Simulation time 60468231 ps
CPU time 0.64 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:03 PM PDT 24
Peak memory 204736 kb
Host smart-e7d066f9-9332-41e9-8ab4-f67005b72124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804950400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.804950400
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2167722172
Short name T57
Test name
Test status
Simulation time 113699318 ps
CPU time 2.09 seconds
Started Jun 05 04:35:58 PM PDT 24
Finished Jun 05 04:36:01 PM PDT 24
Peak memory 213364 kb
Host smart-cd4a3b95-1646-498a-80d9-028d629596fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167722172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2167722172
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2110243119
Short name T435
Test name
Test status
Simulation time 1053185297 ps
CPU time 6.22 seconds
Started Jun 05 04:35:51 PM PDT 24
Finished Jun 05 04:35:57 PM PDT 24
Peak memory 259224 kb
Host smart-c5631442-d7d8-4a3c-8085-73ae3b7cb994
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110243119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2110243119
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4128463546
Short name T158
Test name
Test status
Simulation time 4694789985 ps
CPU time 176.52 seconds
Started Jun 05 04:35:58 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 767360 kb
Host smart-b4fdcf13-2ea0-4aa1-9581-ad0bb80c11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128463546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4128463546
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.859942748
Short name T650
Test name
Test status
Simulation time 2831132498 ps
CPU time 117.05 seconds
Started Jun 05 04:35:54 PM PDT 24
Finished Jun 05 04:37:52 PM PDT 24
Peak memory 574264 kb
Host smart-192a1a04-7568-48f4-80f7-5a61b0007e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859942748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.859942748
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.971285702
Short name T462
Test name
Test status
Simulation time 402233307 ps
CPU time 1.18 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 204952 kb
Host smart-ca10ee44-f7cf-46e3-86bb-c9e062cb660e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971285702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.971285702
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3763270345
Short name T1482
Test name
Test status
Simulation time 359889891 ps
CPU time 11.07 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:36:05 PM PDT 24
Peak memory 240428 kb
Host smart-59d41093-ea7a-4083-a357-e0587381ec9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763270345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3763270345
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3035702503
Short name T183
Test name
Test status
Simulation time 35882957205 ps
CPU time 117.2 seconds
Started Jun 05 04:35:58 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 1121840 kb
Host smart-6d9ef364-cb2f-421f-b48f-d897b76b726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035702503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3035702503
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2138973282
Short name T52
Test name
Test status
Simulation time 520851502 ps
CPU time 16.9 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 205188 kb
Host smart-74fda9c9-e499-4ce4-bec8-a5616eb0a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138973282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2138973282
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1628685704
Short name T318
Test name
Test status
Simulation time 6526667074 ps
CPU time 34.53 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:38 PM PDT 24
Peak memory 411204 kb
Host smart-1558f951-c7ed-4329-a23f-13fca88dedee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628685704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1628685704
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2643046374
Short name T1410
Test name
Test status
Simulation time 45083747 ps
CPU time 0.68 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 204704 kb
Host smart-61b41951-2a3f-4426-aebf-f1bad22afc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643046374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2643046374
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.660886423
Short name T1069
Test name
Test status
Simulation time 5362653412 ps
CPU time 157.84 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 567216 kb
Host smart-ffd569a8-eadd-4fb0-9828-b6851e25167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660886423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.660886423
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2434845796
Short name T947
Test name
Test status
Simulation time 3731671088 ps
CPU time 90.74 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 303464 kb
Host smart-b95f371b-5291-432f-a580-f9d660efda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434845796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2434845796
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.995953439
Short name T131
Test name
Test status
Simulation time 74701638802 ps
CPU time 1044.5 seconds
Started Jun 05 04:35:56 PM PDT 24
Finished Jun 05 04:53:22 PM PDT 24
Peak memory 3577924 kb
Host smart-27d40e7c-bcbf-485b-82b6-012d53478d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995953439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.995953439
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1107215727
Short name T704
Test name
Test status
Simulation time 3496930653 ps
CPU time 19.51 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 221120 kb
Host smart-de800869-7678-406a-9500-335d662d2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107215727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1107215727
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3694912607
Short name T1087
Test name
Test status
Simulation time 10696743465 ps
CPU time 4.01 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:35:58 PM PDT 24
Peak memory 205148 kb
Host smart-84a8c117-dc75-4661-9a6e-84e97d83248e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694912607 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3694912607
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1924236302
Short name T984
Test name
Test status
Simulation time 10181691951 ps
CPU time 12.46 seconds
Started Jun 05 04:35:57 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 234404 kb
Host smart-23718046-75eb-441a-a976-c8ba05a0a67e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924236302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1924236302
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3951766870
Short name T865
Test name
Test status
Simulation time 10639553461 ps
CPU time 14.98 seconds
Started Jun 05 04:35:57 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 321684 kb
Host smart-699407ac-1888-423b-895a-67eefa6fc060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951766870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3951766870
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.1333365339
Short name T662
Test name
Test status
Simulation time 1729230358 ps
CPU time 2.09 seconds
Started Jun 05 04:36:07 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 205068 kb
Host smart-1a448d9c-33c2-48d8-977b-71ef87d76675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333365339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.1333365339
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3404315009
Short name T321
Test name
Test status
Simulation time 1089742870 ps
CPU time 3.27 seconds
Started Jun 05 04:36:06 PM PDT 24
Finished Jun 05 04:36:09 PM PDT 24
Peak memory 205068 kb
Host smart-e4e11330-e06f-4b3c-a1a4-af5d69a59013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404315009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3404315009
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2138491158
Short name T360
Test name
Test status
Simulation time 1643532886 ps
CPU time 2.68 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 205076 kb
Host smart-4d3b45ca-6365-426a-bd53-7eee9c7f8f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138491158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2138491158
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3300818459
Short name T764
Test name
Test status
Simulation time 2542420821 ps
CPU time 7.44 seconds
Started Jun 05 04:35:57 PM PDT 24
Finished Jun 05 04:36:05 PM PDT 24
Peak memory 221464 kb
Host smart-2f33b36b-175b-42f5-b227-a0bb3f935d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300818459 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3300818459
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1055933507
Short name T725
Test name
Test status
Simulation time 822502109 ps
CPU time 28.48 seconds
Started Jun 05 04:35:59 PM PDT 24
Finished Jun 05 04:36:28 PM PDT 24
Peak memory 205036 kb
Host smart-6b78f5f7-8bf2-4877-8181-d0009bcf224d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055933507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1055933507
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.571094788
Short name T347
Test name
Test status
Simulation time 574181229 ps
CPU time 25.3 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:36:18 PM PDT 24
Peak memory 205108 kb
Host smart-35b52014-23b0-40af-b422-31c9889bf62b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571094788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.571094788
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.778858010
Short name T1045
Test name
Test status
Simulation time 32350960796 ps
CPU time 301.16 seconds
Started Jun 05 04:35:53 PM PDT 24
Finished Jun 05 04:40:55 PM PDT 24
Peak memory 3146268 kb
Host smart-b71bc22c-b41b-4a3c-b555-10ea9c789313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778858010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.778858010
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2513363628
Short name T1288
Test name
Test status
Simulation time 5065621056 ps
CPU time 55.25 seconds
Started Jun 05 04:35:52 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 712764 kb
Host smart-7f512466-ef88-403a-b66d-d8dc0d2369b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513363628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2513363628
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1683832682
Short name T988
Test name
Test status
Simulation time 1496960786 ps
CPU time 7.77 seconds
Started Jun 05 04:35:55 PM PDT 24
Finished Jun 05 04:36:04 PM PDT 24
Peak memory 213312 kb
Host smart-2b9712cf-86c7-4a67-93bc-62ac556a0014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683832682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1683832682
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.1382456654
Short name T1223
Test name
Test status
Simulation time 1267436731 ps
CPU time 16.76 seconds
Started Jun 05 04:36:04 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 205068 kb
Host smart-4a6fc75e-bbcb-4cf7-b876-308016aecad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382456654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.1382456654
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2466899972
Short name T685
Test name
Test status
Simulation time 75873993 ps
CPU time 0.59 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:12 PM PDT 24
Peak memory 204756 kb
Host smart-7e0fee50-90f9-42dd-8c41-4c4b2b2d6f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466899972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2466899972
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2396538544
Short name T766
Test name
Test status
Simulation time 2267465418 ps
CPU time 5.84 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:08 PM PDT 24
Peak memory 224220 kb
Host smart-5879c941-d4af-4254-b75d-8d1eef043230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396538544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2396538544
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.88986883
Short name T649
Test name
Test status
Simulation time 2235056060 ps
CPU time 10.48 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:12 PM PDT 24
Peak memory 324184 kb
Host smart-ac56cbf8-4051-4031-a412-e62d3906478d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88986883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty
.88986883
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.389943433
Short name T481
Test name
Test status
Simulation time 4490538095 ps
CPU time 88.47 seconds
Started Jun 05 04:36:03 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 765760 kb
Host smart-d844eb41-68ed-4e49-94ce-8179da0c213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389943433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.389943433
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1822958399
Short name T152
Test name
Test status
Simulation time 8425409346 ps
CPU time 74.17 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 707060 kb
Host smart-cf1329b9-07b7-41af-95d7-8bee55ab013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822958399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1822958399
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3226441361
Short name T1031
Test name
Test status
Simulation time 495169126 ps
CPU time 0.96 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:03 PM PDT 24
Peak memory 204784 kb
Host smart-955352ef-7990-4d37-a15a-248b9f6725db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226441361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3226441361
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.823950509
Short name T929
Test name
Test status
Simulation time 161523555 ps
CPU time 3.81 seconds
Started Jun 05 04:36:05 PM PDT 24
Finished Jun 05 04:36:09 PM PDT 24
Peak memory 205032 kb
Host smart-a91d6293-c7c9-4889-8cf0-c1fff3d7f24e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823950509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
823950509
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.962331880
Short name T374
Test name
Test status
Simulation time 2920241972 ps
CPU time 63.32 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:37:06 PM PDT 24
Peak memory 592904 kb
Host smart-315358da-9d84-4dd1-83b4-f89200291db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962331880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.962331880
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2941057682
Short name T1408
Test name
Test status
Simulation time 5833430849 ps
CPU time 34.62 seconds
Started Jun 05 04:36:08 PM PDT 24
Finished Jun 05 04:36:43 PM PDT 24
Peak memory 205080 kb
Host smart-670590a6-acad-478b-bae7-72e55d09665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941057682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2941057682
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.574010009
Short name T412
Test name
Test status
Simulation time 2011961469 ps
CPU time 89.53 seconds
Started Jun 05 04:36:14 PM PDT 24
Finished Jun 05 04:37:44 PM PDT 24
Peak memory 334832 kb
Host smart-55cbaa69-be9e-4684-97a3-8c9c9a7566c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574010009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.574010009
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2200138049
Short name T144
Test name
Test status
Simulation time 30532520 ps
CPU time 0.72 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:03 PM PDT 24
Peak memory 204712 kb
Host smart-58a8c3c9-2df6-4d3e-8cf8-38dcc6bebecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200138049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2200138049
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1748728044
Short name T53
Test name
Test status
Simulation time 1017620197 ps
CPU time 10.35 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 229664 kb
Host smart-ccdb4f07-4738-446b-8e77-1c9bbf3c8892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748728044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1748728044
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2678620394
Short name T1486
Test name
Test status
Simulation time 4820902639 ps
CPU time 56.44 seconds
Started Jun 05 04:36:03 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 290172 kb
Host smart-a10ac5d4-3c31-49cf-ac73-58665741280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678620394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2678620394
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.705403001
Short name T876
Test name
Test status
Simulation time 61661772467 ps
CPU time 1597.05 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 05:02:40 PM PDT 24
Peak memory 2329824 kb
Host smart-a8e4c233-eb52-458c-a39f-7e89109af400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705403001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.705403001
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1733553990
Short name T117
Test name
Test status
Simulation time 2142497172 ps
CPU time 22.72 seconds
Started Jun 05 04:36:00 PM PDT 24
Finished Jun 05 04:36:23 PM PDT 24
Peak memory 213268 kb
Host smart-ba4a7514-6c56-4cdd-b231-d6c63d73c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733553990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1733553990
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3168399346
Short name T900
Test name
Test status
Simulation time 2316974684 ps
CPU time 5.21 seconds
Started Jun 05 04:36:14 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 205168 kb
Host smart-c3003f8c-a8bc-4475-ad63-fe31d1a724f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168399346 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3168399346
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3871052938
Short name T1382
Test name
Test status
Simulation time 10561113811 ps
CPU time 13 seconds
Started Jun 05 04:36:05 PM PDT 24
Finished Jun 05 04:36:19 PM PDT 24
Peak memory 256584 kb
Host smart-aaa07843-6e68-4137-a1f4-afef79beacd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871052938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3871052938
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.4150069661
Short name T448
Test name
Test status
Simulation time 10119102254 ps
CPU time 13.78 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 284412 kb
Host smart-6d0cfa6b-8544-406d-819c-3d5a10fe4ae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150069661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.4150069661
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1714233329
Short name T352
Test name
Test status
Simulation time 2354339335 ps
CPU time 2.93 seconds
Started Jun 05 04:36:08 PM PDT 24
Finished Jun 05 04:36:12 PM PDT 24
Peak memory 205144 kb
Host smart-ccfe3ec0-135b-49c5-9312-15489ce4e344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714233329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1714233329
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.319689648
Short name T1133
Test name
Test status
Simulation time 1446947443 ps
CPU time 2.3 seconds
Started Jun 05 04:36:16 PM PDT 24
Finished Jun 05 04:36:19 PM PDT 24
Peak memory 205136 kb
Host smart-b0b66f91-87af-441e-b0c2-a7bd5ac32b69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319689648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.319689648
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2939790606
Short name T728
Test name
Test status
Simulation time 1847043728 ps
CPU time 3.11 seconds
Started Jun 05 04:36:09 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 205132 kb
Host smart-6beb1e71-b29b-4b52-a7ac-af014bafa741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939790606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2939790606
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2367474875
Short name T1226
Test name
Test status
Simulation time 6525584335 ps
CPU time 4.28 seconds
Started Jun 05 04:36:01 PM PDT 24
Finished Jun 05 04:36:07 PM PDT 24
Peak memory 205076 kb
Host smart-12e0f2c2-2314-4d5e-bbcd-f6b650a9b332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367474875 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2367474875
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2633837773
Short name T421
Test name
Test status
Simulation time 15166291169 ps
CPU time 19.57 seconds
Started Jun 05 04:36:05 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 598540 kb
Host smart-a2a7a038-2eb9-4d17-befa-d62bee5c8d1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633837773 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2633837773
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3043074567
Short name T794
Test name
Test status
Simulation time 3128000634 ps
CPU time 30.89 seconds
Started Jun 05 04:36:03 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 205144 kb
Host smart-b1a80bca-37ba-46b9-a062-76fe2792c6d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043074567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3043074567
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3973372790
Short name T1346
Test name
Test status
Simulation time 2473932723 ps
CPU time 52.59 seconds
Started Jun 05 04:36:03 PM PDT 24
Finished Jun 05 04:36:56 PM PDT 24
Peak memory 205284 kb
Host smart-e3138663-e2d2-449f-a590-2c47be9f065b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973372790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3973372790
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2444427886
Short name T971
Test name
Test status
Simulation time 56187106645 ps
CPU time 111.66 seconds
Started Jun 05 04:36:06 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 1511872 kb
Host smart-75774283-0840-4430-8f77-de044ea5d36b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444427886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2444427886
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2053592203
Short name T263
Test name
Test status
Simulation time 42943323335 ps
CPU time 190.31 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:39:13 PM PDT 24
Peak memory 1547980 kb
Host smart-be4c80b4-4796-499c-aaab-8a9234be5ccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053592203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2053592203
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3471624258
Short name T1062
Test name
Test status
Simulation time 4615567547 ps
CPU time 6.96 seconds
Started Jun 05 04:36:02 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 213388 kb
Host smart-9ebb552e-474d-4d13-a894-636ed2ad3dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471624258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3471624258
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.233891917
Short name T757
Test name
Test status
Simulation time 1546062739 ps
CPU time 21.29 seconds
Started Jun 05 04:36:11 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 205080 kb
Host smart-9ae3b52e-ca9b-4d7d-bfff-9c7e386faa36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233891917 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.233891917
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3502299619
Short name T184
Test name
Test status
Simulation time 25653100 ps
CPU time 0.63 seconds
Started Jun 05 04:34:36 PM PDT 24
Finished Jun 05 04:34:39 PM PDT 24
Peak memory 204652 kb
Host smart-3bc71280-580b-4d3d-9ede-c40563a2597d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502299619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3502299619
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1855481136
Short name T760
Test name
Test status
Simulation time 368668171 ps
CPU time 1.88 seconds
Started Jun 05 04:35:02 PM PDT 24
Finished Jun 05 04:35:04 PM PDT 24
Peak memory 221428 kb
Host smart-332e12e3-c80c-484a-b8f8-ab0e23d2d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855481136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1855481136
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1451421147
Short name T761
Test name
Test status
Simulation time 2220033172 ps
CPU time 5.24 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:48 PM PDT 24
Peak memory 248828 kb
Host smart-594be037-3422-476a-8663-04511c11d9a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451421147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1451421147
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.878880368
Short name T1261
Test name
Test status
Simulation time 6965809498 ps
CPU time 201.63 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:38:07 PM PDT 24
Peak memory 828664 kb
Host smart-36067386-80f5-44b9-ad1b-c07e4ed3808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878880368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.878880368
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.201465651
Short name T346
Test name
Test status
Simulation time 4074196657 ps
CPU time 71.76 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:35:47 PM PDT 24
Peak memory 728264 kb
Host smart-e66aa193-8861-4288-8ad1-1a6cbda72a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201465651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.201465651
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3020358780
Short name T553
Test name
Test status
Simulation time 251565665 ps
CPU time 1.09 seconds
Started Jun 05 04:34:49 PM PDT 24
Finished Jun 05 04:34:50 PM PDT 24
Peak memory 204940 kb
Host smart-6c039e14-0644-4679-93b9-1c26b96ee7b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020358780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3020358780
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3377017472
Short name T1487
Test name
Test status
Simulation time 630111137 ps
CPU time 3.9 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:34:55 PM PDT 24
Peak memory 205072 kb
Host smart-ca8ad149-09a9-4f8a-8af8-79b68080d31c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377017472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3377017472
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1833645567
Short name T1205
Test name
Test status
Simulation time 4857099993 ps
CPU time 383.77 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:41:01 PM PDT 24
Peak memory 1309128 kb
Host smart-71d99ccf-788f-49d5-80ca-370206f547b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833645567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1833645567
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.4292568304
Short name T1297
Test name
Test status
Simulation time 261528210 ps
CPU time 9.86 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:35:01 PM PDT 24
Peak memory 204996 kb
Host smart-47152fe6-7118-4edc-a050-1ddcd1844f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292568304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.4292568304
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2059745545
Short name T1439
Test name
Test status
Simulation time 4456040469 ps
CPU time 29.71 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 311240 kb
Host smart-19f3e667-52e9-493a-9a3d-2713d1e9eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059745545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2059745545
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.201545253
Short name T1033
Test name
Test status
Simulation time 19114769 ps
CPU time 0.67 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 204708 kb
Host smart-e5a750e2-2585-41bd-b960-76857014c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201545253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.201545253
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.399478506
Short name T639
Test name
Test status
Simulation time 4975666758 ps
CPU time 106.79 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 610352 kb
Host smart-8af49620-8cc4-449f-ba3a-4826f09c2231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399478506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.399478506
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3461775893
Short name T1155
Test name
Test status
Simulation time 1863873662 ps
CPU time 36.16 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:35:13 PM PDT 24
Peak memory 440412 kb
Host smart-4381e74c-728d-4f47-b8c2-a577bcddaf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461775893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3461775893
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.988335958
Short name T1180
Test name
Test status
Simulation time 1857734302 ps
CPU time 17.84 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 221332 kb
Host smart-7b250cdc-47dc-41f9-8220-26410ed3128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988335958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.988335958
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3456946310
Short name T191
Test name
Test status
Simulation time 1054849751 ps
CPU time 0.93 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:34:56 PM PDT 24
Peak memory 222960 kb
Host smart-9f927a09-51f7-4cef-bb5d-2af03d7328d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456946310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3456946310
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.453554026
Short name T1025
Test name
Test status
Simulation time 974695255 ps
CPU time 5.46 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 213496 kb
Host smart-2eadfe65-22bf-4b87-8528-2ae4e2d4c068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453554026 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.453554026
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3743869481
Short name T513
Test name
Test status
Simulation time 10082612754 ps
CPU time 47.63 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:35:33 PM PDT 24
Peak memory 324100 kb
Host smart-9339e106-197d-4216-ba3b-b422a5b14b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743869481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3743869481
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2816725681
Short name T311
Test name
Test status
Simulation time 1849774995 ps
CPU time 2.13 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 205092 kb
Host smart-7952f8cf-5964-4ce0-8438-b7da7ab0cf61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816725681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2816725681
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3616769405
Short name T1332
Test name
Test status
Simulation time 1034398104 ps
CPU time 4.89 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 205112 kb
Host smart-a6d2cace-3d26-4249-a290-22dd077b8024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616769405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3616769405
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3891930225
Short name T292
Test name
Test status
Simulation time 904741203 ps
CPU time 2.77 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:34:54 PM PDT 24
Peak memory 205064 kb
Host smart-2ed9a1b4-3b77-4016-809f-1fff1bad07a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891930225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3891930225
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2496497112
Short name T313
Test name
Test status
Simulation time 3138560747 ps
CPU time 4.41 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:45 PM PDT 24
Peak memory 205304 kb
Host smart-2abd5ca1-e011-48b4-b0fb-d2f32e658aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496497112 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2496497112
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3585296178
Short name T519
Test name
Test status
Simulation time 15997761117 ps
CPU time 72.09 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 1136496 kb
Host smart-ef27e906-6a09-4d6f-bfd2-a26a72bee102
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585296178 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3585296178
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1534836293
Short name T1239
Test name
Test status
Simulation time 1022646983 ps
CPU time 41.15 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:35:19 PM PDT 24
Peak memory 205084 kb
Host smart-30d097a3-051b-4000-b862-b295abc76504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534836293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1534836293
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1762947698
Short name T1121
Test name
Test status
Simulation time 12543996890 ps
CPU time 22.62 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 226508 kb
Host smart-92635aa3-a6e3-4c2c-9d55-c6fdc6fc8547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762947698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1762947698
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1360237911
Short name T25
Test name
Test status
Simulation time 37683145776 ps
CPU time 65.62 seconds
Started Jun 05 04:34:42 PM PDT 24
Finished Jun 05 04:35:49 PM PDT 24
Peak memory 1098904 kb
Host smart-ddf224d8-90fb-4197-9f0b-28613ee835eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360237911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1360237911
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.917191785
Short name T340
Test name
Test status
Simulation time 42815446285 ps
CPU time 3213.43 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 05:28:08 PM PDT 24
Peak memory 4913600 kb
Host smart-823b3232-5cbd-4a0d-8c0f-e2159f24132e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917191785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.917191785
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3350969873
Short name T806
Test name
Test status
Simulation time 2492980400 ps
CPU time 7.08 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 220996 kb
Host smart-60c678fa-154b-46de-82db-20011dcafb05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350969873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3350969873
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2188350703
Short name T746
Test name
Test status
Simulation time 1107062715 ps
CPU time 16.33 seconds
Started Jun 05 04:34:48 PM PDT 24
Finished Jun 05 04:35:05 PM PDT 24
Peak memory 205080 kb
Host smart-72729abe-578f-4d71-9b86-f5adee879d78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188350703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2188350703
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.4061218746
Short name T1229
Test name
Test status
Simulation time 134814442 ps
CPU time 0.63 seconds
Started Jun 05 04:36:08 PM PDT 24
Finished Jun 05 04:36:10 PM PDT 24
Peak memory 204728 kb
Host smart-1966e6a7-d82e-428b-81b5-03f30c0cc151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061218746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.4061218746
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3383622037
Short name T645
Test name
Test status
Simulation time 100247813 ps
CPU time 1.77 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:12 PM PDT 24
Peak memory 216892 kb
Host smart-0db24b48-2cc0-4e05-bb25-ce9684e469a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383622037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3383622037
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2290517184
Short name T1067
Test name
Test status
Simulation time 758928552 ps
CPU time 9.08 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 287884 kb
Host smart-7da7c381-dffd-4ee3-8fc5-f0e535d0377b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290517184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2290517184
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.972991759
Short name T459
Test name
Test status
Simulation time 3774482930 ps
CPU time 120.97 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 535128 kb
Host smart-c6223eda-fdb0-4f4b-8898-753f4b8f7bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972991759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.972991759
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2872503116
Short name T616
Test name
Test status
Simulation time 686737550 ps
CPU time 1.2 seconds
Started Jun 05 04:36:11 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 204944 kb
Host smart-c75f820b-061b-44e5-848b-c26eaeb136f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872503116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2872503116
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3272950455
Short name T41
Test name
Test status
Simulation time 730593548 ps
CPU time 10.85 seconds
Started Jun 05 04:36:12 PM PDT 24
Finished Jun 05 04:36:24 PM PDT 24
Peak memory 239344 kb
Host smart-362458fa-962b-4a23-adc9-a25b715cf374
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272950455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3272950455
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2974669957
Short name T840
Test name
Test status
Simulation time 15827051363 ps
CPU time 111.09 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 1230660 kb
Host smart-8b79b24b-e416-4256-b2e0-a5d8da99c494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974669957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2974669957
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.180867829
Short name T591
Test name
Test status
Simulation time 478247652 ps
CPU time 7.01 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 205036 kb
Host smart-59d1273b-69f7-4b93-91db-cb4c7e30ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180867829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.180867829
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2618005604
Short name T385
Test name
Test status
Simulation time 8550801408 ps
CPU time 100.33 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:37:52 PM PDT 24
Peak memory 412588 kb
Host smart-90a0f9fd-0ab4-4e77-9f5b-3cf048c3e458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618005604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2618005604
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.13865241
Short name T476
Test name
Test status
Simulation time 21754930 ps
CPU time 0.72 seconds
Started Jun 05 04:36:14 PM PDT 24
Finished Jun 05 04:36:15 PM PDT 24
Peak memory 204880 kb
Host smart-4a766ff3-cb31-4068-b47a-bb2943ecb29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13865241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.13865241
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1574822067
Short name T65
Test name
Test status
Simulation time 7061653085 ps
CPU time 699.52 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:47:50 PM PDT 24
Peak memory 1577292 kb
Host smart-e0e2d51b-2965-45c1-925c-151f152deea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574822067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1574822067
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1354844098
Short name T1293
Test name
Test status
Simulation time 5360537868 ps
CPU time 71.95 seconds
Started Jun 05 04:36:08 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 326984 kb
Host smart-e8acd58f-cdcb-44d3-8054-9fcf2c5a9aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354844098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1354844098
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3657266639
Short name T235
Test name
Test status
Simulation time 77658565416 ps
CPU time 536.68 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:45:08 PM PDT 24
Peak memory 2286592 kb
Host smart-c3f28b91-7046-485d-b799-f78c10390c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657266639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3657266639
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3617691741
Short name T1090
Test name
Test status
Simulation time 1912697786 ps
CPU time 43.97 seconds
Started Jun 05 04:36:15 PM PDT 24
Finished Jun 05 04:37:00 PM PDT 24
Peak memory 213156 kb
Host smart-c3aa498d-1ea0-4e13-8f1e-1cb45ec184de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617691741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3617691741
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3645100050
Short name T1465
Test name
Test status
Simulation time 2233441671 ps
CPU time 2.2 seconds
Started Jun 05 04:36:12 PM PDT 24
Finished Jun 05 04:36:15 PM PDT 24
Peak memory 205188 kb
Host smart-25c4456f-c5ea-4d32-b439-a26fe25a6e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645100050 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3645100050
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1140098630
Short name T342
Test name
Test status
Simulation time 10468131905 ps
CPU time 5.73 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 220416 kb
Host smart-4fd81fde-5b5b-4a7f-bc1e-dec8d2a77792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140098630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1140098630
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1381822890
Short name T361
Test name
Test status
Simulation time 10213929106 ps
CPU time 38.78 seconds
Started Jun 05 04:36:09 PM PDT 24
Finished Jun 05 04:36:49 PM PDT 24
Peak memory 418296 kb
Host smart-b1950ec2-fe3f-4e44-80ca-909f009582c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381822890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1381822890
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2245934078
Short name T424
Test name
Test status
Simulation time 1229403093 ps
CPU time 5.31 seconds
Started Jun 05 04:36:14 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 205108 kb
Host smart-13fcfb9c-11c0-460c-a065-c682fd3bd06f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245934078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2245934078
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1325206873
Short name T1089
Test name
Test status
Simulation time 1029917268 ps
CPU time 6.17 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 205040 kb
Host smart-550a4eb6-40e2-4e3f-945c-f5306ac3c245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325206873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1325206873
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3507344177
Short name T658
Test name
Test status
Simulation time 458556486 ps
CPU time 2.81 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 205052 kb
Host smart-d25bf774-9542-468b-a994-2c5200627dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507344177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3507344177
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.4129856037
Short name T447
Test name
Test status
Simulation time 18344897018 ps
CPU time 5.45 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 216576 kb
Host smart-70759b46-88ea-4d9f-97fa-07df719c9a5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129856037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.4129856037
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2509031141
Short name T1212
Test name
Test status
Simulation time 13514115726 ps
CPU time 85.12 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:37:36 PM PDT 24
Peak memory 1636564 kb
Host smart-8b46e256-3ae4-4cdc-98f9-1b7b05ec7cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509031141 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2509031141
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.804079802
Short name T610
Test name
Test status
Simulation time 2542728035 ps
CPU time 22.29 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 205128 kb
Host smart-8b79900f-b953-4704-a931-5af082453777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804079802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.804079802
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.278559268
Short name T1340
Test name
Test status
Simulation time 18001282909 ps
CPU time 26.12 seconds
Started Jun 05 04:36:15 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 220936 kb
Host smart-9d3693fa-fc31-4cfc-8801-008dcd3e0ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278559268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.278559268
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3482159382
Short name T1392
Test name
Test status
Simulation time 39512170409 ps
CPU time 611.17 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:46:25 PM PDT 24
Peak memory 5016436 kb
Host smart-27a23b27-1366-4d71-9fc1-488b5887093f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482159382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3482159382
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2083386459
Short name T401
Test name
Test status
Simulation time 34925468592 ps
CPU time 39.9 seconds
Started Jun 05 04:36:12 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 411604 kb
Host smart-034e3015-3235-45da-8b4b-7bcaa8263dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083386459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2083386459
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3716932076
Short name T1394
Test name
Test status
Simulation time 6283377181 ps
CPU time 6.82 seconds
Started Jun 05 04:36:14 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 220560 kb
Host smart-aea65b1e-b9e5-4082-9e9f-ca929dfeeac2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716932076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3716932076
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.122737436
Short name T1300
Test name
Test status
Simulation time 1050383476 ps
CPU time 20.61 seconds
Started Jun 05 04:36:11 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 205112 kb
Host smart-1f350622-526f-4739-9d19-24221b43b195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122737436 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.122737436
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2594311056
Short name T594
Test name
Test status
Simulation time 55646323 ps
CPU time 0.63 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:36:18 PM PDT 24
Peak memory 204732 kb
Host smart-568093dc-c8e3-4939-af96-591af886e4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594311056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2594311056
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3121475380
Short name T1370
Test name
Test status
Simulation time 314081372 ps
CPU time 6 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 221532 kb
Host smart-bd6af4f7-0809-4323-96b7-fd8e7183df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121475380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3121475380
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.503434106
Short name T957
Test name
Test status
Simulation time 863547021 ps
CPU time 10.23 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 240804 kb
Host smart-ebeed272-f299-4e09-b462-57d5ebf42197
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503434106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.503434106
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2828053149
Short name T853
Test name
Test status
Simulation time 22471223461 ps
CPU time 132.31 seconds
Started Jun 05 04:36:12 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 651504 kb
Host smart-5f4901a2-b91d-4b86-9466-4bbfa9c7a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828053149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2828053149
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3503160828
Short name T162
Test name
Test status
Simulation time 3671853673 ps
CPU time 66.32 seconds
Started Jun 05 04:36:09 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 653476 kb
Host smart-8ea741e1-5d24-4db8-a9ba-95cfddcf1058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503160828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3503160828
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1090060688
Short name T730
Test name
Test status
Simulation time 339335293 ps
CPU time 1.01 seconds
Started Jun 05 04:36:15 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 204624 kb
Host smart-f77dfd2d-e9d3-491d-8a93-8ec5a983d7a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090060688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1090060688
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.297951485
Short name T98
Test name
Test status
Simulation time 1190582706 ps
CPU time 4.04 seconds
Started Jun 05 04:36:10 PM PDT 24
Finished Jun 05 04:36:15 PM PDT 24
Peak memory 229404 kb
Host smart-70d92603-9846-43dd-afd3-da04c8457f04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297951485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
297951485
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.400240192
Short name T1109
Test name
Test status
Simulation time 8014288269 ps
CPU time 136.45 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 1180500 kb
Host smart-f5fc7d9d-d6c5-48b6-a942-718ef8ea9467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400240192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.400240192
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3516960359
Short name T798
Test name
Test status
Simulation time 618696076 ps
CPU time 26.04 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:53 PM PDT 24
Peak memory 204948 kb
Host smart-a4db5aa2-8d38-4e4c-92f8-428bb8b8bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516960359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3516960359
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3290583160
Short name T1015
Test name
Test status
Simulation time 5858998719 ps
CPU time 70.96 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:37:30 PM PDT 24
Peak memory 330972 kb
Host smart-cc329b97-508b-4d07-9e9a-811ef857fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290583160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3290583160
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3162296682
Short name T860
Test name
Test status
Simulation time 55355195 ps
CPU time 0.67 seconds
Started Jun 05 04:36:09 PM PDT 24
Finished Jun 05 04:36:11 PM PDT 24
Peak memory 204684 kb
Host smart-e47c8164-603d-4f6e-9632-beee1a45e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162296682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3162296682
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3113149342
Short name T168
Test name
Test status
Simulation time 7791496605 ps
CPU time 107.38 seconds
Started Jun 05 04:36:11 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 238712 kb
Host smart-58bbed1b-0af7-4425-b069-f27819439e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113149342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3113149342
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.386065734
Short name T367
Test name
Test status
Simulation time 8451324120 ps
CPU time 38.72 seconds
Started Jun 05 04:36:13 PM PDT 24
Finished Jun 05 04:36:53 PM PDT 24
Peak memory 415180 kb
Host smart-24baa1bb-77a0-4a1f-adfe-52ce43324f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386065734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.386065734
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1972393937
Short name T1403
Test name
Test status
Simulation time 13274152062 ps
CPU time 268.61 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:40:48 PM PDT 24
Peak memory 1088240 kb
Host smart-80c9e9eb-96c0-41c0-8225-53ce92f128da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972393937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1972393937
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1176158291
Short name T1179
Test name
Test status
Simulation time 663880467 ps
CPU time 32.13 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 213356 kb
Host smart-c7e9bf3f-1ab9-4a61-b8d9-60b28701b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176158291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1176158291
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1423531205
Short name T642
Test name
Test status
Simulation time 1020101820 ps
CPU time 5.24 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:25 PM PDT 24
Peak memory 213340 kb
Host smart-d0bdfe63-e914-41d2-9478-1f883ce163a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423531205 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1423531205
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.562112603
Short name T93
Test name
Test status
Simulation time 10182305725 ps
CPU time 45.19 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:37:04 PM PDT 24
Peak memory 323676 kb
Host smart-439ff0b8-9aec-478b-bc0f-6e7770fa7195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562112603 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.562112603
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1418649577
Short name T850
Test name
Test status
Simulation time 10411464535 ps
CPU time 31.27 seconds
Started Jun 05 04:36:21 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 397800 kb
Host smart-64f3ab17-ea48-4294-97fc-1a0142988203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418649577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1418649577
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.1549651222
Short name T788
Test name
Test status
Simulation time 2318420642 ps
CPU time 2.14 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 205188 kb
Host smart-5fe4b1b5-563c-4af1-8390-43cb38231cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549651222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.1549651222
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.832308072
Short name T587
Test name
Test status
Simulation time 1614058832 ps
CPU time 1.15 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 204916 kb
Host smart-a3fcc21a-d2a9-4717-8ff9-214387d63d34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832308072 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.832308072
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1274175050
Short name T1088
Test name
Test status
Simulation time 480146196 ps
CPU time 2.79 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:23 PM PDT 24
Peak memory 205064 kb
Host smart-02e7c991-1a02-480a-8889-14e33d0f400e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274175050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1274175050
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1303394848
Short name T733
Test name
Test status
Simulation time 2153991488 ps
CPU time 6.19 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:36:24 PM PDT 24
Peak memory 218404 kb
Host smart-0c6d52d8-861e-4675-a128-cb471e49d042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303394848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1303394848
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2321259206
Short name T344
Test name
Test status
Simulation time 10462254633 ps
CPU time 21.32 seconds
Started Jun 05 04:36:20 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 491244 kb
Host smart-ea256d8d-7437-43da-bcaf-10b8a29b1cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321259206 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2321259206
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3703971254
Short name T1318
Test name
Test status
Simulation time 3958028899 ps
CPU time 13.55 seconds
Started Jun 05 04:36:21 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 205280 kb
Host smart-a64ee752-53fe-4c8e-88c5-48444d97688d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703971254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3703971254
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1776446307
Short name T1257
Test name
Test status
Simulation time 5226393657 ps
CPU time 18.49 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 228492 kb
Host smart-ed6d9846-1efb-43b5-ae88-17d7bda37a30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776446307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1776446307
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1128320510
Short name T1184
Test name
Test status
Simulation time 24256594224 ps
CPU time 34.49 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:55 PM PDT 24
Peak memory 641860 kb
Host smart-7eda353b-f518-48c2-8b59-d0adfc1d4a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128320510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1128320510
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.268723880
Short name T502
Test name
Test status
Simulation time 14685390542 ps
CPU time 142.87 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 645532 kb
Host smart-48ab67b5-891c-4377-a4e0-609c8ce029e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268723880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.268723880
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.652110974
Short name T854
Test name
Test status
Simulation time 1106498745 ps
CPU time 6.81 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:27 PM PDT 24
Peak memory 218228 kb
Host smart-c8f721ae-8f17-453d-b07a-1ed645ce38ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652110974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.652110974
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.2842303925
Short name T1082
Test name
Test status
Simulation time 1111070986 ps
CPU time 16.48 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 205084 kb
Host smart-d2309f39-4dde-40be-a9e1-231e018fc1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842303925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2842303925
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.843819904
Short name T1048
Test name
Test status
Simulation time 23819798 ps
CPU time 0.63 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:36:27 PM PDT 24
Peak memory 204748 kb
Host smart-ccd69069-e0ef-4f99-98ad-988de23a1df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843819904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.843819904
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.763686327
Short name T176
Test name
Test status
Simulation time 277638742 ps
CPU time 1.6 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 213336 kb
Host smart-74e0a069-ca41-438b-bfcb-830dc8b61eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763686327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.763686327
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3893592167
Short name T832
Test name
Test status
Simulation time 374373498 ps
CPU time 6.67 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 255260 kb
Host smart-b098755a-348c-4d55-a37a-3019e896f78d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893592167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3893592167
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1304775073
Short name T527
Test name
Test status
Simulation time 1692975388 ps
CPU time 125.24 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 618972 kb
Host smart-fe75ed6e-57aa-4360-be8a-560c8505c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304775073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1304775073
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2749447775
Short name T163
Test name
Test status
Simulation time 5270176829 ps
CPU time 226.93 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:40:07 PM PDT 24
Peak memory 848180 kb
Host smart-cc233729-1ea0-456f-bee1-793dc5c3fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749447775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2749447775
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3811905638
Short name T837
Test name
Test status
Simulation time 483230605 ps
CPU time 1.09 seconds
Started Jun 05 04:36:19 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 204756 kb
Host smart-0751f72b-24fc-4a1b-8767-883fc28da406
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811905638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3811905638
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.41436352
Short name T317
Test name
Test status
Simulation time 721746350 ps
CPU time 3.95 seconds
Started Jun 05 04:36:17 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 205060 kb
Host smart-45b60505-ddb4-401f-ba4d-1ce0b1c9f4c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41436352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.41436352
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3704290550
Short name T111
Test name
Test status
Simulation time 9132519852 ps
CPU time 105.63 seconds
Started Jun 05 04:36:16 PM PDT 24
Finished Jun 05 04:38:03 PM PDT 24
Peak memory 1115532 kb
Host smart-7a74ddd5-1db7-470b-b131-f24256e806d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704290550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3704290550
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.1379863079
Short name T718
Test name
Test status
Simulation time 2626401838 ps
CPU time 8.42 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:36 PM PDT 24
Peak memory 205168 kb
Host smart-65f03f66-3b52-4948-b34b-aa6604fc3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379863079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.1379863079
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3801445492
Short name T1327
Test name
Test status
Simulation time 8271391914 ps
CPU time 40.52 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:37:07 PM PDT 24
Peak memory 404300 kb
Host smart-ab7b2d56-b1bd-4018-9b08-92761c59ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801445492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3801445492
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1645305606
Short name T1281
Test name
Test status
Simulation time 17904692 ps
CPU time 0.66 seconds
Started Jun 05 04:36:16 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 204688 kb
Host smart-ae6e94e8-1b2e-4843-beeb-f9c40b948052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645305606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1645305606
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1193985005
Short name T236
Test name
Test status
Simulation time 6293135956 ps
CPU time 61.89 seconds
Started Jun 05 04:36:21 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 205116 kb
Host smart-dfc2426c-984f-460d-b3c2-093f872485d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193985005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1193985005
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2015800635
Short name T1302
Test name
Test status
Simulation time 3881766725 ps
CPU time 105.76 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:38:05 PM PDT 24
Peak memory 358564 kb
Host smart-2b687f94-a92d-4b99-978d-32023e492249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015800635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2015800635
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3327774868
Short name T1455
Test name
Test status
Simulation time 1480692787 ps
CPU time 14.66 seconds
Started Jun 05 04:36:18 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 213256 kb
Host smart-89135923-0bad-481b-86e4-b1e842f46975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327774868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3327774868
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.950922528
Short name T843
Test name
Test status
Simulation time 603159816 ps
CPU time 3.06 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 205148 kb
Host smart-155a0f64-7dec-4597-bca5-a209ab67926e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950922528 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.950922528
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1267083589
Short name T88
Test name
Test status
Simulation time 10135496653 ps
CPU time 44.33 seconds
Started Jun 05 04:36:23 PM PDT 24
Finished Jun 05 04:37:08 PM PDT 24
Peak memory 356788 kb
Host smart-11aee06a-bca3-4ce9-a0e1-fbfed207dfdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267083589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1267083589
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1747294536
Short name T1159
Test name
Test status
Simulation time 10348421874 ps
CPU time 35.91 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:37:02 PM PDT 24
Peak memory 463676 kb
Host smart-169a1ea4-48f7-49b0-bc05-5dda0ac2c433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747294536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1747294536
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1722360588
Short name T925
Test name
Test status
Simulation time 2415835083 ps
CPU time 2.84 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:36:29 PM PDT 24
Peak memory 205172 kb
Host smart-a07057de-259e-4bf6-a45b-a2ea15482aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722360588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1722360588
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.634956305
Short name T293
Test name
Test status
Simulation time 1649416516 ps
CPU time 1.51 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 205072 kb
Host smart-8396e9c8-d08b-4d3e-8e8c-79f8f97337d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634956305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.634956305
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.605552022
Short name T15
Test name
Test status
Simulation time 433250662 ps
CPU time 2.74 seconds
Started Jun 05 04:36:23 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 205128 kb
Host smart-c4ac07a7-c25e-4c94-bde1-af55448feb51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605552022 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.605552022
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2556262538
Short name T1107
Test name
Test status
Simulation time 1089834115 ps
CPU time 6.55 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 213348 kb
Host smart-0e81bdcf-2d5b-4dcf-aeba-f34f71df731b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556262538 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2556262538
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3054837037
Short name T1085
Test name
Test status
Simulation time 3713865935 ps
CPU time 7.68 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 205068 kb
Host smart-c824f54b-32f8-4874-b561-399922971ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054837037 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3054837037
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.4264911734
Short name T1063
Test name
Test status
Simulation time 1520204578 ps
CPU time 15.01 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 205032 kb
Host smart-38fb5cf3-34c3-4f03-b0be-46c657780c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264911734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.4264911734
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.282059276
Short name T495
Test name
Test status
Simulation time 1882842356 ps
CPU time 81.9 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:37:46 PM PDT 24
Peak memory 206384 kb
Host smart-051da277-63e5-4d16-bbf4-c7bd5b977a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282059276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.282059276
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3766276182
Short name T397
Test name
Test status
Simulation time 50904743650 ps
CPU time 56.64 seconds
Started Jun 05 04:36:20 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 878208 kb
Host smart-d52996dd-07df-4109-ac68-c3346a936a25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766276182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3766276182
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.440147693
Short name T790
Test name
Test status
Simulation time 41639044341 ps
CPU time 312.45 seconds
Started Jun 05 04:36:27 PM PDT 24
Finished Jun 05 04:41:40 PM PDT 24
Peak memory 2355988 kb
Host smart-d46220a2-d4bd-4061-b14c-81bd550dd6fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440147693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.440147693
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3380676950
Short name T617
Test name
Test status
Simulation time 2723504517 ps
CPU time 6.54 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:36:31 PM PDT 24
Peak memory 213412 kb
Host smart-6a29ed4a-8031-4b9e-9a66-72f5db606b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380676950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3380676950
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.4152262555
Short name T974
Test name
Test status
Simulation time 1044081139 ps
CPU time 18.75 seconds
Started Jun 05 04:36:23 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 205108 kb
Host smart-6fb51111-863b-4d86-bd7c-c0943d73d5dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152262555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.4152262555
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.81624388
Short name T774
Test name
Test status
Simulation time 16864297 ps
CPU time 0.69 seconds
Started Jun 05 04:36:37 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 204904 kb
Host smart-68ed22c7-18e9-415e-a149-353031747d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81624388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.81624388
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2848632878
Short name T615
Test name
Test status
Simulation time 329421836 ps
CPU time 13.56 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:36:43 PM PDT 24
Peak memory 263256 kb
Host smart-a72f67a5-60e1-4c29-977c-6d5430b49eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848632878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2848632878
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3159678878
Short name T387
Test name
Test status
Simulation time 248241259 ps
CPU time 13.28 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:36:40 PM PDT 24
Peak memory 248696 kb
Host smart-cb0b6e67-a6e0-4f8f-a8a4-1a8fc5de2354
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159678878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3159678878
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2947197955
Short name T657
Test name
Test status
Simulation time 8565936804 ps
CPU time 170.22 seconds
Started Jun 05 04:36:28 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 710220 kb
Host smart-adc5eac7-4c5c-40b6-89a8-69635f43fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947197955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2947197955
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.884820758
Short name T1115
Test name
Test status
Simulation time 75609772 ps
CPU time 0.89 seconds
Started Jun 05 04:36:28 PM PDT 24
Finished Jun 05 04:36:30 PM PDT 24
Peak memory 204936 kb
Host smart-dfee6680-99c7-44fd-8d29-254df8592aa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884820758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.884820758
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3502868860
Short name T692
Test name
Test status
Simulation time 342553669 ps
CPU time 5.19 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 245556 kb
Host smart-73bccd56-1e16-46c3-b40b-7f5f3e3fa059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502868860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3502868860
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1780768740
Short name T693
Test name
Test status
Simulation time 5145338329 ps
CPU time 147.86 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:38:53 PM PDT 24
Peak memory 1469720 kb
Host smart-00719973-d2b2-40f6-b9f4-206d1a4259ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780768740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1780768740
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.21357587
Short name T450
Test name
Test status
Simulation time 3879288102 ps
CPU time 6.35 seconds
Started Jun 05 04:36:32 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 205096 kb
Host smart-fbc08bb7-a6b2-4085-90ee-8150758772ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21357587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.21357587
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.978495360
Short name T429
Test name
Test status
Simulation time 4045029158 ps
CPU time 35.9 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:37:06 PM PDT 24
Peak memory 440680 kb
Host smart-966d179b-99db-4b61-8f47-a6bd3eaae8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978495360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.978495360
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.902664193
Short name T142
Test name
Test status
Simulation time 61416499 ps
CPU time 0.67 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 204776 kb
Host smart-849179c7-d303-410f-b24f-4a29f0fb1934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902664193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.902664193
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3250708487
Short name T1116
Test name
Test status
Simulation time 5301711149 ps
CPU time 80.7 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:37:46 PM PDT 24
Peak memory 526248 kb
Host smart-51277ca2-9baa-4766-a2ac-2a4f47aab4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250708487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3250708487
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1304498239
Short name T1328
Test name
Test status
Simulation time 19123795193 ps
CPU time 113.16 seconds
Started Jun 05 04:36:28 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 404868 kb
Host smart-6485382d-4199-48d8-9f49-9241d4296acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304498239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1304498239
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.4016642021
Short name T327
Test name
Test status
Simulation time 8140211425 ps
CPU time 15.75 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:43 PM PDT 24
Peak memory 229784 kb
Host smart-cfae2c97-4b74-42e7-9aaa-10ed34db0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016642021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.4016642021
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.913912994
Short name T1367
Test name
Test status
Simulation time 4198910582 ps
CPU time 5.5 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 205832 kb
Host smart-16f44096-beb1-4acb-af89-4e12f18ec0f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913912994 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.913912994
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2040714529
Short name T87
Test name
Test status
Simulation time 10127021950 ps
CPU time 25.27 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:36:51 PM PDT 24
Peak memory 301524 kb
Host smart-8603069e-e815-4b63-95c1-a10ee7b1b937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040714529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2040714529
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3344266802
Short name T1224
Test name
Test status
Simulation time 10190301531 ps
CPU time 76.3 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:37:42 PM PDT 24
Peak memory 584588 kb
Host smart-2714f3f2-f45d-4a5b-a8e8-b485e5e04eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344266802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3344266802
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.4033196675
Short name T954
Test name
Test status
Simulation time 1108434756 ps
CPU time 5.92 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 205060 kb
Host smart-3660927f-8f86-42fb-bbc4-02130713d662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033196675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.4033196675
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.2079694143
Short name T1357
Test name
Test status
Simulation time 1074871850 ps
CPU time 5.41 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 205072 kb
Host smart-7703044c-755c-46d0-afdf-4addd2240136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079694143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.2079694143
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.743015445
Short name T1189
Test name
Test status
Simulation time 628919907 ps
CPU time 2.25 seconds
Started Jun 05 04:36:29 PM PDT 24
Finished Jun 05 04:36:32 PM PDT 24
Peak memory 205012 kb
Host smart-b76c65f3-2706-460e-a8fb-9404eacdfeb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743015445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.743015445
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2147488788
Short name T856
Test name
Test status
Simulation time 6775314324 ps
CPU time 5.61 seconds
Started Jun 05 04:36:28 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 210956 kb
Host smart-91aa4a9e-7d8c-4702-80a0-47d33b1a5cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147488788 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2147488788
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.173762949
Short name T1282
Test name
Test status
Simulation time 25073021588 ps
CPU time 614.63 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:46:41 PM PDT 24
Peak memory 4688016 kb
Host smart-04be6cc7-6b5e-4157-930c-6cde14654145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173762949 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.173762949
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2027645512
Short name T1166
Test name
Test status
Simulation time 4337437253 ps
CPU time 29.25 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:36:55 PM PDT 24
Peak memory 205268 kb
Host smart-e9613699-326d-42c3-b6a0-d4d20c5bf21d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027645512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2027645512
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3866583189
Short name T407
Test name
Test status
Simulation time 5934425132 ps
CPU time 28.55 seconds
Started Jun 05 04:36:26 PM PDT 24
Finished Jun 05 04:36:56 PM PDT 24
Peak memory 229508 kb
Host smart-a0a18a8e-3492-4da4-bd32-e7372d0cd387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866583189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3866583189
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1149689411
Short name T608
Test name
Test status
Simulation time 21322347158 ps
CPU time 22.97 seconds
Started Jun 05 04:36:24 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 227352 kb
Host smart-c4dcf46c-2938-4f10-b7a4-e465c9233413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149689411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1149689411
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1489358112
Short name T1417
Test name
Test status
Simulation time 33323590716 ps
CPU time 99.11 seconds
Started Jun 05 04:36:25 PM PDT 24
Finished Jun 05 04:38:05 PM PDT 24
Peak memory 1079424 kb
Host smart-de1b71bb-bc65-49a2-b360-009238084e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489358112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1489358112
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1242036222
Short name T835
Test name
Test status
Simulation time 1211099211 ps
CPU time 6.93 seconds
Started Jun 05 04:36:27 PM PDT 24
Finished Jun 05 04:36:34 PM PDT 24
Peak memory 213320 kb
Host smart-c813cef5-f6f9-4104-9630-0a5944ba302d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242036222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1242036222
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2633818290
Short name T1135
Test name
Test status
Simulation time 1062851638 ps
CPU time 20.7 seconds
Started Jun 05 04:36:41 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 205104 kb
Host smart-ae59dcd6-ba7c-4007-9c1a-4a278e7a02b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633818290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2633818290
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.605114697
Short name T314
Test name
Test status
Simulation time 27951364 ps
CPU time 0.64 seconds
Started Jun 05 04:36:31 PM PDT 24
Finished Jun 05 04:36:32 PM PDT 24
Peak memory 204604 kb
Host smart-f325ac58-2f85-4747-8c98-82b4fac1a2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605114697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.605114697
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.869351155
Short name T1022
Test name
Test status
Simulation time 291652918 ps
CPU time 1.19 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:37 PM PDT 24
Peak memory 205092 kb
Host smart-194806f8-4a8e-4b2d-9227-b46318059d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869351155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.869351155
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.776903599
Short name T893
Test name
Test status
Simulation time 813081159 ps
CPU time 13.18 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:49 PM PDT 24
Peak memory 252432 kb
Host smart-d16c1583-ce61-46dd-9934-f5f78e182375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776903599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.776903599
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.4162745750
Short name T1321
Test name
Test status
Simulation time 4457718755 ps
CPU time 65.27 seconds
Started Jun 05 04:36:33 PM PDT 24
Finished Jun 05 04:37:40 PM PDT 24
Peak memory 638988 kb
Host smart-c0a3ddef-22e0-4174-bfd7-ff1a65ad216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162745750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.4162745750
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3086917723
Short name T1101
Test name
Test status
Simulation time 131355274 ps
CPU time 1.29 seconds
Started Jun 05 04:36:38 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 204940 kb
Host smart-9efe345b-a0f7-414b-9da1-d25b1f5ab0e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086917723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3086917723
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3846764838
Short name T2
Test name
Test status
Simulation time 513346461 ps
CPU time 7.17 seconds
Started Jun 05 04:36:37 PM PDT 24
Finished Jun 05 04:36:45 PM PDT 24
Peak memory 205048 kb
Host smart-7cce8a3a-6020-49b5-ac92-61c0e276e97d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846764838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3846764838
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1771339493
Short name T112
Test name
Test status
Simulation time 18702087747 ps
CPU time 124.77 seconds
Started Jun 05 04:36:32 PM PDT 24
Finished Jun 05 04:38:38 PM PDT 24
Peak memory 1367076 kb
Host smart-0eefb8f5-9d8a-4a17-8ada-d4b9609284dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771339493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1771339493
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2969907282
Short name T1055
Test name
Test status
Simulation time 2731871009 ps
CPU time 5.11 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 205132 kb
Host smart-b3c0b1de-ded1-4e5e-8d8e-1e6b96c46fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969907282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2969907282
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2986534896
Short name T247
Test name
Test status
Simulation time 3176932738 ps
CPU time 80.97 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:37:57 PM PDT 24
Peak memory 360916 kb
Host smart-8c664c56-1eaa-40c2-addb-eeeb58d8745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986534896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2986534896
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3737100715
Short name T394
Test name
Test status
Simulation time 25592085 ps
CPU time 0.66 seconds
Started Jun 05 04:36:32 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 204784 kb
Host smart-1b6a8b8d-5286-4c72-a934-a9ca6472f479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737100715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3737100715
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2714354950
Short name T390
Test name
Test status
Simulation time 7171559332 ps
CPU time 46.91 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 205144 kb
Host smart-2dc42ba3-ee32-4ad5-a584-74c6dd775f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714354950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2714354950
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.291908444
Short name T1437
Test name
Test status
Simulation time 1347313402 ps
CPU time 25.41 seconds
Started Jun 05 04:36:33 PM PDT 24
Finished Jun 05 04:36:59 PM PDT 24
Peak memory 364492 kb
Host smart-2c3243d4-f924-4af0-825e-6d90bb368164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291908444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.291908444
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1363338551
Short name T156
Test name
Test status
Simulation time 48340879133 ps
CPU time 1939.91 seconds
Started Jun 05 04:36:33 PM PDT 24
Finished Jun 05 05:08:54 PM PDT 24
Peak memory 2485316 kb
Host smart-40ba4b69-6042-457a-98da-0f385acf14e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363338551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1363338551
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2656738484
Short name T1249
Test name
Test status
Simulation time 2034424811 ps
CPU time 15.97 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:36:51 PM PDT 24
Peak memory 221016 kb
Host smart-d4a5300c-df1d-450b-bd41-73960bedf8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656738484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2656738484
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3884595510
Short name T436
Test name
Test status
Simulation time 619987795 ps
CPU time 3.38 seconds
Started Jun 05 04:36:36 PM PDT 24
Finished Jun 05 04:36:40 PM PDT 24
Peak memory 205040 kb
Host smart-edf6fe22-b1fc-44d5-bcaf-dc431e113db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884595510 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3884595510
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1409833361
Short name T1154
Test name
Test status
Simulation time 10212999103 ps
CPU time 40.87 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 310676 kb
Host smart-ddb581b5-e79d-44ee-9324-3011f4dd8ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409833361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1409833361
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2921772798
Short name T1499
Test name
Test status
Simulation time 10274751969 ps
CPU time 34.95 seconds
Started Jun 05 04:36:38 PM PDT 24
Finished Jun 05 04:37:14 PM PDT 24
Peak memory 371480 kb
Host smart-24b3b5e0-5fa9-4af5-a987-f7609298a3f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921772798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2921772798
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.4197174388
Short name T607
Test name
Test status
Simulation time 1273804037 ps
CPU time 6.23 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 205112 kb
Host smart-c1c3087f-d7f0-49e0-bd85-f1e916f5ec4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197174388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.4197174388
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.547898246
Short name T1176
Test name
Test status
Simulation time 1309749106 ps
CPU time 2.21 seconds
Started Jun 05 04:36:32 PM PDT 24
Finished Jun 05 04:36:35 PM PDT 24
Peak memory 205044 kb
Host smart-b1fbccf8-b902-43bb-b1db-ec5abfcad3c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547898246 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.547898246
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2620882537
Short name T1238
Test name
Test status
Simulation time 1791793254 ps
CPU time 2.62 seconds
Started Jun 05 04:36:36 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 205124 kb
Host smart-85279e34-e145-48a5-bdf2-2918efe8ef96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620882537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2620882537
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2180501625
Short name T1438
Test name
Test status
Simulation time 1957578986 ps
CPU time 5.6 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 213276 kb
Host smart-06633162-9422-43e4-8970-310cf4378147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180501625 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2180501625
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1441278867
Short name T868
Test name
Test status
Simulation time 29955550460 ps
CPU time 23.82 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 586632 kb
Host smart-2e942ae3-2696-4667-b7a4-b57926853eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441278867 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1441278867
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2730256426
Short name T1342
Test name
Test status
Simulation time 628718315 ps
CPU time 9.92 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:36:46 PM PDT 24
Peak memory 205028 kb
Host smart-03cb5881-ade0-440f-856a-e4805f91878b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730256426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2730256426
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.274892273
Short name T1419
Test name
Test status
Simulation time 621484102 ps
CPU time 10.43 seconds
Started Jun 05 04:36:38 PM PDT 24
Finished Jun 05 04:36:49 PM PDT 24
Peak memory 209444 kb
Host smart-5ff57248-6094-4b7c-9887-822d59763d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274892273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.274892273
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3382424381
Short name T289
Test name
Test status
Simulation time 14241868467 ps
CPU time 15.81 seconds
Started Jun 05 04:36:31 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 205164 kb
Host smart-f2c09393-c2c5-4729-a1a9-2f2582f0c0c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382424381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3382424381
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1627661674
Short name T1084
Test name
Test status
Simulation time 33511099540 ps
CPU time 671.91 seconds
Started Jun 05 04:36:39 PM PDT 24
Finished Jun 05 04:47:52 PM PDT 24
Peak memory 1792732 kb
Host smart-ecf9e8f9-4c2a-4474-b542-aef8ad9753e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627661674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1627661674
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2292733151
Short name T1271
Test name
Test status
Simulation time 1548391050 ps
CPU time 7.34 seconds
Started Jun 05 04:36:33 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 205140 kb
Host smart-bd43668a-d734-4710-b230-ee1cc878a165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292733151 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2292733151
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.3003100673
Short name T1296
Test name
Test status
Simulation time 1101155341 ps
CPU time 20.36 seconds
Started Jun 05 04:36:34 PM PDT 24
Finished Jun 05 04:36:55 PM PDT 24
Peak memory 205088 kb
Host smart-f4976a84-02f2-49ac-91d6-44aa4edfbf5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003100673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3003100673
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1380074105
Short name T1270
Test name
Test status
Simulation time 24121661 ps
CPU time 0.64 seconds
Started Jun 05 04:36:43 PM PDT 24
Finished Jun 05 04:36:45 PM PDT 24
Peak memory 204752 kb
Host smart-b5a2fd93-cdc7-4e4b-9f47-5e901dd02487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380074105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1380074105
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3470354929
Short name T1345
Test name
Test status
Simulation time 331391708 ps
CPU time 8.12 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:36:55 PM PDT 24
Peak memory 246528 kb
Host smart-6e9d3b9d-e430-4483-bbe5-50169df3a4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470354929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3470354929
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.68053322
Short name T1198
Test name
Test status
Simulation time 223474227 ps
CPU time 4.01 seconds
Started Jun 05 04:36:48 PM PDT 24
Finished Jun 05 04:36:53 PM PDT 24
Peak memory 240852 kb
Host smart-3aa29a13-4a0a-4ba3-947d-0f7f6d51fca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68053322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty
.68053322
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.692850855
Short name T646
Test name
Test status
Simulation time 8005117841 ps
CPU time 75.44 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 702672 kb
Host smart-2c980e25-c45a-44f7-af2a-dca4d6a4eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692850855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.692850855
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3656177239
Short name T119
Test name
Test status
Simulation time 4804852561 ps
CPU time 77.63 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:38:05 PM PDT 24
Peak memory 774312 kb
Host smart-393ceae6-e47e-4f29-856b-02bad207f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656177239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3656177239
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2104008444
Short name T859
Test name
Test status
Simulation time 99803978 ps
CPU time 1.03 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 204784 kb
Host smart-f4466c3a-31b7-4c55-bb82-7b98541ca881
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104008444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2104008444
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.195936593
Short name T290
Test name
Test status
Simulation time 122507923 ps
CPU time 3.19 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 205036 kb
Host smart-8ada4b86-3ca8-4719-8e15-69de95fbece6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195936593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
195936593
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2081750474
Short name T1323
Test name
Test status
Simulation time 105129515017 ps
CPU time 182.85 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:39:52 PM PDT 24
Peak memory 1479288 kb
Host smart-df13e87a-081f-43d3-ad12-15207fcf8e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081750474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2081750474
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1567589065
Short name T1306
Test name
Test status
Simulation time 525370601 ps
CPU time 6.24 seconds
Started Jun 05 04:36:48 PM PDT 24
Finished Jun 05 04:36:56 PM PDT 24
Peak memory 205040 kb
Host smart-e977fc3a-59ea-4b24-a609-1d108a8470a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567589065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1567589065
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2719797990
Short name T5
Test name
Test status
Simulation time 1901272871 ps
CPU time 101.84 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:38:29 PM PDT 24
Peak memory 431856 kb
Host smart-c907512c-821b-4089-8574-1fac13117735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719797990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2719797990
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.436016280
Short name T618
Test name
Test status
Simulation time 79667648 ps
CPU time 0.7 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:36:49 PM PDT 24
Peak memory 204716 kb
Host smart-ead900dc-6d61-4618-8fe8-0f8cef5e1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436016280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.436016280
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.952514052
Short name T237
Test name
Test status
Simulation time 3985297932 ps
CPU time 12.06 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 205212 kb
Host smart-b96fa825-4645-4a4e-909b-fcaaf445b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952514052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.952514052
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.708504341
Short name T1273
Test name
Test status
Simulation time 7245341718 ps
CPU time 28.32 seconds
Started Jun 05 04:36:35 PM PDT 24
Finished Jun 05 04:37:04 PM PDT 24
Peak memory 296648 kb
Host smart-7170161a-b71e-4f27-b001-7bcc7362e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708504341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.708504341
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2480367481
Short name T4
Test name
Test status
Simulation time 631879034 ps
CPU time 11.85 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:57 PM PDT 24
Peak memory 221528 kb
Host smart-45021803-ca4a-44b1-b307-bf1a26cfba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480367481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2480367481
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.4003297279
Short name T1156
Test name
Test status
Simulation time 458084395 ps
CPU time 2.86 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 205100 kb
Host smart-5af418b8-a86c-4137-889c-176a98bda5be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003297279 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.4003297279
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.526088436
Short name T965
Test name
Test status
Simulation time 10227832888 ps
CPU time 42.74 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 334936 kb
Host smart-b2c2b640-b2e1-4db8-ae09-c827b7a1fc55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526088436 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.526088436
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3252594082
Short name T874
Test name
Test status
Simulation time 10382942251 ps
CPU time 15.59 seconds
Started Jun 05 04:36:43 PM PDT 24
Finished Jun 05 04:37:00 PM PDT 24
Peak memory 282888 kb
Host smart-c5010198-1b8d-4311-8ec1-12658fc98fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252594082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3252594082
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3183052000
Short name T1237
Test name
Test status
Simulation time 1142986965 ps
CPU time 5.72 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 205140 kb
Host smart-882e90ce-74f3-4af9-a019-0f000556a867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183052000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3183052000
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.4249800155
Short name T1097
Test name
Test status
Simulation time 1097619807 ps
CPU time 5.73 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 205128 kb
Host smart-4218deaf-ad8c-4bf8-8091-8e79a9ee2c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249800155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.4249800155
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1280912690
Short name T707
Test name
Test status
Simulation time 333326725 ps
CPU time 2.35 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:47 PM PDT 24
Peak memory 205040 kb
Host smart-b080be61-3c82-4709-a190-7e4147b5d355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280912690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1280912690
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1521875295
Short name T1460
Test name
Test status
Simulation time 5722311693 ps
CPU time 6.1 seconds
Started Jun 05 04:36:43 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 213348 kb
Host smart-ceb202ea-33b6-4ee0-886e-d2a76f99b2b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521875295 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1521875295
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2489123267
Short name T895
Test name
Test status
Simulation time 9156939638 ps
CPU time 13.76 seconds
Started Jun 05 04:36:50 PM PDT 24
Finished Jun 05 04:37:05 PM PDT 24
Peak memory 326936 kb
Host smart-d6e59c65-ead6-49be-97e5-23b99ed519b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489123267 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2489123267
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1090963912
Short name T1425
Test name
Test status
Simulation time 1689648893 ps
CPU time 31.81 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 205096 kb
Host smart-510afc95-1944-4714-a5a8-1a37d7955fd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090963912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1090963912
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1323662022
Short name T316
Test name
Test status
Simulation time 673557654 ps
CPU time 28.5 seconds
Started Jun 05 04:36:43 PM PDT 24
Finished Jun 05 04:37:13 PM PDT 24
Peak memory 205052 kb
Host smart-d19b7801-24f0-4675-abe1-c997b6f3e333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323662022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1323662022
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1686569588
Short name T1351
Test name
Test status
Simulation time 48758744130 ps
CPU time 162.91 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:39:28 PM PDT 24
Peak memory 1806900 kb
Host smart-a61b163d-9d36-4f2d-bc59-5494083dd7e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686569588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1686569588
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3454442302
Short name T500
Test name
Test status
Simulation time 29320409715 ps
CPU time 626.14 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:47:13 PM PDT 24
Peak memory 3603540 kb
Host smart-6de8c4bf-fa2e-4893-901d-4b1ed7b84cea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454442302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3454442302
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.747179436
Short name T348
Test name
Test status
Simulation time 1246608960 ps
CPU time 7.74 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:54 PM PDT 24
Peak memory 217764 kb
Host smart-b0726b4a-8423-49d4-8195-42ea1a4f3803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747179436 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.747179436
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2471640992
Short name T1420
Test name
Test status
Simulation time 1043079035 ps
CPU time 20.79 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:37:09 PM PDT 24
Peak memory 205108 kb
Host smart-8e211812-2aed-45b8-9b18-59206730d9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471640992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2471640992
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1373048993
Short name T1492
Test name
Test status
Simulation time 18662336 ps
CPU time 0.66 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:36:57 PM PDT 24
Peak memory 204752 kb
Host smart-d07b9aaf-4529-4d31-97fc-1d5cf08cebfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373048993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1373048993
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1703222278
Short name T67
Test name
Test status
Simulation time 861260358 ps
CPU time 4.35 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:36:53 PM PDT 24
Peak memory 237452 kb
Host smart-f38c36c0-57f4-4682-b250-dd840145aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703222278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1703222278
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2069775782
Short name T1183
Test name
Test status
Simulation time 303654436 ps
CPU time 15.22 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:37:02 PM PDT 24
Peak memory 253640 kb
Host smart-cba989ba-7078-47ce-af1b-8f689e564625
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069775782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2069775782
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3221951628
Short name T211
Test name
Test status
Simulation time 2651287562 ps
CPU time 87.46 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:38:16 PM PDT 24
Peak memory 756356 kb
Host smart-02c53971-1382-4a56-a635-4d5110b1287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221951628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3221951628
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.438204697
Short name T1343
Test name
Test status
Simulation time 6012593300 ps
CPU time 75.03 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 280776 kb
Host smart-944f9899-1b17-4cb5-b211-0de79686da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438204697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.438204697
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.366382028
Short name T633
Test name
Test status
Simulation time 132869865 ps
CPU time 1.07 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 204776 kb
Host smart-999c95e3-1a67-45b3-8445-b61d4fec51dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366382028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.366382028
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1532777715
Short name T673
Test name
Test status
Simulation time 695061911 ps
CPU time 4.23 seconds
Started Jun 05 04:36:48 PM PDT 24
Finished Jun 05 04:36:53 PM PDT 24
Peak memory 235856 kb
Host smart-fe6d9486-ac7d-4569-a098-7aa8abf8b693
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532777715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1532777715
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.533464391
Short name T780
Test name
Test status
Simulation time 4705064245 ps
CPU time 124.6 seconds
Started Jun 05 04:36:45 PM PDT 24
Finished Jun 05 04:38:51 PM PDT 24
Peak memory 1361396 kb
Host smart-a63bcffa-61d9-4285-a984-e063a08db721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533464391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.533464391
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.361962805
Short name T250
Test name
Test status
Simulation time 1638915607 ps
CPU time 5.97 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 205068 kb
Host smart-4f04dbf5-9625-40b5-9a96-3e2a3a3c16f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361962805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.361962805
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1494836738
Short name T554
Test name
Test status
Simulation time 3815929356 ps
CPU time 57.82 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:57 PM PDT 24
Peak memory 326576 kb
Host smart-4abad0b2-8d8c-4691-8cab-88a2a2dd9abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494836738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1494836738
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1306079941
Short name T1274
Test name
Test status
Simulation time 80437308 ps
CPU time 0.7 seconds
Started Jun 05 04:36:48 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 204712 kb
Host smart-8bddbb72-976c-448f-aad7-e2af347a8faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306079941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1306079941
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.997283387
Short name T927
Test name
Test status
Simulation time 7692152546 ps
CPU time 87.35 seconds
Started Jun 05 04:36:46 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 231624 kb
Host smart-37f60609-3e49-4292-980a-541fcc6c129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997283387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.997283387
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.695293933
Short name T1119
Test name
Test status
Simulation time 2209037470 ps
CPU time 54.71 seconds
Started Jun 05 04:36:47 PM PDT 24
Finished Jun 05 04:37:43 PM PDT 24
Peak memory 317576 kb
Host smart-1f632a93-080b-4525-859a-4a8d2b6ad54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695293933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.695293933
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3654444300
Short name T136
Test name
Test status
Simulation time 5178074711 ps
CPU time 13.03 seconds
Started Jun 05 04:36:44 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 214440 kb
Host smart-f42da7d9-26ab-42a7-8bb1-074b53b7334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654444300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3654444300
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3641557912
Short name T310
Test name
Test status
Simulation time 3533205839 ps
CPU time 5.01 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 204992 kb
Host smart-1e1b0691-928b-45a6-a3a0-7ebdfa87f58e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641557912 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3641557912
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.766276552
Short name T1373
Test name
Test status
Simulation time 10327637711 ps
CPU time 24.96 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 274748 kb
Host smart-a686867b-3564-4617-9ddf-c2cafe393c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766276552 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.766276552
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.798517761
Short name T91
Test name
Test status
Simulation time 10175778561 ps
CPU time 68.98 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:38:06 PM PDT 24
Peak memory 489160 kb
Host smart-d43c25c9-bec6-419f-b7d8-ef13fe57b077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798517761 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.798517761
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.527702261
Short name T1314
Test name
Test status
Simulation time 2973501064 ps
CPU time 3.48 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 205212 kb
Host smart-1fa37992-50eb-474e-8b12-675e79590fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527702261 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.527702261
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.421086526
Short name T550
Test name
Test status
Simulation time 2143769082 ps
CPU time 1.22 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:36:59 PM PDT 24
Peak memory 204916 kb
Host smart-cb16e6ba-7bc3-4e64-9864-d65c3b4ad10d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421086526 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.421086526
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2611890056
Short name T697
Test name
Test status
Simulation time 2429036356 ps
CPU time 3 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:02 PM PDT 24
Peak memory 205168 kb
Host smart-0952f8a3-f7b5-4060-aa64-1ce33b275b5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611890056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2611890056
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3612532024
Short name T1122
Test name
Test status
Simulation time 1008418995 ps
CPU time 5.45 seconds
Started Jun 05 04:36:54 PM PDT 24
Finished Jun 05 04:37:00 PM PDT 24
Peak memory 205096 kb
Host smart-59066f3e-72a6-4850-a65d-c424667956f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612532024 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3612532024
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3567908806
Short name T1181
Test name
Test status
Simulation time 21133224160 ps
CPU time 99.55 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:38:37 PM PDT 24
Peak memory 1329000 kb
Host smart-21159bc7-1a10-4bc3-8e19-20d4662f7573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567908806 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3567908806
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1059837301
Short name T1488
Test name
Test status
Simulation time 4376035628 ps
CPU time 14.91 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:37:13 PM PDT 24
Peak memory 205128 kb
Host smart-6dc27da1-b8b9-498e-8b42-028e0edccd54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059837301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1059837301
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2774606400
Short name T337
Test name
Test status
Simulation time 2065633059 ps
CPU time 13.95 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:11 PM PDT 24
Peak memory 205108 kb
Host smart-f4e26006-8505-47f4-bfe1-ed42cd10ecb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774606400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2774606400
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3663339134
Short name T574
Test name
Test status
Simulation time 57751782307 ps
CPU time 216.1 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:40:34 PM PDT 24
Peak memory 2443688 kb
Host smart-fbc02033-4aff-4583-810e-0789cd5473e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663339134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3663339134
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1787249918
Short name T1304
Test name
Test status
Simulation time 5995535903 ps
CPU time 42.98 seconds
Started Jun 05 04:36:54 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 360152 kb
Host smart-245df678-b070-4a5c-8c4e-7236d9d3d790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787249918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1787249918
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3703055258
Short name T950
Test name
Test status
Simulation time 1488237583 ps
CPU time 7.23 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:37:04 PM PDT 24
Peak memory 211864 kb
Host smart-3c37377f-9930-4cf7-8aa8-1550743df42c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703055258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3703055258
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.873316167
Short name T726
Test name
Test status
Simulation time 1370669578 ps
CPU time 19.62 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 205088 kb
Host smart-dac84deb-dddf-4403-abbe-bd7e13905e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873316167 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.873316167
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3955382276
Short name T575
Test name
Test status
Simulation time 15075101 ps
CPU time 0.64 seconds
Started Jun 05 04:37:00 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 204760 kb
Host smart-d946e374-edad-496d-b15d-7d6527aeaff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955382276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3955382276
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1075947589
Short name T1286
Test name
Test status
Simulation time 2581953831 ps
CPU time 10.01 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:09 PM PDT 24
Peak memory 296712 kb
Host smart-6e0481f6-424a-49ce-b772-2b4a769c706e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075947589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1075947589
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3113372256
Short name T619
Test name
Test status
Simulation time 12140289226 ps
CPU time 107.32 seconds
Started Jun 05 04:36:54 PM PDT 24
Finished Jun 05 04:38:42 PM PDT 24
Peak memory 805868 kb
Host smart-0fb9a794-8e22-4006-8c2f-aca5683ff448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113372256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3113372256
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1394690751
Short name T1412
Test name
Test status
Simulation time 1575644869 ps
CPU time 44.79 seconds
Started Jun 05 04:36:53 PM PDT 24
Finished Jun 05 04:37:39 PM PDT 24
Peak memory 570244 kb
Host smart-2399b898-2d59-47e4-bb59-6b2f04c447be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394690751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1394690751
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3695280303
Short name T592
Test name
Test status
Simulation time 453774658 ps
CPU time 6.79 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 205012 kb
Host smart-cc60c2d1-bccd-451f-b3b7-e619ee1cc354
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695280303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3695280303
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.4273762422
Short name T278
Test name
Test status
Simulation time 5630064599 ps
CPU time 158.4 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:39:35 PM PDT 24
Peak memory 1578944 kb
Host smart-8a912322-7efc-4f66-901a-9226b0071cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273762422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.4273762422
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2952922450
Short name T251
Test name
Test status
Simulation time 2498490954 ps
CPU time 8.13 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 205072 kb
Host smart-725605b7-b762-4d46-bba8-3d6c04397670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952922450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2952922450
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1344468814
Short name T1320
Test name
Test status
Simulation time 3425943277 ps
CPU time 62.52 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 314624 kb
Host smart-b9f24a3c-e8b6-4047-b48f-24bb9380ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344468814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1344468814
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3049824971
Short name T819
Test name
Test status
Simulation time 46423848 ps
CPU time 0.64 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:36:58 PM PDT 24
Peak memory 204708 kb
Host smart-5d481f55-0c28-45cb-a7b0-b7efb7c896a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049824971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3049824971
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.978260149
Short name T1453
Test name
Test status
Simulation time 12826839632 ps
CPU time 1267.47 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:58:05 PM PDT 24
Peak memory 2070460 kb
Host smart-e17ffe28-e33d-4261-8d09-a525e51b7602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978260149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.978260149
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1204332157
Short name T742
Test name
Test status
Simulation time 6699026302 ps
CPU time 27.12 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:37:23 PM PDT 24
Peak memory 327496 kb
Host smart-be0f46b2-e48a-4377-a430-71bd9a7471b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204332157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1204332157
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3172841119
Short name T1187
Test name
Test status
Simulation time 915377354 ps
CPU time 9.14 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:37:07 PM PDT 24
Peak memory 213280 kb
Host smart-efaccce6-c842-4f57-a5d8-a3bef43ffa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172841119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3172841119
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2690703903
Short name T288
Test name
Test status
Simulation time 1396053165 ps
CPU time 3.94 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 205180 kb
Host smart-985dd78c-fa59-4b50-b496-928aa8742b48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690703903 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2690703903
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2861119504
Short name T405
Test name
Test status
Simulation time 10111056717 ps
CPU time 36.85 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 381664 kb
Host smart-eea6eea1-72a0-419f-8da3-fd91874a28d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861119504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2861119504
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2721777359
Short name T147
Test name
Test status
Simulation time 2197411961 ps
CPU time 2.92 seconds
Started Jun 05 04:36:59 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 204496 kb
Host smart-d3ce46fe-8514-48c4-af3d-73b1c5b69f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721777359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2721777359
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.1475941082
Short name T578
Test name
Test status
Simulation time 1023364068 ps
CPU time 4.94 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:04 PM PDT 24
Peak memory 205092 kb
Host smart-c115d3cb-7961-401d-97af-db4d77e4a2f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475941082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.1475941082
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1520711479
Short name T763
Test name
Test status
Simulation time 461471449 ps
CPU time 2.79 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:02 PM PDT 24
Peak memory 205060 kb
Host smart-16a33f93-2719-4806-802d-5daf8a2e91be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520711479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1520711479
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2315806760
Short name T922
Test name
Test status
Simulation time 4295775698 ps
CPU time 5.49 seconds
Started Jun 05 04:36:54 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 213340 kb
Host smart-87ef2bc3-04ea-4674-bba4-48581ae77138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315806760 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2315806760
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.4228167452
Short name T584
Test name
Test status
Simulation time 18620210334 ps
CPU time 289.25 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:41:47 PM PDT 24
Peak memory 2895968 kb
Host smart-53714bc8-91ad-4fe9-a012-f11cd47649f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228167452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.4228167452
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3165360857
Short name T1230
Test name
Test status
Simulation time 1634195827 ps
CPU time 24.12 seconds
Started Jun 05 04:36:56 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 205136 kb
Host smart-c15acddf-dc71-4df8-b6eb-05a44cf7ab50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165360857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3165360857
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.767840054
Short name T483
Test name
Test status
Simulation time 8421613326 ps
CPU time 21.72 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 220336 kb
Host smart-4748aae5-2f0d-4e42-acf1-e1c037a4dd3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767840054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.767840054
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2014791177
Short name T1361
Test name
Test status
Simulation time 44236092769 ps
CPU time 812.5 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:50:29 PM PDT 24
Peak memory 6290216 kb
Host smart-9e032d28-27a0-40ed-96b3-3411d127b1b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014791177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2014791177
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3426912458
Short name T891
Test name
Test status
Simulation time 17351416653 ps
CPU time 92.92 seconds
Started Jun 05 04:36:55 PM PDT 24
Finished Jun 05 04:38:29 PM PDT 24
Peak memory 977824 kb
Host smart-3d2ceb1a-1c77-46e9-98c6-2c3ada6dc5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426912458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3426912458
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2651163729
Short name T540
Test name
Test status
Simulation time 16447566519 ps
CPU time 8.19 seconds
Started Jun 05 04:36:59 PM PDT 24
Finished Jun 05 04:37:08 PM PDT 24
Peak memory 220880 kb
Host smart-d743ba55-45f9-405f-a8e1-c0caacda0ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651163729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2651163729
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.3456192163
Short name T901
Test name
Test status
Simulation time 1226536959 ps
CPU time 17.33 seconds
Started Jun 05 04:36:57 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 205164 kb
Host smart-93793617-bdc8-478b-b4ab-21e143df30c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456192163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3456192163
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.385953746
Short name T1157
Test name
Test status
Simulation time 16088624 ps
CPU time 0.62 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:05 PM PDT 24
Peak memory 204764 kb
Host smart-c353b41a-0c1d-4346-a27e-3f4b98d1e433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385953746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.385953746
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1289935681
Short name T1450
Test name
Test status
Simulation time 264070727 ps
CPU time 3.13 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:08 PM PDT 24
Peak memory 237056 kb
Host smart-3d3139b1-23e4-4867-9bdc-357986c8b58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289935681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1289935681
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1442530558
Short name T426
Test name
Test status
Simulation time 510449734 ps
CPU time 4.84 seconds
Started Jun 05 04:37:00 PM PDT 24
Finished Jun 05 04:37:05 PM PDT 24
Peak memory 254344 kb
Host smart-beacca6e-aa67-4b5d-a744-ce7b6d974ed9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442530558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1442530558
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3309559917
Short name T452
Test name
Test status
Simulation time 5909280439 ps
CPU time 39.83 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:42 PM PDT 24
Peak memory 513628 kb
Host smart-8315a538-5417-4943-a248-0aaa369a3a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309559917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3309559917
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.17941132
Short name T1399
Test name
Test status
Simulation time 6808207154 ps
CPU time 121.61 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:39:03 PM PDT 24
Peak memory 610348 kb
Host smart-5aaff3f6-cb7f-4e59-ba9d-01020be16627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17941132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.17941132
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.181783652
Short name T1476
Test name
Test status
Simulation time 494421869 ps
CPU time 1 seconds
Started Jun 05 04:37:00 PM PDT 24
Finished Jun 05 04:37:01 PM PDT 24
Peak memory 204784 kb
Host smart-ddf5b29b-68ea-47cb-bf65-8da53bca539e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181783652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.181783652
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.162595314
Short name T804
Test name
Test status
Simulation time 167360022 ps
CPU time 4.27 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:37:06 PM PDT 24
Peak memory 205084 kb
Host smart-b046245d-8c94-4d59-b7f6-f6f7ed5c3196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162595314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
162595314
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.983426373
Short name T114
Test name
Test status
Simulation time 4463809755 ps
CPU time 118.25 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:39:00 PM PDT 24
Peak memory 1260968 kb
Host smart-890f1d41-cf0a-4d4c-8d13-01705f83efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983426373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.983426373
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3689162930
Short name T1457
Test name
Test status
Simulation time 960995169 ps
CPU time 5.22 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:09 PM PDT 24
Peak memory 204896 kb
Host smart-8c447a32-ccea-4cbc-a0d3-40470b5e8244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689162930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3689162930
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2240521267
Short name T842
Test name
Test status
Simulation time 3369734107 ps
CPU time 40.22 seconds
Started Jun 05 04:37:15 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 421428 kb
Host smart-b9076600-1679-44ce-a792-d20467073c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240521267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2240521267
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.235335129
Short name T1027
Test name
Test status
Simulation time 48661704 ps
CPU time 0.67 seconds
Started Jun 05 04:36:58 PM PDT 24
Finished Jun 05 04:37:00 PM PDT 24
Peak memory 204724 kb
Host smart-f92480bb-63dd-4296-a60e-62285e7f9581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235335129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.235335129
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2164029739
Short name T698
Test name
Test status
Simulation time 28198930082 ps
CPU time 70.03 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 639580 kb
Host smart-c2bde517-edfd-4d02-b882-02045dc2559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164029739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2164029739
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.264560717
Short name T1366
Test name
Test status
Simulation time 16901400986 ps
CPU time 29.53 seconds
Started Jun 05 04:36:59 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 360588 kb
Host smart-d9b2d564-bc4b-4430-be5b-c4610441cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264560717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.264560717
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2591682386
Short name T124
Test name
Test status
Simulation time 28694666903 ps
CPU time 1399.15 seconds
Started Jun 05 04:37:06 PM PDT 24
Finished Jun 05 05:00:26 PM PDT 24
Peak memory 2601796 kb
Host smart-d4764b29-cb22-4244-87d2-b63a512445f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591682386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2591682386
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.354794801
Short name T273
Test name
Test status
Simulation time 3526470981 ps
CPU time 29.64 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:33 PM PDT 24
Peak memory 213460 kb
Host smart-d9beda2c-b695-4757-991d-fa6286af5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354794801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.354794801
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1966141831
Short name T744
Test name
Test status
Simulation time 655887443 ps
CPU time 3.75 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:07 PM PDT 24
Peak memory 205100 kb
Host smart-53757822-f7c7-46f7-8233-786158c02706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966141831 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1966141831
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.659288255
Short name T959
Test name
Test status
Simulation time 10406621142 ps
CPU time 7.99 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:12 PM PDT 24
Peak memory 234488 kb
Host smart-6d14d89c-982e-4f39-ac88-9594e4cb8349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659288255 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.659288255
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.943387808
Short name T715
Test name
Test status
Simulation time 10152870841 ps
CPU time 33.12 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:36 PM PDT 24
Peak memory 405408 kb
Host smart-1f2b8079-3032-44cf-98a4-4c3c52c14b99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943387808 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.943387808
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.1607718090
Short name T1057
Test name
Test status
Simulation time 3800548706 ps
CPU time 2.84 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:05 PM PDT 24
Peak memory 205128 kb
Host smart-d492df08-76c7-41e3-992f-2d2da33abfa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607718090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.1607718090
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3404685942
Short name T682
Test name
Test status
Simulation time 1133882160 ps
CPU time 5.84 seconds
Started Jun 05 04:37:07 PM PDT 24
Finished Jun 05 04:37:13 PM PDT 24
Peak memory 204952 kb
Host smart-df21e227-0dc4-4529-a1c9-798a207402a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404685942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3404685942
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2715373084
Short name T1331
Test name
Test status
Simulation time 395144896 ps
CPU time 2.83 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:05 PM PDT 24
Peak memory 204992 kb
Host smart-c250f026-2f14-4f20-a767-9a497e7aff65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715373084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2715373084
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1065145194
Short name T620
Test name
Test status
Simulation time 898142688 ps
CPU time 5.43 seconds
Started Jun 05 04:37:04 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 205440 kb
Host smart-e209ab8c-6ec3-4935-8647-4cc4c77eb74b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065145194 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1065145194
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1822876482
Short name T1043
Test name
Test status
Simulation time 21734506106 ps
CPU time 63.48 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:38:07 PM PDT 24
Peak memory 882976 kb
Host smart-d3dc4b63-9772-48e0-879c-1c8fd4e1a0cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822876482 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1822876482
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1148131097
Short name T810
Test name
Test status
Simulation time 1254754138 ps
CPU time 18.59 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 205064 kb
Host smart-13ab39f4-bdb3-4982-b474-6743568d7107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148131097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1148131097
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3768652320
Short name T1377
Test name
Test status
Simulation time 6954783993 ps
CPU time 25.23 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 230620 kb
Host smart-53cec981-c42f-4e89-b20f-a2ecf56fc0b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768652320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3768652320
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3961713939
Short name T1329
Test name
Test status
Simulation time 51301508459 ps
CPU time 167.51 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:39:51 PM PDT 24
Peak memory 2071784 kb
Host smart-53ff92bf-6ebe-4150-9a75-848efd1d4b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961713939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3961713939
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1858129563
Short name T1375
Test name
Test status
Simulation time 38048038552 ps
CPU time 2874.13 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 05:24:59 PM PDT 24
Peak memory 8931388 kb
Host smart-8548ff70-7f88-428e-a582-42a53bf0ceca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858129563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1858129563
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2296270865
Short name T1060
Test name
Test status
Simulation time 13498303514 ps
CPU time 6.82 seconds
Started Jun 05 04:37:15 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 205212 kb
Host smart-b455c054-aed6-472d-a6da-d50de4a6c203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296270865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2296270865
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1228256702
Short name T1068
Test name
Test status
Simulation time 1057638283 ps
CPU time 19.73 seconds
Started Jun 05 04:37:08 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 205116 kb
Host smart-5bfff947-4d31-40d9-a1a8-406c4928b254
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228256702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1228256702
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3327839195
Short name T1075
Test name
Test status
Simulation time 15724116 ps
CPU time 0.62 seconds
Started Jun 05 04:37:12 PM PDT 24
Finished Jun 05 04:37:14 PM PDT 24
Peak memory 204672 kb
Host smart-e4ae56af-3fb5-4155-b578-318924573957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327839195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3327839195
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1936006628
Short name T1096
Test name
Test status
Simulation time 859681742 ps
CPU time 4.07 seconds
Started Jun 05 04:37:06 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 233364 kb
Host smart-884e182f-4ae0-41d5-bf91-77266f352231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936006628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1936006628
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3062860106
Short name T660
Test name
Test status
Simulation time 877503664 ps
CPU time 24.42 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 302924 kb
Host smart-119f8de2-4a92-4bf6-8d3c-c39f7522906e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062860106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3062860106
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1040776999
Short name T83
Test name
Test status
Simulation time 11878738872 ps
CPU time 98.74 seconds
Started Jun 05 04:37:08 PM PDT 24
Finished Jun 05 04:38:47 PM PDT 24
Peak memory 886340 kb
Host smart-ffb64543-4a6f-4d93-b8ac-abb95a21d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040776999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1040776999
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.4232660525
Short name T834
Test name
Test status
Simulation time 24272681859 ps
CPU time 76.62 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:38:31 PM PDT 24
Peak memory 706164 kb
Host smart-34e008c6-907c-477b-85aa-b8e1e46eae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232660525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.4232660525
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2740544411
Short name T994
Test name
Test status
Simulation time 122013647 ps
CPU time 1.02 seconds
Started Jun 05 04:37:05 PM PDT 24
Finished Jun 05 04:37:07 PM PDT 24
Peak memory 204748 kb
Host smart-51ffee6c-4c50-4986-9ffb-0ffbd4f0cd4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740544411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2740544411
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1595063936
Short name T470
Test name
Test status
Simulation time 153623347 ps
CPU time 3.52 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:08 PM PDT 24
Peak memory 225288 kb
Host smart-048fda92-1cfd-4ae7-887c-6bc87c05c137
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595063936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1595063936
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.4144931978
Short name T484
Test name
Test status
Simulation time 3678942026 ps
CPU time 275.36 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:41:38 PM PDT 24
Peak memory 1061196 kb
Host smart-c6526726-2da2-4f93-a007-efb7b1eb1ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144931978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.4144931978
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3698126342
Short name T918
Test name
Test status
Simulation time 510109567 ps
CPU time 8.27 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 205084 kb
Host smart-7d12cb94-1e28-49bc-9ce5-07d801e09b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698126342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3698126342
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3295326606
Short name T1498
Test name
Test status
Simulation time 2504355657 ps
CPU time 18.28 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 311668 kb
Host smart-9ad22c57-9772-4702-8177-a5d85062f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295326606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3295326606
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3193665332
Short name T931
Test name
Test status
Simulation time 29285380 ps
CPU time 0.69 seconds
Started Jun 05 04:37:01 PM PDT 24
Finished Jun 05 04:37:03 PM PDT 24
Peak memory 204704 kb
Host smart-0f4a90eb-799b-4138-bc8d-e059730390ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193665332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3193665332
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1161908003
Short name T174
Test name
Test status
Simulation time 2318215755 ps
CPU time 59.95 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:38:04 PM PDT 24
Peak memory 408088 kb
Host smart-ebd7fb88-414c-4a62-868d-73381935f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161908003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1161908003
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1843138068
Short name T1349
Test name
Test status
Simulation time 1116778115 ps
CPU time 22.45 seconds
Started Jun 05 04:37:05 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 295480 kb
Host smart-9f0bba45-ea62-4d48-8a87-dbd1321ceb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843138068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1843138068
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3720798127
Short name T282
Test name
Test status
Simulation time 28929060721 ps
CPU time 761.48 seconds
Started Jun 05 04:37:06 PM PDT 24
Finished Jun 05 04:49:48 PM PDT 24
Peak memory 2982936 kb
Host smart-5e163b39-412d-4b88-a235-bb97e464b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720798127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3720798127
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.4049092784
Short name T271
Test name
Test status
Simulation time 3248218197 ps
CPU time 12.74 seconds
Started Jun 05 04:37:07 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 221380 kb
Host smart-b1f3c63b-0ec0-4505-90da-ae1ec56c5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049092784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4049092784
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2036693934
Short name T33
Test name
Test status
Simulation time 391463794 ps
CPU time 2.53 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:15 PM PDT 24
Peak memory 205288 kb
Host smart-c01a864f-d50c-42dd-ad96-3b8b4cc8a9a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036693934 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2036693934
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.136067188
Short name T1147
Test name
Test status
Simulation time 10096429812 ps
CPU time 43.9 seconds
Started Jun 05 04:37:15 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 373020 kb
Host smart-e48e333f-37fd-49de-be08-34f749b130d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136067188 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.136067188
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.752284091
Short name T1469
Test name
Test status
Simulation time 10133448152 ps
CPU time 37.32 seconds
Started Jun 05 04:37:06 PM PDT 24
Finished Jun 05 04:37:44 PM PDT 24
Peak memory 361716 kb
Host smart-8f650e7c-5be9-41e6-8457-cf3d80073a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752284091 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.752284091
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.2883555073
Short name T1091
Test name
Test status
Simulation time 1526661744 ps
CPU time 2.15 seconds
Started Jun 05 04:37:09 PM PDT 24
Finished Jun 05 04:37:11 PM PDT 24
Peak memory 205064 kb
Host smart-74fc3b93-a4fc-48d9-b23c-d9955f035f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883555073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.2883555073
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.43179925
Short name T475
Test name
Test status
Simulation time 1304407146 ps
CPU time 1.36 seconds
Started Jun 05 04:37:12 PM PDT 24
Finished Jun 05 04:37:14 PM PDT 24
Peak memory 205072 kb
Host smart-a27355a7-715a-44ea-87ad-8a99c81f1322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43179925 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.43179925
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1368110668
Short name T529
Test name
Test status
Simulation time 1152750239 ps
CPU time 2.4 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 205112 kb
Host smart-5f70c6c4-f7fc-4c83-8d99-007b84196eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368110668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1368110668
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2343464739
Short name T1182
Test name
Test status
Simulation time 3220480238 ps
CPU time 4.24 seconds
Started Jun 05 04:37:14 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 205576 kb
Host smart-557290e7-303c-490e-bc1d-7b38f94be6c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343464739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2343464739
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.350803190
Short name T1120
Test name
Test status
Simulation time 12552775848 ps
CPU time 28.07 seconds
Started Jun 05 04:37:02 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 770364 kb
Host smart-b032ca17-f333-4587-b5f0-a636d241ac5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350803190 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.350803190
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2834340032
Short name T1029
Test name
Test status
Simulation time 4830074198 ps
CPU time 19.22 seconds
Started Jun 05 04:37:04 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 205200 kb
Host smart-f682fc1a-b2e3-4ef4-a297-5582b9df5ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834340032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2834340032
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.685632498
Short name T1160
Test name
Test status
Simulation time 6221490769 ps
CPU time 24.29 seconds
Started Jun 05 04:37:15 PM PDT 24
Finished Jun 05 04:37:40 PM PDT 24
Peak memory 227672 kb
Host smart-fe5f860e-be13-42b9-b2fe-e7ae4f954f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685632498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.685632498
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.1268022022
Short name T1071
Test name
Test status
Simulation time 27331807493 ps
CPU time 7.34 seconds
Started Jun 05 04:37:03 PM PDT 24
Finished Jun 05 04:37:12 PM PDT 24
Peak memory 210828 kb
Host smart-58a4b1a7-82b4-41d2-9e87-657fe01a1ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268022022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.1268022022
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.913949490
Short name T1134
Test name
Test status
Simulation time 30123635340 ps
CPU time 398.29 seconds
Started Jun 05 04:37:00 PM PDT 24
Finished Jun 05 04:43:39 PM PDT 24
Peak memory 2544232 kb
Host smart-75e4ae98-1a66-42f4-8ab0-6a5aa736f65b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913949490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.913949490
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3737258454
Short name T970
Test name
Test status
Simulation time 7080112094 ps
CPU time 7.26 seconds
Started Jun 05 04:37:05 PM PDT 24
Finished Jun 05 04:37:13 PM PDT 24
Peak memory 219508 kb
Host smart-85c42a7d-9768-424a-b589-3a9167421bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737258454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3737258454
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1726609017
Short name T173
Test name
Test status
Simulation time 1168666187 ps
CPU time 18.38 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:30 PM PDT 24
Peak memory 205084 kb
Host smart-abdecc15-7c3e-4ca2-9115-6d170b269c17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726609017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1726609017
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1989195608
Short name T836
Test name
Test status
Simulation time 65573237 ps
CPU time 0.66 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:41 PM PDT 24
Peak memory 204652 kb
Host smart-50f8e4b5-dc44-4488-9bf7-af6ded0e04f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989195608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1989195608
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3727010577
Short name T56
Test name
Test status
Simulation time 298691502 ps
CPU time 1.38 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:42 PM PDT 24
Peak memory 205116 kb
Host smart-e4113a3b-d29c-452e-8b2b-8715b8000670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727010577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3727010577
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.906600409
Short name T942
Test name
Test status
Simulation time 339719800 ps
CPU time 6.32 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 256640 kb
Host smart-0d544ddb-59bb-4a2b-af02-719ebe5a2c27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906600409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.906600409
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3239176922
Short name T468
Test name
Test status
Simulation time 9228684316 ps
CPU time 97 seconds
Started Jun 05 04:34:36 PM PDT 24
Finished Jun 05 04:36:15 PM PDT 24
Peak memory 451500 kb
Host smart-786d1bb6-e04f-4a49-a414-1a0c6aa46db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239176922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3239176922
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2322790814
Short name T398
Test name
Test status
Simulation time 1703462240 ps
CPU time 127.63 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:36:48 PM PDT 24
Peak memory 596056 kb
Host smart-2945c3e4-e4b5-4382-85a9-9fb63afa8b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322790814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2322790814
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.804329670
Short name T1359
Test name
Test status
Simulation time 411170276 ps
CPU time 0.88 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 204752 kb
Host smart-4f9bf4ae-87b5-4d61-b0fa-1a205bf1e12e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804329670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.804329670
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1377663820
Short name T392
Test name
Test status
Simulation time 459028085 ps
CPU time 6.25 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 205052 kb
Host smart-99be1317-ca01-4847-9dad-ca1c60337a78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377663820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1377663820
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1353518163
Short name T833
Test name
Test status
Simulation time 9501294474 ps
CPU time 351.74 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:40:43 PM PDT 24
Peak memory 1306464 kb
Host smart-a6e3238b-8caf-4655-9597-ac2a5c1d7f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353518163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1353518163
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.971305564
Short name T1039
Test name
Test status
Simulation time 1529698152 ps
CPU time 16.23 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:35:10 PM PDT 24
Peak memory 205052 kb
Host smart-c6e7d8ca-3128-4fa4-9814-f2ed670eb994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971305564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.971305564
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2322874148
Short name T442
Test name
Test status
Simulation time 4850449762 ps
CPU time 29.47 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:35:32 PM PDT 24
Peak memory 300388 kb
Host smart-bc0dd755-a949-4e2d-9b66-42ee56268522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322874148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2322874148
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3314802876
Short name T143
Test name
Test status
Simulation time 28668964 ps
CPU time 0.68 seconds
Started Jun 05 04:34:42 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 204784 kb
Host smart-5be814ff-1567-461a-8ad2-1df12582af1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314802876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3314802876
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1095749466
Short name T1324
Test name
Test status
Simulation time 12157586618 ps
CPU time 117.31 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:36:33 PM PDT 24
Peak memory 205132 kb
Host smart-16710761-9665-4265-82fe-3e8feb7256db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095749466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1095749466
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3284565829
Short name T573
Test name
Test status
Simulation time 1222003446 ps
CPU time 19.98 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 290244 kb
Host smart-3126b6f3-39d0-4a4b-886e-69817c7bb3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284565829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3284565829
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3776731937
Short name T127
Test name
Test status
Simulation time 16251210426 ps
CPU time 114.54 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 792148 kb
Host smart-e859e8b3-7817-4fa1-9860-15fdd4549b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776731937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3776731937
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3922978770
Short name T943
Test name
Test status
Simulation time 745679894 ps
CPU time 6.23 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:34:54 PM PDT 24
Peak memory 213740 kb
Host smart-145f97d5-dc11-443d-9518-73d63774a9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922978770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3922978770
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3010444091
Short name T190
Test name
Test status
Simulation time 138391479 ps
CPU time 0.86 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 222040 kb
Host smart-2d2d4924-42d2-4e7c-8a2c-68167a613ab2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010444091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3010444091
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3538466808
Short name T547
Test name
Test status
Simulation time 2280129781 ps
CPU time 3.16 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:34:56 PM PDT 24
Peak memory 205140 kb
Host smart-7f8f1068-3858-4f97-8e27-018a756d6447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538466808 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3538466808
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3917149004
Short name T1397
Test name
Test status
Simulation time 10207505846 ps
CPU time 26.36 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 282236 kb
Host smart-e9af1b0a-4ffc-4234-9846-a302437b5410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917149004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3917149004
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3161201538
Short name T441
Test name
Test status
Simulation time 10097425129 ps
CPU time 31.07 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:35:19 PM PDT 24
Peak memory 389384 kb
Host smart-8e03390f-c751-46d0-a8ca-4a55d5303530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161201538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3161201538
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.1469348341
Short name T637
Test name
Test status
Simulation time 1246719424 ps
CPU time 6.73 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:05 PM PDT 24
Peak memory 205148 kb
Host smart-1eee6775-dc3e-4057-b6ac-1d3583db6e65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469348341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.1469348341
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.3556557867
Short name T501
Test name
Test status
Simulation time 1040184295 ps
CPU time 2.91 seconds
Started Jun 05 04:34:56 PM PDT 24
Finished Jun 05 04:35:00 PM PDT 24
Peak memory 205088 kb
Host smart-3432c86b-cbad-41a4-b37d-004431c12d76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556557867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.3556557867
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1755070089
Short name T738
Test name
Test status
Simulation time 262876268 ps
CPU time 1.91 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:34:56 PM PDT 24
Peak memory 205096 kb
Host smart-d73b58ac-ef80-4095-b549-03b0610fda16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755070089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1755070089
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3742153257
Short name T312
Test name
Test status
Simulation time 1987573267 ps
CPU time 5.56 seconds
Started Jun 05 04:34:49 PM PDT 24
Finished Jun 05 04:34:55 PM PDT 24
Peak memory 217768 kb
Host smart-99693b0e-6e29-4426-a9b4-8e349f8ba488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742153257 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3742153257
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2539031032
Short name T557
Test name
Test status
Simulation time 10044549798 ps
CPU time 39.25 seconds
Started Jun 05 04:34:48 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 743980 kb
Host smart-ea7855a0-9f61-44be-832b-0dd04a35a5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539031032 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2539031032
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1283593985
Short name T463
Test name
Test status
Simulation time 1038232357 ps
CPU time 13.83 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 205116 kb
Host smart-4447c65e-652d-46d8-afbd-af1d2f548abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283593985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1283593985
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3133714012
Short name T1256
Test name
Test status
Simulation time 4331371065 ps
CPU time 72.54 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:36:15 PM PDT 24
Peak memory 207824 kb
Host smart-27749cf4-7642-486b-8e82-2b42135b1dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133714012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3133714012
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3280766250
Short name T781
Test name
Test status
Simulation time 31664525112 ps
CPU time 280.49 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:39:20 PM PDT 24
Peak memory 3049464 kb
Host smart-8fa69cfe-c813-489e-8be0-0abde6c0efe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280766250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3280766250
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.596625952
Short name T323
Test name
Test status
Simulation time 32401291919 ps
CPU time 312.21 seconds
Started Jun 05 04:34:52 PM PDT 24
Finished Jun 05 04:40:05 PM PDT 24
Peak memory 1850028 kb
Host smart-6f8dc7b0-6270-4a55-8c71-a1615bb3fb40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596625952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.596625952
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.675140742
Short name T582
Test name
Test status
Simulation time 5056922711 ps
CPU time 7.03 seconds
Started Jun 05 04:35:00 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 213396 kb
Host smart-ebc1cb1c-7a7e-4a3a-b783-33f650c26e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675140742 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.675140742
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.842557666
Short name T395
Test name
Test status
Simulation time 1034113989 ps
CPU time 18.85 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 205264 kb
Host smart-058cec9b-c361-4cc6-890b-638ee8a84e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842557666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.842557666
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.182430988
Short name T1400
Test name
Test status
Simulation time 15293823 ps
CPU time 0.65 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:11 PM PDT 24
Peak memory 204752 kb
Host smart-2bd9a322-a9bd-4c78-a5ee-236e6e457bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182430988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.182430988
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2167905246
Short name T872
Test name
Test status
Simulation time 1047426757 ps
CPU time 10.46 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 218588 kb
Host smart-17d4b130-8264-46ff-99a8-309c97cf4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167905246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2167905246
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1486825568
Short name T1127
Test name
Test status
Simulation time 768329702 ps
CPU time 19.4 seconds
Started Jun 05 04:37:15 PM PDT 24
Finished Jun 05 04:37:35 PM PDT 24
Peak memory 286648 kb
Host smart-9f3ee94b-7f53-4761-9121-7ddb263f5d7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486825568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1486825568
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1949429726
Short name T813
Test name
Test status
Simulation time 4101654148 ps
CPU time 66.61 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 652492 kb
Host smart-405f0ea5-fcc9-437d-a783-aceda4bbda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949429726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1949429726
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1196803305
Short name T1295
Test name
Test status
Simulation time 8169942809 ps
CPU time 158.52 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:39:51 PM PDT 24
Peak memory 675544 kb
Host smart-19589883-9863-4fa0-8f1d-072d5907afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196803305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1196803305
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2653437828
Short name T514
Test name
Test status
Simulation time 54970687 ps
CPU time 0.89 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:15 PM PDT 24
Peak memory 204760 kb
Host smart-bb24d01b-509a-4ad4-9cc2-90ce034aee9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653437828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2653437828
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3761094395
Short name T796
Test name
Test status
Simulation time 219055282 ps
CPU time 4.7 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:15 PM PDT 24
Peak memory 205004 kb
Host smart-0a7dd9cc-d233-4d6b-a40d-4522d09f7e6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761094395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3761094395
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3289297868
Short name T1416
Test name
Test status
Simulation time 4199535535 ps
CPU time 236.63 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:41:10 PM PDT 24
Peak memory 989996 kb
Host smart-0da7c821-73b0-4c98-a91d-84aa45c7aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289297868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3289297868
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1664037280
Short name T1231
Test name
Test status
Simulation time 336591068 ps
CPU time 4.64 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 205052 kb
Host smart-7769a63c-7270-4a5a-918e-87091bd65432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664037280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1664037280
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.2251672941
Short name T69
Test name
Test status
Simulation time 1274012659 ps
CPU time 19.9 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 288764 kb
Host smart-7b4d7035-02e7-4187-bc1c-b016dcc9520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251672941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2251672941
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.2369467486
Short name T1496
Test name
Test status
Simulation time 94206523 ps
CPU time 0.69 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:12 PM PDT 24
Peak memory 204612 kb
Host smart-c540ffae-7c3c-4285-94da-08b24cb55f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369467486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2369467486
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3227858462
Short name T420
Test name
Test status
Simulation time 3201331840 ps
CPU time 12.98 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:25 PM PDT 24
Peak memory 222472 kb
Host smart-710edd3e-2a93-403b-be40-f261894026ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227858462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3227858462
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2763069081
Short name T1195
Test name
Test status
Simulation time 2026367467 ps
CPU time 30.72 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:44 PM PDT 24
Peak memory 345092 kb
Host smart-0d0332b5-cc4d-4e1d-bfbd-817b040bf5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763069081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2763069081
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2619581464
Short name T1285
Test name
Test status
Simulation time 34024663314 ps
CPU time 635.27 seconds
Started Jun 05 04:37:12 PM PDT 24
Finished Jun 05 04:47:48 PM PDT 24
Peak memory 882660 kb
Host smart-a06133a2-2790-469e-90cc-cbd6dfa34d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619581464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2619581464
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2516914718
Short name T1141
Test name
Test status
Simulation time 9261188790 ps
CPU time 17.08 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:31 PM PDT 24
Peak memory 217376 kb
Host smart-7f0720a2-264c-40c9-b0b8-1a27e1165db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516914718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2516914718
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1187487742
Short name T428
Test name
Test status
Simulation time 832236219 ps
CPU time 4.77 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 213488 kb
Host smart-ed188428-8973-429e-a765-36e0f217ff65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187487742 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1187487742
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3095254149
Short name T674
Test name
Test status
Simulation time 10201843902 ps
CPU time 46.49 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:58 PM PDT 24
Peak memory 345628 kb
Host smart-265a9b59-71cb-476c-99fb-a934646fe528
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095254149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3095254149
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.4277553064
Short name T655
Test name
Test status
Simulation time 10357473764 ps
CPU time 15.96 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 299412 kb
Host smart-7a453258-9a5c-4bb8-9e0d-c57c903871d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277553064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.4277553064
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.1874538119
Short name T688
Test name
Test status
Simulation time 1311878979 ps
CPU time 6.83 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 205100 kb
Host smart-3c6f6b44-d238-4fae-9360-00ab7a191e05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874538119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.1874538119
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.172394127
Short name T899
Test name
Test status
Simulation time 1075507429 ps
CPU time 5.47 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:16 PM PDT 24
Peak memory 205304 kb
Host smart-6f4de5e9-61d8-4b38-a95b-39dfa6ab53aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172394127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.172394127
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2564699168
Short name T1376
Test name
Test status
Simulation time 1600810760 ps
CPU time 2.82 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 205056 kb
Host smart-3dc2f5eb-ca7e-4df8-ac18-baf76543e0ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564699168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2564699168
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2218588428
Short name T1415
Test name
Test status
Simulation time 4363292473 ps
CPU time 5.62 seconds
Started Jun 05 04:37:11 PM PDT 24
Finished Jun 05 04:37:17 PM PDT 24
Peak memory 205140 kb
Host smart-4dfbdf8d-2d3e-490b-84b0-f0bcbb1686ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218588428 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2218588428
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3186652759
Short name T580
Test name
Test status
Simulation time 20922647079 ps
CPU time 166.36 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:40:01 PM PDT 24
Peak memory 1841488 kb
Host smart-2b96209c-68e6-4869-8ae9-55a28827e89e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186652759 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3186652759
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1378308480
Short name T135
Test name
Test status
Simulation time 948160770 ps
CPU time 8.98 seconds
Started Jun 05 04:37:14 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 205012 kb
Host smart-14f85555-c603-4ffc-9c93-6d43a26d2ea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378308480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1378308480
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3940796524
Short name T577
Test name
Test status
Simulation time 3091548728 ps
CPU time 34.65 seconds
Started Jun 05 04:37:13 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 205116 kb
Host smart-3765f879-d879-44aa-a2e1-624f0e8d3b5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940796524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3940796524
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.205929299
Short name T535
Test name
Test status
Simulation time 34898338440 ps
CPU time 5.95 seconds
Started Jun 05 04:37:12 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 205196 kb
Host smart-3ccf38e0-54b1-4ea8-ae1d-1745d2bc406a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205929299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.205929299
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.398544387
Short name T567
Test name
Test status
Simulation time 5142502533 ps
CPU time 7.25 seconds
Started Jun 05 04:37:16 PM PDT 24
Finished Jun 05 04:37:23 PM PDT 24
Peak memory 218220 kb
Host smart-7296bacc-3682-436a-821a-2721355961a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398544387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.398544387
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.789049016
Short name T677
Test name
Test status
Simulation time 1078082185 ps
CPU time 14.77 seconds
Started Jun 05 04:37:10 PM PDT 24
Finished Jun 05 04:37:25 PM PDT 24
Peak memory 205040 kb
Host smart-6f36530d-8dc1-41b5-89dd-ec68d2174ed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789049016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.789049016
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3956179717
Short name T1190
Test name
Test status
Simulation time 30176339 ps
CPU time 0.72 seconds
Started Jun 05 04:37:20 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 204656 kb
Host smart-892b8aea-7a23-407a-8fb5-420d91a76a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956179717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3956179717
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1395698781
Short name T869
Test name
Test status
Simulation time 291219997 ps
CPU time 2.11 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 213436 kb
Host smart-3c938f29-dc4d-49eb-8c28-d25741c4cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395698781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1395698781
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2683533332
Short name T1171
Test name
Test status
Simulation time 800816500 ps
CPU time 9.52 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 308864 kb
Host smart-3829b8a9-bf0a-4875-a454-7d7b7b562141
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683533332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2683533332
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2988361475
Short name T90
Test name
Test status
Simulation time 10831779667 ps
CPU time 104.38 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:39:02 PM PDT 24
Peak memory 854736 kb
Host smart-9791a0ea-19b2-4462-b57b-50c1192bba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988361475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2988361475
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1861104917
Short name T351
Test name
Test status
Simulation time 6573181001 ps
CPU time 112.1 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 534632 kb
Host smart-4cef474b-e8c4-438d-8641-306b5f608e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861104917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1861104917
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.556607865
Short name T533
Test name
Test status
Simulation time 281501118 ps
CPU time 1.07 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 204720 kb
Host smart-d87b88a9-b629-475a-91f4-3e9055581659
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556607865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.556607865
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3460653318
Short name T921
Test name
Test status
Simulation time 837236534 ps
CPU time 5.73 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 243172 kb
Host smart-8dd11895-7be3-42b9-a7f9-81dfca3308be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460653318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3460653318
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4093145678
Short name T851
Test name
Test status
Simulation time 12216783692 ps
CPU time 62.66 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 827236 kb
Host smart-1122b7b4-6788-4a75-a9a9-b83e9356a2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093145678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4093145678
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.918292325
Short name T503
Test name
Test status
Simulation time 223784677 ps
CPU time 8.6 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:37:31 PM PDT 24
Peak memory 205076 kb
Host smart-e7044d7b-cb5f-4a68-a5d2-ba7e40368286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918292325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.918292325
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2362943916
Short name T49
Test name
Test status
Simulation time 2456809675 ps
CPU time 44.91 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:38:04 PM PDT 24
Peak memory 481664 kb
Host smart-fe21b137-97fb-4514-ba68-6754abc88aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362943916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2362943916
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3341130186
Short name T469
Test name
Test status
Simulation time 7299025838 ps
CPU time 97.39 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:38:58 PM PDT 24
Peak memory 788480 kb
Host smart-d925e183-40ca-45e7-823f-f97b460e5d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341130186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3341130186
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1491692106
Short name T431
Test name
Test status
Simulation time 4086587423 ps
CPU time 109.34 seconds
Started Jun 05 04:37:17 PM PDT 24
Finished Jun 05 04:39:07 PM PDT 24
Peak memory 434424 kb
Host smart-227c4608-147f-41b3-92c8-60206064d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491692106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1491692106
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2436083337
Short name T801
Test name
Test status
Simulation time 800174792 ps
CPU time 12.46 seconds
Started Jun 05 04:37:17 PM PDT 24
Finished Jun 05 04:37:30 PM PDT 24
Peak memory 229476 kb
Host smart-571a15b5-7e05-46f1-aa7a-565a8d31d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436083337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2436083337
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2598712976
Short name T536
Test name
Test status
Simulation time 968278203 ps
CPU time 4.69 seconds
Started Jun 05 04:37:16 PM PDT 24
Finished Jun 05 04:37:21 PM PDT 24
Peak memory 205116 kb
Host smart-c632f032-00d9-4ba2-b345-4bb8c994a9b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598712976 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2598712976
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3210816582
Short name T1305
Test name
Test status
Simulation time 10181828558 ps
CPU time 3.9 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 221260 kb
Host smart-13079775-41fd-409f-bb41-b77cac883e16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210816582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3210816582
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.4237128697
Short name T785
Test name
Test status
Simulation time 11888509782 ps
CPU time 4.03 seconds
Started Jun 05 04:37:22 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 225824 kb
Host smart-ed0fb59e-d2a4-4b89-9f8e-6dba494a2105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237128697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.4237128697
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.1148223450
Short name T427
Test name
Test status
Simulation time 1156912527 ps
CPU time 5.68 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 205112 kb
Host smart-a9ccebd6-e7a9-4abb-9bbc-9d5994e55f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148223450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1148223450
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.70015395
Short name T1041
Test name
Test status
Simulation time 1115666622 ps
CPU time 5.58 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:37:25 PM PDT 24
Peak memory 205120 kb
Host smart-dab7310a-cf52-43d2-a2ec-9b046e65fb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70015395 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.70015395
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1490899932
Short name T727
Test name
Test status
Simulation time 746931591 ps
CPU time 2.33 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:22 PM PDT 24
Peak memory 205080 kb
Host smart-7a0f1a29-ef3e-4246-92c6-6c4d5c65676b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490899932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1490899932
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.4053439187
Short name T624
Test name
Test status
Simulation time 865344231 ps
CPU time 5.63 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:37:25 PM PDT 24
Peak memory 216864 kb
Host smart-354c6c5c-4d68-4899-8d3f-448bd7f6e8eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053439187 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.4053439187
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2564906539
Short name T353
Test name
Test status
Simulation time 10482339957 ps
CPU time 165.8 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:40:06 PM PDT 24
Peak memory 2512308 kb
Host smart-12314545-4411-472f-977e-3006abc552e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564906539 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2564906539
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.876118653
Short name T333
Test name
Test status
Simulation time 4141088099 ps
CPU time 39.76 seconds
Started Jun 05 04:37:16 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 205180 kb
Host smart-863b6b90-d1c2-45b4-a4ce-f89d3c12d4b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876118653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.876118653
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1928232206
Short name T254
Test name
Test status
Simulation time 2311672201 ps
CPU time 23.78 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:44 PM PDT 24
Peak memory 218288 kb
Host smart-96537c65-8c2e-4d7c-8996-5cac28bbc41b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928232206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1928232206
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1540568842
Short name T1266
Test name
Test status
Simulation time 67794717430 ps
CPU time 334.32 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:42:56 PM PDT 24
Peak memory 2925584 kb
Host smart-b0b6c27d-2732-4efd-85cd-cc9c921e9bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540568842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1540568842
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1201279125
Short name T864
Test name
Test status
Simulation time 23759822129 ps
CPU time 47.15 seconds
Started Jun 05 04:37:23 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 610716 kb
Host smart-c1a0d0bc-484a-4af7-a481-00a3c7e00659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201279125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1201279125
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3230566758
Short name T505
Test name
Test status
Simulation time 5471769993 ps
CPU time 7.28 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 211680 kb
Host smart-9a48db0a-f401-4b06-8c37-424cdfbb4fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230566758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3230566758
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1859626712
Short name T980
Test name
Test status
Simulation time 1062244978 ps
CPU time 19.87 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:37:40 PM PDT 24
Peak memory 205100 kb
Host smart-7059d67b-aeda-4599-b814-17f9cb1da9a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859626712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1859626712
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2855237341
Short name T1251
Test name
Test status
Simulation time 27142433 ps
CPU time 0.61 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 204732 kb
Host smart-d0883145-093b-488a-8fc5-e3bef0b89a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855237341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2855237341
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.525959262
Short name T1241
Test name
Test status
Simulation time 170160344 ps
CPU time 3.1 seconds
Started Jun 05 04:37:20 PM PDT 24
Finished Jun 05 04:37:24 PM PDT 24
Peak memory 229624 kb
Host smart-ed855bec-9b1f-4156-b887-24e7e81a04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525959262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.525959262
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.412254103
Short name T1114
Test name
Test status
Simulation time 2137438175 ps
CPU time 9.36 seconds
Started Jun 05 04:37:20 PM PDT 24
Finished Jun 05 04:37:31 PM PDT 24
Peak memory 312912 kb
Host smart-ba125ebf-0bb7-4b78-8959-4fa8e3ebc761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412254103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.412254103
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1933915013
Short name T68
Test name
Test status
Simulation time 2488831654 ps
CPU time 48.27 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:38:07 PM PDT 24
Peak memory 384340 kb
Host smart-f6e73673-8732-4fd1-9b70-8d5acbf279e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933915013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1933915013
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1287521452
Short name T1002
Test name
Test status
Simulation time 4422385157 ps
CPU time 73.75 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 754504 kb
Host smart-57dbaae6-8bf4-433f-a127-74d2aecb4689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287521452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1287521452
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.4132179077
Short name T1454
Test name
Test status
Simulation time 420165523 ps
CPU time 1.15 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:37:23 PM PDT 24
Peak memory 204952 kb
Host smart-3075e645-235c-49be-8d5c-28308ed2465f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132179077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.4132179077
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3351121453
Short name T1504
Test name
Test status
Simulation time 855349012 ps
CPU time 12.33 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:37:34 PM PDT 24
Peak memory 247168 kb
Host smart-7f179d00-f170-46b3-bf17-8d5e233da5ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351121453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3351121453
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1257206821
Short name T1218
Test name
Test status
Simulation time 5074553584 ps
CPU time 364.79 seconds
Started Jun 05 04:37:21 PM PDT 24
Finished Jun 05 04:43:27 PM PDT 24
Peak memory 1264508 kb
Host smart-b3574234-5fdf-421f-a706-14a47ddf0cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257206821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1257206821
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1026063225
Short name T1024
Test name
Test status
Simulation time 1301114042 ps
CPU time 14.68 seconds
Started Jun 05 04:37:27 PM PDT 24
Finished Jun 05 04:37:43 PM PDT 24
Peak memory 205032 kb
Host smart-48b89c56-8778-4109-b338-c4a9331bc478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026063225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1026063225
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.51886978
Short name T408
Test name
Test status
Simulation time 1406705613 ps
CPU time 30.71 seconds
Started Jun 05 04:37:29 PM PDT 24
Finished Jun 05 04:38:01 PM PDT 24
Peak memory 382952 kb
Host smart-a68cc72d-1c1b-4cc1-b278-f18af8d01fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51886978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.51886978
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.25418044
Short name T1201
Test name
Test status
Simulation time 16148880 ps
CPU time 0.66 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:37:20 PM PDT 24
Peak memory 204780 kb
Host smart-c2cc4b8e-79bd-4a78-a8cd-acb9dc895466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25418044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.25418044
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3519381872
Short name T1390
Test name
Test status
Simulation time 4792813867 ps
CPU time 50.68 seconds
Started Jun 05 04:37:19 PM PDT 24
Finished Jun 05 04:38:11 PM PDT 24
Peak memory 222540 kb
Host smart-67f5312b-b68a-43be-b2f4-b1b4ae628187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519381872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3519381872
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4041584840
Short name T1414
Test name
Test status
Simulation time 2454982971 ps
CPU time 24.12 seconds
Started Jun 05 04:37:24 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 298760 kb
Host smart-c0471385-74be-4411-af9a-d4a091c0dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041584840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4041584840
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.31998101
Short name T696
Test name
Test status
Simulation time 54597038729 ps
CPU time 1022.11 seconds
Started Jun 05 04:37:24 PM PDT 24
Finished Jun 05 04:54:27 PM PDT 24
Peak memory 2988008 kb
Host smart-6683dd23-ed1a-4277-9c69-099200142a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31998101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.31998101
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2429239177
Short name T430
Test name
Test status
Simulation time 861912090 ps
CPU time 20.9 seconds
Started Jun 05 04:37:16 PM PDT 24
Finished Jun 05 04:37:37 PM PDT 24
Peak memory 213340 kb
Host smart-bea0b646-e245-42d4-b91b-f3290e966a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429239177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2429239177
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.102059284
Short name T479
Test name
Test status
Simulation time 2841304747 ps
CPU time 5.84 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:33 PM PDT 24
Peak memory 205228 kb
Host smart-111b7ff4-b03a-408d-ab5d-ea4d2fd0f520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102059284 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.102059284
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1332264739
Short name T1203
Test name
Test status
Simulation time 10308056981 ps
CPU time 27.04 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:54 PM PDT 24
Peak memory 276720 kb
Host smart-9cf139b4-f765-417c-a83d-05201f74a9e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332264739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1332264739
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3446162314
Short name T1264
Test name
Test status
Simulation time 10116157709 ps
CPU time 72.89 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 618820 kb
Host smart-23693faa-6151-4bad-9a3a-00e75bc43b7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446162314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3446162314
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1689231201
Short name T1258
Test name
Test status
Simulation time 2114981346 ps
CPU time 2.64 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:30 PM PDT 24
Peak memory 205052 kb
Host smart-4d8d3f3b-9aa1-420b-a753-dbb7d24dec58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689231201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1689231201
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.3321949578
Short name T936
Test name
Test status
Simulation time 1130687644 ps
CPU time 3.49 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:31 PM PDT 24
Peak memory 205040 kb
Host smart-9f90ffa6-a394-403a-b85e-bb69d53b355e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321949578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.3321949578
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.1840286762
Short name T1030
Test name
Test status
Simulation time 6612462306 ps
CPU time 2.52 seconds
Started Jun 05 04:37:28 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 205356 kb
Host smart-be966f00-b01b-46c0-aaff-d2721c94f688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840286762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.1840286762
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2702863236
Short name T875
Test name
Test status
Simulation time 5550554493 ps
CPU time 6.75 seconds
Started Jun 05 04:37:24 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 219000 kb
Host smart-f71674bb-3f37-4060-a40e-0fb058114199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702863236 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2702863236
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.264214821
Short name T359
Test name
Test status
Simulation time 5089395343 ps
CPU time 49.01 seconds
Started Jun 05 04:37:27 PM PDT 24
Finished Jun 05 04:38:18 PM PDT 24
Peak memory 1299260 kb
Host smart-874b3a9d-32dc-4327-bc98-860ea8a8a300
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264214821 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.264214821
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2138534919
Short name T486
Test name
Test status
Simulation time 776267877 ps
CPU time 8.72 seconds
Started Jun 05 04:37:18 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 205116 kb
Host smart-98762567-d3f1-4453-8543-1ef3ed4af236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138534919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2138534919
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.374774818
Short name T1011
Test name
Test status
Simulation time 576051319 ps
CPU time 11.17 seconds
Started Jun 05 04:37:25 PM PDT 24
Finished Jun 05 04:37:37 PM PDT 24
Peak memory 205928 kb
Host smart-cc507c42-b4ae-40ff-adb5-2be77cc04a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374774818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.374774818
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3403480737
Short name T1407
Test name
Test status
Simulation time 62083565981 ps
CPU time 31.31 seconds
Started Jun 05 04:37:23 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 542688 kb
Host smart-2ba9ac96-8f3c-4d73-8212-92fe0f2e103e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403480737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3403480737
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3691704976
Short name T1143
Test name
Test status
Simulation time 5656208960 ps
CPU time 149.99 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:39:56 PM PDT 24
Peak memory 1395328 kb
Host smart-72f8ad32-c084-4306-b7f9-df9f4ea4242c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691704976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3691704976
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.4256441661
Short name T734
Test name
Test status
Simulation time 16600843531 ps
CPU time 6.74 seconds
Started Jun 05 04:37:27 PM PDT 24
Finished Jun 05 04:37:35 PM PDT 24
Peak memory 213412 kb
Host smart-fb0bbef3-e3e1-4cd8-ac6c-81a9779dd092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256441661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.4256441661
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.3252817750
Short name T1421
Test name
Test status
Simulation time 1086982231 ps
CPU time 19.97 seconds
Started Jun 05 04:37:28 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 205008 kb
Host smart-2ecff4ad-5cea-4eba-b878-30108cb545a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252817750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.3252817750
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3533712461
Short name T830
Test name
Test status
Simulation time 17701196 ps
CPU time 0.63 seconds
Started Jun 05 04:37:38 PM PDT 24
Finished Jun 05 04:37:39 PM PDT 24
Peak memory 204700 kb
Host smart-ec8aa786-a7d8-45c2-aa61-8324c700006c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533712461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3533712461
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1109846282
Short name T308
Test name
Test status
Simulation time 76239909 ps
CPU time 1.45 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:37:37 PM PDT 24
Peak memory 216752 kb
Host smart-2e52e307-13e3-4674-836a-26a64c5b9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109846282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1109846282
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1307499015
Short name T416
Test name
Test status
Simulation time 1152862207 ps
CPU time 5.95 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:33 PM PDT 24
Peak memory 256620 kb
Host smart-54187e71-a1e1-46f4-bef7-bc5e97d7592c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307499015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1307499015
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2579639603
Short name T270
Test name
Test status
Simulation time 6278210639 ps
CPU time 181.54 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:40:38 PM PDT 24
Peak memory 722820 kb
Host smart-c9786c30-bdeb-4aed-8e2f-132dad66ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579639603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2579639603
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2375736564
Short name T1221
Test name
Test status
Simulation time 2181265575 ps
CPU time 64.33 seconds
Started Jun 05 04:37:27 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 693624 kb
Host smart-78de4dc9-6203-44dc-8e99-a02864183b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375736564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2375736564
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2202013893
Short name T63
Test name
Test status
Simulation time 214443640 ps
CPU time 1.06 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 204940 kb
Host smart-7666c948-1838-4e1c-9d7e-d194418654dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202013893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2202013893
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3693010962
Short name T844
Test name
Test status
Simulation time 224108531 ps
CPU time 12.01 seconds
Started Jun 05 04:37:28 PM PDT 24
Finished Jun 05 04:37:42 PM PDT 24
Peak memory 245568 kb
Host smart-173835ae-4ed7-41db-99a4-73aaf9d8fecb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693010962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3693010962
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3302111640
Short name T464
Test name
Test status
Simulation time 19498998557 ps
CPU time 145 seconds
Started Jun 05 04:37:28 PM PDT 24
Finished Jun 05 04:39:54 PM PDT 24
Peak memory 1271688 kb
Host smart-9d63a480-36ea-4193-872b-3ef1709ab974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302111640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3302111640
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2345509565
Short name T641
Test name
Test status
Simulation time 451219328 ps
CPU time 5.74 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:37:42 PM PDT 24
Peak memory 205020 kb
Host smart-8b64b15c-603c-4545-9d01-8fcb54849e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345509565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2345509565
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1333668911
Short name T1042
Test name
Test status
Simulation time 8612591359 ps
CPU time 35.47 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:38:11 PM PDT 24
Peak memory 399128 kb
Host smart-a03dfb81-2e83-4947-a988-e81758bcc8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333668911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1333668911
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3843197655
Short name T1013
Test name
Test status
Simulation time 32281635 ps
CPU time 0.68 seconds
Started Jun 05 04:37:26 PM PDT 24
Finished Jun 05 04:37:27 PM PDT 24
Peak memory 204768 kb
Host smart-8e690a4c-35b0-455c-ae92-9223b0e71d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843197655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3843197655
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.654655810
Short name T425
Test name
Test status
Simulation time 3065535258 ps
CPU time 18.03 seconds
Started Jun 05 04:37:39 PM PDT 24
Finished Jun 05 04:37:57 PM PDT 24
Peak memory 239004 kb
Host smart-1153f3c6-22a1-4f4f-8167-afebddf436e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654655810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.654655810
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.116149526
Short name T1255
Test name
Test status
Simulation time 30336209060 ps
CPU time 23.66 seconds
Started Jun 05 04:37:28 PM PDT 24
Finished Jun 05 04:37:53 PM PDT 24
Peak memory 317068 kb
Host smart-44d20584-e691-4b09-a650-00f1ff3a7d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116149526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.116149526
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2669212992
Short name T281
Test name
Test status
Simulation time 32354048658 ps
CPU time 263.67 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:42:00 PM PDT 24
Peak memory 1609864 kb
Host smart-345da9db-1507-4b6f-95e7-323291e0fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669212992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2669212992
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1723626089
Short name T494
Test name
Test status
Simulation time 848354344 ps
CPU time 14.73 seconds
Started Jun 05 04:37:34 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 220892 kb
Host smart-6f6f7394-18df-4299-848c-155fdfa4da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723626089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1723626089
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3723023308
Short name T1209
Test name
Test status
Simulation time 1454611977 ps
CPU time 3.45 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:37:40 PM PDT 24
Peak memory 205100 kb
Host smart-c8dc143c-228b-438b-aa63-c7fc032a356c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723023308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3723023308
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2359711851
Short name T962
Test name
Test status
Simulation time 10179001957 ps
CPU time 46.53 seconds
Started Jun 05 04:37:38 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 354852 kb
Host smart-66623d82-eaec-4ca0-a6c7-f630605f186e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359711851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2359711851
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3333844582
Short name T1470
Test name
Test status
Simulation time 10505156267 ps
CPU time 14.77 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:37:51 PM PDT 24
Peak memory 314352 kb
Host smart-6855cdd0-d617-4442-be1c-cdb88d394f17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333844582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3333844582
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.4233774643
Short name T995
Test name
Test status
Simulation time 1093907815 ps
CPU time 1.69 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 205096 kb
Host smart-c06e2281-16c4-4a4f-a276-c611b881a9dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233774643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.4233774643
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.602931877
Short name T811
Test name
Test status
Simulation time 1108272435 ps
CPU time 3.18 seconds
Started Jun 05 04:37:34 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 205124 kb
Host smart-6f6cf6f0-0a2f-48fb-9a50-e992cdd24ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602931877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.602931877
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3751695317
Short name T561
Test name
Test status
Simulation time 1259404190 ps
CPU time 2.08 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 205060 kb
Host smart-f1babb56-9b8c-4065-bd65-633e0d6be0b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751695317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3751695317
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3098563465
Short name T375
Test name
Test status
Simulation time 723064625 ps
CPU time 3.55 seconds
Started Jun 05 04:37:34 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 205092 kb
Host smart-54cdc110-983a-450f-baff-8fee6c98803f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098563465 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3098563465
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2767645615
Short name T157
Test name
Test status
Simulation time 4520743104 ps
CPU time 10.02 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:37:47 PM PDT 24
Peak memory 205152 kb
Host smart-f0a887a8-7e56-43a3-87a9-7d90b135e6ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767645615 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2767645615
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.630986379
Short name T824
Test name
Test status
Simulation time 1017943617 ps
CPU time 38.82 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:38:16 PM PDT 24
Peak memory 205056 kb
Host smart-796b2f88-9b7b-4dc9-aaae-c1c5c86bb1a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630986379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.630986379
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3452899688
Short name T799
Test name
Test status
Simulation time 5893586306 ps
CPU time 62.2 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 206808 kb
Host smart-218e370f-cb5d-4b18-abd5-6b76ae93ae7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452899688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3452899688
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3309366303
Short name T1362
Test name
Test status
Simulation time 22361038837 ps
CPU time 56.4 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:38:34 PM PDT 24
Peak memory 655072 kb
Host smart-f28a88b0-620a-45eb-b5d7-174885c15303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309366303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3309366303
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3653483142
Short name T319
Test name
Test status
Simulation time 20873986052 ps
CPU time 524.92 seconds
Started Jun 05 04:37:38 PM PDT 24
Finished Jun 05 04:46:23 PM PDT 24
Peak memory 2647532 kb
Host smart-83473489-a324-4808-97a5-62e1b9264d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653483142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3653483142
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2334980338
Short name T786
Test name
Test status
Simulation time 1491513784 ps
CPU time 7.04 seconds
Started Jun 05 04:37:41 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 205136 kb
Host smart-67b60d33-3c28-44a2-9525-43e21e965530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334980338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2334980338
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.189828211
Short name T719
Test name
Test status
Simulation time 1084260121 ps
CPU time 14.67 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:37:53 PM PDT 24
Peak memory 204980 kb
Host smart-4cd44a50-84bd-447b-8a69-4fd6523b7155
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189828211 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.189828211
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3741665541
Short name T602
Test name
Test status
Simulation time 35253178 ps
CPU time 0.6 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:37:48 PM PDT 24
Peak memory 204688 kb
Host smart-2b4129e1-cee1-4e63-b8a2-c645a965d8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741665541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3741665541
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.457202118
Short name T1104
Test name
Test status
Simulation time 872263998 ps
CPU time 12.49 seconds
Started Jun 05 04:37:39 PM PDT 24
Finished Jun 05 04:37:52 PM PDT 24
Peak memory 265068 kb
Host smart-1cb0f42a-bd5b-463a-ae6f-9c5cfa9c298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457202118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.457202118
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1134559215
Short name T134
Test name
Test status
Simulation time 1597911394 ps
CPU time 7.94 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:37:44 PM PDT 24
Peak memory 280556 kb
Host smart-780cdb73-7a09-4c28-ac88-522c303b7400
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134559215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1134559215
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2046547648
Short name T363
Test name
Test status
Simulation time 9515439308 ps
CPU time 57.54 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:38:34 PM PDT 24
Peak memory 609200 kb
Host smart-f2811c32-afde-402c-9064-fa6414eda094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046547648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2046547648
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1579826004
Short name T181
Test name
Test status
Simulation time 7834134189 ps
CPU time 57.16 seconds
Started Jun 05 04:37:42 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 629464 kb
Host smart-970fb958-e74e-4437-ba9e-96e528c87199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579826004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1579826004
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2544739413
Short name T1452
Test name
Test status
Simulation time 114724482 ps
CPU time 0.8 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:37:39 PM PDT 24
Peak memory 204688 kb
Host smart-aa8323ec-2290-4832-82c6-f7a8c2fe0efe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544739413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2544739413
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1843332491
Short name T731
Test name
Test status
Simulation time 164385059 ps
CPU time 3.81 seconds
Started Jun 05 04:37:33 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 205052 kb
Host smart-b3ccdbd9-3b4a-4635-8188-361f12205059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843332491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1843332491
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.4040864047
Short name T546
Test name
Test status
Simulation time 3808730517 ps
CPU time 116.83 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:39:32 PM PDT 24
Peak memory 1100644 kb
Host smart-2fa53ea5-a55b-44d8-aea9-e596b973c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040864047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.4040864047
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2676548024
Short name T938
Test name
Test status
Simulation time 2218568817 ps
CPU time 26.51 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:38:11 PM PDT 24
Peak memory 205176 kb
Host smart-3bc23ba9-19ed-4881-9800-591990412fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676548024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2676548024
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1889187168
Short name T283
Test name
Test status
Simulation time 2021598512 ps
CPU time 21.99 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:38:07 PM PDT 24
Peak memory 232808 kb
Host smart-f01abb40-6c21-4c88-a4a3-bef2723cf4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889187168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1889187168
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1243205953
Short name T564
Test name
Test status
Simulation time 15367875 ps
CPU time 0.67 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:37:38 PM PDT 24
Peak memory 204760 kb
Host smart-dfd17671-f00b-4792-8699-6a24b09fc094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243205953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1243205953
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.116925404
Short name T309
Test name
Test status
Simulation time 736130644 ps
CPU time 11.38 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:37:48 PM PDT 24
Peak memory 261420 kb
Host smart-68e2f3a6-601d-4731-8ee1-5555e695985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116925404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.116925404
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3682573898
Short name T966
Test name
Test status
Simulation time 7384914572 ps
CPU time 30.9 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:38:08 PM PDT 24
Peak memory 318752 kb
Host smart-482d086f-8878-4cd5-81eb-f8942138d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682573898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3682573898
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2823437481
Short name T130
Test name
Test status
Simulation time 11650474464 ps
CPU time 337.32 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:43:15 PM PDT 24
Peak memory 1690208 kb
Host smart-e3dea9e6-b121-48f3-8525-470b0fe902e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823437481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2823437481
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3467847299
Short name T604
Test name
Test status
Simulation time 1140866358 ps
CPU time 11.25 seconds
Started Jun 05 04:37:37 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 214296 kb
Host smart-866f61e1-49d6-4cac-b43f-e5c0c1012a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467847299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3467847299
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2326481839
Short name T1350
Test name
Test status
Simulation time 1036627719 ps
CPU time 5.49 seconds
Started Jun 05 04:37:46 PM PDT 24
Finished Jun 05 04:37:53 PM PDT 24
Peak memory 213360 kb
Host smart-8b9e0bc0-8906-4e31-b811-487728c189ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326481839 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2326481839
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2547733386
Short name T1308
Test name
Test status
Simulation time 10334015607 ps
CPU time 18.89 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:38:06 PM PDT 24
Peak memory 299936 kb
Host smart-c29d8e6f-af3e-4a5d-ad4f-a29bf679d32d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547733386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2547733386
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.2359769855
Short name T1423
Test name
Test status
Simulation time 1311116969 ps
CPU time 5.45 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:37:51 PM PDT 24
Peak memory 205108 kb
Host smart-989d2332-0b0b-4303-bd27-78159264b45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359769855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.2359769855
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.2692905305
Short name T294
Test name
Test status
Simulation time 1074167954 ps
CPU time 3.54 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:37:48 PM PDT 24
Peak memory 205208 kb
Host smart-33734604-0777-4e75-ac09-4a45b7dc36cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692905305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.2692905305
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2207759477
Short name T414
Test name
Test status
Simulation time 2287715817 ps
CPU time 3.36 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 205176 kb
Host smart-839edb4f-3128-4e71-8729-da1cf415c491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207759477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2207759477
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1010741817
Short name T1167
Test name
Test status
Simulation time 3965296304 ps
CPU time 5.43 seconds
Started Jun 05 04:37:39 PM PDT 24
Finished Jun 05 04:37:45 PM PDT 24
Peak memory 205124 kb
Host smart-b5375160-e57b-40ad-be28-84eec6c3c5a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010741817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1010741817
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1723090384
Short name T1197
Test name
Test status
Simulation time 16130984946 ps
CPU time 36.67 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 964588 kb
Host smart-2074a8b8-246b-4ecf-a9c4-ee9ba002a296
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723090384 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1723090384
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2957316
Short name T797
Test name
Test status
Simulation time 1469799036 ps
CPU time 11.99 seconds
Started Jun 05 04:37:41 PM PDT 24
Finished Jun 05 04:37:53 PM PDT 24
Peak memory 205040 kb
Host smart-0922b35f-5834-4095-a866-07f2a32f91df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_targe
t_smoke.2957316
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1780396017
Short name T372
Test name
Test status
Simulation time 420377372 ps
CPU time 6.19 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 205056 kb
Host smart-c3228497-9ebc-4ea1-b90a-69bcbf3a48c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780396017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1780396017
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1745281085
Short name T1130
Test name
Test status
Simulation time 68961720341 ps
CPU time 929.54 seconds
Started Jun 05 04:37:35 PM PDT 24
Finished Jun 05 04:53:05 PM PDT 24
Peak memory 6463388 kb
Host smart-0f03db61-de80-4d94-ba8a-d97798305136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745281085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1745281085
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1618422
Short name T1405
Test name
Test status
Simulation time 26660795300 ps
CPU time 65.92 seconds
Started Jun 05 04:37:36 PM PDT 24
Finished Jun 05 04:38:42 PM PDT 24
Peak memory 635216 kb
Host smart-15e1d08d-663b-4255-9ce9-0f80d0037ff2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_stretch.1618422
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2667261753
Short name T370
Test name
Test status
Simulation time 2643265137 ps
CPU time 6.9 seconds
Started Jun 05 04:37:42 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 213396 kb
Host smart-6ecbfc35-36cd-4eb8-8e96-35c7cd77eaf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667261753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2667261753
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.3696285167
Short name T524
Test name
Test status
Simulation time 1051963226 ps
CPU time 19.06 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:38:05 PM PDT 24
Peak memory 205112 kb
Host smart-6079faed-33c7-48b8-93de-f1ecc3721ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696285167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3696285167
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3938137115
Short name T531
Test name
Test status
Simulation time 38200348 ps
CPU time 0.64 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:37:47 PM PDT 24
Peak memory 204728 kb
Host smart-42d28378-2180-4e68-b9ca-e1c46ef5c1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938137115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3938137115
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3482513197
Short name T1402
Test name
Test status
Simulation time 159355294 ps
CPU time 3.05 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:37:47 PM PDT 24
Peak memory 215572 kb
Host smart-91618829-ddff-4a5f-93fa-4bd623040deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482513197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3482513197
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2549698513
Short name T589
Test name
Test status
Simulation time 1038542873 ps
CPU time 4.65 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:37:53 PM PDT 24
Peak memory 251356 kb
Host smart-4b1d5a9f-f1ad-4728-8019-aabb6b8eeeeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549698513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2549698513
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1990074729
Short name T1052
Test name
Test status
Simulation time 1434989048 ps
CPU time 103.98 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 557780 kb
Host smart-f3b3b592-26ca-4c69-a8ea-2b845491f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990074729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1990074729
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3999292178
Short name T1054
Test name
Test status
Simulation time 2650491607 ps
CPU time 95.3 seconds
Started Jun 05 04:37:51 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 836248 kb
Host smart-37b3978f-6a57-4dcf-8dce-1a902b2a0151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999292178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3999292178
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2958655374
Short name T941
Test name
Test status
Simulation time 298654727 ps
CPU time 0.91 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:37:46 PM PDT 24
Peak memory 204936 kb
Host smart-2fe55200-5e54-452b-96b9-b796109908dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958655374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2958655374
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3985304010
Short name T1191
Test name
Test status
Simulation time 360077890 ps
CPU time 7.01 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:37:51 PM PDT 24
Peak memory 205036 kb
Host smart-52eeb38d-6002-4c50-a9d6-29a1c1a3bc81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985304010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3985304010
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3371061227
Short name T1169
Test name
Test status
Simulation time 9721752403 ps
CPU time 130.7 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:39:57 PM PDT 24
Peak memory 1380984 kb
Host smart-d8d7cb7e-2b9d-44cc-baa4-e569ce1f714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371061227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3371061227
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.269096995
Short name T1140
Test name
Test status
Simulation time 399850577 ps
CPU time 17.08 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 205056 kb
Host smart-3413fdc7-fa63-4c5c-9611-2badeb582698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269096995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.269096995
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1444966051
Short name T625
Test name
Test status
Simulation time 1254550910 ps
CPU time 20.71 seconds
Started Jun 05 04:37:48 PM PDT 24
Finished Jun 05 04:38:09 PM PDT 24
Peak memory 298952 kb
Host smart-adf2c667-ec66-43f5-9032-4f87c1b1ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444966051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1444966051
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.984302784
Short name T97
Test name
Test status
Simulation time 16814403 ps
CPU time 0.65 seconds
Started Jun 05 04:37:46 PM PDT 24
Finished Jun 05 04:37:47 PM PDT 24
Peak memory 204760 kb
Host smart-ba3ee46f-0267-470c-86fd-1571d152dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984302784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.984302784
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.457913278
Short name T530
Test name
Test status
Simulation time 2758310091 ps
CPU time 20.7 seconds
Started Jun 05 04:37:49 PM PDT 24
Finished Jun 05 04:38:10 PM PDT 24
Peak memory 230656 kb
Host smart-4638d288-5fe2-49ed-a068-46ce1c75c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457913278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.457913278
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.4074530290
Short name T700
Test name
Test status
Simulation time 1356520028 ps
CPU time 62.48 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 271372 kb
Host smart-e3c6c984-8bdb-44ab-92d0-83403d983a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074530290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4074530290
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2723132035
Short name T128
Test name
Test status
Simulation time 24975554556 ps
CPU time 133.6 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:39:59 PM PDT 24
Peak memory 1148780 kb
Host smart-ebcd4a3a-e4ef-4e1a-94fa-e46668d174af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723132035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2723132035
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.952508771
Short name T982
Test name
Test status
Simulation time 1359233807 ps
CPU time 10.43 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 221344 kb
Host smart-18882196-ea12-4ba6-bf34-1a5dc1a28e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952508771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.952508771
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2123970676
Short name T1269
Test name
Test status
Simulation time 3787205600 ps
CPU time 4.96 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:37:52 PM PDT 24
Peak memory 214004 kb
Host smart-c22eb900-7039-4b0f-9802-1cd5d3e8c7eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123970676 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2123970676
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.431828948
Short name T86
Test name
Test status
Simulation time 10203121510 ps
CPU time 51.76 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:38:38 PM PDT 24
Peak memory 357156 kb
Host smart-4ea72011-4927-4f8d-bad2-adae76ece0c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431828948 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.431828948
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.287701369
Short name T1483
Test name
Test status
Simulation time 10156027089 ps
CPU time 17.36 seconds
Started Jun 05 04:37:46 PM PDT 24
Finished Jun 05 04:38:04 PM PDT 24
Peak memory 336472 kb
Host smart-df1f0d89-6142-4dd3-b0bc-cb95f0e2755e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287701369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.287701369
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1315053829
Short name T1463
Test name
Test status
Simulation time 2526867146 ps
CPU time 2.61 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:37:48 PM PDT 24
Peak memory 205160 kb
Host smart-27443d28-ceca-444d-8558-62a0d5f31a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315053829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1315053829
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.1084788828
Short name T1335
Test name
Test status
Simulation time 1759131203 ps
CPU time 1.02 seconds
Started Jun 05 04:37:50 PM PDT 24
Finished Jun 05 04:37:51 PM PDT 24
Peak memory 204912 kb
Host smart-51720092-829b-472e-8470-98a86c4f45e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084788828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.1084788828
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.4140813669
Short name T32
Test name
Test status
Simulation time 464394361 ps
CPU time 2.98 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:37:48 PM PDT 24
Peak memory 205124 kb
Host smart-ae46cc6d-f9eb-420f-b068-fa4ab4256216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140813669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.4140813669
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.308843404
Short name T946
Test name
Test status
Simulation time 3221709784 ps
CPU time 5.02 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 206516 kb
Host smart-da0bec05-7189-4ab9-af16-63b74ba3c962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308843404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.308843404
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.920359561
Short name T1481
Test name
Test status
Simulation time 17022634071 ps
CPU time 35.45 seconds
Started Jun 05 04:37:48 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 614764 kb
Host smart-337c5a0d-bb07-4416-ada0-750b8ab087b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920359561 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.920359561
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3191394019
Short name T621
Test name
Test status
Simulation time 1265314715 ps
CPU time 54.13 seconds
Started Jun 05 04:37:46 PM PDT 24
Finished Jun 05 04:38:41 PM PDT 24
Peak memory 205136 kb
Host smart-6b89f97f-7d8f-4484-b10b-adb5c8de5702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191394019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3191394019
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.802907378
Short name T320
Test name
Test status
Simulation time 2015369362 ps
CPU time 24.6 seconds
Started Jun 05 04:37:43 PM PDT 24
Finished Jun 05 04:38:09 PM PDT 24
Peak memory 205064 kb
Host smart-55af9ee0-408c-45b4-a0e2-6831446297d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802907378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.802907378
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3860552690
Short name T1277
Test name
Test status
Simulation time 40099542005 ps
CPU time 223.21 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:41:28 PM PDT 24
Peak memory 2553052 kb
Host smart-ee522394-189c-4c0c-a252-ef4970d8cb42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860552690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3860552690
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2603184788
Short name T908
Test name
Test status
Simulation time 22539187928 ps
CPU time 546.79 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:46:52 PM PDT 24
Peak memory 2615216 kb
Host smart-bbaf09cc-8263-488e-bb54-4144397aa360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603184788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2603184788
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3852257522
Short name T379
Test name
Test status
Simulation time 5530904154 ps
CPU time 7.66 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:37:55 PM PDT 24
Peak memory 215400 kb
Host smart-93430b97-05d9-457f-be91-a08c8788fdaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852257522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3852257522
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.4132805324
Short name T23
Test name
Test status
Simulation time 1273683677 ps
CPU time 16.7 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:38:03 PM PDT 24
Peak memory 205116 kb
Host smart-142063cb-966c-4f2a-b559-cfad4ad3eeb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132805324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.4132805324
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1136272603
Short name T978
Test name
Test status
Simulation time 18038832 ps
CPU time 0.65 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:37:55 PM PDT 24
Peak memory 204716 kb
Host smart-549181d3-514c-4ff3-9cfb-dda7f70ae134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136272603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1136272603
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.864742008
Short name T1272
Test name
Test status
Simulation time 150241097 ps
CPU time 2.39 seconds
Started Jun 05 04:37:56 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 213388 kb
Host smart-1b823ac5-e797-4dac-9226-5bcb9cbc2cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864742008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.864742008
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2188344801
Short name T1247
Test name
Test status
Simulation time 1222746324 ps
CPU time 7.61 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:38:04 PM PDT 24
Peak memory 272864 kb
Host smart-d0b9b0eb-7405-446b-9c1e-d7731cd8db56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188344801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2188344801
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.258508457
Short name T453
Test name
Test status
Simulation time 8231550874 ps
CPU time 58.82 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 654724 kb
Host smart-52a8ba4d-a180-423f-b5a9-1484d9977322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258508457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.258508457
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2826679227
Short name T1225
Test name
Test status
Simulation time 6344217445 ps
CPU time 40.89 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:36 PM PDT 24
Peak memory 508684 kb
Host smart-5d88407e-331b-4708-92cc-ba3a52efddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826679227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2826679227
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.4045114641
Short name T754
Test name
Test status
Simulation time 73735251 ps
CPU time 0.75 seconds
Started Jun 05 04:37:51 PM PDT 24
Finished Jun 05 04:37:52 PM PDT 24
Peak memory 204800 kb
Host smart-cb1432e4-c1c9-4aaa-a91e-c37eec46d071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045114641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.4045114641
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3068148904
Short name T1311
Test name
Test status
Simulation time 213316749 ps
CPU time 10.51 seconds
Started Jun 05 04:37:59 PM PDT 24
Finished Jun 05 04:38:10 PM PDT 24
Peak memory 205008 kb
Host smart-bd456077-399c-4881-99d9-024680f06196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068148904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3068148904
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2636082130
Short name T992
Test name
Test status
Simulation time 5742672698 ps
CPU time 180.24 seconds
Started Jun 05 04:37:47 PM PDT 24
Finished Jun 05 04:40:48 PM PDT 24
Peak memory 1617740 kb
Host smart-78fce7f6-40c4-49de-8e2a-20eca2f97344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636082130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2636082130
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.517865225
Short name T687
Test name
Test status
Simulation time 366213546 ps
CPU time 15.73 seconds
Started Jun 05 04:37:57 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 205060 kb
Host smart-5ce2122d-ecb4-431c-94fd-70af5e694ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517865225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.517865225
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1644339855
Short name T362
Test name
Test status
Simulation time 8454242767 ps
CPU time 105.61 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:39:42 PM PDT 24
Peak memory 359040 kb
Host smart-21b22a36-5a20-4581-be5a-bb45900e2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644339855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1644339855
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1176063002
Short name T1303
Test name
Test status
Simulation time 27616373 ps
CPU time 0.7 seconds
Started Jun 05 04:37:44 PM PDT 24
Finished Jun 05 04:37:45 PM PDT 24
Peak memory 204776 kb
Host smart-f7750561-46d2-43ac-9a50-002a2a66b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176063002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1176063002
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.4218515440
Short name T166
Test name
Test status
Simulation time 19039921669 ps
CPU time 339.83 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:43:34 PM PDT 24
Peak memory 1731832 kb
Host smart-090701f6-1222-43dc-baa8-41c0894861c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218515440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.4218515440
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1327334698
Short name T1236
Test name
Test status
Simulation time 1974675492 ps
CPU time 42.46 seconds
Started Jun 05 04:37:45 PM PDT 24
Finished Jun 05 04:38:28 PM PDT 24
Peak memory 411948 kb
Host smart-0377046d-5853-45db-a1c9-17f3fa193310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327334698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1327334698
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.1007664250
Short name T66
Test name
Test status
Simulation time 11707463926 ps
CPU time 1207.24 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:58:01 PM PDT 24
Peak memory 2509656 kb
Host smart-85accde2-3c96-4160-8134-d3c8f72420f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007664250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1007664250
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3185953633
Short name T1250
Test name
Test status
Simulation time 678029787 ps
CPU time 11.79 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:38:08 PM PDT 24
Peak memory 213308 kb
Host smart-c1eab009-dff7-4eac-a84d-2cf0637eb690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185953633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3185953633
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2742978341
Short name T516
Test name
Test status
Simulation time 934433800 ps
CPU time 4.12 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 205100 kb
Host smart-47e02f7d-bc98-4059-99fa-2e7f86635eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742978341 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2742978341
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.288162789
Short name T1066
Test name
Test status
Simulation time 10509995431 ps
CPU time 10.16 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:05 PM PDT 24
Peak memory 242120 kb
Host smart-a74dc796-b3e8-4414-a164-bc3ab20d494f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288162789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.288162789
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2304529172
Short name T438
Test name
Test status
Simulation time 10158835545 ps
CPU time 75.36 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 529076 kb
Host smart-4b52755d-a302-47b7-82f0-52fd180441a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304529172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2304529172
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2682750972
Short name T680
Test name
Test status
Simulation time 4127661616 ps
CPU time 2.62 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:37:57 PM PDT 24
Peak memory 205156 kb
Host smart-24183066-5dbf-43eb-b52f-e52ef7ad66b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682750972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2682750972
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.524813413
Short name T389
Test name
Test status
Simulation time 1275950049 ps
CPU time 3.47 seconds
Started Jun 05 04:37:56 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 205104 kb
Host smart-27e5e2c2-962d-49de-a860-3b1956b96d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524813413 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.524813413
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3085889815
Short name T1070
Test name
Test status
Simulation time 595264447 ps
CPU time 3.21 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:37:58 PM PDT 24
Peak memory 205068 kb
Host smart-1f731b4e-fb02-4882-be33-30dec2815c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085889815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3085889815
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2295797859
Short name T1178
Test name
Test status
Simulation time 10848652118 ps
CPU time 5.69 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 205136 kb
Host smart-197d7cfa-3def-422c-bd71-b3d6429907f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295797859 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2295797859
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3997580832
Short name T332
Test name
Test status
Simulation time 9367100371 ps
CPU time 7.4 seconds
Started Jun 05 04:37:51 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 229136 kb
Host smart-5afc68ce-7ba6-43cd-9986-aa55382c5c5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997580832 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3997580832
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1972805391
Short name T1301
Test name
Test status
Simulation time 1612440804 ps
CPU time 12.83 seconds
Started Jun 05 04:37:52 PM PDT 24
Finished Jun 05 04:38:06 PM PDT 24
Peak memory 205052 kb
Host smart-abb8b298-8233-4204-b70a-1759a9548b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972805391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1972805391
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2696154038
Short name T888
Test name
Test status
Simulation time 2523259895 ps
CPU time 27.86 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:23 PM PDT 24
Peak memory 205084 kb
Host smart-2d688c1b-0406-4a2e-9359-768fe62fa655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696154038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2696154038
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1847112372
Short name T845
Test name
Test status
Simulation time 49266597980 ps
CPU time 145.64 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:40:21 PM PDT 24
Peak memory 1843560 kb
Host smart-486da4d5-4d52-4f30-8a61-15a8c5523fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847112372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1847112372
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.607570578
Short name T1014
Test name
Test status
Simulation time 24987155684 ps
CPU time 1299.62 seconds
Started Jun 05 04:37:56 PM PDT 24
Finished Jun 05 04:59:37 PM PDT 24
Peak memory 5994036 kb
Host smart-efb99cbd-7745-4085-8994-5d820661ed6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607570578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.607570578
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.981890993
Short name T76
Test name
Test status
Simulation time 4964666568 ps
CPU time 7.02 seconds
Started Jun 05 04:37:52 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 220612 kb
Host smart-a2c17841-c375-43c9-9de7-e2df45a34343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981890993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.981890993
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.261619483
Short name T1316
Test name
Test status
Simulation time 1303642184 ps
CPU time 16.86 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:38:13 PM PDT 24
Peak memory 205084 kb
Host smart-335b933f-da0b-4a8a-812c-d2614dd65e8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261619483 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.261619483
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2337166580
Short name T1177
Test name
Test status
Simulation time 38751249 ps
CPU time 0.63 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 204748 kb
Host smart-56c85141-2658-4beb-8012-1d90db0989a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337166580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2337166580
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3648907000
Short name T1418
Test name
Test status
Simulation time 247033431 ps
CPU time 3.24 seconds
Started Jun 05 04:37:58 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 213300 kb
Host smart-a40a8443-7e70-4b75-83f5-12b1c7b318c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648907000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3648907000
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3306139554
Short name T393
Test name
Test status
Simulation time 1048959546 ps
CPU time 5.58 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:38:02 PM PDT 24
Peak memory 261196 kb
Host smart-f2431b34-2c57-418f-9c31-ec642fcb11d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306139554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3306139554
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2133256266
Short name T586
Test name
Test status
Simulation time 6392176704 ps
CPU time 174.46 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:40:50 PM PDT 24
Peak memory 747308 kb
Host smart-a15b4873-02d7-47ca-b778-81448a7de608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133256266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2133256266
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3688524279
Short name T932
Test name
Test status
Simulation time 2207775107 ps
CPU time 183.42 seconds
Started Jun 05 04:37:58 PM PDT 24
Finished Jun 05 04:41:02 PM PDT 24
Peak memory 753672 kb
Host smart-ada286e9-6414-498a-845c-acf7cde0b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688524279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3688524279
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1798380333
Short name T656
Test name
Test status
Simulation time 132021282 ps
CPU time 1.07 seconds
Started Jun 05 04:37:59 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 205004 kb
Host smart-3e77f28a-c96d-406a-874e-29fc89d1d2b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798380333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1798380333
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1285998295
Short name T391
Test name
Test status
Simulation time 1028984124 ps
CPU time 4.42 seconds
Started Jun 05 04:37:56 PM PDT 24
Finished Jun 05 04:38:01 PM PDT 24
Peak memory 205020 kb
Host smart-aadb26bb-0056-47a5-ba2a-d5c156a0e400
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285998295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1285998295
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2939863031
Short name T870
Test name
Test status
Simulation time 30238078864 ps
CPU time 167.26 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:40:41 PM PDT 24
Peak memory 1547120 kb
Host smart-dea31840-7cb1-44a8-861e-a708e728dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939863031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2939863031
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3152829491
Short name T720
Test name
Test status
Simulation time 1992108174 ps
CPU time 8.56 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 205080 kb
Host smart-5505385a-7f59-4711-a697-508263e13f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152829491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3152829491
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3592143883
Short name T883
Test name
Test status
Simulation time 1995638397 ps
CPU time 87.26 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:39:39 PM PDT 24
Peak memory 331620 kb
Host smart-f69d1132-2945-44f3-86ce-d59b7f186388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592143883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3592143883
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3630087373
Short name T1243
Test name
Test status
Simulation time 16984931 ps
CPU time 0.7 seconds
Started Jun 05 04:37:56 PM PDT 24
Finished Jun 05 04:37:58 PM PDT 24
Peak memory 204744 kb
Host smart-519c06dd-af20-40eb-8050-7950700023aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630087373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3630087373
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1656891707
Short name T40
Test name
Test status
Simulation time 1393744829 ps
CPU time 14.53 seconds
Started Jun 05 04:37:55 PM PDT 24
Finished Jun 05 04:38:11 PM PDT 24
Peak memory 346172 kb
Host smart-d41bca26-f9dc-4f62-ac78-8b2b225e9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656891707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1656891707
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3883835316
Short name T1038
Test name
Test status
Simulation time 1763530096 ps
CPU time 66.59 seconds
Started Jun 05 04:37:53 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 302252 kb
Host smart-32470ab3-7cf1-4281-99c4-4c46bb3d7cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883835316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3883835316
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3061540517
Short name T1083
Test name
Test status
Simulation time 1003047986 ps
CPU time 29.94 seconds
Started Jun 05 04:37:54 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 213176 kb
Host smart-39df3684-a20c-47c1-a5ea-49c68f3bd542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061540517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3061540517
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3087076165
Short name T689
Test name
Test status
Simulation time 7547408274 ps
CPU time 3.28 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:16 PM PDT 24
Peak memory 205224 kb
Host smart-042f5d0d-a19e-4f17-becc-d7edd6ced5fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087076165 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3087076165
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.4093152912
Short name T1163
Test name
Test status
Simulation time 10111988210 ps
CPU time 44.13 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 314116 kb
Host smart-eb71dd12-195a-44e5-ac65-d63a2e586393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093152912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.4093152912
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1018417413
Short name T670
Test name
Test status
Simulation time 10124562011 ps
CPU time 38.43 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:49 PM PDT 24
Peak memory 423520 kb
Host smart-5c44822f-9b6a-406f-a01a-27fe842f7ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018417413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1018417413
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.2836408427
Short name T747
Test name
Test status
Simulation time 1121705014 ps
CPU time 4.99 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 205044 kb
Host smart-c2f8d5ff-9734-4f80-a03d-e34b0c375fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836408427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.2836408427
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.805194489
Short name T1149
Test name
Test status
Simulation time 1059338385 ps
CPU time 5.67 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 205136 kb
Host smart-b46768c7-4240-41af-95e3-5d42f92ffef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805194489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.805194489
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1535256075
Short name T334
Test name
Test status
Simulation time 2242241149 ps
CPU time 3.21 seconds
Started Jun 05 04:38:08 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 205060 kb
Host smart-41fbbd80-e823-4dd8-a4b7-f9e69b957f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535256075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1535256075
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1883768457
Short name T1292
Test name
Test status
Simulation time 4969271892 ps
CPU time 7.37 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 220064 kb
Host smart-fa74e735-f11b-420c-a737-4eb10b33ba09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883768457 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1883768457
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3687062359
Short name T913
Test name
Test status
Simulation time 24863906902 ps
CPU time 79.32 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:39:33 PM PDT 24
Peak memory 1494104 kb
Host smart-bbaf7308-3c98-479d-b62d-a6e8ccf7f188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687062359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3687062359
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1950323732
Short name T714
Test name
Test status
Simulation time 2506303083 ps
CPU time 46.11 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:57 PM PDT 24
Peak memory 205200 kb
Host smart-2f31416b-17b8-44b8-a79c-a2094631b0bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950323732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1950323732
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3506154112
Short name T381
Test name
Test status
Simulation time 1149491109 ps
CPU time 18.59 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:29 PM PDT 24
Peak memory 214332 kb
Host smart-3e3fd163-934d-4fa7-91e9-8847a7c1163d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506154112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3506154112
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1436416665
Short name T373
Test name
Test status
Simulation time 19109764952 ps
CPU time 36.16 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:47 PM PDT 24
Peak memory 205092 kb
Host smart-d2df729f-5c02-420e-aff1-a746c0bfc81a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436416665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1436416665
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3761428587
Short name T489
Test name
Test status
Simulation time 30068489024 ps
CPU time 1903.07 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 05:09:57 PM PDT 24
Peak memory 7277620 kb
Host smart-15ecfb21-5b6a-42de-9fc9-12d3decc7e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761428587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3761428587
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3753145778
Short name T417
Test name
Test status
Simulation time 3261234907 ps
CPU time 6.92 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:18 PM PDT 24
Peak memory 213356 kb
Host smart-827035aa-d569-4a99-b3fb-6391fbaa15d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753145778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3753145778
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.2910433928
Short name T1172
Test name
Test status
Simulation time 1078765684 ps
CPU time 21.43 seconds
Started Jun 05 04:38:08 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 205108 kb
Host smart-510bd127-4657-4d4a-95cf-cd5601436761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910433928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2910433928
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.715447429
Short name T466
Test name
Test status
Simulation time 25879509 ps
CPU time 0.62 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 204752 kb
Host smart-07375806-83e6-4376-a196-4cce899e5bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715447429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.715447429
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2046202312
Short name T903
Test name
Test status
Simulation time 558876487 ps
CPU time 1.98 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 213372 kb
Host smart-ddcfd4b1-f9e4-4895-ae19-b01675d53651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046202312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2046202312
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2094644511
Short name T1353
Test name
Test status
Simulation time 310092472 ps
CPU time 5.78 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:16 PM PDT 24
Peak memory 269808 kb
Host smart-2c0e6183-6b95-4ea3-bdb5-a99b0f1e91cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094644511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2094644511
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3379166942
Short name T1464
Test name
Test status
Simulation time 9920715984 ps
CPU time 89.19 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:39:41 PM PDT 24
Peak memory 825380 kb
Host smart-5ed54375-2528-40a8-964d-d32c031c9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379166942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3379166942
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.621379447
Short name T1072
Test name
Test status
Simulation time 3196242387 ps
CPU time 58.25 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:39:11 PM PDT 24
Peak memory 592336 kb
Host smart-0767bc8e-9091-4691-ab9f-051814b11ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621379447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.621379447
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.4092905669
Short name T611
Test name
Test status
Simulation time 278626868 ps
CPU time 1.07 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 204784 kb
Host smart-45b0783c-a568-4b47-b4fc-d8a77bbe01c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092905669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.4092905669
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3137350763
Short name T443
Test name
Test status
Simulation time 141468676 ps
CPU time 3.76 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:17 PM PDT 24
Peak memory 229500 kb
Host smart-932cdeb7-1293-4498-a7c9-68a57bdcfbe1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137350763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3137350763
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1365005685
Short name T1073
Test name
Test status
Simulation time 11263696179 ps
CPU time 198.75 seconds
Started Jun 05 04:38:08 PM PDT 24
Finished Jun 05 04:41:28 PM PDT 24
Peak memory 878392 kb
Host smart-259b0caa-6f29-4b23-867a-839ce3bf6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365005685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1365005685
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1019561292
Short name T659
Test name
Test status
Simulation time 1655738786 ps
CPU time 5.56 seconds
Started Jun 05 04:38:20 PM PDT 24
Finished Jun 05 04:38:26 PM PDT 24
Peak memory 205020 kb
Host smart-dcf45f59-8bbd-4478-aea7-61eb68bef97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019561292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1019561292
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2049379826
Short name T44
Test name
Test status
Simulation time 1448687917 ps
CPU time 20.42 seconds
Started Jun 05 04:38:08 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 244604 kb
Host smart-bb78d11d-a194-48b3-a7ea-94829fc7add3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049379826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2049379826
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1848706556
Short name T1411
Test name
Test status
Simulation time 32073749 ps
CPU time 0.66 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 204712 kb
Host smart-865a7851-7c83-4106-ad9d-550e1c96d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848706556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1848706556
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3567081587
Short name T39
Test name
Test status
Simulation time 3136303071 ps
CPU time 14.21 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 347224 kb
Host smart-d6480d14-cf08-49d8-87ee-cec2ed9db5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567081587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3567081587
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1054310039
Short name T793
Test name
Test status
Simulation time 6539350470 ps
CPU time 33.29 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:44 PM PDT 24
Peak memory 359336 kb
Host smart-fd182f88-c4b0-4352-b6c5-c4217073d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054310039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1054310039
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2047205007
Short name T272
Test name
Test status
Simulation time 2195706060 ps
CPU time 40.99 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:51 PM PDT 24
Peak memory 213360 kb
Host smart-bdbdafba-ced2-4451-9a62-7be9a341d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047205007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2047205007
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3047627392
Short name T803
Test name
Test status
Simulation time 1140300580 ps
CPU time 4.24 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 205124 kb
Host smart-3f888b84-7c75-47d3-a011-d114aa85b417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047627392 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3047627392
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.659547591
Short name T1434
Test name
Test status
Simulation time 10346153102 ps
CPU time 10.15 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 230432 kb
Host smart-9922f9b6-3a83-4f5a-a734-26fe6bebdc61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659547591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.659547591
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3592801684
Short name T440
Test name
Test status
Simulation time 10156443148 ps
CPU time 67.8 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:39:20 PM PDT 24
Peak memory 490596 kb
Host smart-f28171a7-821a-4061-ad17-420ee1343cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592801684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3592801684
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.4229690005
Short name T478
Test name
Test status
Simulation time 1165384355 ps
CPU time 5.56 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 205248 kb
Host smart-45a7904d-1cb6-442d-925a-3131ddeb01ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229690005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.4229690005
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2045984540
Short name T710
Test name
Test status
Simulation time 1026196144 ps
CPU time 6.22 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:20 PM PDT 24
Peak memory 205068 kb
Host smart-e56896ec-f4f1-4795-bada-e131e16bf384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045984540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2045984540
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1877140691
Short name T1081
Test name
Test status
Simulation time 539233939 ps
CPU time 3.31 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 205056 kb
Host smart-854c03c6-184b-4b78-a1c1-362adea6e6bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877140691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1877140691
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2742919998
Short name T1040
Test name
Test status
Simulation time 926151119 ps
CPU time 4.57 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 205092 kb
Host smart-fee166c9-af2e-4d94-979a-2dfab51b6c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742919998 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2742919998
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1455856751
Short name T709
Test name
Test status
Simulation time 14989185349 ps
CPU time 4.84 seconds
Started Jun 05 04:38:07 PM PDT 24
Finished Jun 05 04:38:12 PM PDT 24
Peak memory 205188 kb
Host smart-e71d1822-82ee-4820-84d8-0f87e334747f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455856751 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1455856751
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3199737835
Short name T590
Test name
Test status
Simulation time 2563512193 ps
CPU time 10.58 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:20 PM PDT 24
Peak memory 205304 kb
Host smart-26be5df9-876a-4f52-9c1a-f3a9658f5f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199737835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3199737835
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1577796003
Short name T1334
Test name
Test status
Simulation time 2125915680 ps
CPU time 23.95 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:38 PM PDT 24
Peak memory 224940 kb
Host smart-e27be589-040c-40a8-a5f5-3258feaf823f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577796003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1577796003
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2596919237
Short name T614
Test name
Test status
Simulation time 28334612693 ps
CPU time 24.51 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 546052 kb
Host smart-0f6227d0-a54a-4c24-8186-e218481ff0a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596919237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2596919237
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.981483721
Short name T376
Test name
Test status
Simulation time 30324397529 ps
CPU time 614.57 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:48:27 PM PDT 24
Peak memory 1744100 kb
Host smart-5df71012-b15c-4dbf-ba09-3f399d7202a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981483721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.981483721
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1375139322
Short name T492
Test name
Test status
Simulation time 1358174693 ps
CPU time 7.39 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 213320 kb
Host smart-fdc2e571-a836-4e20-95f6-170bfda74b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375139322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1375139322
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3869824169
Short name T410
Test name
Test status
Simulation time 82966897 ps
CPU time 0.61 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 204672 kb
Host smart-3dc142d4-0ef2-4fbc-a4bf-1535b3fe7257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869824169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3869824169
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2999695855
Short name T635
Test name
Test status
Simulation time 108376124 ps
CPU time 2.58 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:18 PM PDT 24
Peak memory 213036 kb
Host smart-92941713-bd3f-4da5-aecb-b0f3d5690413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999695855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2999695855
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2425453680
Short name T881
Test name
Test status
Simulation time 184931146 ps
CPU time 9.2 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:22 PM PDT 24
Peak memory 233408 kb
Host smart-5b896cef-5aa2-4bd2-878e-52c288242ac7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425453680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2425453680
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3447698126
Short name T638
Test name
Test status
Simulation time 2993582414 ps
CPU time 102.21 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:39:57 PM PDT 24
Peak memory 921536 kb
Host smart-ee225fdc-a861-49ab-a5b5-b8cab1f108f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447698126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3447698126
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1534680172
Short name T789
Test name
Test status
Simulation time 4694969315 ps
CPU time 85.67 seconds
Started Jun 05 04:38:25 PM PDT 24
Finished Jun 05 04:39:51 PM PDT 24
Peak memory 506612 kb
Host smart-da304f5d-7bf6-4511-a6b1-052212913238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534680172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1534680172
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1399175086
Short name T1396
Test name
Test status
Simulation time 70900249 ps
CPU time 1 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 204968 kb
Host smart-aed451f5-c26a-4a2f-9832-1a90cd8212dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399175086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1399175086
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1906310534
Short name T526
Test name
Test status
Simulation time 245383049 ps
CPU time 5.57 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:28 PM PDT 24
Peak memory 250764 kb
Host smart-f336f99b-b345-4928-beab-7cbe8cf7b461
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906310534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1906310534
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1667302751
Short name T539
Test name
Test status
Simulation time 3982498781 ps
CPU time 307.69 seconds
Started Jun 05 04:38:09 PM PDT 24
Finished Jun 05 04:43:18 PM PDT 24
Peak memory 1173120 kb
Host smart-2990de5b-1fe6-48fb-a952-fcd509b180a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667302751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1667302751
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.27249859
Short name T444
Test name
Test status
Simulation time 570002488 ps
CPU time 7.98 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 205012 kb
Host smart-79c1bd50-8ab8-4310-a111-5c7571b707ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27249859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.27249859
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2052299203
Short name T1443
Test name
Test status
Simulation time 2089724444 ps
CPU time 43.23 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 390344 kb
Host smart-e2f3af5d-7fbe-48ee-b6aa-9222e62ce373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052299203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2052299203
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3941716700
Short name T145
Test name
Test status
Simulation time 28476746 ps
CPU time 0.68 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 204756 kb
Host smart-9589b1ca-3bdf-420d-b0cd-ae83c39c505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941716700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3941716700
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.271512552
Short name T238
Test name
Test status
Simulation time 49449106483 ps
CPU time 254.31 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:42:28 PM PDT 24
Peak memory 282516 kb
Host smart-9134a26e-4b1e-4db5-a039-119aa036c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271512552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.271512552
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2643791740
Short name T672
Test name
Test status
Simulation time 1506265235 ps
CPU time 78.54 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:39:35 PM PDT 24
Peak memory 381084 kb
Host smart-3a78b176-e1b2-451d-be36-0cc87b5fcf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643791740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2643791740
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1969788032
Short name T129
Test name
Test status
Simulation time 61881088464 ps
CPU time 327.11 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:43:40 PM PDT 24
Peak memory 767780 kb
Host smart-b033ceac-7102-4e55-b7ac-f320984fa024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969788032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1969788032
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3731228911
Short name T1207
Test name
Test status
Simulation time 1254539989 ps
CPU time 29.42 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:44 PM PDT 24
Peak memory 213276 kb
Host smart-ad162126-7dd9-4358-9349-bf35c7e2c2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731228911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3731228911
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1893415614
Short name T1276
Test name
Test status
Simulation time 3043380400 ps
CPU time 4.89 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 213332 kb
Host smart-ac0e3665-8b2e-4bd4-9b00-f6a3d5439b47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893415614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1893415614
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.610486948
Short name T92
Test name
Test status
Simulation time 10312871670 ps
CPU time 15.15 seconds
Started Jun 05 04:38:16 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 241632 kb
Host smart-07ed5103-68e5-4b25-9030-4a195c2aa393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610486948 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.610486948
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.267267528
Short name T512
Test name
Test status
Simulation time 10151480381 ps
CPU time 65.88 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:39:21 PM PDT 24
Peak memory 626112 kb
Host smart-490111f4-784d-47e2-9ea7-ac76ad3092f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267267528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.267267528
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3863326226
Short name T456
Test name
Test status
Simulation time 1122295271 ps
CPU time 4.7 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:18 PM PDT 24
Peak memory 205076 kb
Host smart-4268dc59-6805-42cb-b75b-53390b10157f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863326226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3863326226
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1647301895
Short name T1467
Test name
Test status
Simulation time 1377709867 ps
CPU time 2.11 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:15 PM PDT 24
Peak memory 205052 kb
Host smart-8392c0dd-4c8a-4214-8cb8-dfd2f8f0bc5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647301895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1647301895
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.4042477122
Short name T28
Test name
Test status
Simulation time 336703361 ps
CPU time 2.37 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:17 PM PDT 24
Peak memory 205016 kb
Host smart-7315b5ce-74e0-4767-8174-22f9544b790c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042477122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.4042477122
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3229466637
Short name T829
Test name
Test status
Simulation time 4613392990 ps
CPU time 6.18 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 213416 kb
Host smart-4af11a4d-3401-441d-836c-a286fd2c6b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229466637 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3229466637
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1823443440
Short name T905
Test name
Test status
Simulation time 16589850697 ps
CPU time 35 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 647888 kb
Host smart-3b3f02e1-d3da-4ac1-b561-250c2643ecf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823443440 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1823443440
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1540889302
Short name T1113
Test name
Test status
Simulation time 759389362 ps
CPU time 10.09 seconds
Started Jun 05 04:38:10 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 205076 kb
Host smart-aaf7e404-7d0b-4300-b7a8-1d5ebe6408d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540889302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1540889302
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4206229319
Short name T1220
Test name
Test status
Simulation time 1599920089 ps
CPU time 34.4 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:50 PM PDT 24
Peak memory 205052 kb
Host smart-bb009fad-6d37-4d01-acfd-3b4e9f0a8c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206229319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4206229319
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3114908381
Short name T149
Test name
Test status
Simulation time 64728413747 ps
CPU time 305.73 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:43:22 PM PDT 24
Peak memory 2836168 kb
Host smart-5b52fe0a-db5b-4369-b213-9b9e1c1f890a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114908381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3114908381
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1408463839
Short name T461
Test name
Test status
Simulation time 18675850584 ps
CPU time 730.04 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:50:32 PM PDT 24
Peak memory 3815240 kb
Host smart-700c2711-79af-447c-b92b-2065c0c20bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408463839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1408463839
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2909933661
Short name T1363
Test name
Test status
Simulation time 1527411159 ps
CPU time 7.11 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:22 PM PDT 24
Peak memory 213324 kb
Host smart-a987429e-bf50-4fba-ae4b-5e34af02d616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909933661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2909933661
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1459137623
Short name T1388
Test name
Test status
Simulation time 1192246691 ps
CPU time 16.29 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 205076 kb
Host smart-d0dcbe70-b25e-45cc-a423-816e6362490c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459137623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1459137623
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3197372088
Short name T555
Test name
Test status
Simulation time 19594898 ps
CPU time 0.64 seconds
Started Jun 05 04:34:47 PM PDT 24
Finished Jun 05 04:34:49 PM PDT 24
Peak memory 204756 kb
Host smart-67360c03-271a-41b5-8ed0-51bbd00d3cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197372088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3197372088
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.444476136
Short name T357
Test name
Test status
Simulation time 807066411 ps
CPU time 3.26 seconds
Started Jun 05 04:34:48 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 213296 kb
Host smart-dc88a5b1-faa2-40d1-aef2-0c616c28823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444476136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.444476136
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2433262793
Short name T820
Test name
Test status
Simulation time 841470778 ps
CPU time 7.27 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 266008 kb
Host smart-a2f35fd9-33c4-4417-9085-31659d9e666c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433262793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2433262793
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1474806790
Short name T1458
Test name
Test status
Simulation time 2218605526 ps
CPU time 70.26 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:35:51 PM PDT 24
Peak memory 754156 kb
Host smart-8071d827-951d-4640-9d43-9cdfca870b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474806790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1474806790
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2889873138
Short name T1105
Test name
Test status
Simulation time 2696179368 ps
CPU time 95.42 seconds
Started Jun 05 04:35:13 PM PDT 24
Finished Jun 05 04:36:49 PM PDT 24
Peak memory 791672 kb
Host smart-6e6c37d7-3ce3-401f-a27f-0a0ca98c39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889873138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2889873138
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.20898449
Short name T325
Test name
Test status
Simulation time 340857161 ps
CPU time 1.05 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:01 PM PDT 24
Peak memory 204936 kb
Host smart-55d467be-0454-4d7e-a93d-9e84bc415b60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.20898449
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2392710628
Short name T380
Test name
Test status
Simulation time 215200556 ps
CPU time 11.11 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:50 PM PDT 24
Peak memory 205032 kb
Host smart-25ee2ff0-b44a-46ba-8c91-6cbcfdaecc02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392710628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2392710628
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1069991851
Short name T110
Test name
Test status
Simulation time 13836575780 ps
CPU time 84.46 seconds
Started Jun 05 04:34:56 PM PDT 24
Finished Jun 05 04:36:21 PM PDT 24
Peak memory 999636 kb
Host smart-5c0ede24-f2cb-434d-8ce5-84c59500ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069991851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1069991851
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2366361274
Short name T739
Test name
Test status
Simulation time 2738288867 ps
CPU time 5.72 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 205100 kb
Host smart-0a830aa1-5207-440b-94c6-858606d6214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366361274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2366361274
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1005480806
Short name T322
Test name
Test status
Simulation time 5378898803 ps
CPU time 67.81 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:35:55 PM PDT 24
Peak memory 335564 kb
Host smart-7a277742-1fae-44fa-8359-5eb47892d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005480806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1005480806
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.329701475
Short name T1386
Test name
Test status
Simulation time 19393253 ps
CPU time 0.69 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 204716 kb
Host smart-010d2370-495e-4ce1-aec1-774818c0880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329701475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.329701475
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2692018758
Short name T521
Test name
Test status
Simulation time 51263178112 ps
CPU time 240.22 seconds
Started Jun 05 04:34:42 PM PDT 24
Finished Jun 05 04:38:43 PM PDT 24
Peak memory 205184 kb
Host smart-c7ba258e-34ec-4e82-b2fb-45c28c930a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692018758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2692018758
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.766659414
Short name T299
Test name
Test status
Simulation time 2763744985 ps
CPU time 100.35 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:36:26 PM PDT 24
Peak memory 363100 kb
Host smart-2fa4d19d-128c-4867-aa01-9d8d8208b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766659414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.766659414
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2763441058
Short name T654
Test name
Test status
Simulation time 491788175 ps
CPU time 9.91 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 221304 kb
Host smart-3a2facf5-3ab5-40d7-a674-b513f16231e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763441058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2763441058
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2445593826
Short name T189
Test name
Test status
Simulation time 200950765 ps
CPU time 0.92 seconds
Started Jun 05 04:34:38 PM PDT 24
Finished Jun 05 04:34:40 PM PDT 24
Peak memory 221960 kb
Host smart-2fb5ca8b-cc8e-476f-a593-2c0d5569b822
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445593826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2445593826
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2996054577
Short name T34
Test name
Test status
Simulation time 12911110848 ps
CPU time 5.16 seconds
Started Jun 05 04:34:47 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 212364 kb
Host smart-d343c115-1284-4c0f-a6ed-c0838155fcb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996054577 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2996054577
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.491564200
Short name T1364
Test name
Test status
Simulation time 10098838010 ps
CPU time 12.33 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 279312 kb
Host smart-3db8e478-3966-4760-9702-8f6b4c7aaf12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491564200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.491564200
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3906585597
Short name T812
Test name
Test status
Simulation time 10238410002 ps
CPU time 34.8 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:33 PM PDT 24
Peak memory 442112 kb
Host smart-cddf92d1-0460-4189-9875-3b798b93bde6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906585597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3906585597
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.1210336425
Short name T1110
Test name
Test status
Simulation time 1242229878 ps
CPU time 5.54 seconds
Started Jun 05 04:34:44 PM PDT 24
Finished Jun 05 04:34:51 PM PDT 24
Peak memory 205032 kb
Host smart-918e7a37-9a81-4d59-a3c7-0163513b9a74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210336425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.1210336425
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2419592442
Short name T1053
Test name
Test status
Simulation time 1187703525 ps
CPU time 3.19 seconds
Started Jun 05 04:34:48 PM PDT 24
Finished Jun 05 04:34:52 PM PDT 24
Peak memory 205076 kb
Host smart-2f0120c5-7b5e-4b69-af12-a0c29feadd8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419592442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2419592442
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2567630677
Short name T12
Test name
Test status
Simulation time 284671019 ps
CPU time 2.13 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:00 PM PDT 24
Peak memory 205076 kb
Host smart-b1f32a38-aa24-405e-a52d-ce13b030f73e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567630677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2567630677
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3208280824
Short name T1186
Test name
Test status
Simulation time 610717060 ps
CPU time 3.53 seconds
Started Jun 05 04:34:47 PM PDT 24
Finished Jun 05 04:34:51 PM PDT 24
Peak memory 205148 kb
Host smart-563e35f9-3edd-4b7d-8962-19c6567d843f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208280824 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3208280824
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3048620595
Short name T148
Test name
Test status
Simulation time 4642952921 ps
CPU time 3.47 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:01 PM PDT 24
Peak memory 205116 kb
Host smart-67f60000-b1fb-4980-92cf-eb6a69452c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048620595 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3048620595
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2426400043
Short name T178
Test name
Test status
Simulation time 1094586521 ps
CPU time 40.63 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 205092 kb
Host smart-ebb3ddb9-3a7c-4ad0-b422-17246b4369f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426400043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2426400043
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3070391025
Short name T1173
Test name
Test status
Simulation time 509235376 ps
CPU time 19.6 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 205056 kb
Host smart-26946733-5fd8-4514-8dcf-f105c16983c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070391025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3070391025
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2391895734
Short name T1466
Test name
Test status
Simulation time 10391948551 ps
CPU time 20.2 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:35:10 PM PDT 24
Peak memory 205316 kb
Host smart-8e3b2d9a-4433-41fd-8e90-664f8c291bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391895734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2391895734
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.914235073
Short name T1008
Test name
Test status
Simulation time 30555644242 ps
CPU time 2501.73 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 05:16:21 PM PDT 24
Peak memory 7393392 kb
Host smart-d9645985-a870-48b7-bf87-07e8f42109d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914235073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.914235073
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2580680842
Short name T1056
Test name
Test status
Simulation time 2956643876 ps
CPU time 7.72 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:07 PM PDT 24
Peak memory 215384 kb
Host smart-7ce71f44-0b5b-481f-a87f-09e364c72a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580680842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2580680842
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.3426466894
Short name T403
Test name
Test status
Simulation time 1326077930 ps
CPU time 18.25 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 205060 kb
Host smart-73ac6930-36ca-4ec7-a154-0ef554dae09b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426466894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.3426466894
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1601448874
Short name T1290
Test name
Test status
Simulation time 34251464 ps
CPU time 0.61 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 204764 kb
Host smart-a03b8110-0102-4aac-99c5-aa9e266440c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601448874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1601448874
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2109859246
Short name T1216
Test name
Test status
Simulation time 81271414 ps
CPU time 1.88 seconds
Started Jun 05 04:38:16 PM PDT 24
Finished Jun 05 04:38:19 PM PDT 24
Peak memory 213316 kb
Host smart-1efdb116-9c69-44a0-ad91-fb5124687bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109859246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2109859246
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3469557500
Short name T7
Test name
Test status
Simulation time 4806237919 ps
CPU time 5.62 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:20 PM PDT 24
Peak memory 252892 kb
Host smart-72e6546a-d297-41e8-b9ea-08dc61647dc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469557500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3469557500
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2751573896
Short name T961
Test name
Test status
Simulation time 1632547792 ps
CPU time 113.4 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:40:09 PM PDT 24
Peak memory 534488 kb
Host smart-9bed6797-3122-4ce3-bfad-649b4038ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751573896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2751573896
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.725088997
Short name T62
Test name
Test status
Simulation time 78939749 ps
CPU time 0.81 seconds
Started Jun 05 04:38:11 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 204780 kb
Host smart-2842adea-6403-42be-a112-10818e6f1aa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725088997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.725088997
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1369439657
Short name T998
Test name
Test status
Simulation time 346907098 ps
CPU time 5.56 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 237492 kb
Host smart-add673b2-a9da-4114-b5dd-2b2c519ac56a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369439657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1369439657
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.398693487
Short name T1484
Test name
Test status
Simulation time 4298603638 ps
CPU time 326.87 seconds
Started Jun 05 04:38:12 PM PDT 24
Finished Jun 05 04:43:40 PM PDT 24
Peak memory 1231600 kb
Host smart-61c5989a-846b-4110-a25f-02a95a3a3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398693487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.398693487
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.4060357673
Short name T55
Test name
Test status
Simulation time 250571401 ps
CPU time 9.86 seconds
Started Jun 05 04:38:23 PM PDT 24
Finished Jun 05 04:38:34 PM PDT 24
Peak memory 205020 kb
Host smart-1eb77fff-6488-4836-b1f0-33412de6bbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060357673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.4060357673
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1627734595
Short name T1265
Test name
Test status
Simulation time 6575968997 ps
CPU time 33.14 seconds
Started Jun 05 04:38:23 PM PDT 24
Finished Jun 05 04:38:57 PM PDT 24
Peak memory 374188 kb
Host smart-06a25feb-ffd8-43ff-bb06-7ff3d49f1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627734595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1627734595
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3294555022
Short name T1145
Test name
Test status
Simulation time 27126218 ps
CPU time 0.68 seconds
Started Jun 05 04:38:15 PM PDT 24
Finished Jun 05 04:38:17 PM PDT 24
Peak memory 204892 kb
Host smart-a40b0d4b-6731-4506-86e5-4a616a6475d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294555022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3294555022
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2536913444
Short name T924
Test name
Test status
Simulation time 4967798274 ps
CPU time 53.26 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 259632 kb
Host smart-9bb29834-fce1-4ed3-a5c7-a7fb8ef7f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536913444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2536913444
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1287767738
Short name T787
Test name
Test status
Simulation time 4949230830 ps
CPU time 54.75 seconds
Started Jun 05 04:38:16 PM PDT 24
Finished Jun 05 04:39:11 PM PDT 24
Peak memory 368748 kb
Host smart-40852d29-329c-4874-892f-846f1a6f2532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287767738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1287767738
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.93736005
Short name T268
Test name
Test status
Simulation time 23725843139 ps
CPU time 2237.78 seconds
Started Jun 05 04:38:14 PM PDT 24
Finished Jun 05 05:15:34 PM PDT 24
Peak memory 1630704 kb
Host smart-194f378c-e4a8-4a67-8fec-ab971aeea355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93736005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.93736005
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1217168581
Short name T1493
Test name
Test status
Simulation time 4314491335 ps
CPU time 9.91 seconds
Started Jun 05 04:38:13 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 218332 kb
Host smart-1e255947-1820-4c66-b1c1-e71bfdbffef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217168581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1217168581
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1304795496
Short name T487
Test name
Test status
Simulation time 600801057 ps
CPU time 3.72 seconds
Started Jun 05 04:38:20 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 213332 kb
Host smart-ce375ae8-844a-4cc0-a97d-03def737830c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304795496 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1304795496
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1038141041
Short name T1471
Test name
Test status
Simulation time 10275623867 ps
CPU time 9.18 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 240476 kb
Host smart-e57eeed4-9ad6-4753-a41c-b2274fcf7950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038141041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1038141041
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3597848908
Short name T686
Test name
Test status
Simulation time 10105224079 ps
CPU time 72.06 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:39:35 PM PDT 24
Peak memory 674656 kb
Host smart-b5b99d68-26a2-4a45-ac99-b3b409acbd54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597848908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3597848908
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.35520473
Short name T366
Test name
Test status
Simulation time 4319204698 ps
CPU time 2.03 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:25 PM PDT 24
Peak memory 205180 kb
Host smart-e631602c-257e-4880-a489-1a3c33cd2a0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520473 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.35520473
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.283456174
Short name T651
Test name
Test status
Simulation time 1064282182 ps
CPU time 5.28 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:34 PM PDT 24
Peak memory 205076 kb
Host smart-cf5d9f58-03b4-409e-9f88-7737b354cbf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283456174 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.283456174
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1102335669
Short name T1034
Test name
Test status
Simulation time 767236761 ps
CPU time 2.64 seconds
Started Jun 05 04:38:20 PM PDT 24
Finished Jun 05 04:38:24 PM PDT 24
Peak memory 205088 kb
Host smart-53ab9197-6054-4b34-8322-d5428976e3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102335669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1102335669
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1658793944
Short name T298
Test name
Test status
Simulation time 576754513 ps
CPU time 3.41 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:26 PM PDT 24
Peak memory 205136 kb
Host smart-680ce7d4-dc40-4787-a024-5b65a0cbde99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658793944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1658793944
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.284257745
Short name T1032
Test name
Test status
Simulation time 27056620699 ps
CPU time 81.87 seconds
Started Jun 05 04:38:20 PM PDT 24
Finished Jun 05 04:39:43 PM PDT 24
Peak memory 1461476 kb
Host smart-ec081b76-520f-4399-9cce-5adf4ccbf295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284257745 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.284257745
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1632575322
Short name T37
Test name
Test status
Simulation time 824751872 ps
CPU time 13.07 seconds
Started Jun 05 04:38:16 PM PDT 24
Finished Jun 05 04:38:29 PM PDT 24
Peak memory 205116 kb
Host smart-e7210884-bfc3-4c32-8798-e6276b9d4349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632575322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1632575322
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3686207800
Short name T411
Test name
Test status
Simulation time 11323873056 ps
CPU time 15.61 seconds
Started Jun 05 04:38:18 PM PDT 24
Finished Jun 05 04:38:34 PM PDT 24
Peak memory 213320 kb
Host smart-f04134b0-0add-4d8d-a61e-fc2775429d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686207800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3686207800
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4075298179
Short name T297
Test name
Test status
Simulation time 7006263335 ps
CPU time 7.61 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:29 PM PDT 24
Peak memory 205100 kb
Host smart-4d8f64dc-038f-4093-927d-a9005a0b64f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075298179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4075298179
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2605105005
Short name T791
Test name
Test status
Simulation time 22465228501 ps
CPU time 1370.01 seconds
Started Jun 05 04:38:19 PM PDT 24
Finished Jun 05 05:01:10 PM PDT 24
Peak memory 2809196 kb
Host smart-68f316a5-017a-4503-b3b7-bd5d11f8b61e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605105005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2605105005
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1737578710
Short name T150
Test name
Test status
Simulation time 5633010074 ps
CPU time 7.31 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 211368 kb
Host smart-92674415-60ff-4ccd-90a6-5f5688136036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737578710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1737578710
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.4071899756
Short name T1426
Test name
Test status
Simulation time 1034477878 ps
CPU time 16.79 seconds
Started Jun 05 04:38:20 PM PDT 24
Finished Jun 05 04:38:38 PM PDT 24
Peak memory 205120 kb
Host smart-aa91a131-355a-442d-ad56-450906bdcde8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071899756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.4071899756
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2321299924
Short name T593
Test name
Test status
Simulation time 200058602 ps
CPU time 0.62 seconds
Started Jun 05 04:38:26 PM PDT 24
Finished Jun 05 04:38:27 PM PDT 24
Peak memory 204724 kb
Host smart-666e2e44-3bef-4a23-bc8e-42109fb54d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321299924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2321299924
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1060628346
Short name T1427
Test name
Test status
Simulation time 3549064788 ps
CPU time 13.69 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:37 PM PDT 24
Peak memory 252004 kb
Host smart-b746101b-4713-4bd5-b4f5-f9bccaa09253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060628346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1060628346
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1362294965
Short name T284
Test name
Test status
Simulation time 2226700927 ps
CPU time 31.01 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:53 PM PDT 24
Peak memory 327188 kb
Host smart-18e6aa7a-c380-479e-88cc-93a26845e58b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362294965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1362294965
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.933034125
Short name T1263
Test name
Test status
Simulation time 1438914559 ps
CPU time 46.81 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:39:09 PM PDT 24
Peak memory 559664 kb
Host smart-103a123e-fa29-403f-bee0-6b273d342eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933034125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.933034125
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.778788994
Short name T1162
Test name
Test status
Simulation time 5769752363 ps
CPU time 41.17 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:39:03 PM PDT 24
Peak memory 517296 kb
Host smart-1336d1ef-8203-4c73-b317-7df772829ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778788994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.778788994
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2889301752
Short name T1326
Test name
Test status
Simulation time 488011453 ps
CPU time 0.99 seconds
Started Jun 05 04:38:19 PM PDT 24
Finished Jun 05 04:38:21 PM PDT 24
Peak memory 204788 kb
Host smart-9886611b-efd2-4798-81c0-7efa0d11f1a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889301752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2889301752
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2162004377
Short name T960
Test name
Test status
Simulation time 2668684911 ps
CPU time 7.45 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 205076 kb
Host smart-f1828c5c-3a26-423c-8820-0d7b697f5553
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162004377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2162004377
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.3406204737
Short name T151
Test name
Test status
Simulation time 4594763295 ps
CPU time 147.84 seconds
Started Jun 05 04:38:24 PM PDT 24
Finished Jun 05 04:40:52 PM PDT 24
Peak memory 1268412 kb
Host smart-a69214e6-e1c9-4ea1-9333-ba3911d682d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406204737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.3406204737
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.832186350
Short name T563
Test name
Test status
Simulation time 724833241 ps
CPU time 3.24 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 205024 kb
Host smart-83ea4158-b95a-49fe-8a28-3844d509be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832186350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.832186350
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2215116768
Short name T1385
Test name
Test status
Simulation time 28781341012 ps
CPU time 27.99 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 349120 kb
Host smart-f7aca3bc-35c5-4bf5-ae9f-2481296bb9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215116768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2215116768
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1701926943
Short name T809
Test name
Test status
Simulation time 59334478 ps
CPU time 0.69 seconds
Started Jun 05 04:38:19 PM PDT 24
Finished Jun 05 04:38:20 PM PDT 24
Peak memory 204684 kb
Host smart-ac211dc6-cd20-4763-bb24-d42f2037d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701926943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1701926943
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.214890061
Short name T1475
Test name
Test status
Simulation time 3440357944 ps
CPU time 53.45 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 520120 kb
Host smart-f979e275-7364-41b5-b49c-ba3e01b0c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214890061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.214890061
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1861924686
Short name T967
Test name
Test status
Simulation time 2128732315 ps
CPU time 97.6 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:40:00 PM PDT 24
Peak memory 454328 kb
Host smart-2aabac2d-de00-446b-a813-667d44f9311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861924686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1861924686
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2012567173
Short name T122
Test name
Test status
Simulation time 33277710258 ps
CPU time 380.77 seconds
Started Jun 05 04:38:24 PM PDT 24
Finished Jun 05 04:44:46 PM PDT 24
Peak memory 1666516 kb
Host smart-219533ec-bdcf-480c-8209-3231df050143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012567173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2012567173
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2264751035
Short name T1245
Test name
Test status
Simulation time 659198208 ps
CPU time 12.33 seconds
Started Jun 05 04:38:21 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 221424 kb
Host smart-26560c45-0c9c-438c-be6b-de02de4d49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264751035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2264751035
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3251536783
Short name T690
Test name
Test status
Simulation time 4037394759 ps
CPU time 3.48 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 205208 kb
Host smart-03db2952-7c8a-4137-84db-27cb82b39f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251536783 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3251536783
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3014479829
Short name T1501
Test name
Test status
Simulation time 11366685449 ps
CPU time 3.73 seconds
Started Jun 05 04:38:31 PM PDT 24
Finished Jun 05 04:38:36 PM PDT 24
Peak memory 213844 kb
Host smart-38ab37ce-d823-4f33-82d1-7baa3ca8b594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014479829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3014479829
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.650325265
Short name T1244
Test name
Test status
Simulation time 10138721237 ps
CPU time 34.47 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:39:04 PM PDT 24
Peak memory 384788 kb
Host smart-d59cd56f-b5f2-43e8-ba10-0b73dca6b168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650325265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.650325265
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1943062644
Short name T1275
Test name
Test status
Simulation time 2293340707 ps
CPU time 2.76 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:38:43 PM PDT 24
Peak memory 204900 kb
Host smart-79d36a13-68a9-4db4-ac83-5cdb0bda7d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943062644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1943062644
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3427636214
Short name T350
Test name
Test status
Simulation time 1097747443 ps
CPU time 6.03 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 205132 kb
Host smart-ca2e2581-5487-4c88-ab31-e34c58450bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427636214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3427636214
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2673725161
Short name T31
Test name
Test status
Simulation time 1389556335 ps
CPU time 2.25 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:38:42 PM PDT 24
Peak memory 204812 kb
Host smart-3fe25200-4a84-4713-9eed-00332094f908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673725161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2673725161
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1996484139
Short name T27
Test name
Test status
Simulation time 4418849416 ps
CPU time 5.17 seconds
Started Jun 05 04:38:27 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 205084 kb
Host smart-13af59cb-9777-4c0b-b768-0d9f0a12cd17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996484139 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1996484139
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2740854517
Short name T132
Test name
Test status
Simulation time 18990288006 ps
CPU time 393.87 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:45:03 PM PDT 24
Peak memory 4532416 kb
Host smart-9c003207-7062-4e19-a58e-0d79fbf35bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740854517 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2740854517
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.963814179
Short name T1422
Test name
Test status
Simulation time 1836753024 ps
CPU time 14.15 seconds
Started Jun 05 04:38:26 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 205100 kb
Host smart-098e7365-d63a-48ba-be82-50720c6021ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963814179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.963814179
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1754171196
Short name T880
Test name
Test status
Simulation time 1221885566 ps
CPU time 21.91 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:51 PM PDT 24
Peak memory 222900 kb
Host smart-cc4cb3b6-4857-491d-a6b6-05cff547fadc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754171196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1754171196
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.882319199
Short name T1497
Test name
Test status
Simulation time 10960009194 ps
CPU time 6.85 seconds
Started Jun 05 04:38:22 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 205180 kb
Host smart-b14506ec-a736-4711-bfd4-024ec86cf1a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882319199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.882319199
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2467720137
Short name T433
Test name
Test status
Simulation time 10813365640 ps
CPU time 148.35 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:40:58 PM PDT 24
Peak memory 694792 kb
Host smart-d23d9d34-2bda-41d4-be34-6ca9e241c47a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467720137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2467720137
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.342459304
Short name T1333
Test name
Test status
Simulation time 2451473421 ps
CPU time 7.21 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 205164 kb
Host smart-5e669e60-398a-46fc-9534-08b2f7cb6d37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342459304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.342459304
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.2466616446
Short name T1339
Test name
Test status
Simulation time 1079781452 ps
CPU time 20.24 seconds
Started Jun 05 04:38:32 PM PDT 24
Finished Jun 05 04:38:53 PM PDT 24
Peak memory 205104 kb
Host smart-6e8b20f2-1aa8-4ab5-85cc-e98f88da6b5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466616446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.2466616446
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1199723694
Short name T186
Test name
Test status
Simulation time 25768121 ps
CPU time 0.65 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:39 PM PDT 24
Peak memory 204728 kb
Host smart-1bf78fd0-226e-4770-b104-c0cbfac94f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199723694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1199723694
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1187730962
Short name T861
Test name
Test status
Simulation time 346546160 ps
CPU time 5.17 seconds
Started Jun 05 04:38:26 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 229528 kb
Host smart-be0436c6-ef21-49e8-85fb-892a3b6b17c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187730962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1187730962
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.618998098
Short name T1117
Test name
Test status
Simulation time 1236061458 ps
CPU time 14.02 seconds
Started Jun 05 04:38:30 PM PDT 24
Finished Jun 05 04:38:45 PM PDT 24
Peak memory 247696 kb
Host smart-19acac7b-ddee-4203-9472-3ac1e2fa2f39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618998098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.618998098
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3863261426
Short name T498
Test name
Test status
Simulation time 13366003787 ps
CPU time 189.61 seconds
Started Jun 05 04:38:32 PM PDT 24
Finished Jun 05 04:41:42 PM PDT 24
Peak memory 802580 kb
Host smart-e7c0855f-3964-45c6-89ad-eb9a2c323720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863261426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3863261426
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.4279333125
Short name T396
Test name
Test status
Simulation time 1849141936 ps
CPU time 64.15 seconds
Started Jun 05 04:38:30 PM PDT 24
Finished Jun 05 04:39:35 PM PDT 24
Peak memory 657236 kb
Host smart-daefc53a-1612-4666-99b2-a2ad7d748bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279333125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.4279333125
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.198016426
Short name T702
Test name
Test status
Simulation time 125225980 ps
CPU time 0.94 seconds
Started Jun 05 04:38:25 PM PDT 24
Finished Jun 05 04:38:27 PM PDT 24
Peak memory 204748 kb
Host smart-89ed3ad9-2a57-4c8d-aa2f-e4ae73141f41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198016426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.198016426
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.771168809
Short name T1010
Test name
Test status
Simulation time 554914884 ps
CPU time 4.04 seconds
Started Jun 05 04:38:28 PM PDT 24
Finished Jun 05 04:38:32 PM PDT 24
Peak memory 226012 kb
Host smart-d356cd61-c74c-44fa-810c-f3f30efbb15a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771168809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
771168809
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.638935513
Short name T451
Test name
Test status
Simulation time 9580153133 ps
CPU time 365.04 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:44:45 PM PDT 24
Peak memory 1471716 kb
Host smart-12295c38-1f5d-4e15-97f4-710f40923cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638935513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.638935513
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.4192986610
Short name T170
Test name
Test status
Simulation time 492973898 ps
CPU time 10.56 seconds
Started Jun 05 04:38:38 PM PDT 24
Finished Jun 05 04:38:49 PM PDT 24
Peak memory 205036 kb
Host smart-986d4e88-e2a9-4aee-b60c-b4311ecb7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192986610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.4192986610
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.873743212
Short name T990
Test name
Test status
Simulation time 1993434281 ps
CPU time 39.18 seconds
Started Jun 05 04:38:38 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 380452 kb
Host smart-b0c9dd31-4fa4-4ea9-9944-82b158fde224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873743212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.873743212
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1364542287
Short name T1086
Test name
Test status
Simulation time 57387948 ps
CPU time 0.67 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:38:30 PM PDT 24
Peak memory 204656 kb
Host smart-b549811b-e9f0-4410-a962-28952bce57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364542287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1364542287
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2998635630
Short name T167
Test name
Test status
Simulation time 12831668819 ps
CPU time 281.72 seconds
Started Jun 05 04:38:26 PM PDT 24
Finished Jun 05 04:43:08 PM PDT 24
Peak memory 1611252 kb
Host smart-ff081d05-cf84-4b5a-84c1-09201911545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998635630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2998635630
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3777443107
Short name T722
Test name
Test status
Simulation time 1262003733 ps
CPU time 20.29 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 327764 kb
Host smart-245548a3-ec3b-4b04-9786-ee56b13e91a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777443107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3777443107
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2058211307
Short name T1004
Test name
Test status
Simulation time 19477010077 ps
CPU time 856.95 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:52:57 PM PDT 24
Peak memory 2780884 kb
Host smart-5ac6a830-d54e-4bea-87ad-e3d3dde27aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058211307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2058211307
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3387627880
Short name T935
Test name
Test status
Simulation time 542600177 ps
CPU time 24.64 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:38:54 PM PDT 24
Peak memory 213288 kb
Host smart-fc521442-142e-4420-ba79-1d6534cbed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387627880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3387627880
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.4139200971
Short name T669
Test name
Test status
Simulation time 3656989750 ps
CPU time 4.5 seconds
Started Jun 05 04:38:29 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 213368 kb
Host smart-2f75ec3e-fea1-4701-8700-07d150d88b5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139200971 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.4139200971
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2739835425
Short name T18
Test name
Test status
Simulation time 10721524849 ps
CPU time 5.53 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:38:45 PM PDT 24
Peak memory 217864 kb
Host smart-fcf0d030-e805-4881-b71e-30ec19169973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739835425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2739835425
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1614378187
Short name T866
Test name
Test status
Simulation time 10104653376 ps
CPU time 62.8 seconds
Started Jun 05 04:38:40 PM PDT 24
Finished Jun 05 04:39:44 PM PDT 24
Peak memory 610152 kb
Host smart-883f2c31-166d-40e5-8c72-3944dbd49e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614378187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1614378187
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.826033414
Short name T1051
Test name
Test status
Simulation time 1342883774 ps
CPU time 6.63 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:45 PM PDT 24
Peak memory 205080 kb
Host smart-cc5ab6e5-7afb-431c-8509-4981a539560b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826033414 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.826033414
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.137549958
Short name T701
Test name
Test status
Simulation time 1099868908 ps
CPU time 1.92 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:38:42 PM PDT 24
Peak memory 205076 kb
Host smart-2af694ca-2c44-475b-abce-9264da4750ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137549958 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.137549958
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1833329817
Short name T30
Test name
Test status
Simulation time 314512242 ps
CPU time 2.23 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 205076 kb
Host smart-236ce289-4f58-4f67-a6d0-a22b75950759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833329817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1833329817
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.486064655
Short name T38
Test name
Test status
Simulation time 4066378012 ps
CPU time 6.13 seconds
Started Jun 05 04:38:26 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 221312 kb
Host smart-1a7dd292-a74d-49ef-805c-5aa6f7fc7695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486064655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.486064655
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2167366097
Short name T159
Test name
Test status
Simulation time 15587319573 ps
CPU time 5.47 seconds
Started Jun 05 04:38:30 PM PDT 24
Finished Jun 05 04:38:36 PM PDT 24
Peak memory 205168 kb
Host smart-5134ef2a-d5c6-40ee-ae1e-70ee296463d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167366097 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2167366097
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2669508730
Short name T544
Test name
Test status
Simulation time 1000774526 ps
CPU time 16.87 seconds
Started Jun 05 04:38:32 PM PDT 24
Finished Jun 05 04:38:50 PM PDT 24
Peak memory 205016 kb
Host smart-69c4be60-4844-4598-b38f-41bbf8f1eef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669508730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2669508730
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.42209224
Short name T694
Test name
Test status
Simulation time 1668963654 ps
CPU time 26.77 seconds
Started Jun 05 04:38:30 PM PDT 24
Finished Jun 05 04:38:57 PM PDT 24
Peak memory 231528 kb
Host smart-d565efe4-f476-4596-a30a-21d177fd7280
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42209224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stress_rd.42209224
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.1533013940
Short name T666
Test name
Test status
Simulation time 9945700682 ps
CPU time 6.62 seconds
Started Jun 05 04:38:41 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 204872 kb
Host smart-ff4c2688-c633-4970-a169-65cc56811de8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533013940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.1533013940
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.985507219
Short name T897
Test name
Test status
Simulation time 17108852867 ps
CPU time 134.46 seconds
Started Jun 05 04:38:30 PM PDT 24
Finished Jun 05 04:40:45 PM PDT 24
Peak memory 639856 kb
Host smart-1ea7c435-1691-43bc-ae0a-610d38aee083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985507219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.985507219
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2989646747
Short name T879
Test name
Test status
Simulation time 2541519379 ps
CPU time 6.59 seconds
Started Jun 05 04:38:27 PM PDT 24
Finished Jun 05 04:38:35 PM PDT 24
Peak memory 205176 kb
Host smart-f642cdff-f9a6-4fce-bf44-63fb004c5f44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989646747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2989646747
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.3388344682
Short name T515
Test name
Test status
Simulation time 1044370833 ps
CPU time 19.07 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:38:56 PM PDT 24
Peak memory 205012 kb
Host smart-4af8662d-eabf-4ac1-a31c-5b6dadedcc09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388344682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3388344682
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3261557756
Short name T771
Test name
Test status
Simulation time 15939494 ps
CPU time 0.61 seconds
Started Jun 05 04:38:43 PM PDT 24
Finished Jun 05 04:38:44 PM PDT 24
Peak memory 204752 kb
Host smart-3e121c2c-f90b-41f2-8854-e375722bac24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261557756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3261557756
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4217799512
Short name T1139
Test name
Test status
Simulation time 1246925314 ps
CPU time 10.67 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 253712 kb
Host smart-6b7ec252-e749-4bb1-a4d3-e7ed7523c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217799512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4217799512
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1289108960
Short name T1222
Test name
Test status
Simulation time 870111985 ps
CPU time 23.4 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:39:02 PM PDT 24
Peak memory 294608 kb
Host smart-baeb12e3-9f48-4ca3-9639-401b6ec0bd75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289108960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1289108960
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1628668254
Short name T795
Test name
Test status
Simulation time 1577815146 ps
CPU time 47.68 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:39:25 PM PDT 24
Peak memory 441168 kb
Host smart-5e9a4524-c9da-4f80-8c42-ead230877024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628668254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1628668254
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.287530995
Short name T542
Test name
Test status
Simulation time 4315872493 ps
CPU time 169.54 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:41:28 PM PDT 24
Peak memory 710596 kb
Host smart-49070790-9309-473a-96bb-42af6a7d4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287530995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.287530995
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3751223036
Short name T945
Test name
Test status
Simulation time 271465168 ps
CPU time 1.06 seconds
Started Jun 05 04:38:41 PM PDT 24
Finished Jun 05 04:38:42 PM PDT 24
Peak memory 204896 kb
Host smart-37a84786-0beb-4960-8bbc-410e76f11d14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751223036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3751223036
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2002774702
Short name T1170
Test name
Test status
Simulation time 204942070 ps
CPU time 6.56 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:45 PM PDT 24
Peak memory 244704 kb
Host smart-bfb92840-db4c-4b1e-b38f-75d9e7de6a07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002774702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2002774702
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.685197778
Short name T987
Test name
Test status
Simulation time 10055519455 ps
CPU time 183.82 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:41:41 PM PDT 24
Peak memory 1461268 kb
Host smart-a376046c-5812-4bbf-a1ce-b87414308288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685197778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.685197778
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2426611091
Short name T1495
Test name
Test status
Simulation time 946090112 ps
CPU time 7.45 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 205028 kb
Host smart-aeae8dde-76c4-4f12-9abf-351a934f9fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426611091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2426611091
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1190328793
Short name T1232
Test name
Test status
Simulation time 7403480259 ps
CPU time 31.75 seconds
Started Jun 05 04:38:45 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 361844 kb
Host smart-79e39081-6c99-409e-a5ad-b79caffcd32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190328793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1190328793
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3224273433
Short name T972
Test name
Test status
Simulation time 96618989 ps
CPU time 0.69 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:38:40 PM PDT 24
Peak memory 204708 kb
Host smart-a227bb3e-cc10-4c0b-8fd2-c1be4ffc12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224273433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3224273433
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2388389762
Short name T1098
Test name
Test status
Simulation time 1484992553 ps
CPU time 76.26 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:39:53 PM PDT 24
Peak memory 373880 kb
Host smart-d243e92b-563a-46cf-bd33-9f1dd6d26c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388389762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2388389762
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.418104985
Short name T60
Test name
Test status
Simulation time 37927298010 ps
CPU time 813.76 seconds
Started Jun 05 04:38:42 PM PDT 24
Finished Jun 05 04:52:16 PM PDT 24
Peak memory 2509092 kb
Host smart-e6433b98-3dcd-4b64-87cf-c9a7f442aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418104985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.418104985
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3644642037
Short name T1012
Test name
Test status
Simulation time 2875275727 ps
CPU time 14.02 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:52 PM PDT 24
Peak memory 213376 kb
Host smart-1858f481-8341-40ee-9b99-28f5c05d0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644642037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3644642037
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2921549597
Short name T1217
Test name
Test status
Simulation time 10944662147 ps
CPU time 5.32 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:43 PM PDT 24
Peak memory 213396 kb
Host smart-89c8d772-50f1-4604-ae81-9b7d900b4706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921549597 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2921549597
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4206735569
Short name T94
Test name
Test status
Simulation time 10262496240 ps
CPU time 17.16 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:38:54 PM PDT 24
Peak memory 249940 kb
Host smart-7cba0daf-30f8-4223-bff4-9b72dcd41d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206735569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4206735569
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.920002620
Short name T612
Test name
Test status
Simulation time 10101769689 ps
CPU time 22.43 seconds
Started Jun 05 04:38:38 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 377940 kb
Host smart-1b3e6924-8186-4a67-8dd9-5c7b69dcfc97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920002620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.920002620
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.3964493921
Short name T1020
Test name
Test status
Simulation time 4614940717 ps
CPU time 2.22 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:49 PM PDT 24
Peak memory 205176 kb
Host smart-51a014a0-dbce-4bea-a8ee-b529671d8e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964493921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.3964493921
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.11763438
Short name T1259
Test name
Test status
Simulation time 1081980615 ps
CPU time 5.16 seconds
Started Jun 05 04:38:45 PM PDT 24
Finished Jun 05 04:38:51 PM PDT 24
Peak memory 205152 kb
Host smart-7dc9a27c-ba51-47cd-af1e-c004540038c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11763438 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.11763438
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2713527126
Short name T400
Test name
Test status
Simulation time 694957926 ps
CPU time 2.26 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:38:39 PM PDT 24
Peak memory 205056 kb
Host smart-6ab68c6b-d71c-41b7-b9c5-b5a9bd93408b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713527126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2713527126
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.252426450
Short name T1447
Test name
Test status
Simulation time 1855867753 ps
CPU time 6.77 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:38:44 PM PDT 24
Peak memory 221140 kb
Host smart-f7eeca09-7b75-4674-8523-e85233be4118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252426450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.252426450
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3249560843
Short name T509
Test name
Test status
Simulation time 5336291098 ps
CPU time 9.33 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:38:46 PM PDT 24
Peak memory 440548 kb
Host smart-6ea52b5b-81d2-4852-bf91-50e7e66102f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249560843 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3249560843
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1001125422
Short name T902
Test name
Test status
Simulation time 1217372929 ps
CPU time 27.77 seconds
Started Jun 05 04:38:37 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 205072 kb
Host smart-7ae2e492-766b-414e-85b2-b6217f642c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001125422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1001125422
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2214908838
Short name T885
Test name
Test status
Simulation time 4377406424 ps
CPU time 10.81 seconds
Started Jun 05 04:38:36 PM PDT 24
Finished Jun 05 04:38:47 PM PDT 24
Peak memory 209664 kb
Host smart-f6d6bd7a-e9b4-4c21-bb67-acdf8e03932b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214908838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2214908838
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.267359287
Short name T912
Test name
Test status
Simulation time 25283408748 ps
CPU time 18.15 seconds
Started Jun 05 04:38:38 PM PDT 24
Finished Jun 05 04:38:57 PM PDT 24
Peak memory 406592 kb
Host smart-e8b29d4e-bce8-4899-9604-acda5d1c7f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267359287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.267359287
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2353376642
Short name T419
Test name
Test status
Simulation time 30303320486 ps
CPU time 726.96 seconds
Started Jun 05 04:38:39 PM PDT 24
Finished Jun 05 04:50:46 PM PDT 24
Peak memory 1906208 kb
Host smart-18b7686a-9eda-48b3-b6cc-f71427b50039
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353376642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2353376642
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2553226261
Short name T413
Test name
Test status
Simulation time 1409577896 ps
CPU time 7.2 seconds
Started Jun 05 04:38:38 PM PDT 24
Finished Jun 05 04:38:46 PM PDT 24
Peak memory 213332 kb
Host smart-9f6f5a46-db77-4574-9887-c036f36a417d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553226261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2553226261
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.2520645041
Short name T588
Test name
Test status
Simulation time 1101633617 ps
CPU time 16.68 seconds
Started Jun 05 04:38:44 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 205100 kb
Host smart-3b7d295b-e2e5-4deb-9322-b84906de367c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520645041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2520645041
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2565315906
Short name T1491
Test name
Test status
Simulation time 35517803 ps
CPU time 0.62 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 204756 kb
Host smart-1458527f-290a-412f-8287-65c7d0543739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565315906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2565315906
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3846317939
Short name T1393
Test name
Test status
Simulation time 266617252 ps
CPU time 4.92 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:52 PM PDT 24
Peak memory 251380 kb
Host smart-1992a0df-4a6c-4156-9712-503f9f68d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846317939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3846317939
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.359627116
Short name T975
Test name
Test status
Simulation time 240485466 ps
CPU time 5.17 seconds
Started Jun 05 04:38:48 PM PDT 24
Finished Jun 05 04:38:54 PM PDT 24
Peak memory 250308 kb
Host smart-ac7c9a19-36fb-4791-850f-834fb6dc5d46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359627116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.359627116
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1470119671
Short name T841
Test name
Test status
Simulation time 4316542072 ps
CPU time 67.16 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:39:54 PM PDT 24
Peak memory 721844 kb
Host smart-93fbf9c7-da67-4d58-9c28-bb38f338e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470119671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1470119671
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.443495376
Short name T976
Test name
Test status
Simulation time 2185456074 ps
CPU time 146.74 seconds
Started Jun 05 04:38:43 PM PDT 24
Finished Jun 05 04:41:11 PM PDT 24
Peak memory 660936 kb
Host smart-92a33c53-31b9-4615-87ac-9833cc706de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443495376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.443495376
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.321907156
Short name T244
Test name
Test status
Simulation time 547917039 ps
CPU time 0.99 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 204760 kb
Host smart-fe3e83ac-1e89-4813-b8d0-0ad967ad0ec1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321907156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.321907156
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.521196048
Short name T241
Test name
Test status
Simulation time 304978381 ps
CPU time 3.23 seconds
Started Jun 05 04:38:45 PM PDT 24
Finished Jun 05 04:38:49 PM PDT 24
Peak memory 205032 kb
Host smart-9d0db9e3-7789-43a5-87ce-df70797b3b15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521196048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
521196048
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2896110662
Short name T81
Test name
Test status
Simulation time 15386772925 ps
CPU time 96.99 seconds
Started Jun 05 04:38:43 PM PDT 24
Finished Jun 05 04:40:21 PM PDT 24
Peak memory 1163364 kb
Host smart-7600a377-9518-4904-989e-4a2c6439f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896110662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2896110662
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2594419652
Short name T814
Test name
Test status
Simulation time 1690346343 ps
CPU time 9.24 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 205032 kb
Host smart-df9a29a1-c966-455f-9141-5f87e89054fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594419652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2594419652
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.43122587
Short name T775
Test name
Test status
Simulation time 1488236755 ps
CPU time 28.14 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:39:16 PM PDT 24
Peak memory 300848 kb
Host smart-f05087d0-a173-461a-aa9a-3a7ce7056890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43122587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.43122587
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1508422718
Short name T1246
Test name
Test status
Simulation time 91240511 ps
CPU time 0.66 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:47 PM PDT 24
Peak memory 204708 kb
Host smart-2ef3888a-5c7d-41de-a78d-b498099576ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508422718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1508422718
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1890200674
Short name T538
Test name
Test status
Simulation time 6208945284 ps
CPU time 343.3 seconds
Started Jun 05 04:38:44 PM PDT 24
Finished Jun 05 04:44:28 PM PDT 24
Peak memory 571932 kb
Host smart-52a316ce-e522-4577-b5a9-2dcb8275ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890200674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1890200674
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3919086969
Short name T873
Test name
Test status
Simulation time 13339907286 ps
CPU time 38.04 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:39:24 PM PDT 24
Peak memory 355416 kb
Host smart-b1ab0664-4614-4b27-888f-6d7b76d10576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919086969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3919086969
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1779490673
Short name T896
Test name
Test status
Simulation time 31221224669 ps
CPU time 1476.56 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 05:03:25 PM PDT 24
Peak memory 3775684 kb
Host smart-d91f7761-27c3-4008-9794-616f79a0f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779490673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1779490673
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1676898263
Short name T338
Test name
Test status
Simulation time 1665449571 ps
CPU time 7.36 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 221428 kb
Host smart-5d5964e6-1074-47d0-93b3-8824e16549be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676898263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1676898263
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3684834450
Short name T458
Test name
Test status
Simulation time 506629681 ps
CPU time 2.94 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:02 PM PDT 24
Peak memory 205176 kb
Host smart-4856296f-2dda-4037-bb1c-8df8cd13e30a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684834450 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3684834450
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2619266264
Short name T525
Test name
Test status
Simulation time 10659925515 ps
CPU time 11.42 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 251640 kb
Host smart-f552f9fc-daed-4748-a86d-1bfb58f873ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619266264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2619266264
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3101954737
Short name T240
Test name
Test status
Simulation time 10130490499 ps
CPU time 72.06 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:40:00 PM PDT 24
Peak memory 514420 kb
Host smart-6d6fb1e7-9e21-4d1f-94ba-5836f7c2e800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101954737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3101954737
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.3200837410
Short name T653
Test name
Test status
Simulation time 1139164177 ps
CPU time 5.54 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:04 PM PDT 24
Peak memory 205120 kb
Host smart-28811bcf-57d1-4aa0-85cd-4e9c305eef86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200837410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.3200837410
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.1011177784
Short name T1360
Test name
Test status
Simulation time 1403146003 ps
CPU time 1.64 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:38:50 PM PDT 24
Peak memory 205068 kb
Host smart-26557ac6-186f-4da1-baf6-425eeb3a976d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011177784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.1011177784
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1607589093
Short name T296
Test name
Test status
Simulation time 454851347 ps
CPU time 2.74 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:38:57 PM PDT 24
Peak memory 204888 kb
Host smart-18c22dd6-461a-4b0f-979e-9deb565c5550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607589093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1607589093
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1796427005
Short name T1391
Test name
Test status
Simulation time 1418047145 ps
CPU time 5.1 seconds
Started Jun 05 04:38:42 PM PDT 24
Finished Jun 05 04:38:48 PM PDT 24
Peak memory 205080 kb
Host smart-a1f2ed78-d561-42ed-afa2-cc540f936f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796427005 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1796427005
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3863217251
Short name T1021
Test name
Test status
Simulation time 10851115659 ps
CPU time 5.62 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:38:54 PM PDT 24
Peak memory 205168 kb
Host smart-5d8a42b5-5383-4536-bcb3-6b7582cfdfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863217251 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3863217251
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.826770704
Short name T336
Test name
Test status
Simulation time 538180888 ps
CPU time 22.09 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:39:10 PM PDT 24
Peak memory 205036 kb
Host smart-c3de0f27-6226-4e0f-a004-dc16bed37e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826770704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.826770704
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2766210727
Short name T1188
Test name
Test status
Simulation time 1307032296 ps
CPU time 59.19 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:39:46 PM PDT 24
Peak memory 205136 kb
Host smart-ceaa5629-3a4f-4b77-9a76-203533fdfcb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766210727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2766210727
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.734426445
Short name T437
Test name
Test status
Simulation time 49275884633 ps
CPU time 95.05 seconds
Started Jun 05 04:38:45 PM PDT 24
Finished Jun 05 04:40:20 PM PDT 24
Peak memory 1335356 kb
Host smart-33a10380-453a-4b77-a70a-feb522c77341
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734426445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.734426445
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.4059707404
Short name T558
Test name
Test status
Simulation time 4925940292 ps
CPU time 112.97 seconds
Started Jun 05 04:38:47 PM PDT 24
Finished Jun 05 04:40:40 PM PDT 24
Peak memory 1326340 kb
Host smart-71083fff-4eec-403a-86d5-139a4290292d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059707404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.4059707404
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3631309535
Short name T1337
Test name
Test status
Simulation time 3021687773 ps
CPU time 7.89 seconds
Started Jun 05 04:38:44 PM PDT 24
Finished Jun 05 04:38:52 PM PDT 24
Peak memory 219420 kb
Host smart-1db9a011-5014-4426-aae1-a7bd2413888c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631309535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3631309535
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.313015559
Short name T623
Test name
Test status
Simulation time 1028705117 ps
CPU time 18.56 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:17 PM PDT 24
Peak memory 205108 kb
Host smart-79e3fbff-5862-41d5-8703-21dd55826581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313015559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.313015559
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.583496410
Short name T1299
Test name
Test status
Simulation time 35365375 ps
CPU time 0.67 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:38:54 PM PDT 24
Peak memory 204712 kb
Host smart-2dc5042d-716a-4234-82f1-ed7ae567cd8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583496410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.583496410
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2153591888
Short name T948
Test name
Test status
Simulation time 1050345108 ps
CPU time 9.19 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 221288 kb
Host smart-e0c3c61e-1232-49a2-98b7-9b55eff531e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153591888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2153591888
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.786335813
Short name T627
Test name
Test status
Simulation time 593037181 ps
CPU time 8 seconds
Started Jun 05 04:38:56 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 230664 kb
Host smart-cf5ef8af-1750-495c-bb6d-418ab8374dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786335813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.786335813
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2063982332
Short name T570
Test name
Test status
Simulation time 1887122651 ps
CPU time 46.64 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:42 PM PDT 24
Peak memory 446612 kb
Host smart-bf3c6b10-db37-4dc7-9244-f3ab7d044460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063982332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2063982332
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.4024498366
Short name T326
Test name
Test status
Simulation time 10000246887 ps
CPU time 109.16 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:40:44 PM PDT 24
Peak memory 854368 kb
Host smart-51eb0f07-6acc-49ce-bf95-bffb79bb3071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024498366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.4024498366
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.765815855
Short name T755
Test name
Test status
Simulation time 861000529 ps
CPU time 1.07 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:00 PM PDT 24
Peak memory 204628 kb
Host smart-12c38fd4-4c29-44fb-99a0-3378021bdb43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765815855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.765815855
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3526183991
Short name T504
Test name
Test status
Simulation time 1716852460 ps
CPU time 4.88 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 232136 kb
Host smart-7fcf3e3f-67e4-40a5-9253-ad109adef15d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526183991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3526183991
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3513608887
Short name T1344
Test name
Test status
Simulation time 8423553609 ps
CPU time 146.75 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:41:26 PM PDT 24
Peak memory 1506336 kb
Host smart-53e18169-640b-4c28-856f-5a816d72c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513608887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3513608887
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3146470449
Short name T1219
Test name
Test status
Simulation time 1496498580 ps
CPU time 6.4 seconds
Started Jun 05 04:38:58 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 204872 kb
Host smart-4307ae0b-7d55-4ed0-aa20-7467ede97880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146470449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3146470449
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.339178910
Short name T1355
Test name
Test status
Simulation time 1753098253 ps
CPU time 78.88 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:40:14 PM PDT 24
Peak memory 426500 kb
Host smart-23e14cf7-7eb1-47d3-815e-261645f872b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339178910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.339178910
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1292644380
Short name T1459
Test name
Test status
Simulation time 27961796 ps
CPU time 0.67 seconds
Started Jun 05 04:38:48 PM PDT 24
Finished Jun 05 04:38:49 PM PDT 24
Peak memory 204704 kb
Host smart-e5d5db13-6e57-4ea4-af9e-a41972d974b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292644380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1292644380
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4013233936
Short name T827
Test name
Test status
Simulation time 7280535574 ps
CPU time 70.56 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:40:07 PM PDT 24
Peak memory 221360 kb
Host smart-229580bd-5e2b-49fe-a74a-6149d81e2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013233936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4013233936
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2143414402
Short name T708
Test name
Test status
Simulation time 2766464759 ps
CPU time 27.37 seconds
Started Jun 05 04:38:46 PM PDT 24
Finished Jun 05 04:39:14 PM PDT 24
Peak memory 294536 kb
Host smart-feb1c8d5-74c5-4d02-a9e6-f8b9f5de0b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143414402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2143414402
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4039417778
Short name T301
Test name
Test status
Simulation time 3551916038 ps
CPU time 38.9 seconds
Started Jun 05 04:38:59 PM PDT 24
Finished Jun 05 04:39:39 PM PDT 24
Peak memory 213248 kb
Host smart-58ab1da9-fa57-4614-b951-950ef8f0ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039417778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4039417778
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3989977354
Short name T1374
Test name
Test status
Simulation time 986816611 ps
CPU time 4.63 seconds
Started Jun 05 04:38:56 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 213172 kb
Host smart-d2aea80f-a8c6-4171-9119-393bc2a284bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989977354 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3989977354
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.966605571
Short name T1199
Test name
Test status
Simulation time 10215497035 ps
CPU time 24.88 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 301200 kb
Host smart-e75c02c7-f18d-4abc-bbec-bafd0dc950a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966605571 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.966605571
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3590873111
Short name T454
Test name
Test status
Simulation time 10237757766 ps
CPU time 14.6 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:10 PM PDT 24
Peak memory 322144 kb
Host smart-576e7295-7d07-43bb-af62-7dac661d1961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590873111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3590873111
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.2291193024
Short name T1312
Test name
Test status
Simulation time 1144757824 ps
CPU time 5.09 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:01 PM PDT 24
Peak memory 205012 kb
Host smart-e41e7388-809b-48d8-b619-0d12d7478fbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291193024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.2291193024
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3430205803
Short name T1003
Test name
Test status
Simulation time 1196693517 ps
CPU time 1.73 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:38:56 PM PDT 24
Peak memory 205132 kb
Host smart-0e20878c-f969-4391-b1ab-322881f6514a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430205803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3430205803
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2955272443
Short name T1294
Test name
Test status
Simulation time 443638287 ps
CPU time 2.84 seconds
Started Jun 05 04:38:52 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 205040 kb
Host smart-62bc10d0-cbe3-4fc1-9593-5294bf217a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955272443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2955272443
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3718446219
Short name T559
Test name
Test status
Simulation time 2357289926 ps
CPU time 6.57 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:03 PM PDT 24
Peak memory 213388 kb
Host smart-2beb38d4-8820-4ee5-aa31-99ffb0081a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718446219 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3718446219
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2380071869
Short name T543
Test name
Test status
Simulation time 17141676333 ps
CPU time 239.95 seconds
Started Jun 05 04:39:00 PM PDT 24
Finished Jun 05 04:43:00 PM PDT 24
Peak memory 2643428 kb
Host smart-15df0f5b-eb02-4d01-9f6e-61fd9826a25a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380071869 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2380071869
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.90225374
Short name T979
Test name
Test status
Simulation time 1746155894 ps
CPU time 29.97 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:39:24 PM PDT 24
Peak memory 205096 kb
Host smart-da2293b7-5107-441f-b683-a697a8cf34c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90225374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_targ
et_smoke.90225374
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.204998129
Short name T422
Test name
Test status
Simulation time 1539509864 ps
CPU time 63.85 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:39:58 PM PDT 24
Peak memory 205756 kb
Host smart-c84b9b93-c615-44df-9a62-3c4215c81fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204998129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.204998129
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2591164916
Short name T751
Test name
Test status
Simulation time 21419382488 ps
CPU time 41.66 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:39:36 PM PDT 24
Peak memory 396904 kb
Host smart-d525130c-20d8-4b37-bb5f-0e207ea98cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591164916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2591164916
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3405040005
Short name T1099
Test name
Test status
Simulation time 20125952700 ps
CPU time 74.84 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:40:09 PM PDT 24
Peak memory 388500 kb
Host smart-beca5483-98e5-43f4-8eed-ec1276dea4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405040005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3405040005
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1120268450
Short name T78
Test name
Test status
Simulation time 1392459390 ps
CPU time 6.89 seconds
Started Jun 05 04:38:52 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 213340 kb
Host smart-29a46ebe-c82d-4545-91e3-4baa67cb3375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120268450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1120268450
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.3546864454
Short name T499
Test name
Test status
Simulation time 1209154273 ps
CPU time 17.88 seconds
Started Jun 05 04:38:56 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 205052 kb
Host smart-7d240820-b0ad-4246-a4e9-c6da6ef41bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546864454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3546864454
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1734391685
Short name T1009
Test name
Test status
Simulation time 25972783 ps
CPU time 0.71 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 204656 kb
Host smart-00e85a6b-cb47-424d-8ca3-e7dc14b4c952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734391685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1734391685
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1804316329
Short name T1061
Test name
Test status
Simulation time 924290481 ps
CPU time 5.85 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 215636 kb
Host smart-5b80a57a-367d-4c63-82cd-68b0c00e57a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804316329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1804316329
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2768478298
Short name T1430
Test name
Test status
Simulation time 954750199 ps
CPU time 11.84 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 231232 kb
Host smart-ac652a43-7f21-4576-9c29-b16c5ff50016
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768478298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2768478298
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3187614895
Short name T699
Test name
Test status
Simulation time 2329945770 ps
CPU time 87.02 seconds
Started Jun 05 04:38:56 PM PDT 24
Finished Jun 05 04:40:24 PM PDT 24
Peak memory 761524 kb
Host smart-d67fc140-4921-420e-8e9d-da3b5c702677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187614895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3187614895
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.49783527
Short name T1478
Test name
Test status
Simulation time 1364653499 ps
CPU time 98.8 seconds
Started Jun 05 04:38:54 PM PDT 24
Finished Jun 05 04:40:33 PM PDT 24
Peak memory 543192 kb
Host smart-49f786a1-c66e-40cf-a032-eb9dd6b4eaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49783527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.49783527
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1862135740
Short name T1150
Test name
Test status
Simulation time 80794813 ps
CPU time 0.96 seconds
Started Jun 05 04:38:53 PM PDT 24
Finished Jun 05 04:38:55 PM PDT 24
Peak memory 204968 kb
Host smart-d4b19e47-bdb7-46aa-997b-e183ec2e0e52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862135740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1862135740
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.689113164
Short name T828
Test name
Test status
Simulation time 649275473 ps
CPU time 8.48 seconds
Started Jun 05 04:38:57 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 204888 kb
Host smart-e0d56356-7e30-4295-9f93-c61784cb5671
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689113164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
689113164
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1877545139
Short name T1202
Test name
Test status
Simulation time 6043888368 ps
CPU time 107.03 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:40:43 PM PDT 24
Peak memory 1180684 kb
Host smart-aebe5a11-cb70-4832-9a3e-2f449955e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877545139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1877545139
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2772973367
Short name T556
Test name
Test status
Simulation time 537587739 ps
CPU time 8.13 seconds
Started Jun 05 04:39:07 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 204932 kb
Host smart-6e4b76ba-f8aa-4999-a053-f934847c182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772973367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2772973367
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.584470091
Short name T508
Test name
Test status
Simulation time 17487614977 ps
CPU time 32.94 seconds
Started Jun 05 04:39:01 PM PDT 24
Finished Jun 05 04:39:34 PM PDT 24
Peak memory 351168 kb
Host smart-2ccccb42-72bf-48ef-aaa9-2f257dfe40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584470091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.584470091
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.4236018316
Short name T878
Test name
Test status
Simulation time 51244057 ps
CPU time 0.66 seconds
Started Jun 05 04:38:57 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 204772 kb
Host smart-afa1f33a-c136-486b-a6b0-2b8a7427a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236018316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.4236018316
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3516835353
Short name T1100
Test name
Test status
Simulation time 1490212306 ps
CPU time 6.06 seconds
Started Jun 05 04:38:55 PM PDT 24
Finished Jun 05 04:39:02 PM PDT 24
Peak memory 213308 kb
Host smart-7931f40d-5464-43d5-912b-68e042d20ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516835353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3516835353
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.4189668642
Short name T1005
Test name
Test status
Simulation time 3444341096 ps
CPU time 33.53 seconds
Started Jun 05 04:38:57 PM PDT 24
Finished Jun 05 04:39:31 PM PDT 24
Peak memory 383248 kb
Host smart-6e873f4f-2282-4e5b-a86f-b7604648fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189668642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.4189668642
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3435361373
Short name T1253
Test name
Test status
Simulation time 79210558730 ps
CPU time 1606.62 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 05:05:53 PM PDT 24
Peak memory 2529848 kb
Host smart-07c3bd42-9dce-430d-953c-c89bcb8a651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435361373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3435361373
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2609225716
Short name T632
Test name
Test status
Simulation time 3262598181 ps
CPU time 12.91 seconds
Started Jun 05 04:39:01 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 213436 kb
Host smart-9d2c5794-7165-4bb1-af0d-cb34c70f2c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609225716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2609225716
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1509558895
Short name T1146
Test name
Test status
Simulation time 1976260514 ps
CPU time 2.93 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:39:05 PM PDT 24
Peak memory 205176 kb
Host smart-ed411534-5c29-4ce5-baa5-ab4f7b6f2fb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509558895 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1509558895
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3326820279
Short name T839
Test name
Test status
Simulation time 10226125236 ps
CPU time 14.64 seconds
Started Jun 05 04:39:00 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 239912 kb
Host smart-ac0e15c4-1c20-429b-8272-971380f27ee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326820279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3326820279
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3369033851
Short name T917
Test name
Test status
Simulation time 10230614145 ps
CPU time 7.9 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:39:11 PM PDT 24
Peak memory 244684 kb
Host smart-d827191b-b302-4d8f-acc8-95adcd78df7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369033851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3369033851
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.7588406
Short name T330
Test name
Test status
Simulation time 1301164593 ps
CPU time 5.89 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:17 PM PDT 24
Peak memory 205036 kb
Host smart-c6a08c95-d280-49b5-b1c6-cecfddb43677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7588406 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.7588406
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.590190355
Short name T1446
Test name
Test status
Simulation time 1598534889 ps
CPU time 1.82 seconds
Started Jun 05 04:39:07 PM PDT 24
Finished Jun 05 04:39:09 PM PDT 24
Peak memory 204976 kb
Host smart-d714d79f-f96d-4e49-9a04-fb391b480734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590190355 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.590190355
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2065056546
Short name T1307
Test name
Test status
Simulation time 2247162078 ps
CPU time 3.3 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:09 PM PDT 24
Peak memory 205180 kb
Host smart-93e7486a-cc16-4708-b174-0666da012dc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065056546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2065056546
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3098049553
Short name T1077
Test name
Test status
Simulation time 942151410 ps
CPU time 4.89 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:39:07 PM PDT 24
Peak memory 205152 kb
Host smart-aae3970d-8125-467a-a962-6cc7fd47c315
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098049553 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3098049553
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4073872573
Short name T423
Test name
Test status
Simulation time 28688713034 ps
CPU time 12.14 seconds
Started Jun 05 04:39:04 PM PDT 24
Finished Jun 05 04:39:17 PM PDT 24
Peak memory 354032 kb
Host smart-aaf86cf8-05bd-4a82-8770-9eaaeb9ee599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073872573 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4073872573
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2046373484
Short name T1
Test name
Test status
Simulation time 1455461783 ps
CPU time 22.72 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 205136 kb
Host smart-c2ccc489-1d6c-4375-8fe7-e5abb201f031
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046373484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2046373484
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3799202511
Short name T329
Test name
Test status
Simulation time 2469105956 ps
CPU time 57.94 seconds
Started Jun 05 04:39:04 PM PDT 24
Finished Jun 05 04:40:03 PM PDT 24
Peak memory 206744 kb
Host smart-12c85298-64b5-4369-af1c-f2d5376086b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799202511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3799202511
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2996230884
Short name T1102
Test name
Test status
Simulation time 21990959624 ps
CPU time 26.28 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:39:35 PM PDT 24
Peak memory 374276 kb
Host smart-0a11e491-16cc-4bb7-bb88-9e5e4ad86a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996230884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2996230884
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2588547795
Short name T1142
Test name
Test status
Simulation time 22504931372 ps
CPU time 168.85 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:41:51 PM PDT 24
Peak memory 1277244 kb
Host smart-98724ba6-7fe7-4b31-aec0-159e8dec7362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588547795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2588547795
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.3326150755
Short name T1315
Test name
Test status
Simulation time 1211645568 ps
CPU time 17.01 seconds
Started Jun 05 04:39:00 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 205088 kb
Host smart-75ea181a-87f6-4972-b2fa-070146ce2214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326150755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3326150755
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2850345940
Short name T1429
Test name
Test status
Simulation time 16616418 ps
CPU time 0.62 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 204744 kb
Host smart-04e073e5-f030-47d3-9f0f-1ba3d266c9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850345940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2850345940
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.4124676920
Short name T528
Test name
Test status
Simulation time 215983013 ps
CPU time 7.42 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:13 PM PDT 24
Peak memory 213208 kb
Host smart-f5095f54-716e-4269-bd2a-31c59b66e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124676920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.4124676920
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.367966198
Short name T568
Test name
Test status
Simulation time 306126444 ps
CPU time 6.77 seconds
Started Jun 05 04:39:07 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 268080 kb
Host smart-6c430266-40a7-40dd-ad9e-43343004667d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367966198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.367966198
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3684237707
Short name T1125
Test name
Test status
Simulation time 9479673286 ps
CPU time 57.75 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:40:07 PM PDT 24
Peak memory 284436 kb
Host smart-c9a0b7eb-de61-4778-86bf-51b9cf1fd2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684237707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3684237707
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1469111224
Short name T713
Test name
Test status
Simulation time 7351389345 ps
CPU time 57.26 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:40:00 PM PDT 24
Peak memory 661552 kb
Host smart-ded744f9-8f53-43dd-98b3-db0b5e805951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469111224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1469111224
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1435136419
Short name T768
Test name
Test status
Simulation time 146893579 ps
CPU time 0.92 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 204760 kb
Host smart-0ec7f828-0c6c-4f7a-8938-e4d4be7a975b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435136419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1435136419
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1652335330
Short name T996
Test name
Test status
Simulation time 369714941 ps
CPU time 3.86 seconds
Started Jun 05 04:39:04 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 228116 kb
Host smart-f8a45b86-48e1-4439-88ad-0573708c4aae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652335330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1652335330
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1710062003
Short name T928
Test name
Test status
Simulation time 20623149620 ps
CPU time 418.23 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:46:08 PM PDT 24
Peak memory 1464800 kb
Host smart-185002b8-07dc-4659-9cc7-08d00ea36b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710062003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1710062003
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3351081283
Short name T1058
Test name
Test status
Simulation time 324105271 ps
CPU time 5.31 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:39:14 PM PDT 24
Peak memory 205188 kb
Host smart-a133dc13-503d-4b24-8988-9220f2dd261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351081283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3351081283
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2987639829
Short name T894
Test name
Test status
Simulation time 15766679729 ps
CPU time 28.37 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:40 PM PDT 24
Peak memory 270312 kb
Host smart-5ee3b614-e418-4e94-b9eb-7a849a1b2fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987639829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2987639829
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.430373896
Short name T140
Test name
Test status
Simulation time 58945226 ps
CPU time 0.65 seconds
Started Jun 05 04:39:06 PM PDT 24
Finished Jun 05 04:39:08 PM PDT 24
Peak memory 204776 kb
Host smart-1a99464f-ca5b-49f3-9053-8ee91370ff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430373896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.430373896
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.700425141
Short name T1153
Test name
Test status
Simulation time 46960568173 ps
CPU time 2883.1 seconds
Started Jun 05 04:39:04 PM PDT 24
Finished Jun 05 05:27:08 PM PDT 24
Peak memory 4185988 kb
Host smart-22db67b7-efa2-467d-9dfa-03c56ab34dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700425141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.700425141
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2648965157
Short name T729
Test name
Test status
Simulation time 2977465060 ps
CPU time 108.7 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:40:53 PM PDT 24
Peak memory 406072 kb
Host smart-bc5ba5a9-d5f9-4f51-8233-f12f941deae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648965157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2648965157
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3797740318
Short name T1164
Test name
Test status
Simulation time 10326728464 ps
CPU time 173.04 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:41:59 PM PDT 24
Peak memory 897684 kb
Host smart-8451f862-d060-4d14-8264-e28c0695e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797740318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3797740318
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1392682115
Short name T572
Test name
Test status
Simulation time 1258234430 ps
CPU time 10.49 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:14 PM PDT 24
Peak memory 220672 kb
Host smart-73946e60-b05a-434b-9d42-99d6147e9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392682115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1392682115
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.621794307
Short name T636
Test name
Test status
Simulation time 912496578 ps
CPU time 4.61 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:39:13 PM PDT 24
Peak memory 205092 kb
Host smart-ccfa0e1d-11fd-46ef-b60b-5237ad8c6e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621794307 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.621794307
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2473746450
Short name T455
Test name
Test status
Simulation time 10612398951 ps
CPU time 12.99 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:17 PM PDT 24
Peak memory 259568 kb
Host smart-035bfab5-bc92-4456-a862-0593e0c6d37c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473746450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2473746450
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1277993619
Short name T678
Test name
Test status
Simulation time 10199946474 ps
CPU time 82.15 seconds
Started Jun 05 04:39:02 PM PDT 24
Finished Jun 05 04:40:25 PM PDT 24
Peak memory 538540 kb
Host smart-d9662e74-ce6d-4648-8293-e0d934009f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277993619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1277993619
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3698518579
Short name T613
Test name
Test status
Simulation time 1366657581 ps
CPU time 6 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 205116 kb
Host smart-54c79208-73af-4b6a-a1c0-54a8d5f11f88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698518579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3698518579
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1904042657
Short name T1505
Test name
Test status
Simulation time 1450902391 ps
CPU time 2.2 seconds
Started Jun 05 04:39:13 PM PDT 24
Finished Jun 05 04:39:16 PM PDT 24
Peak memory 205092 kb
Host smart-84616616-a2ae-433c-8c1e-32bd7ff8babd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904042657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1904042657
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3417463780
Short name T265
Test name
Test status
Simulation time 467493358 ps
CPU time 2.82 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:09 PM PDT 24
Peak memory 204948 kb
Host smart-08f7bc53-4484-4fd3-b379-88ffd2e405cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417463780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3417463780
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3310488223
Short name T1252
Test name
Test status
Simulation time 2161210756 ps
CPU time 6.44 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 220420 kb
Host smart-b4f5a7e4-dc25-4a08-adc0-ae2bc1866242
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310488223 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3310488223
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2535171872
Short name T1076
Test name
Test status
Simulation time 3150059536 ps
CPU time 25.6 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:29 PM PDT 24
Peak memory 911884 kb
Host smart-5f6ebd0c-0bb8-4c6d-bf41-f198d42a1e50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535171872 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2535171872
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3833349560
Short name T1330
Test name
Test status
Simulation time 1637482087 ps
CPU time 14.58 seconds
Started Jun 05 04:39:03 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 205088 kb
Host smart-288873d9-7006-482f-80f6-a9045fa512d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833349560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3833349560
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1457179293
Short name T838
Test name
Test status
Simulation time 2442861252 ps
CPU time 20.92 seconds
Started Jun 05 04:39:04 PM PDT 24
Finished Jun 05 04:39:26 PM PDT 24
Peak memory 225076 kb
Host smart-92e662f8-24ed-4a98-ac90-bf8d37cb2700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457179293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1457179293
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.541534498
Short name T1185
Test name
Test status
Simulation time 55563189720 ps
CPU time 209.41 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:42:38 PM PDT 24
Peak memory 2438100 kb
Host smart-795c8d6a-faec-4fd6-9e19-0848fed81daa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541534498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.541534498
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1770471816
Short name T404
Test name
Test status
Simulation time 1180752890 ps
CPU time 6.42 seconds
Started Jun 05 04:39:05 PM PDT 24
Finished Jun 05 04:39:13 PM PDT 24
Peak memory 213356 kb
Host smart-e1ff8a9d-1660-429a-ac75-35cad62a76b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770471816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1770471816
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.3545101177
Short name T496
Test name
Test status
Simulation time 1110746655 ps
CPU time 21.8 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:32 PM PDT 24
Peak memory 205064 kb
Host smart-dc79e23f-4d64-4c2f-94e7-22207bedc0e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545101177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3545101177
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2445946288
Short name T944
Test name
Test status
Simulation time 51332073 ps
CPU time 0.62 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:11 PM PDT 24
Peak memory 204752 kb
Host smart-53d0a2cd-e93a-414f-bf39-11c2aae40e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445946288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2445946288
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.802978405
Short name T1235
Test name
Test status
Simulation time 292181872 ps
CPU time 1.74 seconds
Started Jun 05 04:39:11 PM PDT 24
Finished Jun 05 04:39:14 PM PDT 24
Peak memory 213336 kb
Host smart-82f39bdb-44d8-45ff-9e2f-fa66dee6d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802978405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.802978405
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.871308479
Short name T1369
Test name
Test status
Simulation time 130975646 ps
CPU time 6.25 seconds
Started Jun 05 04:39:14 PM PDT 24
Finished Jun 05 04:39:21 PM PDT 24
Peak memory 222548 kb
Host smart-67bfd606-5b1b-40f7-b8af-3a1d4f972cfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871308479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.871308479
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3538273003
Short name T705
Test name
Test status
Simulation time 5287903007 ps
CPU time 35.6 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:47 PM PDT 24
Peak memory 484344 kb
Host smart-9cc1f56c-9a85-47a0-96c4-a58bedbe8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538273003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3538273003
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.384643195
Short name T920
Test name
Test status
Simulation time 11743593072 ps
CPU time 56.09 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:40:06 PM PDT 24
Peak memory 644872 kb
Host smart-e3d15487-544b-467d-9991-04a6e3aefd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384643195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.384643195
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.4001662613
Short name T520
Test name
Test status
Simulation time 90024568 ps
CPU time 0.86 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 204740 kb
Host smart-fe36a4e9-2f25-43ba-b28b-8f5d3a0e482d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001662613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.4001662613
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3595457628
Short name T324
Test name
Test status
Simulation time 583063031 ps
CPU time 7.52 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 205044 kb
Host smart-cda87363-ef7d-489e-874a-2fede0277c11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595457628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3595457628
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2665134789
Short name T356
Test name
Test status
Simulation time 16927007209 ps
CPU time 363.91 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:45:14 PM PDT 24
Peak memory 1289544 kb
Host smart-f7f93a97-d564-40bf-8f72-94a2246b7322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665134789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2665134789
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.348947386
Short name T51
Test name
Test status
Simulation time 250767656 ps
CPU time 10.43 seconds
Started Jun 05 04:39:11 PM PDT 24
Finished Jun 05 04:39:22 PM PDT 24
Peak memory 205116 kb
Host smart-c2089bed-7c0a-4090-b3cc-868dd8051116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348947386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.348947386
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1443331296
Short name T884
Test name
Test status
Simulation time 5996584992 ps
CPU time 26.81 seconds
Started Jun 05 04:39:08 PM PDT 24
Finished Jun 05 04:39:37 PM PDT 24
Peak memory 270296 kb
Host smart-3e013a6e-12fe-4b10-8157-4146050b72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443331296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1443331296
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3529587448
Short name T963
Test name
Test status
Simulation time 29069416 ps
CPU time 0.75 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:12 PM PDT 24
Peak memory 204772 kb
Host smart-dc001642-6f1b-43a9-889e-a36a8b1cdc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529587448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3529587448
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3422839704
Short name T926
Test name
Test status
Simulation time 12438338356 ps
CPU time 144.34 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:41:36 PM PDT 24
Peak memory 205172 kb
Host smart-e8562a4e-1e7f-4913-a361-adee8f494928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422839704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3422839704
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1712163515
Short name T406
Test name
Test status
Simulation time 1339895612 ps
CPU time 21.83 seconds
Started Jun 05 04:39:11 PM PDT 24
Finished Jun 05 04:39:34 PM PDT 24
Peak memory 294084 kb
Host smart-fb21b000-e732-4557-9dad-901146d98c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712163515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1712163515
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.482304960
Short name T1079
Test name
Test status
Simulation time 1451334237 ps
CPU time 53.58 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:40:05 PM PDT 24
Peak memory 221528 kb
Host smart-111e87dc-0815-4e2a-aa99-f42ecca63b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482304960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.482304960
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1336542801
Short name T532
Test name
Test status
Simulation time 4194279340 ps
CPU time 4.13 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 213416 kb
Host smart-f7c7e76e-78dd-4f34-b035-d24f5d1e8678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336542801 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1336542801
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3228622776
Short name T1336
Test name
Test status
Simulation time 11055062059 ps
CPU time 7.62 seconds
Started Jun 05 04:39:14 PM PDT 24
Finished Jun 05 04:39:22 PM PDT 24
Peak memory 224420 kb
Host smart-0b737d7b-3c64-4bef-99e7-7ce50d274271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228622776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3228622776
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1533797025
Short name T818
Test name
Test status
Simulation time 10713759963 ps
CPU time 5.45 seconds
Started Jun 05 04:39:15 PM PDT 24
Finished Jun 05 04:39:21 PM PDT 24
Peak memory 244300 kb
Host smart-b67ab6c2-0f52-4b8d-b8f6-5d5f0e91924b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533797025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1533797025
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2984897027
Short name T640
Test name
Test status
Simulation time 1061964365 ps
CPU time 2.75 seconds
Started Jun 05 04:39:14 PM PDT 24
Finished Jun 05 04:39:17 PM PDT 24
Peak memory 205148 kb
Host smart-44864ea1-cb63-4f73-8598-a30992f3f644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984897027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2984897027
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3229825703
Short name T1124
Test name
Test status
Simulation time 1172171981 ps
CPU time 4.46 seconds
Started Jun 05 04:39:11 PM PDT 24
Finished Jun 05 04:39:16 PM PDT 24
Peak memory 205152 kb
Host smart-fd845623-c198-41cf-88c0-9a7fc379fdf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229825703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3229825703
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.2665351681
Short name T889
Test name
Test status
Simulation time 1349278911 ps
CPU time 2.56 seconds
Started Jun 05 04:39:12 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 205012 kb
Host smart-64ce973a-968f-4a6a-a05f-7c89aa30f71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665351681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.2665351681
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3301124879
Short name T477
Test name
Test status
Simulation time 2444769440 ps
CPU time 6.3 seconds
Started Jun 05 04:39:11 PM PDT 24
Finished Jun 05 04:39:18 PM PDT 24
Peak memory 213972 kb
Host smart-ff72254d-3939-443b-a270-7f525cab0347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301124879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3301124879
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2746272044
Short name T671
Test name
Test status
Simulation time 2221926820 ps
CPU time 15.31 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:25 PM PDT 24
Peak memory 667896 kb
Host smart-cd789efe-e59c-4237-8c9e-299d1f8a9faf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746272044 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2746272044
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1869648991
Short name T914
Test name
Test status
Simulation time 16750064006 ps
CPU time 12.06 seconds
Started Jun 05 04:39:12 PM PDT 24
Finished Jun 05 04:39:25 PM PDT 24
Peak memory 205176 kb
Host smart-34280a6c-04a5-464f-81cd-cdb34cdc0732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869648991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1869648991
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3924335030
Short name T255
Test name
Test status
Simulation time 4032330275 ps
CPU time 43.83 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:39:55 PM PDT 24
Peak memory 205116 kb
Host smart-879de93a-cde0-4a61-820b-833a7c442ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924335030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3924335030
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2363522158
Short name T647
Test name
Test status
Simulation time 45521332033 ps
CPU time 256.37 seconds
Started Jun 05 04:39:15 PM PDT 24
Finished Jun 05 04:43:32 PM PDT 24
Peak memory 2728560 kb
Host smart-9f55f7e2-333c-4152-9ec5-b856a9ad53ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363522158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2363522158
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2157275182
Short name T1049
Test name
Test status
Simulation time 16414321993 ps
CPU time 1017.27 seconds
Started Jun 05 04:39:10 PM PDT 24
Finished Jun 05 04:56:09 PM PDT 24
Peak memory 4131864 kb
Host smart-0b8fccff-1502-44a0-8b67-70e5b60c342b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157275182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2157275182
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1962233093
Short name T541
Test name
Test status
Simulation time 1368604485 ps
CPU time 7.13 seconds
Started Jun 05 04:39:12 PM PDT 24
Finished Jun 05 04:39:20 PM PDT 24
Peak memory 218976 kb
Host smart-b0c76bee-555d-4ab7-8030-ce1eefbb714e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962233093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1962233093
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2246112178
Short name T583
Test name
Test status
Simulation time 1472055345 ps
CPU time 17.54 seconds
Started Jun 05 04:39:09 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 205216 kb
Host smart-23c568a1-d0fd-4f03-882c-cb0ecd00e185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246112178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2246112178
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.247874399
Short name T415
Test name
Test status
Simulation time 38148428 ps
CPU time 0.67 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:21 PM PDT 24
Peak memory 204752 kb
Host smart-8c77973f-a5e9-4cdd-96b4-d18ec5cfcc60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247874399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.247874399
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1628596641
Short name T847
Test name
Test status
Simulation time 1255788288 ps
CPU time 7.02 seconds
Started Jun 05 04:39:18 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 268784 kb
Host smart-f81f0801-4cce-40b6-bfc1-1e890abb3b7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628596641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1628596641
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.380326141
Short name T1260
Test name
Test status
Simulation time 2282645098 ps
CPU time 175.67 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:42:16 PM PDT 24
Peak memory 769960 kb
Host smart-8b2f985d-de4e-497f-9234-3da7d745b376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380326141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.380326141
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3086454482
Short name T133
Test name
Test status
Simulation time 2282698816 ps
CPU time 74.34 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:40:34 PM PDT 24
Peak memory 761076 kb
Host smart-24161357-ec1f-4193-9ec1-b83bf9182ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086454482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3086454482
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1836102595
Short name T953
Test name
Test status
Simulation time 179444811 ps
CPU time 0.86 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:22 PM PDT 24
Peak memory 204740 kb
Host smart-97db381c-3b55-466b-92cd-4eef2ea7b9ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836102595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1836102595
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1816847678
Short name T1175
Test name
Test status
Simulation time 640660800 ps
CPU time 9.56 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:31 PM PDT 24
Peak memory 233712 kb
Host smart-9ebbcd5b-d0d5-41c8-8493-6b99cd1a8f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816847678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1816847678
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1338089494
Short name T116
Test name
Test status
Simulation time 3017841495 ps
CPU time 71.96 seconds
Started Jun 05 04:39:21 PM PDT 24
Finished Jun 05 04:40:35 PM PDT 24
Peak memory 912964 kb
Host smart-20243570-2b89-432d-a515-e4e073abf707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338089494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1338089494
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.2612662039
Short name T1267
Test name
Test status
Simulation time 733995997 ps
CPU time 6.25 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:28 PM PDT 24
Peak memory 205024 kb
Host smart-f46b6815-4d44-4fc3-b98b-5ea6b9cb0b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612662039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2612662039
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1248176190
Short name T249
Test name
Test status
Simulation time 1707991866 ps
CPU time 33.18 seconds
Started Jun 05 04:39:21 PM PDT 24
Finished Jun 05 04:39:55 PM PDT 24
Peak memory 361868 kb
Host smart-076a5dda-6c05-442a-b89b-706e4ef210df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248176190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1248176190
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.696554378
Short name T1016
Test name
Test status
Simulation time 64021732 ps
CPU time 0.65 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:21 PM PDT 24
Peak memory 204728 kb
Host smart-09f6b4c4-1eb9-4fae-8319-f5b3de4dea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696554378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.696554378
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.559138016
Short name T418
Test name
Test status
Simulation time 4968607211 ps
CPU time 20.34 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:41 PM PDT 24
Peak memory 337920 kb
Host smart-dc98a018-a384-4067-bdbc-f9c56bad5d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559138016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.559138016
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.238568147
Short name T566
Test name
Test status
Simulation time 7072649753 ps
CPU time 100.34 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:41:01 PM PDT 24
Peak memory 353492 kb
Host smart-fdae8de2-f566-4ac6-9637-36fa5160830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238568147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.238568147
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.24335460
Short name T409
Test name
Test status
Simulation time 14318087732 ps
CPU time 273.06 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:43:54 PM PDT 24
Peak memory 1125708 kb
Host smart-632e6f2f-605f-40c2-b3dc-90ef5511c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24335460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.24335460
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.849247198
Short name T1019
Test name
Test status
Simulation time 11557392877 ps
CPU time 14.37 seconds
Started Jun 05 04:39:17 PM PDT 24
Finished Jun 05 04:39:33 PM PDT 24
Peak memory 213384 kb
Host smart-e3f531aa-a2b3-45b2-ae6a-ca16174b5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849247198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.849247198
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1837370584
Short name T497
Test name
Test status
Simulation time 865034354 ps
CPU time 4.76 seconds
Started Jun 05 04:39:18 PM PDT 24
Finished Jun 05 04:39:24 PM PDT 24
Peak memory 205104 kb
Host smart-e31b1927-a0b2-48b8-83c1-d552eeb41dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837370584 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1837370584
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1863402435
Short name T161
Test name
Test status
Simulation time 10118659434 ps
CPU time 28.21 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:49 PM PDT 24
Peak memory 265384 kb
Host smart-2a666432-4b73-47f2-a1df-20e0e1dc3552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863402435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1863402435
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3315428916
Short name T1383
Test name
Test status
Simulation time 10115792370 ps
CPU time 70.76 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:40:30 PM PDT 24
Peak memory 518332 kb
Host smart-cf1f8b37-56e7-4a4a-b1a5-9416f5e73e08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315428916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3315428916
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2956458051
Short name T601
Test name
Test status
Simulation time 1243147556 ps
CPU time 1.98 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:23 PM PDT 24
Peak memory 205144 kb
Host smart-33c463e2-778a-4fc3-b923-e5a765bb1e3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956458051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2956458051
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.722572549
Short name T1387
Test name
Test status
Simulation time 1229259404 ps
CPU time 3.33 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:25 PM PDT 24
Peak memory 205072 kb
Host smart-94650de1-7bd6-4323-bd6e-2d40f15a9f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722572549 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.722572549
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1042713221
Short name T1287
Test name
Test status
Simulation time 474820480 ps
CPU time 2.94 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:24 PM PDT 24
Peak memory 205060 kb
Host smart-9a038a07-4640-4821-b881-a7c18a93aaab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042713221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1042713221
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1499720526
Short name T1227
Test name
Test status
Simulation time 3236442025 ps
CPU time 6.49 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:27 PM PDT 24
Peak memory 218732 kb
Host smart-4e168590-2a10-40ef-8233-363602d20243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499720526 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1499720526
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.297365318
Short name T826
Test name
Test status
Simulation time 19383047659 ps
CPU time 448.23 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:46:50 PM PDT 24
Peak memory 4629868 kb
Host smart-389bf355-810d-4622-b851-12bdb019eefc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297365318 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.297365318
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.812752994
Short name T956
Test name
Test status
Simulation time 919843946 ps
CPU time 15.49 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:39:36 PM PDT 24
Peak memory 205108 kb
Host smart-797d73ec-5c72-4b4d-b13c-577f6aabc428
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812752994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.812752994
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3888955939
Short name T1001
Test name
Test status
Simulation time 3833564509 ps
CPU time 30.77 seconds
Started Jun 05 04:39:21 PM PDT 24
Finished Jun 05 04:39:53 PM PDT 24
Peak memory 235868 kb
Host smart-b9ad2186-5af5-45b8-b35d-41c3194e7dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888955939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3888955939
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1998176551
Short name T1404
Test name
Test status
Simulation time 32169444745 ps
CPU time 272.13 seconds
Started Jun 05 04:39:19 PM PDT 24
Finished Jun 05 04:43:52 PM PDT 24
Peak memory 2987964 kb
Host smart-67999766-e2a1-4ac4-94ed-163bd4dfb2f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998176551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1998176551
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3177912753
Short name T863
Test name
Test status
Simulation time 33373199978 ps
CPU time 348.23 seconds
Started Jun 05 04:39:18 PM PDT 24
Finished Jun 05 04:45:07 PM PDT 24
Peak memory 1111968 kb
Host smart-2d9e5760-1c19-4730-9f73-744283d9961a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177912753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3177912753
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3413979221
Short name T569
Test name
Test status
Simulation time 4545817330 ps
CPU time 7.04 seconds
Started Jun 05 04:39:18 PM PDT 24
Finished Jun 05 04:39:26 PM PDT 24
Peak memory 213380 kb
Host smart-44ca7357-2efa-408b-bbc1-fd167aed86eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413979221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3413979221
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.408744662
Short name T1462
Test name
Test status
Simulation time 1109959176 ps
CPU time 21.4 seconds
Started Jun 05 04:39:20 PM PDT 24
Finished Jun 05 04:39:43 PM PDT 24
Peak memory 205104 kb
Host smart-bdc7eb55-e903-49ab-aece-4e498cba1314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408744662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.408744662
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3978512090
Short name T1080
Test name
Test status
Simulation time 30566651 ps
CPU time 0.64 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:35:12 PM PDT 24
Peak memory 204752 kb
Host smart-24a2bab1-7003-4db1-93c6-e33b703a584c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978512090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3978512090
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3066658130
Short name T74
Test name
Test status
Simulation time 487416634 ps
CPU time 1.92 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:34:50 PM PDT 24
Peak memory 213272 kb
Host smart-326e3e6c-1715-4266-b128-74fe6c419558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066658130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3066658130
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.840264883
Short name T1489
Test name
Test status
Simulation time 306771865 ps
CPU time 6.53 seconds
Started Jun 05 04:34:52 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 244396 kb
Host smart-bd208f84-c0a5-458c-a1d3-eb480f95f5bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840264883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.840264883
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2726902499
Short name T446
Test name
Test status
Simulation time 5540650806 ps
CPU time 94.22 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:36:43 PM PDT 24
Peak memory 548180 kb
Host smart-4ad3f2cf-cda1-469d-90dd-b147d20b8d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726902499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2726902499
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1575144409
Short name T1317
Test name
Test status
Simulation time 2531310077 ps
CPU time 200.72 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:38:08 PM PDT 24
Peak memory 746176 kb
Host smart-72b2e635-de3e-43c6-9488-1e1435c595e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575144409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1575144409
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1532689349
Short name T1137
Test name
Test status
Simulation time 156183317 ps
CPU time 0.9 seconds
Started Jun 05 04:34:42 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 204760 kb
Host smart-a853e5d4-97f2-4f4b-a1dc-b120a0ac2662
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532689349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1532689349
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1415928020
Short name T164
Test name
Test status
Simulation time 187558370 ps
CPU time 3.94 seconds
Started Jun 05 04:35:06 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 204988 kb
Host smart-89a0a4f3-98a4-49f2-9dc2-330c4a0fb8f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415928020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1415928020
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.52887017
Short name T723
Test name
Test status
Simulation time 2808931801 ps
CPU time 179.85 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:37:55 PM PDT 24
Peak memory 814796 kb
Host smart-c1bd06db-27ab-4c5f-9731-792f19aa7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52887017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.52887017
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.291861770
Short name T43
Test name
Test status
Simulation time 2467267077 ps
CPU time 122.77 seconds
Started Jun 05 04:35:09 PM PDT 24
Finished Jun 05 04:37:12 PM PDT 24
Peak memory 448268 kb
Host smart-22443410-9647-4b4c-af4d-ff1c0b788ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291861770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.291861770
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3887969714
Short name T96
Test name
Test status
Simulation time 150065268 ps
CPU time 0.68 seconds
Started Jun 05 04:34:46 PM PDT 24
Finished Jun 05 04:34:48 PM PDT 24
Peak memory 204728 kb
Host smart-e8099022-0127-4028-8264-97ea548642b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887969714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3887969714
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3723851674
Short name T631
Test name
Test status
Simulation time 6668172269 ps
CPU time 64.55 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 740408 kb
Host smart-5d3b1f01-4deb-47de-bf5a-50ead316ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723851674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3723851674
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.4249145230
Short name T518
Test name
Test status
Simulation time 10173709884 ps
CPU time 47.04 seconds
Started Jun 05 04:34:47 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 458732 kb
Host smart-f29cbc4d-088f-4ffe-9f6c-b8ea03eac8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249145230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.4249145230
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2620708038
Short name T126
Test name
Test status
Simulation time 11893811034 ps
CPU time 533.52 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:43:50 PM PDT 24
Peak memory 2509808 kb
Host smart-5f7c33ed-bb45-4c84-8b34-06211541ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620708038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2620708038
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1731618798
Short name T276
Test name
Test status
Simulation time 2440581025 ps
CPU time 28.66 seconds
Started Jun 05 04:34:56 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 213396 kb
Host smart-623fc43f-ec87-45a0-a995-925d56ec2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731618798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1731618798
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.106746728
Short name T549
Test name
Test status
Simulation time 601388070 ps
CPU time 3.6 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:35:09 PM PDT 24
Peak memory 213268 kb
Host smart-8be80e0d-4b72-4c50-9b07-7e9ec655a3eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106746728 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.106746728
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2003567561
Short name T95
Test name
Test status
Simulation time 10131112421 ps
CPU time 47.84 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:53 PM PDT 24
Peak memory 366432 kb
Host smart-563369dc-45f4-4d7e-b51a-b69e190b5156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003567561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2003567561
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.590667172
Short name T585
Test name
Test status
Simulation time 10134855676 ps
CPU time 70.71 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:36:11 PM PDT 24
Peak memory 609048 kb
Host smart-c46f77f6-614a-433e-9c4c-7a3587bdaeb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590667172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.590667172
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.2234501891
Short name T802
Test name
Test status
Simulation time 1365759275 ps
CPU time 5.57 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 205124 kb
Host smart-78865c83-8af3-41d2-ac48-796d1666783f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234501891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.2234501891
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2137336669
Short name T691
Test name
Test status
Simulation time 1066509810 ps
CPU time 5.16 seconds
Started Jun 05 04:34:47 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 205128 kb
Host smart-72c954e5-10fa-4eb0-8b57-d1c547495f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137336669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2137336669
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1918241162
Short name T16
Test name
Test status
Simulation time 884677930 ps
CPU time 2.35 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 205328 kb
Host smart-61952b55-6c48-4818-b9b3-88205b302dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918241162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1918241162
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3212626042
Short name T315
Test name
Test status
Simulation time 2272869059 ps
CPU time 6.7 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:03 PM PDT 24
Peak memory 205144 kb
Host smart-ef4906e7-021f-41e3-a19d-96e139d28cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212626042 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3212626042
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2295451476
Short name T777
Test name
Test status
Simulation time 9681836144 ps
CPU time 48.93 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 1213288 kb
Host smart-9ea7859e-14db-4b06-8846-75234b427c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295451476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2295451476
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2838262717
Short name T606
Test name
Test status
Simulation time 765451837 ps
CPU time 30.38 seconds
Started Jun 05 04:35:07 PM PDT 24
Finished Jun 05 04:35:38 PM PDT 24
Peak memory 205068 kb
Host smart-17020b5c-21cc-4b72-84b3-481c988b22cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838262717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2838262717
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2781172815
Short name T1347
Test name
Test status
Simulation time 663875694 ps
CPU time 12.65 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:12 PM PDT 24
Peak memory 208656 kb
Host smart-873c9e0b-e122-4cf0-bf5c-46d5f2a7025a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781172815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2781172815
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.4058854775
Short name T964
Test name
Test status
Simulation time 42043267366 ps
CPU time 106.66 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:36:38 PM PDT 24
Peak memory 1493440 kb
Host smart-888eb8e2-de25-40ef-a3f8-a07d297fa091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058854775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.4058854775
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1991845112
Short name T11
Test name
Test status
Simulation time 28847730059 ps
CPU time 247.01 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:38:59 PM PDT 24
Peak memory 1712388 kb
Host smart-19da6199-bc61-4deb-983f-9e5382300a43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991845112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1991845112
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1276093752
Short name T1106
Test name
Test status
Simulation time 2906807126 ps
CPU time 8.39 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:09 PM PDT 24
Peak memory 221468 kb
Host smart-c180a0d5-0c6d-4b26-ba17-8e651b9b4dd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276093752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1276093752
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.18282115
Short name T480
Test name
Test status
Simulation time 1076208096 ps
CPU time 16.27 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 205084 kb
Host smart-454e0042-c446-41d6-8ec0-5d18a95edc74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18282115 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.18282115
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.459992409
Short name T1206
Test name
Test status
Simulation time 40712475 ps
CPU time 0.64 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:34:55 PM PDT 24
Peak memory 204740 kb
Host smart-fc930f85-01d3-4a88-a38f-441010c33787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459992409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.459992409
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1720223021
Short name T172
Test name
Test status
Simulation time 63735450 ps
CPU time 1.35 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:34:56 PM PDT 24
Peak memory 215768 kb
Host smart-3bc3fabc-b058-45a9-8f20-75c86c127c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720223021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1720223021
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1634265822
Short name T993
Test name
Test status
Simulation time 1189585658 ps
CPU time 6.55 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 259804 kb
Host smart-88864701-b659-4cc2-b020-e6d7e069e3a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634265822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1634265822
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2962087668
Short name T1490
Test name
Test status
Simulation time 10140754458 ps
CPU time 90.22 seconds
Started Jun 05 04:34:51 PM PDT 24
Finished Jun 05 04:36:22 PM PDT 24
Peak memory 788020 kb
Host smart-3810fb5a-eeeb-45f1-aaf7-03978e7c2e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962087668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2962087668
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2111479515
Short name T736
Test name
Test status
Simulation time 1577781392 ps
CPU time 53.38 seconds
Started Jun 05 04:35:00 PM PDT 24
Finished Jun 05 04:35:54 PM PDT 24
Peak memory 593828 kb
Host smart-7aa19c69-14a2-437e-bb1b-0c94220fc2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111479515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2111479515
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1851125724
Short name T740
Test name
Test status
Simulation time 277620591 ps
CPU time 0.95 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:07 PM PDT 24
Peak memory 204776 kb
Host smart-7269822e-083b-4c0e-a382-64070f120639
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851125724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1851125724
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.201438141
Short name T1194
Test name
Test status
Simulation time 548464369 ps
CPU time 7.87 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 227740 kb
Host smart-cc6b05fa-57b5-40e8-92cd-821a9aafc2dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201438141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.201438141
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2213761234
Short name T716
Test name
Test status
Simulation time 13472001733 ps
CPU time 182.69 seconds
Started Jun 05 04:35:12 PM PDT 24
Finished Jun 05 04:38:16 PM PDT 24
Peak memory 1508948 kb
Host smart-2b59c9be-08a1-4313-b02b-9b45d49ae8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213761234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2213761234
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2820955265
Short name T345
Test name
Test status
Simulation time 302451763 ps
CPU time 12.59 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:35:25 PM PDT 24
Peak memory 205000 kb
Host smart-1c91cae5-e67a-41bb-a30d-6cae565c03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820955265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2820955265
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3526676176
Short name T805
Test name
Test status
Simulation time 2016510921 ps
CPU time 103.18 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:36:40 PM PDT 24
Peak memory 440128 kb
Host smart-a806ee6e-a26c-4348-b1db-1dd52b932e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526676176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3526676176
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1634399877
Short name T1092
Test name
Test status
Simulation time 50805438 ps
CPU time 0.69 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:34:57 PM PDT 24
Peak memory 204780 kb
Host smart-7b224cac-4bf2-43e8-9539-0b629904d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634399877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1634399877
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.394792177
Short name T1064
Test name
Test status
Simulation time 78532959366 ps
CPU time 978.22 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:51:16 PM PDT 24
Peak memory 3044780 kb
Host smart-cedca908-b18c-4259-9a54-1252c318c1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394792177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.394792177
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.716245103
Short name T302
Test name
Test status
Simulation time 4323896653 ps
CPU time 97.93 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:36:29 PM PDT 24
Peak memory 432240 kb
Host smart-28f2e6fb-d08a-4d90-b04d-074e28299325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716245103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.716245103
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2875628721
Short name T1322
Test name
Test status
Simulation time 73087236885 ps
CPU time 1035.93 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:52:35 PM PDT 24
Peak memory 1940132 kb
Host smart-ce685d8b-a9b7-49c4-b2e7-f672edfbcf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875628721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2875628721
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1965667320
Short name T605
Test name
Test status
Simulation time 1185079056 ps
CPU time 26.64 seconds
Started Jun 05 04:34:45 PM PDT 24
Finished Jun 05 04:35:13 PM PDT 24
Peak memory 213292 kb
Host smart-76c9227d-2c16-4ef4-abf2-37390402d2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965667320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1965667320
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2291528257
Short name T341
Test name
Test status
Simulation time 4103700752 ps
CPU time 5.26 seconds
Started Jun 05 04:35:14 PM PDT 24
Finished Jun 05 04:35:20 PM PDT 24
Peak memory 213420 kb
Host smart-e4dccf7c-8b6b-4f3e-8c1c-451b2689c2c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291528257 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2291528257
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3477951713
Short name T1381
Test name
Test status
Simulation time 10352174320 ps
CPU time 11.95 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 238144 kb
Host smart-114c2703-142a-4cc9-b996-b48218af4ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477951713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3477951713
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3515391292
Short name T474
Test name
Test status
Simulation time 10158029455 ps
CPU time 15.44 seconds
Started Jun 05 04:34:52 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 286712 kb
Host smart-60027ff4-b1b7-434d-a107-d8d59dfbc472
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515391292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3515391292
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.1471880479
Short name T511
Test name
Test status
Simulation time 1435985293 ps
CPU time 6.77 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:35:01 PM PDT 24
Peak memory 205148 kb
Host smart-7ef42c25-fc82-4a7d-a1f8-97f759e1a327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471880479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.1471880479
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.330050463
Short name T1108
Test name
Test status
Simulation time 1505002971 ps
CPU time 2.32 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 205068 kb
Host smart-20062ec9-8882-4dec-aa04-991fb52ba76d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330050463 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.330050463
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3631258042
Short name T772
Test name
Test status
Simulation time 1923158496 ps
CPU time 2.79 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:34:58 PM PDT 24
Peak memory 205084 kb
Host smart-35275917-7b7d-4400-ba2d-ef505838c4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631258042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3631258042
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.4139220051
Short name T1479
Test name
Test status
Simulation time 2255429356 ps
CPU time 5.94 seconds
Started Jun 05 04:35:18 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 219792 kb
Host smart-369c5020-5beb-4e83-90ba-e229ab7a7a61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139220051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.4139220051
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1032996296
Short name T382
Test name
Test status
Simulation time 4326728651 ps
CPU time 2.87 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:00 PM PDT 24
Peak memory 205140 kb
Host smart-41e8d640-fcda-4fa0-8559-daa97a08ef8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032996296 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1032996296
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.358204658
Short name T490
Test name
Test status
Simulation time 1582655340 ps
CPU time 25.33 seconds
Started Jun 05 04:34:50 PM PDT 24
Finished Jun 05 04:35:16 PM PDT 24
Peak memory 205232 kb
Host smart-62dfa808-46e8-4b3a-bd3c-fe3b442651b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358204658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.358204658
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2896321638
Short name T752
Test name
Test status
Simulation time 418076153 ps
CPU time 16.2 seconds
Started Jun 05 04:35:00 PM PDT 24
Finished Jun 05 04:35:17 PM PDT 24
Peak memory 205044 kb
Host smart-62b145ee-314a-4617-8074-78745f1786ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896321638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2896321638
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3744430681
Short name T1398
Test name
Test status
Simulation time 34379081727 ps
CPU time 397.71 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:41:40 PM PDT 24
Peak memory 3728228 kb
Host smart-00e0d7c7-21c4-4458-9ed4-3221bfc51c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744430681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3744430681
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.621691367
Short name T748
Test name
Test status
Simulation time 35161156465 ps
CPU time 2268.86 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 05:13:14 PM PDT 24
Peak memory 8356832 kb
Host smart-161354f1-896c-4309-bde0-ca4c46128388
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621691367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.621691367
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1165032362
Short name T1473
Test name
Test status
Simulation time 24331795096 ps
CPU time 6.53 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 213384 kb
Host smart-43598081-5c13-40d0-a4c9-3b439709bbc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165032362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1165032362
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.3682436426
Short name T377
Test name
Test status
Simulation time 1032934181 ps
CPU time 16.02 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 205068 kb
Host smart-8b09bdad-1fbe-4494-b281-2686cc574d9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682436426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.3682436426
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1798715835
Short name T1278
Test name
Test status
Simulation time 50522776 ps
CPU time 0.64 seconds
Started Jun 05 04:34:58 PM PDT 24
Finished Jun 05 04:35:00 PM PDT 24
Peak memory 204700 kb
Host smart-262107a5-5846-44ba-afdb-a42030f6c53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798715835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1798715835
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4184374894
Short name T910
Test name
Test status
Simulation time 365106470 ps
CPU time 7.62 seconds
Started Jun 05 04:35:12 PM PDT 24
Finished Jun 05 04:35:20 PM PDT 24
Peak memory 238312 kb
Host smart-d11e10e7-04f5-47c7-bed7-a240edc8fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184374894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4184374894
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.699617634
Short name T823
Test name
Test status
Simulation time 4645821407 ps
CPU time 10.05 seconds
Started Jun 05 04:34:58 PM PDT 24
Finished Jun 05 04:35:09 PM PDT 24
Peak memory 299596 kb
Host smart-f18fc1a6-ea4f-4caa-9ebb-5dbd635d83c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699617634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.699617634
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.853949822
Short name T1309
Test name
Test status
Simulation time 6768219109 ps
CPU time 54.7 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:36:13 PM PDT 24
Peak memory 642252 kb
Host smart-95e0db9c-0a0f-4533-9fbc-f8b8dbdeff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853949822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.853949822
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2875838150
Short name T10
Test name
Test status
Simulation time 1487260484 ps
CPU time 101.98 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:36:42 PM PDT 24
Peak memory 503404 kb
Host smart-536d1be8-38a3-4621-bcde-a9f9f9c9d060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875838150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2875838150
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3949154097
Short name T328
Test name
Test status
Simulation time 74174391 ps
CPU time 0.78 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 204452 kb
Host smart-e7171f45-041d-4508-a7e2-1ca94b46aa5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949154097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3949154097
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2004911405
Short name T402
Test name
Test status
Simulation time 607586045 ps
CPU time 4.84 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:35:14 PM PDT 24
Peak memory 232960 kb
Host smart-e5c2f9a6-f43d-48f9-83c3-fbe324469a58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004911405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2004911405
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2565233426
Short name T1168
Test name
Test status
Simulation time 3974340903 ps
CPU time 88.19 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:36:39 PM PDT 24
Peak memory 1111660 kb
Host smart-de1a944b-b0eb-4835-aeb8-fd592f0184b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565233426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2565233426
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1541179696
Short name T916
Test name
Test status
Simulation time 1555203262 ps
CPU time 5.41 seconds
Started Jun 05 04:34:58 PM PDT 24
Finished Jun 05 04:35:04 PM PDT 24
Peak memory 205048 kb
Host smart-bd5535c5-8710-4f51-98cf-51748ee35b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541179696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1541179696
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.987253522
Short name T75
Test name
Test status
Simulation time 1352246879 ps
CPU time 69.71 seconds
Started Jun 05 04:35:26 PM PDT 24
Finished Jun 05 04:36:36 PM PDT 24
Peak memory 384984 kb
Host smart-a8030f32-2d14-4a1e-b833-bb224903c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987253522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.987253522
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1936812609
Short name T141
Test name
Test status
Simulation time 62125511 ps
CPU time 0.67 seconds
Started Jun 05 04:34:58 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 204660 kb
Host smart-9661a841-1182-442a-b39e-ab1a234d019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936812609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1936812609
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1791301422
Short name T165
Test name
Test status
Simulation time 5008760069 ps
CPU time 93.49 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:36:29 PM PDT 24
Peak memory 771972 kb
Host smart-c9b1db49-d954-4bbe-ac81-6e1adf5b1479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791301422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1791301422
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.743501946
Short name T482
Test name
Test status
Simulation time 1305435737 ps
CPU time 23.73 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:35:28 PM PDT 24
Peak memory 350800 kb
Host smart-1773c451-e5bc-43f8-9659-1baca1d4db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743501946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.743501946
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1621433603
Short name T465
Test name
Test status
Simulation time 43777873826 ps
CPU time 1874.8 seconds
Started Jun 05 04:35:20 PM PDT 24
Finished Jun 05 05:06:36 PM PDT 24
Peak memory 2317812 kb
Host smart-e9c0af93-12ad-4f0a-b375-ddc86b3893c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621433603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1621433603
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3207065626
Short name T305
Test name
Test status
Simulation time 8708945761 ps
CPU time 43.09 seconds
Started Jun 05 04:34:58 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 213392 kb
Host smart-834905ae-77c7-4523-b5cf-773e76783ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207065626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3207065626
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2386658069
Short name T1380
Test name
Test status
Simulation time 4097179155 ps
CPU time 5.36 seconds
Started Jun 05 04:34:54 PM PDT 24
Finished Jun 05 04:35:00 PM PDT 24
Peak memory 205324 kb
Host smart-d55a569e-3df8-4449-8f20-59ab22f26444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386658069 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2386658069
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.203720765
Short name T1485
Test name
Test status
Simulation time 10474012783 ps
CPU time 16.86 seconds
Started Jun 05 04:35:26 PM PDT 24
Finished Jun 05 04:35:43 PM PDT 24
Peak memory 246348 kb
Host smart-c5437009-2fe6-4b85-a5f5-7ba0b8f4e823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203720765 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.203720765
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2781905368
Short name T285
Test name
Test status
Simulation time 10170512091 ps
CPU time 72.82 seconds
Started Jun 05 04:35:07 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 638164 kb
Host smart-8c261154-ee6e-438e-9ebc-28cafabdf10e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781905368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2781905368
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2106996269
Short name T890
Test name
Test status
Simulation time 1793984311 ps
CPU time 2.52 seconds
Started Jun 05 04:35:01 PM PDT 24
Finished Jun 05 04:35:04 PM PDT 24
Peak memory 205060 kb
Host smart-310fac6a-2dcc-4d9d-b370-a053c7a810a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106996269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2106996269
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.3768294753
Short name T36
Test name
Test status
Simulation time 1361372801 ps
CPU time 1.72 seconds
Started Jun 05 04:35:09 PM PDT 24
Finished Jun 05 04:35:12 PM PDT 24
Peak memory 205100 kb
Host smart-646f96bf-1c3f-4135-9119-d2e4534678fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768294753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.3768294753
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3458916829
Short name T909
Test name
Test status
Simulation time 369368521 ps
CPU time 2.43 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:35:13 PM PDT 24
Peak memory 205136 kb
Host smart-d5b15469-6e3d-4650-a4d1-d4645fdb1dec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458916829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3458916829
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.4234171294
Short name T137
Test name
Test status
Simulation time 4494119417 ps
CPU time 6.61 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:03 PM PDT 24
Peak memory 218020 kb
Host smart-38d9551d-7514-4767-a86e-c968bbc7e6fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234171294 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.4234171294
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.244381778
Short name T706
Test name
Test status
Simulation time 13158722661 ps
CPU time 22.78 seconds
Started Jun 05 04:34:53 PM PDT 24
Finished Jun 05 04:35:17 PM PDT 24
Peak memory 539424 kb
Host smart-6ccdf395-65f2-4b00-bc1e-a1cd9e98d027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244381778 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.244381778
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1485070403
Short name T1448
Test name
Test status
Simulation time 10778765642 ps
CPU time 11.83 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:35:23 PM PDT 24
Peak memory 205204 kb
Host smart-054ad7f0-f22f-474a-b4ab-9e60a48e2995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485070403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1485070403
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.1911290383
Short name T339
Test name
Test status
Simulation time 3323272537 ps
CPU time 19.87 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:36 PM PDT 24
Peak memory 215332 kb
Host smart-a4351fd7-e526-4c4e-be15-b468b513c170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911290383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.1911290383
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1464962733
Short name T378
Test name
Test status
Simulation time 13974145367 ps
CPU time 28.25 seconds
Started Jun 05 04:35:12 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 205128 kb
Host smart-c88f2dfe-3b4f-44cc-8e0c-366386b84659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464962733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1464962733
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.133686116
Short name T703
Test name
Test status
Simulation time 23813571190 ps
CPU time 427.75 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:42:11 PM PDT 24
Peak memory 1281892 kb
Host smart-7f0853d1-4806-4a28-af36-d25c5a591fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133686116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.133686116
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3895488584
Short name T997
Test name
Test status
Simulation time 1431897557 ps
CPU time 8.04 seconds
Started Jun 05 04:34:56 PM PDT 24
Finished Jun 05 04:35:05 PM PDT 24
Peak memory 219084 kb
Host smart-b840e2a6-5248-4474-ace0-ef0e5db24338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895488584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3895488584
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.1650465395
Short name T807
Test name
Test status
Simulation time 1113561363 ps
CPU time 15.67 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:35:25 PM PDT 24
Peak memory 204156 kb
Host smart-e1e25a50-9a5a-4c37-8d7b-c05acb0ef514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650465395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.1650465395
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3133995953
Short name T684
Test name
Test status
Simulation time 63258713 ps
CPU time 0.6 seconds
Started Jun 05 04:35:17 PM PDT 24
Finished Jun 05 04:35:20 PM PDT 24
Peak memory 204680 kb
Host smart-8404c993-dba1-4607-a98b-6337234e1ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133995953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3133995953
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.966806933
Short name T724
Test name
Test status
Simulation time 300335679 ps
CPU time 5.88 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:30 PM PDT 24
Peak memory 213300 kb
Host smart-c21dfb19-6005-43f1-8a82-4f92f929380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966806933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.966806933
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1930486193
Short name T560
Test name
Test status
Simulation time 370569443 ps
CPU time 8.46 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 286336 kb
Host smart-a93d7cb1-53fa-4a51-9607-e3bd7f459685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930486193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1930486193
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2797770604
Short name T576
Test name
Test status
Simulation time 4629935871 ps
CPU time 250.78 seconds
Started Jun 05 04:35:14 PM PDT 24
Finished Jun 05 04:39:26 PM PDT 24
Peak memory 932564 kb
Host smart-6fe52d15-8fa8-4dca-8640-20b4caab720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797770604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2797770604
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2825654431
Short name T138
Test name
Test status
Simulation time 7497381398 ps
CPU time 70.01 seconds
Started Jun 05 04:35:06 PM PDT 24
Finished Jun 05 04:36:17 PM PDT 24
Peak memory 673600 kb
Host smart-1b662691-0739-46cf-b14e-40282330bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825654431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2825654431
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2162340151
Short name T460
Test name
Test status
Simulation time 164557942 ps
CPU time 0.85 seconds
Started Jun 05 04:35:02 PM PDT 24
Finished Jun 05 04:35:03 PM PDT 24
Peak memory 204724 kb
Host smart-c3e799b3-ab9d-4aa9-a1e0-d12c7cfe2ab6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162340151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2162340151
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2781648851
Short name T1234
Test name
Test status
Simulation time 171796082 ps
CPU time 10.02 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:27 PM PDT 24
Peak memory 234540 kb
Host smart-bda1ba85-d6c5-4ded-a32a-fbe182da8e1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781648851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2781648851
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.567760764
Short name T115
Test name
Test status
Simulation time 8466168514 ps
CPU time 120 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:37:10 PM PDT 24
Peak memory 1491532 kb
Host smart-02d2691e-44ea-4c68-a7ea-e931eed233b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567760764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.567760764
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.4047538757
Short name T432
Test name
Test status
Simulation time 1467422109 ps
CPU time 15.69 seconds
Started Jun 05 04:35:27 PM PDT 24
Finished Jun 05 04:35:43 PM PDT 24
Peak memory 205116 kb
Host smart-fc9e116d-5baa-4cbd-ac70-04d2ffc6f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047538757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.4047538757
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.146179915
Short name T1196
Test name
Test status
Simulation time 3722583115 ps
CPU time 39.33 seconds
Started Jun 05 04:35:06 PM PDT 24
Finished Jun 05 04:35:46 PM PDT 24
Peak memory 409936 kb
Host smart-5d0ec47e-0687-45bd-8cff-91156e727b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146179915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.146179915
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1546357171
Short name T146
Test name
Test status
Simulation time 80283212 ps
CPU time 0.65 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:21 PM PDT 24
Peak memory 204760 kb
Host smart-7e79aa75-7796-4bba-9bbb-c7baadb2cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546357171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1546357171
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.91565854
Short name T643
Test name
Test status
Simulation time 27491622413 ps
CPU time 88.39 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:36:41 PM PDT 24
Peak memory 213352 kb
Host smart-dc76299a-5468-4f5b-87d3-f5d973035992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91565854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.91565854
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.95317817
Short name T3
Test name
Test status
Simulation time 6422867833 ps
CPU time 49.92 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:36:20 PM PDT 24
Peak memory 251956 kb
Host smart-762d4401-4111-4509-9ad1-d75af70883df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95317817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.95317817
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.987913709
Short name T1442
Test name
Test status
Simulation time 654691715 ps
CPU time 26.89 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:23 PM PDT 24
Peak memory 213168 kb
Host smart-1b7cda65-b5c3-42e9-acf5-61b8f033c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987913709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.987913709
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1008989102
Short name T522
Test name
Test status
Simulation time 2158890671 ps
CPU time 4.13 seconds
Started Jun 05 04:35:09 PM PDT 24
Finished Jun 05 04:35:14 PM PDT 24
Peak memory 205228 kb
Host smart-8a42dc95-e961-497b-b067-108951163b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008989102 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1008989102
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1347961909
Short name T581
Test name
Test status
Simulation time 10124971324 ps
CPU time 47.76 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:35:52 PM PDT 24
Peak memory 327064 kb
Host smart-89d63201-c207-4df1-a096-647a9bb597b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347961909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1347961909
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2071846575
Short name T457
Test name
Test status
Simulation time 10527240084 ps
CPU time 11.04 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:35:35 PM PDT 24
Peak memory 259340 kb
Host smart-6bfbfee2-82bb-44f6-8e9f-f4d352b252f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071846575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2071846575
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.3367099077
Short name T303
Test name
Test status
Simulation time 1872810150 ps
CPU time 2.64 seconds
Started Jun 05 04:35:08 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 204908 kb
Host smart-a52515d5-99ef-4aba-a1f6-6743b90b41f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367099077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.3367099077
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3500314520
Short name T815
Test name
Test status
Simulation time 1111900540 ps
CPU time 2.57 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:35:23 PM PDT 24
Peak memory 205056 kb
Host smart-5e63ce8a-5376-4133-adb3-db20ff545e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500314520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3500314520
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3676507109
Short name T295
Test name
Test status
Simulation time 944813892 ps
CPU time 1.75 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:35:34 PM PDT 24
Peak memory 205076 kb
Host smart-ff9a2279-91d0-4251-b10b-ffdc99df823c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676507109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3676507109
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.4102857020
Short name T862
Test name
Test status
Simulation time 1113401136 ps
CPU time 3.28 seconds
Started Jun 05 04:35:00 PM PDT 24
Finished Jun 05 04:35:04 PM PDT 24
Peak memory 205092 kb
Host smart-01bc6935-140b-42b3-ad50-0c5031b3fd5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102857020 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.4102857020
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2043941666
Short name T822
Test name
Test status
Simulation time 15143253667 ps
CPU time 38.01 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 04:35:34 PM PDT 24
Peak memory 934908 kb
Host smart-91b7e193-e546-4ec1-8bb9-cf34c357db97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043941666 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2043941666
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3523181424
Short name T597
Test name
Test status
Simulation time 964598938 ps
CPU time 13.3 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 205116 kb
Host smart-2a642502-0c58-4725-b988-63b5de66b156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523181424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3523181424
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1299919574
Short name T331
Test name
Test status
Simulation time 1317781140 ps
CPU time 9.41 seconds
Started Jun 05 04:34:57 PM PDT 24
Finished Jun 05 04:35:07 PM PDT 24
Peak memory 208880 kb
Host smart-3352031e-da43-4e34-bb29-8cc4b973fe1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299919574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1299919574
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3991838986
Short name T388
Test name
Test status
Simulation time 34849140466 ps
CPU time 41.04 seconds
Started Jun 05 04:34:59 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 771012 kb
Host smart-aff8a499-6c36-4a22-888c-31a5c8900dc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991838986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3991838986
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2111439697
Short name T1200
Test name
Test status
Simulation time 22698610414 ps
CPU time 1980.43 seconds
Started Jun 05 04:34:55 PM PDT 24
Finished Jun 05 05:07:57 PM PDT 24
Peak memory 5420688 kb
Host smart-ebbe47bd-298b-4d0b-a4aa-95b57a6e7112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111439697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2111439697
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2479745954
Short name T537
Test name
Test status
Simulation time 2962995998 ps
CPU time 7.49 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:24 PM PDT 24
Peak memory 211856 kb
Host smart-668f312d-a716-4aaf-a758-341c31e6d60a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479745954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2479745954
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.453087618
Short name T571
Test name
Test status
Simulation time 1318282996 ps
CPU time 18.32 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:35:22 PM PDT 24
Peak memory 205196 kb
Host smart-a148bc25-118c-49a5-80bb-624f06e5f7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453087618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.453087618
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3123793482
Short name T1165
Test name
Test status
Simulation time 17768212 ps
CPU time 0.65 seconds
Started Jun 05 04:35:28 PM PDT 24
Finished Jun 05 04:35:30 PM PDT 24
Peak memory 204732 kb
Host smart-4b75bcc6-c873-450f-8d97-c3e3c6043572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123793482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3123793482
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1195786892
Short name T1352
Test name
Test status
Simulation time 2140283970 ps
CPU time 27.76 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:35:32 PM PDT 24
Peak memory 279416 kb
Host smart-a6063266-c7fb-48c6-960f-c59b8eeeedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195786892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1195786892
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.629661696
Short name T1500
Test name
Test status
Simulation time 1353262552 ps
CPU time 7.77 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:35:12 PM PDT 24
Peak memory 268224 kb
Host smart-4cd0bda9-19a2-4fbb-bdcc-a8e64d66dd9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629661696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.629661696
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3025752402
Short name T1338
Test name
Test status
Simulation time 8632743066 ps
CPU time 138.35 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:37:43 PM PDT 24
Peak memory 623136 kb
Host smart-96573187-5763-40ea-898e-792668a7c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025752402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3025752402
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3214098505
Short name T907
Test name
Test status
Simulation time 22284631511 ps
CPU time 79.34 seconds
Started Jun 05 04:35:19 PM PDT 24
Finished Jun 05 04:36:40 PM PDT 24
Peak memory 690448 kb
Host smart-0c47697b-9ef7-45c9-b582-925f76c492a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214098505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3214098505
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2741784683
Short name T676
Test name
Test status
Simulation time 138596338 ps
CPU time 1.07 seconds
Started Jun 05 04:35:14 PM PDT 24
Finished Jun 05 04:35:16 PM PDT 24
Peak memory 204972 kb
Host smart-fbcb967b-4ce6-42d8-aacd-5dbb36e2149b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741784683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2741784683
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3442350343
Short name T952
Test name
Test status
Simulation time 181565191 ps
CPU time 4.38 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:35:10 PM PDT 24
Peak memory 235248 kb
Host smart-3461b9f2-90cc-433a-be29-108b5ef2e841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442350343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3442350343
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2355753154
Short name T1123
Test name
Test status
Simulation time 21699931631 ps
CPU time 164.17 seconds
Started Jun 05 04:35:04 PM PDT 24
Finished Jun 05 04:37:49 PM PDT 24
Peak memory 1365180 kb
Host smart-cf96eae9-0303-4bea-87ab-8029eae811df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355753154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2355753154
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2437819918
Short name T260
Test name
Test status
Simulation time 2049286482 ps
CPU time 8.07 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 205036 kb
Host smart-ccc874d1-d6e9-410c-81e4-578949353a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437819918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2437819918
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2410068780
Short name T252
Test name
Test status
Simulation time 8480955567 ps
CPU time 32.71 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:36:05 PM PDT 24
Peak memory 324644 kb
Host smart-6d51e275-8f5f-4a0d-a442-4ded06c3146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410068780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2410068780
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2730493895
Short name T139
Test name
Test status
Simulation time 29526113 ps
CPU time 0.73 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:31 PM PDT 24
Peak memory 204672 kb
Host smart-bfaa2a06-aa19-4578-beb2-38ed4ae1ab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730493895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2730493895
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3157154360
Short name T1310
Test name
Test status
Simulation time 26741276970 ps
CPU time 44.6 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:35:49 PM PDT 24
Peak memory 590076 kb
Host smart-190e1906-ce10-4f9b-8de8-2d42d3f2d5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157154360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3157154360
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3653230278
Short name T485
Test name
Test status
Simulation time 17615985793 ps
CPU time 32.02 seconds
Started Jun 05 04:35:10 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 326552 kb
Host smart-5c78cac8-c531-4ea8-b679-a54ef3ca3650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653230278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3653230278
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1587850195
Short name T82
Test name
Test status
Simulation time 77872327935 ps
CPU time 1362.6 seconds
Started Jun 05 04:35:21 PM PDT 24
Finished Jun 05 04:58:05 PM PDT 24
Peak memory 2849348 kb
Host smart-0d03b377-7e50-47e3-815b-6a583c06d4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587850195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1587850195
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2112459710
Short name T267
Test name
Test status
Simulation time 940300772 ps
CPU time 42.45 seconds
Started Jun 05 04:35:11 PM PDT 24
Finished Jun 05 04:35:54 PM PDT 24
Peak memory 213416 kb
Host smart-1a2558c6-0b30-4ed4-80b1-7049662d392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112459710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2112459710
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3323045805
Short name T1240
Test name
Test status
Simulation time 10194441387 ps
CPU time 12.28 seconds
Started Jun 05 04:35:16 PM PDT 24
Finished Jun 05 04:35:30 PM PDT 24
Peak memory 244104 kb
Host smart-d5069c74-1c0e-4138-9a96-3f31f62dd76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323045805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3323045805
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.3842700852
Short name T1151
Test name
Test status
Simulation time 10136635731 ps
CPU time 37.39 seconds
Started Jun 05 04:35:03 PM PDT 24
Finished Jun 05 04:35:42 PM PDT 24
Peak memory 406072 kb
Host smart-0c476a26-2194-4a26-acba-c02e9c6177bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842700852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.3842700852
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.686557340
Short name T756
Test name
Test status
Simulation time 1397508018 ps
CPU time 2.17 seconds
Started Jun 05 04:35:13 PM PDT 24
Finished Jun 05 04:35:16 PM PDT 24
Peak memory 205140 kb
Host smart-4bad2fbd-f4a5-4275-9b98-616ef3baa721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686557340 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.686557340
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.535819354
Short name T287
Test name
Test status
Simulation time 2256086736 ps
CPU time 1.13 seconds
Started Jun 05 04:35:22 PM PDT 24
Finished Jun 05 04:35:24 PM PDT 24
Peak memory 204980 kb
Host smart-4c8e0f3f-a6b8-4c3b-980f-da3a2302d3db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535819354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.535819354
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2492081749
Short name T609
Test name
Test status
Simulation time 933234519 ps
CPU time 2.84 seconds
Started Jun 05 04:35:07 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 205012 kb
Host smart-4ed5c064-1493-4e8f-baa2-c9ba8ab10c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492081749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2492081749
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1709125094
Short name T1461
Test name
Test status
Simulation time 8709438700 ps
CPU time 5.22 seconds
Started Jun 05 04:35:30 PM PDT 24
Finished Jun 05 04:35:36 PM PDT 24
Peak memory 205264 kb
Host smart-455044f5-9e7e-4963-80e7-25b86ee83f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709125094 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1709125094
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.468835965
Short name T1129
Test name
Test status
Simulation time 32512589995 ps
CPU time 35.38 seconds
Started Jun 05 04:35:29 PM PDT 24
Finished Jun 05 04:36:05 PM PDT 24
Peak memory 793580 kb
Host smart-44e8dbc1-2456-4559-993f-ea6217b6b593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468835965 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.468835965
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2395170918
Short name T667
Test name
Test status
Simulation time 3410516654 ps
CPU time 12.89 seconds
Started Jun 05 04:35:31 PM PDT 24
Finished Jun 05 04:35:45 PM PDT 24
Peak memory 205116 kb
Host smart-f983ef15-930b-44c0-9520-de03305aa037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395170918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2395170918
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2707998260
Short name T1503
Test name
Test status
Simulation time 1825929573 ps
CPU time 5.38 seconds
Started Jun 05 04:35:05 PM PDT 24
Finished Jun 05 04:35:11 PM PDT 24
Peak memory 205008 kb
Host smart-3779c179-7033-47c4-a881-c94fba1f6ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707998260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2707998260
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1635084775
Short name T35
Test name
Test status
Simulation time 58660516525 ps
CPU time 1843.53 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 05:06:08 PM PDT 24
Peak memory 9788948 kb
Host smart-7c9ae726-a809-43bb-90bd-0660105b1c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635084775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1635084775
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3633226579
Short name T1424
Test name
Test status
Simulation time 8049147973 ps
CPU time 122.92 seconds
Started Jun 05 04:35:25 PM PDT 24
Finished Jun 05 04:37:28 PM PDT 24
Peak memory 1073948 kb
Host smart-ab92b97a-6a9b-4a74-94fb-dc9f1e3f2402
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633226579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3633226579
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.4010579306
Short name T904
Test name
Test status
Simulation time 2623666795 ps
CPU time 7.36 seconds
Started Jun 05 04:35:15 PM PDT 24
Finished Jun 05 04:35:24 PM PDT 24
Peak memory 213392 kb
Host smart-1b7484ff-df71-4197-856e-33e488635574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010579306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.4010579306
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.1988424
Short name T668
Test name
Test status
Simulation time 1181907364 ps
CPU time 15.85 seconds
Started Jun 05 04:35:23 PM PDT 24
Finished Jun 05 04:35:40 PM PDT 24
Peak memory 205088 kb
Host smart-bf1c78d5-12c6-4176-9fec-6f2ce2a1e8db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988424 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_tx_stretch_ctrl.1988424
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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