Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	850529	1			T1	3		T2	8274		T3	3
all_values[1]	850529	1			T1	3		T2	8274		T3	3
all_values[2]	850529	1			T1	3		T2	8274		T3	3
all_values[3]	850529	1			T1	3		T2	8274		T3	3
all_values[4]	850529	1			T1	3		T2	8274		T3	3
all_values[5]	850529	1			T1	3		T2	8274		T3	3
all_values[6]	850529	1			T1	3		T2	8274		T3	3
all_values[7]	850529	1			T1	3		T2	8274		T3	3
all_values[8]	850529	1			T1	3		T2	8274		T3	3
all_values[9]	850529	1			T1	3		T2	8274		T3	3
all_values[10]	850529	1			T1	3		T2	8274		T3	3
all_values[11]	850529	1			T1	3		T2	8274		T3	3
all_values[12]	850529	1			T1	3		T2	8274		T3	3
all_values[13]	850529	1			T1	3		T2	8274		T3	3
all_values[14]	850529	1			T1	3		T2	8274		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10395663

1

T1

38

T2

99693

T3

38

auto[1]

2362272

1

T1

7

T2

24417

T3

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10472280

1

T1

45

T2

124110

T3

45

auto[1]

2285655

1

T31

57

T46

421100

T99

74272

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	61866	1			T2	228		T4	1		T6	99
all_values[0]	auto[0]	auto[1]	11639	1			T46	3687		T99	585		T123	74
all_values[0]	auto[1]	auto[0]	650644	1			T1	3		T2	8046		T3	3
all_values[0]	auto[1]	auto[1]	126380	1			T46	26390		T99	4363		T123	471
all_values[1]	auto[0]	auto[0]	690401	1			T1	3		T2	8274		T3	3
all_values[1]	auto[0]	auto[1]	159541	1			T31	3		T46	30069		T99	4945
all_values[1]	auto[1]	auto[0]	296	1			T29	1		T42	2		T220	2
all_values[1]	auto[1]	auto[1]	291	1			T31	2		T46	9		T99	1
all_values[2]	auto[0]	auto[0]	710785	1			T1	3		T2	8274		T3	3
all_values[2]	auto[0]	auto[1]	139424	1			T31	4		T46	30071		T99	4951
all_values[2]	auto[1]	auto[0]	112	1			T17	3		T221	1		T222	2
all_values[2]	auto[1]	auto[1]	208	1			T31	2		T46	7		T99	2
all_values[3]	auto[0]	auto[0]	737424	1			T1	3		T2	8274		T3	3
all_values[3]	auto[0]	auto[1]	112852	1			T46	9		T99	4946		T123	542
all_values[3]	auto[1]	auto[1]	253	1			T46	8		T99	1		T123	4
all_values[4]	auto[0]	auto[0]	690296	1			T1	3		T2	8274		T3	3
all_values[4]	auto[0]	auto[1]	159990	1			T31	3		T46	30067		T99	4948
all_values[4]	auto[1]	auto[0]	10	1			T41	2		T223	2		T224	1
all_values[4]	auto[1]	auto[1]	233	1			T31	3		T46	8		T99	5
all_values[5]	auto[0]	auto[0]	690298	1			T1	3		T2	8274		T3	3
all_values[5]	auto[0]	auto[1]	159959	1			T31	2		T46	30062		T99	4947
all_values[5]	auto[1]	auto[1]	272	1			T31	2		T46	16		T99	6
all_values[6]	auto[0]	auto[0]	690333	1			T1	3		T2	8274		T3	3
all_values[6]	auto[0]	auto[1]	159941	1			T31	3		T46	30070		T99	4947
all_values[6]	auto[1]	auto[1]	255	1			T31	3		T46	8		T99	6
all_values[7]	auto[0]	auto[0]	669524	1			T1	3		T2	8180		T3	3
all_values[7]	auto[0]	auto[1]	150038	1			T31	2		T46	29726		T99	4338
all_values[7]	auto[1]	auto[0]	26689	1			T2	94		T4	1		T6	130
all_values[7]	auto[1]	auto[1]	4278	1			T31	2		T46	352		T99	615
all_values[8]	auto[0]	auto[0]	696565	1			T1	3		T2	8274		T3	3
all_values[8]	auto[0]	auto[1]	153732	1			T46	30067		T99	4947		T123	542
all_values[8]	auto[1]	auto[1]	232	1			T46	10		T99	6		T123	4
all_values[9]	auto[0]	auto[0]	131205	1			T1	2		T2	262		T3	2
all_values[9]	auto[0]	auto[1]	15573	1			T31	2		T46	426		T99	1461
all_values[9]	auto[1]	auto[0]	559644	1			T1	1		T2	8012		T3	1
all_values[9]	auto[1]	auto[1]	144107	1			T31	3		T46	29652		T99	3492
all_values[10]	auto[0]	auto[0]	690305	1			T1	3		T2	8274		T3	3
all_values[10]	auto[0]	auto[1]	159990	1			T31	3		T46	30067		T99	4950
all_values[10]	auto[1]	auto[1]	234	1			T31	1		T46	11		T99	3
all_values[11]	auto[0]	auto[0]	2578	1			T2	9		T4	1		T6	9
all_values[11]	auto[0]	auto[1]	575	1			T46	24		T99	30		T123	18
all_values[11]	auto[1]	auto[0]	687732	1			T1	3		T2	8265		T3	3
all_values[11]	auto[1]	auto[1]	159644	1			T46	30054		T99	4923		T123	527
all_values[12]	auto[0]	auto[0]	690250	1			T1	3		T2	8274		T3	3
all_values[12]	auto[0]	auto[1]	160011	1			T31	5		T46	30068		T99	4946
all_values[12]	auto[1]	auto[0]	25	1			T17	1		T222	1		T225	1
all_values[12]	auto[1]	auto[1]	243	1			T31	1		T46	8		T99	2
all_values[13]	auto[0]	auto[0]	690569	1			T1	3		T2	8274		T3	3
all_values[13]	auto[0]	auto[1]	159716	1			T31	2		T46	30067		T99	4948
all_values[13]	auto[1]	auto[1]	244	1			T31	3		T46	9		T99	5
all_values[14]	auto[0]	auto[0]	704729	1			T1	3		T2	8274		T3	3
all_values[14]	auto[0]	auto[1]	145554	1			T31	2		T46	30066		T99	4947
all_values[14]	auto[1]	auto[1]	246	1			T31	4		T46	12		T99	6