Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	850529	1			T1	3		T2	8274		T3	3
all_pins[1]	850529	1			T1	3		T2	8274		T3	3
all_pins[2]	850529	1			T1	3		T2	8274		T3	3
all_pins[3]	850529	1			T1	3		T2	8274		T3	3
all_pins[4]	850529	1			T1	3		T2	8274		T3	3
all_pins[5]	850529	1			T1	3		T2	8274		T3	3
all_pins[6]	850529	1			T1	3		T2	8274		T3	3
all_pins[7]	850529	1			T1	3		T2	8274		T3	3
all_pins[8]	850529	1			T1	3		T2	8274		T3	3
all_pins[9]	850529	1			T1	3		T2	8274		T3	3
all_pins[10]	850529	1			T1	3		T2	8274		T3	3
all_pins[11]	850529	1			T1	3		T2	8274		T3	3
all_pins[12]	850529	1			T1	3		T2	8274		T3	3
all_pins[13]	850529	1			T1	3		T2	8274		T3	3
all_pins[14]	850529	1			T1	3		T2	8274		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10400731	1			T1	38		T2	99667		T3	38
values[0x1]	2357204	1			T1	7		T2	24443		T3	7
transitions[0x0=>0x1]	2356291	1			T1	7		T2	24443		T3	7
transitions[0x1=>0x0]	2355118	1			T1	6		T2	24442		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76875	1			T2	229		T4	1		T6	97
all_pins[0]	values[0x1]	773654	1			T1	3		T2	8045		T3	3
all_pins[0]	transitions[0x0=>0x1]	773212	1			T1	3		T2	8045		T3	3
all_pins[0]	transitions[0x1=>0x0]	92	1			T31	2		T46	3		T249	7
all_pins[1]	values[0x0]	849995	1			T1	3		T2	8274		T3	3
all_pins[1]	values[0x1]	534	1			T31	2		T29	1		T46	5
all_pins[1]	transitions[0x0=>0x1]	510	1			T31	1		T29	1		T46	5
all_pins[1]	transitions[0x1=>0x0]	190	1			T31	1		T46	4		T17	3
all_pins[2]	values[0x0]	850315	1			T1	3		T2	8274		T3	3
all_pins[2]	values[0x1]	214	1			T31	2		T46	4		T17	3
all_pins[2]	transitions[0x0=>0x1]	184	1			T31	2		T46	2		T17	3
all_pins[2]	transitions[0x1=>0x0]	102	1			T46	2		T99	1		T207	2
all_pins[3]	values[0x0]	850397	1			T1	3		T2	8274		T3	3
all_pins[3]	values[0x1]	132	1			T46	4		T99	1		T207	2
all_pins[3]	transitions[0x0=>0x1]	100	1			T46	4		T207	2		T248	2
all_pins[3]	transitions[0x1=>0x0]	97	1			T46	4		T99	1		T123	2
all_pins[4]	values[0x0]	850400	1			T1	3		T2	8274		T3	3
all_pins[4]	values[0x1]	129	1			T46	4		T99	2		T123	2
all_pins[4]	transitions[0x0=>0x1]	98	1			T46	3		T123	2		T41	2
all_pins[4]	transitions[0x1=>0x0]	99	1			T46	6		T99	3		T207	1
all_pins[5]	values[0x0]	850399	1			T1	3		T2	8274		T3	3
all_pins[5]	values[0x1]	130	1			T46	7		T99	5		T207	1
all_pins[5]	transitions[0x0=>0x1]	98	1			T46	7		T99	3		T248	4
all_pins[5]	transitions[0x1=>0x0]	76	1			T31	1		T46	2		T99	1
all_pins[6]	values[0x0]	850421	1			T1	3		T2	8274		T3	3
all_pins[6]	values[0x1]	108	1			T31	1		T46	2		T99	3
all_pins[6]	transitions[0x0=>0x1]	83	1			T31	1		T46	2		T99	2
all_pins[6]	transitions[0x1=>0x0]	34302	1			T2	121		T4	1		T6	171
all_pins[7]	values[0x0]	816202	1			T1	3		T2	8153		T3	3
all_pins[7]	values[0x1]	34327	1			T2	121		T4	1		T6	171
all_pins[7]	transitions[0x0=>0x1]	34295	1			T2	121		T4	1		T6	171
all_pins[7]	transitions[0x1=>0x0]	97	1			T46	5		T99	1		T123	2
all_pins[8]	values[0x0]	850400	1			T1	3		T2	8274		T3	3
all_pins[8]	values[0x1]	129	1			T46	5		T99	3		T123	3
all_pins[8]	transitions[0x0=>0x1]	105	1			T46	1		T99	2		T123	3
all_pins[8]	transitions[0x1=>0x0]	703677	1			T1	1		T2	8012		T3	1
all_pins[9]	values[0x0]	146828	1			T1	2		T2	262		T3	2
all_pins[9]	values[0x1]	703701	1			T1	1		T2	8012		T3	1
all_pins[9]	transitions[0x0=>0x1]	703673	1			T1	1		T2	8012		T3	1
all_pins[9]	transitions[0x1=>0x0]	82	1			T46	4		T99	2		T123	2
all_pins[10]	values[0x0]	850419	1			T1	3		T2	8274		T3	3
all_pins[10]	values[0x1]	110	1			T46	5		T99	2		T123	2
all_pins[10]	transitions[0x0=>0x1]	71	1			T46	3		T99	1		T123	2
all_pins[10]	transitions[0x1=>0x0]	843592	1			T1	3		T2	8265		T3	3
all_pins[11]	values[0x0]	6898	1			T2	9		T4	1		T6	9
all_pins[11]	values[0x1]	843631	1			T1	3		T2	8265		T3	3
all_pins[11]	transitions[0x0=>0x1]	843564	1			T1	3		T2	8265		T3	3
all_pins[11]	transitions[0x1=>0x0]	89	1			T46	2		T207	3		T248	1
all_pins[12]	values[0x0]	850373	1			T1	3		T2	8274		T3	3
all_pins[12]	values[0x1]	156	1			T46	5		T17	1		T222	1
all_pins[12]	transitions[0x0=>0x1]	126	1			T46	4		T17	1		T222	1
all_pins[12]	transitions[0x1=>0x0]	95	1			T31	1		T46	3		T99	3
all_pins[13]	values[0x0]	850404	1			T1	3		T2	8274		T3	3
all_pins[13]	values[0x1]	125	1			T31	1		T46	4		T99	4
all_pins[13]	transitions[0x0=>0x1]	95	1			T31	1		T46	4		T99	2
all_pins[13]	transitions[0x1=>0x0]	94	1			T31	2		T46	4		T123	2
all_pins[14]	values[0x0]	850405	1			T1	3		T2	8274		T3	3
all_pins[14]	values[0x1]	124	1			T31	2		T46	4		T99	2
all_pins[14]	transitions[0x0=>0x1]	77	1			T31	2		T46	2		T99	2
all_pins[14]	transitions[0x1=>0x0]	772434	1			T1	2		T2	8044		T3	2