Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	531	1			T31	4		T46	21		T99	8
all_values[1]	531	1			T31	4		T46	21		T99	8
all_values[2]	531	1			T31	4		T46	21		T99	8
all_values[3]	531	1			T31	4		T46	21		T99	8
all_values[4]	531	1			T31	4		T46	21		T99	8
all_values[5]	531	1			T31	4		T46	21		T99	8
all_values[6]	531	1			T31	4		T46	21		T99	8
all_values[7]	531	1			T31	4		T46	21		T99	8
all_values[8]	531	1			T31	4		T46	21		T99	8
all_values[9]	531	1			T31	4		T46	21		T99	8
all_values[10]	531	1			T31	4		T46	21		T99	8
all_values[11]	531	1			T31	4		T46	21		T99	8
all_values[12]	531	1			T31	4		T46	21		T99	8
all_values[13]	531	1			T31	4		T46	21		T99	8
all_values[14]	531	1			T31	4		T46	21		T99	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4160

1

T31

32

T46

164

T99

54

auto[1]

3805

1

T31

28

T46

151

T99

66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1242

1

T31

25

T46

19

T99

19

auto[1]

6723

1

T31

35

T46

296

T99

101

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4660

1

T31

40

T46

176

T99

74

auto[1]

3305

1

T31

20

T46

139

T99

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	41	1			T46	1		T99	1		T123	1
all_values[0]	auto[0]	auto[0]	auto[1]	115	1			T46	4		T99	1		T207	2
all_values[0]	auto[0]	auto[1]	auto[0]	43	1			T31	4		T99	3		T48	1
all_values[0]	auto[0]	auto[1]	auto[1]	122	1			T46	8		T99	2		T123	2
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T46	2		T123	1		T48	1
all_values[0]	auto[1]	auto[1]	auto[1]	96	1			T46	6		T99	1		T207	1
all_values[1]	auto[0]	auto[0]	auto[0]	56	1			T31	1		T99	5		T250	1
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T46	3		T99	1		T123	1
all_values[1]	auto[0]	auto[1]	auto[0]	40	1			T99	1		T207	1		T251	1
all_values[1]	auto[0]	auto[1]	auto[1]	124	1			T31	1		T46	9		T123	2
all_values[1]	auto[1]	auto[0]	auto[1]	110	1			T46	3		T99	1		T123	1
all_values[1]	auto[1]	auto[1]	auto[1]	107	1			T31	2		T46	6		T248	1
all_values[2]	auto[0]	auto[0]	auto[0]	63	1			T123	3		T248	4		T252	1
all_values[2]	auto[0]	auto[0]	auto[1]	100	1			T31	1		T46	7		T99	1
all_values[2]	auto[0]	auto[1]	auto[0]	52	1			T123	1		T248	3		T252	1
all_values[2]	auto[0]	auto[1]	auto[1]	108	1			T31	1		T46	7		T99	5
all_values[2]	auto[1]	auto[0]	auto[1]	113	1			T46	4		T99	1		T48	1
all_values[2]	auto[1]	auto[1]	auto[1]	95	1			T31	2		T46	3		T99	1
all_values[3]	auto[0]	auto[0]	auto[0]	49	1			T31	2		T46	6		T99	4
all_values[3]	auto[0]	auto[0]	auto[1]	113	1			T46	2		T123	3		T207	2
all_values[3]	auto[0]	auto[1]	auto[0]	47	1			T31	2		T46	4		T99	1
all_values[3]	auto[0]	auto[1]	auto[1]	106	1			T46	1		T99	1		T248	1
all_values[3]	auto[1]	auto[0]	auto[1]	120	1			T46	6		T123	1		T207	4
all_values[3]	auto[1]	auto[1]	auto[1]	96	1			T46	2		T99	2		T248	3
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T46	2		T251	2		T242	1
all_values[4]	auto[0]	auto[0]	auto[1]	113	1			T31	1		T46	2		T99	2
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T46	1		T252	1		T253	1
all_values[4]	auto[0]	auto[1]	auto[1]	107	1			T46	8		T99	1		T123	1
all_values[4]	auto[1]	auto[0]	auto[1]	113	1			T31	3		T46	2		T99	3
all_values[4]	auto[1]	auto[1]	auto[1]	120	1			T46	6		T99	2		T123	2
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T31	1		T123	2		T253	1
all_values[5]	auto[0]	auto[0]	auto[1]	107	1			T31	1		T46	7		T123	1
all_values[5]	auto[0]	auto[1]	auto[0]	26	1			T31	1		T251	1		T253	2
all_values[5]	auto[0]	auto[1]	auto[1]	122	1			T46	3		T99	4		T207	2
all_values[5]	auto[1]	auto[0]	auto[1]	122	1			T31	1		T46	6		T99	1
all_values[5]	auto[1]	auto[1]	auto[1]	112	1			T46	5		T99	3		T207	2
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T252	1		T251	2		T253	1
all_values[6]	auto[0]	auto[0]	auto[1]	129	1			T31	1		T46	7		T99	1
all_values[6]	auto[0]	auto[1]	auto[0]	45	1			T248	2		T252	1		T251	3
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T31	1		T46	3		T99	3
all_values[6]	auto[1]	auto[0]	auto[1]	125	1			T31	1		T46	7		T99	3
all_values[6]	auto[1]	auto[1]	auto[1]	87	1			T31	1		T46	4		T99	1
all_values[7]	auto[0]	auto[0]	auto[0]	50	1			T31	1		T207	1		T252	1
all_values[7]	auto[0]	auto[0]	auto[1]	124	1			T46	7		T123	3		T207	2
all_values[7]	auto[0]	auto[1]	auto[0]	38	1			T31	1		T207	1		T248	1
all_values[7]	auto[0]	auto[1]	auto[1]	108	1			T31	1		T46	6		T99	5
all_values[7]	auto[1]	auto[0]	auto[1]	102	1			T46	7		T99	1		T123	1
all_values[7]	auto[1]	auto[1]	auto[1]	109	1			T31	1		T46	1		T99	2
all_values[8]	auto[0]	auto[0]	auto[0]	42	1			T31	2		T46	1		T48	1
all_values[8]	auto[0]	auto[0]	auto[1]	125	1			T46	2		T99	2		T207	1
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T31	2		T207	2		T48	6
all_values[8]	auto[0]	auto[1]	auto[1]	125	1			T46	6		T99	2		T123	1
all_values[8]	auto[1]	auto[0]	auto[1]	104	1			T46	6		T99	2		T123	2
all_values[8]	auto[1]	auto[1]	auto[1]	104	1			T46	6		T99	2		T123	1
all_values[9]	auto[0]	auto[0]	auto[0]	42	1			T31	1		T123	4		T254	1
all_values[9]	auto[0]	auto[0]	auto[1]	122	1			T31	1		T46	4		T99	2
all_values[9]	auto[0]	auto[1]	auto[0]	35	1			T248	1		T48	1		T254	1
all_values[9]	auto[0]	auto[1]	auto[1]	112	1			T46	6		T99	2		T207	2
all_values[9]	auto[1]	auto[0]	auto[1]	117	1			T31	2		T46	4		T99	4
all_values[9]	auto[1]	auto[1]	auto[1]	103	1			T46	7		T207	3		T248	1
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T250	1		T112	3		T255	2
all_values[10]	auto[0]	auto[0]	auto[1]	123	1			T31	1		T46	7		T99	3
all_values[10]	auto[0]	auto[1]	auto[0]	32	1			T31	2		T207	3		T48	1
all_values[10]	auto[0]	auto[1]	auto[1]	104	1			T46	3		T99	2		T207	1
all_values[10]	auto[1]	auto[0]	auto[1]	131	1			T31	1		T46	8		T99	2
all_values[10]	auto[1]	auto[1]	auto[1]	103	1			T46	3		T99	1		T123	1
all_values[11]	auto[0]	auto[0]	auto[0]	40	1			T31	2		T123	1		T207	1
all_values[11]	auto[0]	auto[0]	auto[1]	104	1			T46	4		T99	1		T207	1
all_values[11]	auto[0]	auto[1]	auto[0]	38	1			T31	2		T207	1		T248	3
all_values[11]	auto[0]	auto[1]	auto[1]	122	1			T46	6		T99	4		T123	1
all_values[11]	auto[1]	auto[0]	auto[1]	133	1			T46	7		T99	1		T123	1
all_values[11]	auto[1]	auto[1]	auto[1]	94	1			T46	4		T99	2		T123	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1			T46	1		T99	3		T252	1
all_values[12]	auto[0]	auto[0]	auto[1]	119	1			T31	3		T46	7		T123	2
all_values[12]	auto[0]	auto[1]	auto[0]	21	1			T46	1		T99	1		T48	1
all_values[12]	auto[0]	auto[1]	auto[1]	121	1			T46	4		T99	2		T207	1
all_values[12]	auto[1]	auto[0]	auto[1]	130	1			T31	1		T46	4		T99	1
all_values[12]	auto[1]	auto[1]	auto[1]	113	1			T46	4		T99	1		T207	4
all_values[13]	auto[0]	auto[0]	auto[0]	54	1			T46	2		T252	4		T251	2
all_values[13]	auto[0]	auto[0]	auto[1]	116	1			T31	1		T46	6		T99	1
all_values[13]	auto[0]	auto[1]	auto[0]	35	1			T31	1		T207	2		T248	2
all_values[13]	auto[0]	auto[1]	auto[1]	110	1			T46	5		T99	3		T207	1
all_values[13]	auto[1]	auto[0]	auto[1]	115	1			T31	1		T46	4		T99	1
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T31	1		T46	4		T99	3
all_values[14]	auto[0]	auto[0]	auto[0]	38	1			T207	1		T252	1		T112	2
all_values[14]	auto[0]	auto[0]	auto[1]	106	1			T46	7		T99	2		T207	1
all_values[14]	auto[0]	auto[1]	auto[0]	46	1			T207	1		T48	1		T256	2
all_values[14]	auto[0]	auto[1]	auto[1]	125	1			T31	1		T46	6		T99	2
all_values[14]	auto[1]	auto[0]	auto[1]	121	1			T31	2		T46	5		T99	3
all_values[14]	auto[1]	auto[1]	auto[1]	95	1			T31	1		T46	3		T99	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal